# SPDX-License-Identifier: GPL-2.0
# Audio subsystem clock support for Cixtech SoC family
menu "Cixtech Audio Subsystem Clock Driver"

config CLK_SKY1_AUDSS
	tristate "Cixtech Sky1 Audio Subsystem Clock Driver"
	depends on ARCH_CIX || COMPILE_TEST
	select AUXILIARY_BUS
	select REGMAP_MMIO
	select RESET_CONTROLLER
	help
	  Support for the Audio Subsystem clock controller present on
	  Cixtech Sky1 SoC. This driver provides mux, divider and gate
	  clocks for DSP, I2S, HDA and related blocks in the audio
	  subsystem. Say M or Y here if you want to build this driver.
endmenu