/* * C293 Silicon/SoC Device Tree Source (post include) * * Copyright 2012 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ &ifc { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,ifc"; interrupts = <19 2 0 0>; }; /* controller at 0xa000 */ &pci0 { compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <16 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <16 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 >; }; }; &soc { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "simple-bus"; bus-frequency = <0>; // Filled out by uboot. ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; fsl,num-laws = <12>; }; ecm@1000 { compatible = "fsl,c293-ecm", "fsl,ecm"; reg = <0x1000 0x1000>; interrupts = <16 2 0 0>; }; memory-controller@2000 { compatible = "fsl,c293-memory-controller"; reg = <0x2000 0x1000>; interrupts = <16 2 0 0>; }; /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" /include/ "pq3-duart-0.dtsi" /include/ "pq3-espi-0.dtsi" spi0: spi@7000 { fsl,espi-num-chipselects = <1>; }; /include/ "pq3-gpio-0.dtsi" L2: l2-cache-controller@20000 { compatible = "fsl,c293-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes cache-size = <0x80000>; // L2,512K interrupts = <16 2 0 0>; }; /include/ "pq3-dma-0.dtsi" /include/ "pq3-esdhc-0.dtsi" sdhc@2e000 { compatible = "fsl,c293-esdhc", "fsl,esdhc"; sdhci,auto-cmd12; }; crypto@80000 { /include/ "qoriq-sec6.0-0.dtsi" }; crypto@80000 { reg = <0x80000 0x20000>; ranges = <0x0 0x80000 0x20000>; jr@1000 { interrupts = <45 2 0 0>; }; jr@2000 { interrupts = <57 2 0 0>; }; }; crypto@a0000 { /include/ "qoriq-sec6.0-0.dtsi" }; crypto@a0000 { reg = <0xa0000 0x20000>; ranges = <0x0 0xa0000 0x20000>; jr@1000 { interrupts = <49 2 0 0>; }; jr@2000 { interrupts = <50 2 0 0>; }; }; crypto@c0000 { /include/ "qoriq-sec6.0-0.dtsi" }; crypto@c0000 { reg = <0xc0000 0x20000>; ranges = <0x0 0xc0000 0x20000>; jr@1000 { interrupts = <55 2 0 0>; }; jr@2000 { interrupts = <56 2 0 0>; }; }; /include/ "pq3-mpic.dtsi" /include/ "pq3-mpic-timer-B.dtsi" /include/ "pq3-etsec2-0.dtsi" enet0: ethernet@b0000 { queue-group@b0000 { reg = <0x10000 0x1000>; }; }; /include/ "pq3-etsec2-1.dtsi" enet1: ethernet@b1000 { queue-group@b1000 { reg = <0x11000 0x1000>; }; }; global-utilities@e0000 { compatible = "fsl,c293-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; };