// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) /* * Copyright (C) STMicroelectronics 2023 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ #include "stm32mp251.dtsi" / { cpus { cpu1: cpu@1 { compatible = "arm,cortex-a35"; device_type = "cpu"; reg = <1>; enable-method = "psci"; power-domains = <&CPU_PD1>; power-domain-names = "psci"; }; }; arm-pmu { interrupts = , ; interrupt-affinity = <&cpu0>, <&cpu1>; }; psci { CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; }; }; timer { interrupts = , , , ; }; }; &optee { interrupts = ; }; &rifsc { ethernet2: ethernet@482d0000 { compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg = <0x482d0000 0x4000>; reg-names = "stmmaceth"; interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", "ptp_ref", "ethstp", "eth-ck"; clocks = <&rcc CK_ETH2_MAC>, <&rcc CK_ETH2_TX>, <&rcc CK_ETH2_RX>, <&rcc CK_KER_ETH2PTP>, <&rcc CK_ETH2_STP>, <&rcc CK_KER_ETH2>; snps,axi-config = <&stmmac_axi_config_2>; snps,mixed-burst; snps,mtl-rx-config = <&mtl_rx_setup_2>; snps,mtl-tx-config = <&mtl_tx_setup_2>; snps,pbl = <2>; snps,tso; st,syscon = <&syscfg 0x3400>; access-controllers = <&rifsc 61>; status = "disabled"; mtl_rx_setup_2: rx-queues-config { snps,rx-queues-to-use = <2>; queue0 {}; queue1 {}; }; mtl_tx_setup_2: tx-queues-config { snps,tx-queues-to-use = <4>; queue0 {}; queue1 {}; queue2 {}; queue3 {}; }; stmmac_axi_config_2: stmmac-axi-config { snps,blen = <0 0 0 0 16 8 4>; snps,rd_osr_lmt = <0x7>; snps,wr_osr_lmt = <0x7>; }; }; };