// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2022, Linaro Limited */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include / { interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; chosen { }; clocks { xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; bi_tcxo_div2: bi-tcxo-div2-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-mult = <1>; clock-div = <2>; }; bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&rpmhcc RPMH_CXO_CLK_A>; clock-mult = <1>; clock-div = <2>; }; }; cpus { #address-cells = <2>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a510"; reg = <0 0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; }; }; }; CPU1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a510"; reg = <0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a510"; reg = <0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a715"; reg = <0 0x300>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <270>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU4: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a715"; reg = <0 0x400>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <270>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU5: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a710"; reg = <0 0x500>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <270>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU6: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-a710"; reg = <0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <270>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU7: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-x3"; reg = <0 0x700>; clocks = <&cpufreq_hw 2>; enable-method = "psci"; next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <588>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; core4 { cpu = <&CPU4>; }; core5 { cpu = <&CPU5>; }; core6 { cpu = <&CPU6>; }; core7 { cpu = <&CPU7>; }; }; }; idle-states { entry-method = "psci"; LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <550>; exit-latency-us = <750>; min-residency-us = <6700>; local-timer-stop; }; BIG_CPU_SLEEP_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <600>; exit-latency-us = <1300>; min-residency-us = <8136>; local-timer-stop; }; PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { compatible = "arm,idle-state"; idle-state-name = "goldplus-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <500>; exit-latency-us = <1350>; min-residency-us = <7480>; local-timer-stop; }; }; domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x41000044>; entry-latency-us = <750>; exit-latency-us = <2350>; min-residency-us = <9144>; }; CLUSTER_SLEEP_1: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <2800>; exit-latency-us = <4400>; min-residency-us = <10150>; }; }; }; firmware { scm: scm { compatible = "qcom,scm-sm8550", "qcom,scm"; qcom,dload-mode = <&tcsr 0x19000>; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; }; }; clk_virt: interconnect-0 { compatible = "qcom,sm8550-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect-1 { compatible = "qcom,sm8550-mc-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; memory@a0000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0 0xa0000000 0 0>; }; pmu-a510 { compatible = "arm,cortex-a510-pmu"; interrupts = ; }; pmu-a710 { compatible = "arm,cortex-a710-pmu"; interrupts = ; }; pmu-a715 { compatible = "arm,cortex-a715-pmu"; interrupts = ; }; pmu-x3 { compatible = "arm,cortex-x3-pmu"; interrupts = ; }; psci { compatible = "arm,psci-1.0"; method = "smc"; CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&PRIME_CPU_SLEEP_0>; }; CLUSTER_PD: power-domain-cluster { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; }; }; reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; hyp_mem: hyp-region@80000000 { reg = <0 0x80000000 0 0xa00000>; no-map; }; cpusys_vm_mem: cpusys-vm-region@80a00000 { reg = <0 0x80a00000 0 0x400000>; no-map; }; hyp_tags_mem: hyp-tags-region@80e00000 { reg = <0 0x80e00000 0 0x3d0000>; no-map; }; xbl_sc_mem: xbl-sc-region@d8100000 { reg = <0 0xd8100000 0 0x40000>; no-map; }; hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { reg = <0 0x811d0000 0 0x30000>; no-map; }; /* merged xbl_dt_log, xbl_ramdump, aop_image */ xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { reg = <0 0x81a00000 0 0x260000>; no-map; }; aop_cmd_db_mem: aop-cmd-db-region@81c60000 { compatible = "qcom,cmd-db"; reg = <0 0x81c60000 0 0x20000>; no-map; }; /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ aop_config_merged_mem: aop-config-merged-region@81c80000 { reg = <0 0x81c80000 0 0x74000>; no-map; }; /* secdata region can be reused by apps */ smem: smem@81d00000 { compatible = "qcom,smem"; reg = <0 0x81d00000 0 0x200000>; hwlocks = <&tcsr_mutex 3>; no-map; }; adsp_mhi_mem: adsp-mhi-region@81f00000 { reg = <0 0x81f00000 0 0x20000>; no-map; }; global_sync_mem: global-sync-region@82600000 { reg = <0 0x82600000 0 0x100000>; no-map; }; tz_stat_mem: tz-stat-region@82700000 { reg = <0 0x82700000 0 0x100000>; no-map; }; cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { reg = <0 0x82800000 0 0x4600000>; no-map; }; mpss_mem: mpss-region@8a800000 { reg = <0 0x8a800000 0 0x10800000>; no-map; }; q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { reg = <0 0x9b000000 0 0x80000>; no-map; }; ipa_fw_mem: ipa-fw-region@9b080000 { reg = <0 0x9b080000 0 0x10000>; no-map; }; ipa_gsi_mem: ipa-gsi-region@9b090000 { reg = <0 0x9b090000 0 0xa000>; no-map; }; gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { reg = <0 0x9b09a000 0 0x2000>; no-map; }; spss_region_mem: spss-region@9b100000 { reg = <0 0x9b100000 0 0x180000>; no-map; }; /* First part of the "SPU secure shared memory" region */ spu_tz_shared_mem: spu-tz-shared-region@9b280000 { reg = <0 0x9b280000 0 0x60000>; no-map; }; /* Second part of the "SPU secure shared memory" region */ spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { reg = <0 0x9b2e0000 0 0x20000>; no-map; }; camera_mem: camera-region@9b300000 { reg = <0 0x9b300000 0 0x800000>; no-map; }; video_mem: video-region@9bb00000 { reg = <0 0x9bb00000 0 0x700000>; no-map; }; cvp_mem: cvp-region@9c200000 { reg = <0 0x9c200000 0 0x700000>; no-map; }; cdsp_mem: cdsp-region@9c900000 { reg = <0 0x9c900000 0 0x2000000>; no-map; }; q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { reg = <0 0x9e900000 0 0x80000>; no-map; }; q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { reg = <0 0x9e980000 0 0x80000>; no-map; }; adspslpi_mem: adspslpi-region@9ea00000 { reg = <0 0x9ea00000 0 0x4080000>; no-map; }; /* uefi region can be reused by apps */ /* Linux kernel image is loaded at 0xa8000000 */ rmtfs_mem: rmtfs-region@d4a80000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0xd4a80000 0x0 0x280000>; no-map; qcom,client-id = <1>; qcom,vmid = ; }; mpss_dsm_mem: mpss-dsm-region@d4d00000 { reg = <0 0xd4d00000 0 0x3300000>; no-map; }; tz_reserved_mem: tz-reserved-region@d8000000 { reg = <0 0xd8000000 0 0x100000>; no-map; }; cpucp_fw_mem: cpucp-fw-region@d8140000 { reg = <0 0xd8140000 0 0x1c0000>; no-map; }; qtee_mem: qtee-region@d8300000 { reg = <0 0xd8300000 0 0x500000>; no-map; }; ta_mem: ta-region@d8800000 { reg = <0 0xd8800000 0 0x8a00000>; no-map; }; tz_tags_mem: tz-tags-region@e1200000 { reg = <0 0xe1200000 0 0x2740000>; no-map; }; hwfence_shbuf: hwfence-shbuf-region@e6440000 { reg = <0 0xe6440000 0 0x279000>; no-map; }; trust_ui_vm_mem: trust-ui-vm-region@f3600000 { reg = <0 0xf3600000 0 0x4aee000>; no-map; }; trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { reg = <0 0xf80ee000 0 0x1000>; no-map; }; trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { reg = <0 0xf80ef000 0 0x9000>; no-map; }; trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { reg = <0 0xf80f8000 0 0x4000>; no-map; }; trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { reg = <0 0xf80fc000 0 0x4000>; no-map; }; trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { reg = <0 0xf8100000 0 0x100000>; no-map; }; oem_vm_mem: oem-vm-region@f8400000 { reg = <0 0xf8400000 0 0x4800000>; no-map; }; oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { reg = <0 0xfcc00000 0 0x4000>; no-map; }; oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { reg = <0 0xfcc04000 0 0x100000>; no-map; }; hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { reg = <0 0xfce00000 0 0x2900000>; no-map; }; hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { reg = <0 0xff700000 0 0x100000>; no-map; }; }; smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <2>; smp2p_adsp_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; smp2p_adsp_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupts-extended = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <5>; smp2p_cdsp_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; smp2p_cdsp_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-modem { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupts-extended = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <1>; smp2p_modem_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; smp2p_modem_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; ipa_smp2p_out: ipa-ap-to-modem { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; ipa_smp2p_in: ipa-modem-to-ap { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; soc: soc@0 { compatible = "simple-bus"; ranges = <0 0 0 0 0x10 0>; dma-ranges = <0 0 0 0 0x10 0>; #address-cells = <2>; #size-cells = <2>; gcc: clock-controller@100000 { compatible = "qcom,sm8550-gcc"; reg = <0 0x00100000 0 0x1f4200>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; clocks = <&bi_tcxo_div2>, <&sleep_clk>, <&pcie0_phy>, <&pcie1_phy QMP_PCIE_PIPE_CLK>, <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; ipcc: mailbox@408000 { compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; reg = <0 0x00408000 0 0x1000>; interrupts = ; interrupt-controller; #interrupt-cells = <3>; #mbox-cells = <2>; }; gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; reg = <0 0x00800000 0 0x60000>; interrupts = , , , , , , , , , , , ; dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; dma-coherent; status = "disabled"; }; qupv3_id_1: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x2000>; ranges; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x423 0>; dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; i2c8: i2c@880000 { compatible = "qcom,geni-i2c"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi8: spi@880000 { compatible = "qcom,geni-spi"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c9: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi9: spi@884000 { compatible = "qcom,geni-spi"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c10: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi10: spi@888000 { compatible = "qcom,geni-spi"; reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c11: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi11: spi@88c000 { compatible = "qcom,geni-spi"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c12: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi12: spi@890000 { compatible = "qcom,geni-spi"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c13: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi13: spi@894000 { compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; uart14: serial@898000 { compatible = "qcom,geni-uart"; reg = <0 0x898000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c15: i2c@89c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, <&gpi_dma2 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi15: spi@89c000 { compatible = "qcom,geni-spi"; reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, <&gpi_dma2 1 7 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; i2c_master_hub_0: geniqup@9c0000 { compatible = "qcom,geni-se-i2c-master-hub"; reg = <0x0 0x009c0000 0x0 0x2000>; clock-names = "s-ahb"; clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; i2c_hub_0: i2c@980000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0x0 0x00980000 0x0 0x4000>; clock-names = "se", "core"; clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c0_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c_hub_1: i2c@984000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0x0 0x00984000 0x0 0x4000>; clock-names = "se", "core"; clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c1_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c_hub_2: i2c@988000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0x0 0x00988000 0x0 0x4000>; clock-names = "se", "core"; clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c2_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c_hub_3: i2c@98c000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0x0 0x0098c000 0x0 0x4000>; clock-names = "se", "core"; clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c3_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c_hub_4: i2c@990000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0x0 0x00990000 0x0 0x4000>; clock-names = "se", "core"; clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c4_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c_hub_5: i2c@994000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00994000 0 0x4000>; clock-names = "se", "core"; clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c5_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c_hub_6: i2c@998000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00998000 0 0x4000>; clock-names = "se", "core"; clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c6_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c_hub_7: i2c@99c000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x0099c000 0 0x4000>; clock-names = "se", "core"; clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c7_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c_hub_8: i2c@9a0000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x009a0000 0 0x4000>; clock-names = "se", "core"; clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c8_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c_hub_9: i2c@9a4000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x009a4000 0 0x4000>; clock-names = "se", "core"; clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c9_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; gpi_dma1: dma-controller@a00000 { compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; reg = <0 0x00a00000 0 0x60000>; interrupts = , , , , , , , , , , , ; dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; dma-coherent; status = "disabled"; }; qupv3_id_0: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x2000>; ranges; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; iommus = <&apps_smmu 0xa3 0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; interconnect-names = "qup-core"; dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; i2c0: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi0: spi@a80000 { compatible = "qcom,geni-spi"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi1: spi@a84000 { compatible = "qcom,geni-spi"; reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi2: spi@a88000 { compatible = "qcom,geni-spi"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi3: spi@a8c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c4: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi4: spi@a90000 { compatible = "qcom,geni-spi"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c5: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_data_clk>; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi5: spi@a94000 { compatible = "qcom,geni-spi"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c6: i2c@a98000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a98000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_data_clk>; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi6: spi@a98000 { compatible = "qcom,geni-spi"; reg = <0 0x00a98000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; uart7: serial@a9c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x00a9c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_default>; interrupts = ; interconnect-names = "qup-core", "qup-config"; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; status = "disabled"; }; }; cnoc_main: interconnect@1500000 { compatible = "qcom,sm8550-cnoc-main"; reg = <0 0x01500000 0 0x13080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; config_noc: interconnect@1600000 { compatible = "qcom,sm8550-config-noc"; reg = <0 0x01600000 0 0x6200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1680000 { compatible = "qcom,sm8550-system-noc"; reg = <0 0x01680000 0 0x1d080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; pcie_noc: interconnect@16c0000 { compatible = "qcom,sm8550-pcie-anoc"; reg = <0 0x016c0000 0 0x12200>; #interconnect-cells = <2>; clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sm8550-aggre1-noc"; reg = <0 0x016e0000 0 0x14400>; #interconnect-cells = <2>; clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sm8550-aggre2-noc"; reg = <0 0x01700000 0 0x1e400>; #interconnect-cells = <2>; clocks = <&rpmhcc RPMH_IPA_CLK>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1780000 { compatible = "qcom,sm8550-mmss-noc"; reg = <0 0x01780000 0 0x5b800>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; rng: rng@10c3000 { compatible = "qcom,sm8550-trng", "qcom,trng"; reg = <0 0x010c3000 0 0x1000>; }; pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-sm8550"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, <0 0x60001000 0 0x1000>, <0 0x60100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; bus-range = <0x00 0xff>; dma-coherent; linux,pci-domain = <0>; num-lanes = <2>; interrupts = , , , , , , , ; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", "noc_aggr"; interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; msi-map = <0x0 &gic_its 0x1400 0x1>, <0x100 &gic_its 0x1401 0x1>; iommu-map = <0x0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; phy-names = "pciephy"; status = "disabled"; pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie0_phy: phy@1c06000 { compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; reg = <0 0x01c06000 0 0x2000>; clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&tcsr TCSR_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; power-domains = <&gcc PCIE_0_PHY_GDSC>; #clock-cells = <0>; clock-output-names = "pcie0_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; pcie1: pcie@1c08000 { device_type = "pci"; compatible = "qcom,pcie-sm8550"; reg = <0x0 0x01c08000 0x0 0x3000>, <0x0 0x40000000 0x0 0xf1d>, <0x0 0x40000f20 0x0 0xa8>, <0x0 0x40001000 0x0 0x1000>, <0x0 0x40100000 0x0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; bus-range = <0x00 0xff>; dma-coherent; linux,pci-domain = <1>; num-lanes = <2>; interrupts = , , , , , , , ; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", "noc_aggr", "cnoc_sf_axi"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; msi-map = <0x0 &gic_its 0x1480 0x1>, <0x100 &gic_its 0x1481 0x1>; iommu-map = <0x0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; reset-names = "pci", "link_down"; power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; phy-names = "pciephy"; status = "disabled"; pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; reg = <0x0 0x01c0e000 0x0 0x2000>; clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&tcsr TCSR_PCIE_1_CLKREF_EN>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; resets = <&gcc GCC_PCIE_1_PHY_BCR>, <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; reset-names = "phy", "phy_nocsr"; assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; power-domains = <&gcc PCIE_1_PHY_GDSC>; #clock-cells = <1>; clock-output-names = "pcie1_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; interrupts = ; #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; iommus = <&apps_smmu 0x480 0x0>, <&apps_smmu 0x481 0x0>; }; crypto: crypto@1dfa000 { compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; reg = <0x0 0x01dfa000 0x0 0x6000>; dmas = <&cryptobam 4>, <&cryptobam 5>; dma-names = "rx", "tx"; iommus = <&apps_smmu 0x480 0x0>, <&apps_smmu 0x481 0x0>; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "memory"; }; ufs_mem_phy: phy@1d80000 { compatible = "qcom,sm8550-qmp-ufs-phy"; reg = <0x0 0x01d80000 0x0 0x2000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&tcsr TCSR_UFS_CLKREF_EN>; clock-names = "ref", "ref_aux", "qref"; power-domains = <&gcc UFS_MEM_PHY_GDSC>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; ufs_mem_hc: ufs@1d84000 { compatible = "qcom,sm8550-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; interrupts = ; phys = <&ufs_mem_phy>; phy-names = "ufsphy"; lanes-per-direction = <2>; #reset-cells = <1>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; power-domains = <&gcc UFS_PHY_GDSC>; required-opps = <&rpmhpd_opp_nom>; iommus = <&apps_smmu 0x60 0x0>; dma-coherent; operating-points-v2 = <&ufs_opp_table>; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; interconnect-names = "ufs-ddr", "cpu-ufs"; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&tcsr TCSR_UFS_PAD_CLKREF_EN>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; qcom,ice = <&ice>; status = "disabled"; ufs_opp_table: opp-table { compatible = "operating-points-v2"; opp-75000000 { opp-hz = /bits/ 64 <75000000>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <75000000>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <0>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-150000000 { opp-hz = /bits/ 64 <150000000>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <150000000>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <0>; required-opps = <&rpmhpd_opp_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <300000000>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <0>; required-opps = <&rpmhpd_opp_nom>; }; }; }; ice: crypto@1d88000 { compatible = "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; #hwlock-cells = <1>; }; tcsr: clock-controller@1fc0000 { compatible = "qcom,sm8550-tcsr", "syscon"; reg = <0 0x01fc0000 0 0x30000>; clocks = <&rpmhcc RPMH_CXO_CLK>; #clock-cells = <1>; #reset-cells = <1>; }; gpu: gpu@3d00000 { compatible = "qcom,adreno-43050a01", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, <0x0 0x03d9e000 0x0 0x1000>, <0x0 0x03d61000 0x0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; interrupts = ; iommus = <&adreno_smmu 0 0x0>, <&adreno_smmu 1 0x0>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; #cooling-cells = <2>; status = "disabled"; zap-shader { memory-region = <&gpu_micro_code_mem>; }; /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; }; }; }; gmu: gmu@3d6a000 { compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; reg = <0x0 0x03d6a000 0x0 0x35000>, <0x0 0x03d50000 0x0 0x10000>, <0x0 0x0b280000 0x0 0x10000>; reg-names = "gmu", "rscc", "gmu_pdc"; interrupts = , ; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_HUB_CX_INT_CLK>, <&gpucc GPU_CC_DEMET_CLK>; clock-names = "ahb", "gmu", "cxo", "axi", "memnoc", "hub", "demet"; power-domains = <&gpucc GPU_CC_CX_GDSC>, <&gpucc GPU_CC_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5 0x0>; qcom,qmp = <&aoss_qmp>; operating-points-v2 = <&gmu_opp_table>; gmu_opp_table: opp-table { compatible = "operating-points-v2"; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-level = ; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-level = ; }; }; }; gpucc: clock-controller@3d90000 { compatible = "qcom,sm8550-gpucc"; reg = <0 0x03d90000 0 0xa000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; adreno_smmu: iommu@3da0000 { compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x03da0000 0x0 0x40000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = , , , , , , , , , , , , , , , , , , , , , , , , , ; clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>; clock-names = "hlos", "bus", "iface", "ahb"; power-domains = <&gpucc GPU_CC_CX_GDSC>; dma-coherent; }; ipa: ipa@3f40000 { compatible = "qcom,sm8550-ipa"; iommus = <&apps_smmu 0x4a0 0x0>, <&apps_smmu 0x4a2 0x0>; reg = <0 0x3f40000 0 0x10000>, <0 0x3f50000 0 0x5000>, <0 0x3e04000 0 0xfc000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", "gsi", "ipa-clock-query", "ipa-setup-ready"; clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; interconnect-names = "memory", "config"; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; status = "disabled"; }; remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8550-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd RPMHPD_CX>, <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&smp2p_modem_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "mpss"; qcom,remote-pid = <1>; }; }; lpass_wsa2macro: codec@6aa0000 { compatible = "qcom,sm8550-lpass-wsa-macro"; reg = <0 0x06aa0000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&lpass_vamacro>; clock-names = "mclk", "macro", "dcodec", "fsgen"; #clock-cells = <0>; clock-output-names = "wsa2-mclk"; #sound-dai-cells = <1>; }; swr3: soundwire@6ab0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ab0000 0 0x10000>; interrupts = ; clocks = <&lpass_wsa2macro>; clock-names = "iface"; label = "WSA2"; pinctrl-0 = <&wsa2_swr_active>; pinctrl-names = "default"; qcom,din-ports = <4>; qcom,dout-ports = <9>; qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; status = "disabled"; }; lpass_rxmacro: codec@6ac0000 { compatible = "qcom,sm8550-lpass-rx-macro"; reg = <0 0x06ac0000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&lpass_vamacro>; clock-names = "mclk", "macro", "dcodec", "fsgen"; #clock-cells = <0>; clock-output-names = "mclk"; #sound-dai-cells = <1>; }; swr1: soundwire@6ad0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ad0000 0 0x10000>; interrupts = ; clocks = <&lpass_rxmacro>; clock-names = "iface"; label = "RX"; pinctrl-0 = <&rx_swr_active>; pinctrl-names = "default"; qcom,din-ports = <1>; qcom,dout-ports = <11>; qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; status = "disabled"; }; lpass_txmacro: codec@6ae0000 { compatible = "qcom,sm8550-lpass-tx-macro"; reg = <0 0x06ae0000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&lpass_vamacro>; clock-names = "mclk", "macro", "dcodec", "fsgen"; #clock-cells = <0>; clock-output-names = "mclk"; #sound-dai-cells = <1>; }; lpass_wsamacro: codec@6b00000 { compatible = "qcom,sm8550-lpass-wsa-macro"; reg = <0 0x06b00000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&lpass_vamacro>; clock-names = "mclk", "macro", "dcodec", "fsgen"; #clock-cells = <0>; clock-output-names = "mclk"; #sound-dai-cells = <1>; }; swr0: soundwire@6b10000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06b10000 0 0x10000>; interrupts = ; clocks = <&lpass_wsamacro>; clock-names = "iface"; label = "WSA"; pinctrl-0 = <&wsa_swr_active>; pinctrl-names = "default"; qcom,din-ports = <4>; qcom,dout-ports = <9>; qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; status = "disabled"; }; swr2: soundwire@6d30000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06d30000 0 0x10000>; interrupts = , ; interrupt-names = "core", "wakeup"; clocks = <&lpass_txmacro>; clock-names = "iface"; label = "TX"; pinctrl-0 = <&tx_swr_active>; pinctrl-names = "default"; qcom,din-ports = <4>; qcom,dout-ports = <0>; qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; status = "disabled"; }; lpass_vamacro: codec@6d44000 { compatible = "qcom,sm8550-lpass-va-macro"; reg = <0 0x06d44000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; clock-names = "mclk", "macro", "dcodec"; #clock-cells = <0>; clock-output-names = "fsgen"; #sound-dai-cells = <1>; }; lpass_tlmm: pinctrl@6e80000 { compatible = "qcom,sm8550-lpass-lpi-pinctrl"; reg = <0 0x06e80000 0 0x20000>, <0 0x07250000 0 0x10000>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 23>; clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; clock-names = "core", "audio"; tx_swr_active: tx-swr-active-state { clk-pins { pins = "gpio0"; function = "swr_tx_clk"; drive-strength = <2>; slew-rate = <1>; bias-disable; }; data-pins { pins = "gpio1", "gpio2", "gpio14"; function = "swr_tx_data"; drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; }; rx_swr_active: rx-swr-active-state { clk-pins { pins = "gpio3"; function = "swr_rx_clk"; drive-strength = <2>; slew-rate = <1>; bias-disable; }; data-pins { pins = "gpio4", "gpio5"; function = "swr_rx_data"; drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; }; dmic01_default: dmic01-default-state { clk-pins { pins = "gpio6"; function = "dmic1_clk"; drive-strength = <8>; output-high; }; data-pins { pins = "gpio7"; function = "dmic1_data"; drive-strength = <8>; input-enable; }; }; dmic23_default: dmic23-default-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; drive-strength = <8>; output-high; }; data-pins { pins = "gpio9"; function = "dmic2_data"; drive-strength = <8>; input-enable; }; }; wsa_swr_active: wsa-swr-active-state { clk-pins { pins = "gpio10"; function = "wsa_swr_clk"; drive-strength = <2>; slew-rate = <1>; bias-disable; }; data-pins { pins = "gpio11"; function = "wsa_swr_data"; drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; }; wsa2_swr_active: wsa2-swr-active-state { clk-pins { pins = "gpio15"; function = "wsa2_swr_clk"; drive-strength = <2>; slew-rate = <1>; bias-disable; }; data-pins { pins = "gpio16"; function = "wsa2_swr_data"; drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; }; }; lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,sm8550-lpass-lpiaon-noc"; reg = <0 0x07400000 0 0x19080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; lpass_lpicx_noc: interconnect@7430000 { compatible = "qcom,sm8550-lpass-lpicx-noc"; reg = <0 0x07430000 0 0x3a200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,sm8550-lpass-ag-noc"; reg = <0 0x07e40000 0 0xe080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; sdhc_2: mmc@8804000 { compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x540 0>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; bus-width = <4>; dma-coherent; /* Forbid SDR104/SDR50 - broken hw! */ sdhci-caps-mask = <0x3 0>; status = "disabled"; sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { opp-hz = /bits/ 64 <19200000>; required-opps = <&rpmhpd_opp_min_svs>; }; opp-50000000 { opp-hz = /bits/ 64 <50000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-202000000 { opp-hz = /bits/ 64 <202000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; }; }; videocc: clock-controller@aaf0000 { compatible = "qcom,sm8550-videocc"; reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; cci0: cci@ac15000 { compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; reg = <0 0x0ac15000 0 0x1000>; interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, <&camcc CAM_CC_CCI_0_CLK>; clock-names = "camnoc_axi", "cpas_ahb", "cci"; pinctrl-0 = <&cci0_0_default &cci0_1_default>; pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; pinctrl-names = "default", "sleep"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; cci0_i2c0: i2c-bus@0 { reg = <0>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; cci0_i2c1: i2c-bus@1 { reg = <1>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; }; cci1: cci@ac16000 { compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; reg = <0 0x0ac16000 0 0x1000>; interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, <&camcc CAM_CC_CCI_1_CLK>; clock-names = "camnoc_axi", "cpas_ahb", "cci"; pinctrl-0 = <&cci1_0_default>; pinctrl-1 = <&cci1_0_sleep>; pinctrl-names = "default", "sleep"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; cci1_i2c0: i2c-bus@0 { reg = <0>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; }; cci2: cci@ac17000 { compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; reg = <0 0x0ac17000 0 0x1000>; interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, <&camcc CAM_CC_CCI_2_CLK>; clock-names = "camnoc_axi", "cpas_ahb", "cci"; pinctrl-0 = <&cci2_0_default &cci2_1_default>; pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; pinctrl-names = "default", "sleep"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; cci2_i2c0: i2c-bus@0 { reg = <0>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; cci2_i2c1: i2c-bus@1 { reg = <1>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; }; camcc: clock-controller@ade0000 { compatible = "qcom,sm8550-camcc"; reg = <0 0x0ade0000 0 0x20000>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; power-domains = <&rpmhpd SM8550_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; mdss: display-subsystem@ae00000 { compatible = "qcom,sm8550-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; interrupts = ; interrupt-controller; #interrupt-cells = <1>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; power-domains = <&dispcc MDSS_GDSC>; interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "mdp0-mem", "mdp1-mem"; iommus = <&apps_smmu 0x1c00 0x2>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8550-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; interrupt-parent = <&mdss>; interrupts = <0>; clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "nrt_bus", "iface", "lut", "core", "vsync"; power-domains = <&rpmhpd RPMHPD_MMCX>; assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dpu_intf1_out: endpoint { remote-endpoint = <&mdss_dsi0_in>; }; }; port@1 { reg = <1>; dpu_intf2_out: endpoint { remote-endpoint = <&mdss_dsi1_in>; }; }; port@2 { reg = <2>; dpu_intf0_out: endpoint { remote-endpoint = <&mdss_dp0_in>; }; }; }; mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-325000000 { opp-hz = /bits/ 64 <325000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-375000000 { opp-hz = /bits/ 64 <375000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-514000000 { opp-hz = /bits/ 64 <514000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss_dp0: displayport-controller@ae90000 { compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; reg = <0 0xae90000 0 0x200>, <0 0xae90200 0 0x200>, <0 0xae90400 0 0xc00>, <0 0xae91000 0 0x400>, <0 0xae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss_dp0_in: endpoint { remote-endpoint = <&dpu_intf0_out>; }; }; port@1 { reg = <1>; mdss_dp0_out: endpoint { remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; }; dp_opp_table: opp-table { compatible = "operating-points-v2"; opp-162000000 { opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs_d1>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>; clock-names = "byte", "byte_intf", "pixel", "core", "iface", "bus"; power-domains = <&rpmhpd RPMHPD_MMCX>; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&mdss_dsi_opp_table>; phys = <&mdss_dsi0_phy>; phy-names = "dsi"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; mdss_dsi0_out: endpoint { }; }; }; mdss_dsi_opp_table: opp-table { compatible = "operating-points-v2"; opp-187500000 { opp-hz = /bits/ 64 <187500000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-358000000 { opp-hz = /bits/ 64 <358000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; }; }; mdss_dsi0_phy: phy@ae95000 { compatible = "qcom,sm8550-dsi-phy-4nm"; reg = <0 0x0ae95000 0 0x200>, <0 0x0ae95200 0 0x280>, <0 0x0ae95500 0 0x400>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "ref"; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; mdss_dsi1: dsi@ae96000 { compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>; clock-names = "byte", "byte_intf", "pixel", "core", "iface", "bus"; power-domains = <&rpmhpd RPMHPD_MMCX>; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; operating-points-v2 = <&mdss_dsi_opp_table>; phys = <&mdss_dsi1_phy>; phy-names = "dsi"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss_dsi1_in: endpoint { remote-endpoint = <&dpu_intf2_out>; }; }; port@1 { reg = <1>; mdss_dsi1_out: endpoint { }; }; }; }; mdss_dsi1_phy: phy@ae97000 { compatible = "qcom,sm8550-dsi-phy-4nm"; reg = <0 0x0ae97000 0 0x200>, <0 0x0ae97200 0 0x280>, <0 0x0ae97500 0 0x400>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "ref"; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; }; dispcc: clock-controller@af00000 { compatible = "qcom,sm8550-dispcc"; reg = <0 0x0af00000 0 0x20000>; clocks = <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ <0>, <0>, /* dp2 */ <0>, <0>, /* dp3 */ <0>; power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8550-snps-eusb2-phy"; reg = <0x0 0x088e3000 0x0 0x154>; #phy-cells = <0>; clocks = <&tcsr TCSR_USB2_CLKREF_EN>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; status = "disabled"; }; usb_dp_qmpphy: phy@88e8000 { compatible = "qcom,sm8550-qmp-usb3-dp-phy"; reg = <0x0 0x088e8000 0x0 0x3000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", "usb3_pipe"; power-domains = <&gcc USB3_PHY_GDSC>; resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; #phy-cells = <1>; orientation-switch; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb_dp_qmpphy_out: endpoint { }; }; port@1 { reg = <1>; usb_dp_qmpphy_usb_ss_in: endpoint { remote-endpoint = <&usb_1_dwc3_ss>; }; }; port@2 { reg = <2>; usb_dp_qmpphy_dp_in: endpoint { remote-endpoint = <&mdss_dp0_out>; }; }; }; }; usb_1: usb@a6f8800 { compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; reg = <0x0 0x0a6f8800 0x0 0x400>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&tcsr TCSR_USB3_CLKREF_EN>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_PRIM_BCR>; interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; interconnect-names = "usb-ddr", "apps-usb"; status = "disabled"; usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0x0 0x0a600000 0x0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x40 0x0>; phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; snps,hird-threshold = /bits/ 8 <0x0>; snps,usb2-gadget-lpm-disable; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,is-utmi-l1-suspend; snps,usb3_lpm_capable; snps,usb2-lpm-disable; snps,has-lpm-erratum; tx-fifo-resize; dma-coherent; usb-role-switch; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb_1_dwc3_hs: endpoint { }; }; port@1 { reg = <1>; usb_1_dwc3_ss: endpoint { remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; }; }; pdc: interrupt-controller@b220000 { compatible = "qcom,sm8550-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>, <138 251 5>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; }; tsens0: thermal-sensor@c271000 { compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; reg = <0 0x0c271000 0 0x1000>, /* TM */ <0 0x0c222000 0 0x1000>; /* SROT */ #qcom,sensors = <16>; interrupts = , ; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; tsens1: thermal-sensor@c272000 { compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; reg = <0 0x0c272000 0 0x1000>, /* TM */ <0 0x0c223000 0 0x1000>; /* SROT */ #qcom,sensors = <16>; interrupts = , ; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; tsens2: thermal-sensor@c273000 { compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; reg = <0 0x0c273000 0 0x1000>, /* TM */ <0 0x0c224000 0 0x1000>; /* SROT */ #qcom,sensors = <16>; interrupts = , ; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; aoss_qmp: power-management@c300000 { compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupt-parent = <&ipcc>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; }; sram@c3f0000 { compatible = "qcom,rpmh-stats"; reg = <0 0x0c3f0000 0 0x400>; }; spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c400000 0 0x3000>, <0 0x0c500000 0 0x400000>, <0 0x0c440000 0 0x80000>, <0 0x0c4c0000 0 0x20000>, <0 0x0c42d000 0 0x4000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; qcom,bus-id = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; tlmm: pinctrl@f100000 { compatible = "qcom,sm8550-tlmm"; reg = <0 0x0f100000 0 0x300000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; cci0_0_default: cci0-0-default-state { sda-pins { pins = "gpio110"; function = "cci_i2c_sda"; drive-strength = <2>; bias-pull-up = <2200>; }; scl-pins { pins = "gpio111"; function = "cci_i2c_scl"; drive-strength = <2>; bias-pull-up = <2200>; }; }; cci0_0_sleep: cci0-0-sleep-state { sda-pins { pins = "gpio110"; function = "cci_i2c_sda"; drive-strength = <2>; bias-pull-down; }; scl-pins { pins = "gpio111"; function = "cci_i2c_scl"; drive-strength = <2>; bias-pull-down; }; }; cci0_1_default: cci0-1-default-state { sda-pins { pins = "gpio112"; function = "cci_i2c_sda"; drive-strength = <2>; bias-pull-up = <2200>; }; scl-pins { pins = "gpio113"; function = "cci_i2c_scl"; drive-strength = <2>; bias-pull-up = <2200>; }; }; cci0_1_sleep: cci0-1-sleep-state { sda-pins { pins = "gpio112"; function = "cci_i2c_sda"; drive-strength = <2>; bias-pull-down; }; scl-pins { pins = "gpio113"; function = "cci_i2c_scl"; drive-strength = <2>; bias-pull-down; }; }; cci1_0_default: cci1-0-default-state { sda-pins { pins = "gpio114"; function = "cci_i2c_sda"; drive-strength = <2>; bias-pull-up = <2200>; }; scl-pins { pins = "gpio115"; function = "cci_i2c_scl"; drive-strength = <2>; bias-pull-up = <2200>; }; }; cci1_0_sleep: cci1-0-sleep-state { sda-pins { pins = "gpio114"; function = "cci_i2c_sda"; drive-strength = <2>; bias-pull-down; }; scl-pins { pins = "gpio115"; function = "cci_i2c_scl"; drive-strength = <2>; bias-pull-down; }; }; cci2_0_default: cci2-0-default-state { sda-pins { pins = "gpio74"; function = "cci_i2c_sda"; drive-strength = <2>; bias-pull-up = <2200>; }; scl-pins { pins = "gpio75"; function = "cci_i2c_scl"; drive-strength = <2>; bias-pull-up = <2200>; }; }; cci2_0_sleep: cci2-0-sleep-state { sda-pins { pins = "gpio74"; function = "cci_i2c_sda"; drive-strength = <2>; bias-pull-down; }; scl-pins { pins = "gpio75"; function = "cci_i2c_scl"; drive-strength = <2>; bias-pull-down; }; }; cci2_1_default: cci2-1-default-state { sda-pins { pins = "gpio0"; function = "cci_i2c_sda"; drive-strength = <2>; bias-pull-up = <2200>; }; scl-pins { pins = "gpio1"; function = "cci_i2c_scl"; drive-strength = <2>; bias-pull-up = <2200>; }; }; cci2_1_sleep: cci2-1-sleep-state { sda-pins { pins = "gpio0"; function = "cci_i2c_sda"; drive-strength = <2>; bias-pull-down; }; scl-pins { pins = "gpio1"; function = "cci_i2c_scl"; drive-strength = <2>; bias-pull-down; }; }; hub_i2c0_data_clk: hub-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio16", "gpio17"; function = "i2chub0_se0"; drive-strength = <2>; bias-pull-up; }; hub_i2c1_data_clk: hub-i2c1-data-clk-state { /* SDA, SCL */ pins = "gpio18", "gpio19"; function = "i2chub0_se1"; drive-strength = <2>; bias-pull-up; }; hub_i2c2_data_clk: hub-i2c2-data-clk-state { /* SDA, SCL */ pins = "gpio20", "gpio21"; function = "i2chub0_se2"; drive-strength = <2>; bias-pull-up; }; hub_i2c3_data_clk: hub-i2c3-data-clk-state { /* SDA, SCL */ pins = "gpio22", "gpio23"; function = "i2chub0_se3"; drive-strength = <2>; bias-pull-up; }; hub_i2c4_data_clk: hub-i2c4-data-clk-state { /* SDA, SCL */ pins = "gpio4", "gpio5"; function = "i2chub0_se4"; drive-strength = <2>; bias-pull-up; }; hub_i2c5_data_clk: hub-i2c5-data-clk-state { /* SDA, SCL */ pins = "gpio6", "gpio7"; function = "i2chub0_se5"; drive-strength = <2>; bias-pull-up; }; hub_i2c6_data_clk: hub-i2c6-data-clk-state { /* SDA, SCL */ pins = "gpio8", "gpio9"; function = "i2chub0_se6"; drive-strength = <2>; bias-pull-up; }; hub_i2c7_data_clk: hub-i2c7-data-clk-state { /* SDA, SCL */ pins = "gpio10", "gpio11"; function = "i2chub0_se7"; drive-strength = <2>; bias-pull-up; }; hub_i2c8_data_clk: hub-i2c8-data-clk-state { /* SDA, SCL */ pins = "gpio206", "gpio207"; function = "i2chub0_se8"; drive-strength = <2>; bias-pull-up; }; hub_i2c9_data_clk: hub-i2c9-data-clk-state { /* SDA, SCL */ pins = "gpio84", "gpio85"; function = "i2chub0_se9"; drive-strength = <2>; bias-pull-up; }; pcie0_default_state: pcie0-default-state { perst-pins { pins = "gpio94"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; clkreq-pins { pins = "gpio95"; function = "pcie0_clk_req_n"; drive-strength = <2>; bias-pull-up; }; wake-pins { pins = "gpio96"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; }; pcie1_default_state: pcie1-default-state { perst-pins { pins = "gpio97"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; clkreq-pins { pins = "gpio98"; function = "pcie1_clk_req_n"; drive-strength = <2>; bias-pull-up; }; wake-pins { pins = "gpio99"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; }; qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio28", "gpio29"; function = "qup1_se0"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c1_data_clk: qup-i2c1-data-clk-state { /* SDA, SCL */ pins = "gpio32", "gpio33"; function = "qup1_se1"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c2_data_clk: qup-i2c2-data-clk-state { /* SDA, SCL */ pins = "gpio36", "gpio37"; function = "qup1_se2"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c3_data_clk: qup-i2c3-data-clk-state { /* SDA, SCL */ pins = "gpio40", "gpio41"; function = "qup1_se3"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c4_data_clk: qup-i2c4-data-clk-state { /* SDA, SCL */ pins = "gpio44", "gpio45"; function = "qup1_se4"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c5_data_clk: qup-i2c5-data-clk-state { /* SDA, SCL */ pins = "gpio52", "gpio53"; function = "qup1_se5"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c6_data_clk: qup-i2c6-data-clk-state { /* SDA, SCL */ pins = "gpio48", "gpio49"; function = "qup1_se6"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c8_data_clk: qup-i2c8-data-clk-state { scl-pins { pins = "gpio57"; function = "qup2_se0_l1_mira"; drive-strength = <2>; bias-pull-up = <2200>; }; sda-pins { pins = "gpio56"; function = "qup2_se0_l0_mira"; drive-strength = <2>; bias-pull-up = <2200>; }; }; qup_i2c9_data_clk: qup-i2c9-data-clk-state { /* SDA, SCL */ pins = "gpio60", "gpio61"; function = "qup2_se1"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c10_data_clk: qup-i2c10-data-clk-state { /* SDA, SCL */ pins = "gpio64", "gpio65"; function = "qup2_se2"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c11_data_clk: qup-i2c11-data-clk-state { /* SDA, SCL */ pins = "gpio68", "gpio69"; function = "qup2_se3"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c12_data_clk: qup-i2c12-data-clk-state { /* SDA, SCL */ pins = "gpio2", "gpio3"; function = "qup2_se4"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c13_data_clk: qup-i2c13-data-clk-state { /* SDA, SCL */ pins = "gpio80", "gpio81"; function = "qup2_se5"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_i2c15_data_clk: qup-i2c15-data-clk-state { /* SDA, SCL */ pins = "gpio72", "gpio106"; function = "qup2_se7"; drive-strength = <2>; bias-pull-up = <2200>; }; qup_spi0_cs: qup-spi0-cs-state { pins = "gpio31"; function = "qup1_se0"; drive-strength = <6>; bias-disable; }; qup_spi0_data_clk: qup-spi0-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio28", "gpio29", "gpio30"; function = "qup1_se0"; drive-strength = <6>; bias-disable; }; qup_spi1_cs: qup-spi1-cs-state { pins = "gpio35"; function = "qup1_se1"; drive-strength = <6>; bias-disable; }; qup_spi1_data_clk: qup-spi1-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio32", "gpio33", "gpio34"; function = "qup1_se1"; drive-strength = <6>; bias-disable; }; qup_spi2_cs: qup-spi2-cs-state { pins = "gpio39"; function = "qup1_se2"; drive-strength = <6>; bias-disable; }; qup_spi2_data_clk: qup-spi2-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio36", "gpio37", "gpio38"; function = "qup1_se2"; drive-strength = <6>; bias-disable; }; qup_spi3_cs: qup-spi3-cs-state { pins = "gpio43"; function = "qup1_se3"; drive-strength = <6>; bias-disable; }; qup_spi3_data_clk: qup-spi3-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio40", "gpio41", "gpio42"; function = "qup1_se3"; drive-strength = <6>; bias-disable; }; qup_spi4_cs: qup-spi4-cs-state { pins = "gpio47"; function = "qup1_se4"; drive-strength = <6>; bias-disable; }; qup_spi4_data_clk: qup-spi4-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio44", "gpio45", "gpio46"; function = "qup1_se4"; drive-strength = <6>; bias-disable; }; qup_spi5_cs: qup-spi5-cs-state { pins = "gpio55"; function = "qup1_se5"; drive-strength = <6>; bias-disable; }; qup_spi5_data_clk: qup-spi5-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio52", "gpio53", "gpio54"; function = "qup1_se5"; drive-strength = <6>; bias-disable; }; qup_spi6_cs: qup-spi6-cs-state { pins = "gpio51"; function = "qup1_se6"; drive-strength = <6>; bias-disable; }; qup_spi6_data_clk: qup-spi6-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio48", "gpio49", "gpio50"; function = "qup1_se6"; drive-strength = <6>; bias-disable; }; qup_spi8_cs: qup-spi8-cs-state { pins = "gpio59"; function = "qup2_se0_l3_mira"; drive-strength = <6>; bias-disable; }; qup_spi8_data_clk: qup-spi8-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio56", "gpio57", "gpio58"; function = "qup2_se0_l2_mira"; drive-strength = <6>; bias-disable; }; qup_spi9_cs: qup-spi9-cs-state { pins = "gpio63"; function = "qup2_se1"; drive-strength = <6>; bias-disable; }; qup_spi9_data_clk: qup-spi9-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio60", "gpio61", "gpio62"; function = "qup2_se1"; drive-strength = <6>; bias-disable; }; qup_spi10_cs: qup-spi10-cs-state { pins = "gpio67"; function = "qup2_se2"; drive-strength = <6>; bias-disable; }; qup_spi10_data_clk: qup-spi10-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio64", "gpio65", "gpio66"; function = "qup2_se2"; drive-strength = <6>; bias-disable; }; qup_spi11_cs: qup-spi11-cs-state { pins = "gpio71"; function = "qup2_se3"; drive-strength = <6>; bias-disable; }; qup_spi11_data_clk: qup-spi11-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio68", "gpio69", "gpio70"; function = "qup2_se3"; drive-strength = <6>; bias-disable; }; qup_spi12_cs: qup-spi12-cs-state { pins = "gpio119"; function = "qup2_se4"; drive-strength = <6>; bias-disable; }; qup_spi12_data_clk: qup-spi12-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio2", "gpio3", "gpio118"; function = "qup2_se4"; drive-strength = <6>; bias-disable; }; qup_spi13_cs: qup-spi13-cs-state { pins = "gpio83"; function = "qup2_se5"; drive-strength = <6>; bias-disable; }; qup_spi13_data_clk: qup-spi13-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio80", "gpio81", "gpio82"; function = "qup2_se5"; drive-strength = <6>; bias-disable; }; qup_spi15_cs: qup-spi15-cs-state { pins = "gpio75"; function = "qup2_se7"; drive-strength = <6>; bias-disable; }; qup_spi15_data_clk: qup-spi15-data-clk-state { /* MISO, MOSI, CLK */ pins = "gpio72", "gpio106", "gpio74"; function = "qup2_se7"; drive-strength = <6>; bias-disable; }; qup_uart7_default: qup-uart7-default-state { /* TX, RX */ pins = "gpio26", "gpio27"; function = "qup1_se7"; drive-strength = <2>; bias-disable; }; qup_uart14_default: qup-uart14-default-state { /* TX, RX */ pins = "gpio78", "gpio79"; function = "qup2_se6"; drive-strength = <2>; bias-pull-up; }; qup_uart14_cts_rts: qup-uart14-cts-rts-state { /* CTS, RTS */ pins = "gpio76", "gpio77"; function = "qup2_se6"; drive-strength = <2>; bias-pull-down; }; sdc2_sleep: sdc2-sleep-state { clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <2>; }; }; sdc2_default: sdc2-default-state { clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; }; apps_smmu: iommu@15000000 { compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ; dma-coherent; }; intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; reg = <0 0x17100000 0 0x10000>, /* GICD */ <0 0x17180000 0 0x200000>; /* GICR * 8 */ ranges; #interrupt-cells = <3>; interrupt-controller; #redistributor-regions = <1>; redistributor-stride = <0 0x40000>; interrupts = ; #address-cells = <2>; #size-cells = <2>; gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; reg = <0 0x17140000 0 0x20000>; msi-controller; #msi-cells = <1>; }; }; timer@17420000 { compatible = "arm,armv7-timer-mem"; reg = <0 0x17420000 0 0x1000>; ranges = <0 0 0 0x20000000>; #address-cells = <1>; #size-cells = <1>; frame@17421000 { reg = <0x17421000 0x1000>, <0x17422000 0x1000>; frame-number = <0>; interrupts = , ; }; frame@17423000 { reg = <0x17423000 0x1000>; frame-number = <1>; interrupts = ; status = "disabled"; }; frame@17425000 { reg = <0x17425000 0x1000>; frame-number = <2>; interrupts = ; status = "disabled"; }; frame@17427000 { reg = <0x17427000 0x1000>; frame-number = <3>; interrupts = ; status = "disabled"; }; frame@17429000 { reg = <0x17429000 0x1000>; frame-number = <4>; interrupts = ; status = "disabled"; }; frame@1742b000 { reg = <0x1742b000 0x1000>; frame-number = <5>; interrupts = ; status = "disabled"; }; frame@1742d000 { reg = <0x1742d000 0x1000>; frame-number = <6>; interrupts = ; status = "disabled"; }; }; apps_rsc: rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0 0x17a00000 0 0x10000>, <0 0x17a10000 0 0x10000>, <0 0x17a20000 0 0x10000>, <0 0x17a30000 0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; interrupts = , , ; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , , , ; power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; rpmhcc: clock-controller { compatible = "qcom,sm8550-rpmh-clk"; #clock-cells = <1>; clock-names = "xo"; clocks = <&xo_board>; }; rpmhpd: power-controller { compatible = "qcom,sm8550-rpmhpd"; #power-domain-cells = <1>; operating-points-v2 = <&rpmhpd_opp_table>; rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmhpd_opp_ret: opp-16 { opp-level = ; }; rpmhpd_opp_min_svs: opp-48 { opp-level = ; }; rpmhpd_opp_low_svs_d2: opp-52 { opp-level = ; }; rpmhpd_opp_low_svs_d1: opp-56 { opp-level = ; }; rpmhpd_opp_low_svs_d0: opp-60 { opp-level = ; }; rpmhpd_opp_low_svs: opp-64 { opp-level = ; }; rpmhpd_opp_low_svs_l1: opp-80 { opp-level = ; }; rpmhpd_opp_svs: opp-128 { opp-level = ; }; rpmhpd_opp_svs_l0: opp-144 { opp-level = ; }; rpmhpd_opp_svs_l1: opp-192 { opp-level = ; }; rpmhpd_opp_nom: opp-256 { opp-level = ; }; rpmhpd_opp_nom_l1: opp-320 { opp-level = ; }; rpmhpd_opp_nom_l2: opp-336 { opp-level = ; }; rpmhpd_opp_turbo: opp-384 { opp-level = ; }; rpmhpd_opp_turbo_l1: opp-416 { opp-level = ; }; }; }; }; cpufreq_hw: cpufreq@17d91000 { compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x17d91000 0 0x1000>, <0 0x17d92000 0 0x1000>, <0 0x17d93000 0 0x1000>; reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; interrupts = , , ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; #clock-cells = <1>; }; pmu@24091000 { compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>; interrupts = ; interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; operating-points-v2 = <&llcc_bwmon_opp_table>; llcc_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; opp-0 { opp-peak-kBps = <2086000>; }; opp-1 { opp-peak-kBps = <2929000>; }; opp-2 { opp-peak-kBps = <5931000>; }; opp-3 { opp-peak-kBps = <6515000>; }; opp-4 { opp-peak-kBps = <7980000>; }; opp-5 { opp-peak-kBps = <10437000>; }; opp-6 { opp-peak-kBps = <12157000>; }; opp-7 { opp-peak-kBps = <14060000>; }; opp-8 { opp-peak-kBps = <16113000>; }; }; }; pmu@240b6400 { compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b6400 0 0x600>; interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; operating-points-v2 = <&cpu_bwmon_opp_table>; cpu_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; opp-0 { opp-peak-kBps = <4577000>; }; opp-1 { opp-peak-kBps = <7110000>; }; opp-2 { opp-peak-kBps = <9155000>; }; opp-3 { opp-peak-kBps = <12298000>; }; opp-4 { opp-peak-kBps = <14236000>; }; opp-5 { opp-peak-kBps = <16265000>; }; }; }; gem_noc: interconnect@24100000 { compatible = "qcom,sm8550-gem-noc"; reg = <0 0x24100000 0 0xbb800>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system-cache-controller@25000000 { compatible = "qcom,sm8550-llcc"; reg = <0 0x25000000 0 0x200000>, <0 0x25200000 0 0x200000>, <0 0x25400000 0 0x200000>, <0 0x25600000 0 0x200000>, <0 0x25800000 0 0x200000>, <0 0x25a00000 0 0x200000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", "llcc_broadcast_base", "llcc_broadcast_and_base"; interrupts = ; }; remoteproc_adsp: remoteproc@30000000 { compatible = "qcom,sm8550-adsp-pas"; reg = <0x0 0x30000000 0x0 0x100>; interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd RPMHPD_LCX>, <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&smp2p_adsp_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; remoteproc_adsp_glink: glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "lpass"; qcom,remote-pid = <2>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x1003 0x80>, <&apps_smmu 0x1063 0x0>; dma-coherent; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x1004 0x80>, <&apps_smmu 0x1064 0x0>; dma-coherent; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x1005 0x80>, <&apps_smmu 0x1065 0x0>; dma-coherent; }; compute-cb@6 { compatible = "qcom,fastrpc-compute-cb"; reg = <6>; iommus = <&apps_smmu 0x1006 0x80>, <&apps_smmu 0x1066 0x0>; dma-coherent; }; compute-cb@7 { compatible = "qcom,fastrpc-compute-cb"; reg = <7>; iommus = <&apps_smmu 0x1007 0x80>, <&apps_smmu 0x1067 0x0>; dma-coherent; }; }; gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; qcom,domain = ; qcom,intents = <512 20>; #address-cells = <1>; #size-cells = <0>; q6apm: service@1 { compatible = "qcom,q6apm"; reg = ; #sound-dai-cells = <0>; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; q6apmdai: dais { compatible = "qcom,q6apm-dais"; iommus = <&apps_smmu 0x1001 0x80>, <&apps_smmu 0x1061 0x0>; }; q6apmbedai: bedais { compatible = "qcom,q6apm-lpass-dais"; #sound-dai-cells = <1>; }; }; q6prm: service@2 { compatible = "qcom,q6prm"; reg = ; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; q6prmcc: clock-controller { compatible = "qcom,q6prm-lpass-clocks"; #clock-cells = <2>; }; }; }; }; }; nsp_noc: interconnect@320c0000 { compatible = "qcom,sm8550-nsp-noc"; reg = <0 0x320c0000 0 0xe080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; remoteproc_cdsp: remoteproc@32300000 { compatible = "qcom,sm8550-cdsp-pas"; reg = <0x0 0x32300000 0x0 0x1400000>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd RPMHPD_CX>, <&rpmhpd RPMHPD_MXC>, <&rpmhpd RPMHPD_NSP>; power-domain-names = "cx", "mxc", "nsp"; interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&smp2p_cdsp_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "cdsp"; qcom,remote-pid = <5>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; compute-cb@1 { compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x1961 0x0>, <&apps_smmu 0x0c01 0x20>, <&apps_smmu 0x19c1 0x10>; dma-coherent; }; compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x1962 0x0>, <&apps_smmu 0x0c02 0x20>, <&apps_smmu 0x19c2 0x10>; dma-coherent; }; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x1963 0x0>, <&apps_smmu 0x0c03 0x20>, <&apps_smmu 0x19c3 0x10>; dma-coherent; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x1964 0x0>, <&apps_smmu 0x0c04 0x20>, <&apps_smmu 0x19c4 0x10>; dma-coherent; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x1965 0x0>, <&apps_smmu 0x0c05 0x20>, <&apps_smmu 0x19c5 0x10>; dma-coherent; }; compute-cb@6 { compatible = "qcom,fastrpc-compute-cb"; reg = <6>; iommus = <&apps_smmu 0x1966 0x0>, <&apps_smmu 0x0c06 0x20>, <&apps_smmu 0x19c6 0x10>; dma-coherent; }; compute-cb@7 { compatible = "qcom,fastrpc-compute-cb"; reg = <7>; iommus = <&apps_smmu 0x1967 0x0>, <&apps_smmu 0x0c07 0x20>, <&apps_smmu 0x19c7 0x10>; dma-coherent; }; compute-cb@8 { compatible = "qcom,fastrpc-compute-cb"; reg = <8>; iommus = <&apps_smmu 0x1968 0x0>, <&apps_smmu 0x0c08 0x20>, <&apps_smmu 0x19c8 0x10>; dma-coherent; }; /* note: secure cb9 in downstream */ }; }; }; }; thermal-zones { aoss0-thermal { thermal-sensors = <&tsens0 0>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; cpuss0-thermal { thermal-sensors = <&tsens0 1>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; cpuss1-thermal { thermal-sensors = <&tsens0 2>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; cpuss2-thermal { thermal-sensors = <&tsens0 3>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; cpuss3-thermal { thermal-sensors = <&tsens0 4>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; cpu3-top-thermal { thermal-sensors = <&tsens0 5>; trips { cpu3_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu3_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu3_top_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu3-bottom-thermal { thermal-sensors = <&tsens0 6>; trips { cpu3_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu3_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu3_bottom_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu4-top-thermal { thermal-sensors = <&tsens0 7>; trips { cpu4_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu4_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu4_top_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu4-bottom-thermal { thermal-sensors = <&tsens0 8>; trips { cpu4_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu4_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu4_bottom_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu5-top-thermal { thermal-sensors = <&tsens0 9>; trips { cpu5_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu5_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu5_top_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu5-bottom-thermal { thermal-sensors = <&tsens0 10>; trips { cpu5_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu5_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu5_bottom_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu6-top-thermal { thermal-sensors = <&tsens0 11>; trips { cpu6_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu6_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu6_top_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu6-bottom-thermal { thermal-sensors = <&tsens0 12>; trips { cpu6_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu6_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu6_bottom_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu7-top-thermal { thermal-sensors = <&tsens0 13>; trips { cpu7_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu7_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu7_top_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu7-middle-thermal { thermal-sensors = <&tsens0 14>; trips { cpu7_middle_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu7_middle_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu7_middle_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu7-bottom-thermal { thermal-sensors = <&tsens0 15>; trips { cpu7_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu7_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu7_bottom_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; aoss1-thermal { thermal-sensors = <&tsens1 0>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; cpu0-thermal { thermal-sensors = <&tsens1 1>; trips { cpu0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu0_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu0_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu1-thermal { thermal-sensors = <&tsens1 2>; trips { cpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu1_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu1_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu2-thermal { thermal-sensors = <&tsens1 3>; trips { cpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu2_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu2_crit: cpu-critical { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cdsp0-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 4>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; thermal-hal-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; cdsp0_junction_config: junction-config { temperature = <95000>; hysteresis = <5000>; type = "passive"; }; }; }; cdsp1-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 5>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; thermal-hal-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; cdsp1_junction_config: junction-config { temperature = <95000>; hysteresis = <5000>; type = "passive"; }; }; }; cdsp2-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 6>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; thermal-hal-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; cdsp2_junction_config: junction-config { temperature = <95000>; hysteresis = <5000>; type = "passive"; }; }; }; cdsp3-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 7>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; thermal-hal-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; cdsp3_junction_config: junction-config { temperature = <95000>; hysteresis = <5000>; type = "passive"; }; }; }; video-thermal { thermal-sensors = <&tsens1 8>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; mem-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens1 9>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; ddr_config0: ddr0-config { temperature = <90000>; hysteresis = <5000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; modem0-thermal { thermal-sensors = <&tsens1 10>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; mdmss0_config0: mdmss0-config0 { temperature = <102000>; hysteresis = <3000>; type = "passive"; }; mdmss0_config1: mdmss0-config1 { temperature = <105000>; hysteresis = <3000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; modem1-thermal { thermal-sensors = <&tsens1 11>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; mdmss1_config0: mdmss1-config0 { temperature = <102000>; hysteresis = <3000>; type = "passive"; }; mdmss1_config1: mdmss1-config1 { temperature = <105000>; hysteresis = <3000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; modem2-thermal { thermal-sensors = <&tsens1 12>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; mdmss2_config0: mdmss2-config0 { temperature = <102000>; hysteresis = <3000>; type = "passive"; }; mdmss2_config1: mdmss2-config1 { temperature = <105000>; hysteresis = <3000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; modem3-thermal { thermal-sensors = <&tsens1 13>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; mdmss3_config0: mdmss3-config0 { temperature = <102000>; hysteresis = <3000>; type = "passive"; }; mdmss3_config1: mdmss3-config1 { temperature = <105000>; hysteresis = <3000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; camera0-thermal { thermal-sensors = <&tsens1 14>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; camera1-thermal { thermal-sensors = <&tsens1 15>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; aoss2-thermal { thermal-sensors = <&tsens2 0>; trips { thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-config { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; gpuss-0-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 1>; cooling-maps { map0 { trip = <&gpu0_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu0_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; gpuss-1-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 2>; cooling-maps { map0 { trip = <&gpu1_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu1_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; gpuss-2-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 3>; cooling-maps { map0 { trip = <&gpu2_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu2_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; gpuss-3-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 4>; cooling-maps { map0 { trip = <&gpu3_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu3_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; gpuss-4-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 5>; cooling-maps { map0 { trip = <&gpu4_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu4_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; gpuss-5-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 6>; cooling-maps { map0 { trip = <&gpu5_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu5_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; gpuss-6-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 7>; cooling-maps { map0 { trip = <&gpu6_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu6_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; gpuss-7-thermal { polling-delay-passive = <10>; thermal-sensors = <&tsens2 8>; cooling-maps { map0 { trip = <&gpu7_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu7_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; };