// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2015-2016 Freescale Semiconductor, Inc.
 * Copyright 2016-2018 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x80000000 0x00010000;

/ {
	compatible = "fsl,s32v234";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster0_l2_cache>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster0_l2_cache>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster1_l2_cache>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster1_l2_cache>;
		};

		cluster0_l2_cache: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};

		cluster1_l2_cache: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>;
		/* clock-frequency might be modified by u-boot, depending on the
		 * chip version.
		 */
		clock-frequency = <10000000>;
	};

	gic: interrupt-controller@7d001000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x7d001000 0 0x1000>,
		      <0 0x7d002000 0 0x2000>,
		      <0 0x7d004000 0 0x2000>,
		      <0 0x7d006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		aips0: bus@40000000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			reg = <0x0 0x40000000 0x0 0x7d000>;
			ranges;

			uart0: serial@40053000 {
				compatible = "fsl,s32v234-linflexuart";
				reg = <0x0 0x40053000 0x0 0x1000>;
				interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};
		};

		aips1: bus@40080000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			reg = <0x0 0x40080000 0x0 0x70000>;
			ranges;

			uart1: serial@400bc000 {
				compatible = "fsl,s32v234-linflexuart";
				reg = <0x0 0x400bc000 0x0 0x1000>;
				interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};
		};
	};
};