// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright 2021-2024 NXP
 *
 * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
 *          Ciprian Costea <ciprianmarian.costea@nxp.com>
 *          Andra-Teodora Ilie <andra.ilie@nxp.com>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "nxp,s32g3";
	interrupt-parent = <&gic>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};

				core1 {
					cpu = <&cpu5>;
				};

				core2 {
					cpu = <&cpu6>;
				};

				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&dfs 0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			clocks = <&dfs 0>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			enable-method = "psci";
			clocks = <&dfs 0>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			enable-method = "psci";
			clocks = <&dfs 0>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
			clocks = <&dfs 0>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
			clocks = <&dfs 0>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			enable-method = "psci";
			clocks = <&dfs 0>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			enable-method = "psci";
			clocks = <&dfs 0>;
		};
	};

	firmware {
		scmi: scmi {
			compatible = "arm,scmi-smc";
			shmem = <&scmi_shmem>;
			arm,smc-id = <0xc20000fe>;
			#address-cells = <1>;
			#size-cells = <0>;

			dfs: protocol@13 {
				reg = <0x13>;
				#clock-cells = <1>;
			};

			clks: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};
		};

		psci: psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};


	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	reserved-memory  {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		scmi_shmem: shm@d0000000 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0xd0000000 0x0 0x80>;
			no-map;
		};
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0x80000000>;

		pinctrl: pinctrl@4009c240 {
			compatible = "nxp,s32g2-siul2-pinctrl";
				/* MSCR0-MSCR101 registers on siul2_0 */
			reg = <0x4009c240 0x198>,
				/* MSCR112-MSCR122 registers on siul2_1 */
			      <0x44010400 0x2c>,
				/* MSCR144-MSCR190 registers on siul2_1 */
			      <0x44010480 0xbc>,
				/* IMCR0-IMCR83 registers on siul2_0 */
			      <0x4009ca40 0x150>,
				/* IMCR119-IMCR397 registers on siul2_1 */
			      <0x44010c1c 0x45c>,
				/* IMCR430-IMCR495 registers on siul2_1 */
			      <0x440110f8 0x108>;

			jtag_pins: jtag-pins {
				jtag-grp0 {
					pinmux = <0x0>;
					input-enable;
					bias-pull-up;
					slew-rate = <166>;
				};

				jtag-grp1 {
					pinmux = <0x11>;
					slew-rate = <166>;
				};

				jtag-grp2 {
					pinmux = <0x40>;
					input-enable;
					bias-pull-down;
					slew-rate = <166>;
				};

				jtag-grp3 {
					pinmux = <0x23c0>,
						 <0x23d0>,
						 <0x2320>;
				};

				jtag-grp4 {
					pinmux = <0x51>;
					input-enable;
					bias-pull-up;
					slew-rate = <166>;
				};
			};
		};

		uart0: serial@401c8000 {
			compatible = "nxp,s32g3-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x401c8000 0x3000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		uart1: serial@401cc000 {
			compatible = "nxp,s32g3-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x401cc000 0x3000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		uart2: serial@402bc000 {
			compatible = "nxp,s32g3-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x402bc000 0x3000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		usdhc0: mmc@402f0000 {
			compatible = "nxp,s32g3-usdhc",
				     "nxp,s32g2-usdhc";
			reg = <0x402f0000 0x1000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 32>,
				 <&clks 31>,
				 <&clks 33>;
			clock-names = "ipg", "ahb", "per";
			status = "disabled";
		};

		gic: interrupt-controller@50800000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x50800000 0x10000>,
			      <0x50900000 0x200000>,
			      <0x50400000 0x2000>,
			      <0x50410000 0x2000>,
			      <0x50420000 0x2000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
		arm,no-tick-in-suspend;
	};
};