// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&intc>;

	chosen { };

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			compatible = "arm,cortex-a7";
			enable-method = "qcom,msm8226-smp";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			clocks = <&apcs>;
			operating-points-v2 = <&cpu_opp_table>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			#cooling-cells = <2>;
		};

		CPU1: cpu@1 {
			compatible = "arm,cortex-a7";
			enable-method = "qcom,msm8226-smp";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			clocks = <&apcs>;
			operating-points-v2 = <&cpu_opp_table>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			#cooling-cells = <2>;
		};

		CPU2: cpu@2 {
			compatible = "arm,cortex-a7";
			enable-method = "qcom,msm8226-smp";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			clocks = <&apcs>;
			operating-points-v2 = <&cpu_opp_table>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			#cooling-cells = <2>;
		};

		CPU3: cpu@3 {
			compatible = "arm,cortex-a7";
			enable-method = "qcom,msm8226-smp";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			clocks = <&apcs>;
			operating-points-v2 = <&cpu_opp_table>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			#cooling-cells = <2>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-msm8226", "qcom,scm";
			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
			clock-names = "core", "bus", "iface";
		};
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	cpu_opp_table: opp-table-cpu {
		compatible = "operating-points-v2";
		opp-shared;

		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
		};

		opp-384000000 {
			opp-hz = /bits/ 64 <384000000>;
		};

		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
		};

		opp-787200000 {
			opp-hz = /bits/ 64 <787200000>;
		};

		/* Higher CPU frequencies need speedbin support */
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

	rpm: remoteproc {
		compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc";

		master-stats {
			compatible = "qcom,rpm-master-stats";
			qcom,rpm-msg-ram = <&apss_master_stats>,
					   <&mpss_master_stats>,
					   <&lpss_master_stats>,
					   <&pronto_master_stats>;
			qcom,master-names = "APSS",
					    "MPSS",
					    "LPSS",
					    "PRONTO";
		};

		smd-edge {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			mboxes = <&apcs 0>;
			qcom,smd-edge = <15>;

			rpm_requests: rpm-requests {
				compatible = "qcom,rpm-msm8226", "qcom,smd-rpm";
				qcom,smd-channels = "rpm_requests";

				rpmcc: clock-controller {
					compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc";
					#clock-cells = <1>;
					clocks = <&xo_board>;
					clock-names = "xo";
				};

				rpmpd: power-controller {
					compatible = "qcom,msm8226-rpmpd";
					#power-domain-cells = <1>;
					operating-points-v2 = <&rpmpd_opp_table>;

					rpmpd_opp_table: opp-table {
						compatible = "operating-points-v2";

						rpmpd_opp_ret: opp1 {
							opp-level = <1>;
						};
						rpmpd_opp_svs_krait: opp2 {
							opp-level = <2>;
						};
						rpmpd_opp_svs_soc: opp3 {
							opp-level = <3>;
						};
						rpmpd_opp_nom: opp4 {
							opp-level = <4>;
						};
						rpmpd_opp_turbo: opp5 {
							opp-level = <5>;
						};
						rpmpd_opp_super_turbo: opp6 {
							opp-level = <6>;
						};
					};
				};
			};
		};
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_region: smem@3000000 {
			reg = <0x3000000 0x100000>;
			no-map;
		};

		adsp_region: adsp@dc00000 {
			reg = <0x0dc00000 0x1900000>;
			no-map;
		};
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_region>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;

		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apcs 10>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		apcs: mailbox@f9011000 {
			compatible = "qcom,msm8226-apcs-kpss-global",
				     "qcom,msm8916-apcs-kpss-global", "syscon";
			reg = <0xf9011000 0x1000>;
			#mbox-cells = <1>;
			clocks = <&a7pll>, <&gcc GPLL0_VOTE>;
			clock-names = "pll", "aux";
			#clock-cells = <0>;
		};

		a7pll: clock@f9016000 {
			compatible = "qcom,msm8226-a7pll";
			reg = <0xf9016000 0x40>;
			#clock-cells = <0>;
			clocks = <&xo_board>;
			clock-names = "xo";
			operating-points-v2 = <&a7pll_opp_table>;

			a7pll_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-768000000 {
					opp-hz = /bits/ 64 <768000000>;
				};

				opp-787200000 {
					opp-hz = /bits/ 64 <787200000>;
				};

				opp-998400000 {
					opp-hz = /bits/ 64 <998400000>;
				};

				opp-1094400000 {
					opp-hz = /bits/ 64 <1094400000>;
				};

				opp-1190400000 {
					opp-hz = /bits/ 64 <1190400000>;
				};

				opp-1305600000 {
					opp-hz = /bits/ 64 <1305600000>;
				};

				opp-1344000000 {
					opp-hz = /bits/ 64 <1344000000>;
				};

				opp-1401600000 {
					opp-hz = /bits/ 64 <1401600000>;
				};

				opp-1497600000 {
					opp-hz = /bits/ 64 <1497600000>;
				};

				opp-1593600000 {
					opp-hz = /bits/ 64 <1593600000>;
				};

				opp-1689600000 {
					opp-hz = /bits/ 64 <1689600000>;
				};

				opp-1785600000 {
					opp-hz = /bits/ 64 <1785600000>;
				};
			};
		};

		saw_l2: power-manager@f9012000 {
			compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2";
			reg = <0xf9012000 0x1000>;
		};

		watchdog@f9017000 {
			compatible = "qcom,apss-wdt-msm8226", "qcom,kpss-wdt";
			reg = <0xf9017000 0x1000>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sleep_clk>;
		};

		timer@f9020000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		acc0: power-manager@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
		};

		saw0: power-manager@f9089000 {
			compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>;
		};

		acc1: power-manager@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
		};

		saw1: power-manager@f9099000 {
			compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>;
		};

		acc2: power-manager@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
		};

		saw2: power-manager@f90a9000 {
			compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>;
		};

		acc3: power-manager@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
		};

		saw3: power-manager@f90b9000 {
			compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>;
		};

		sdhc_1: mmc@f9824900 {
			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc", "core";
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>,
				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
			clock-names = "iface", "core", "xo";
			pinctrl-names = "default";
			pinctrl-0 = <&sdhc1_default_state>;
			status = "disabled";
		};

		sdhc_3: mmc@f9864900 {
			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
			reg-names = "hc", "core";
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC3_AHB_CLK>,
				 <&gcc GCC_SDCC3_APPS_CLK>,
				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
			clock-names = "iface", "core", "xo";
			pinctrl-names = "default";
			pinctrl-0 = <&sdhc3_default_state>;
			status = "disabled";
		};

		sdhc_2: mmc@f98a4900 {
			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc", "core";
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
			clock-names = "iface", "core", "xo";
			pinctrl-names = "default";
			pinctrl-0 = <&sdhc2_default_state>;
			status = "disabled";
		};

		blsp1_uart1: serial@f991d000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991d000 0x1000>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart2: serial@f991e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991e000 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core",
				      "iface";
			status = "disabled";
		};

		blsp1_uart3: serial@f991f000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991f000 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart4: serial@f9920000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf9920000 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_i2c1: i2c@f9923000 {
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9923000 0x1000>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c1_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c2: i2c@f9924000 {
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9924000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c2_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c3: i2c@f9925000 {
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9925000 0x1000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c3_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c4: i2c@f9926000 {
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9926000 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c4_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c5: i2c@f9927000 {
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9927000 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c5_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c6: i2c@f9928000 {
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9928000 0x1000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core",
				      "iface";
			pinctrl-0 = <&blsp1_i2c6_pins>;
			pinctrl-names = "default";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		usb: usb@f9a55000 {
			compatible = "qcom,ci-hdrc";
			reg = <0xf9a55000 0x200>,
			      <0xf9a55200 0x200>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
			clock-names = "iface", "core";
			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
			assigned-clock-rates = <75000000>;
			resets = <&gcc GCC_USB_HS_BCR>;
			reset-names = "core";
			phy_type = "ulpi";
			dr_mode = "otg";
			hnp-disable;
			srp-disable;
			adp-disable;
			ahb-burst-config = <0>;
			phy-names = "usb-phy";
			phys = <&usb_hs_phy>;
			status = "disabled";
			#reset-cells = <1>;

			ulpi {
				usb_hs_phy: phy {
					compatible = "qcom,usb-hs-phy-msm8226",
						     "qcom,usb-hs-phy";
					#phy-cells = <0>;
					clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
						 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
					clock-names = "ref", "sleep";
					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
					reset-names = "phy", "por";
					qcom,init-seq = /bits/ 8 <0x0 0x44
						0x1 0x68 0x2 0x24 0x3 0x13>;
				};
			};
		};

		rng@f9bff000 {
			compatible = "qcom,prng";
			reg = <0xf9bff000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		sram@fc190000 {
			compatible = "qcom,msm8226-rpm-stats";
			reg = <0xfc190000 0x10000>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8226";
			reg = <0xfc400000 0x4000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;

			clocks = <&xo_board>,
				 <&sleep_clk>;
			clock-names = "xo",
				      "sleep_clk";
		};

		rpm_msg_ram: sram@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0xfc428000 0x4000>;

			apss_master_stats: sram@150 {
				reg = <0x150 0x14>;
			};

			mpss_master_stats: sram@b50 {
				reg = <0xb50 0x14>;
			};

			lpss_master_stats: sram@1550 {
				reg = <0x1550 0x14>;
			};

			pronto_master_stats: sram@1f50 {
				reg = <0x1f50 0x14>;
			};
		};

		tsens: thermal-sensor@fc4a9000 {
			compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1";
			reg = <0xfc4a9000 0x1000>, /* TM */
			      <0xfc4a8000 0x1000>; /* SROT */
			nvmem-cells = <&tsens_mode>,
				      <&tsens_base1>, <&tsens_base2>,
				      <&tsens_s0_p1>, <&tsens_s0_p2>,
				      <&tsens_s1_p1>, <&tsens_s1_p2>,
				      <&tsens_s2_p1>, <&tsens_s2_p2>,
				      <&tsens_s3_p1>, <&tsens_s3_p2>,
				      <&tsens_s4_p1>, <&tsens_s4_p2>,
				      <&tsens_s5_p1>, <&tsens_s5_p2>,
				      <&tsens_s6_p1>, <&tsens_s6_p2>;
			nvmem-cell-names = "mode",
					   "base1", "base2",
					   "s0_p1", "s0_p2",
					   "s1_p1", "s1_p2",
					   "s2_p1", "s2_p2",
					   "s3_p1", "s3_p2",
					   "s4_p1", "s4_p2",
					   "s5_p1", "s5_p2",
					   "s6_p1", "s6_p2";
			#qcom,sensors = <6>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow";
			#thermal-sensor-cells = <1>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		qfprom: efuse@fc4bc000 {
			compatible = "qcom,msm8226-qfprom", "qcom,qfprom";
			reg = <0xfc4bc000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			tsens_base1: base1@1c1 {
				reg = <0x1c1 0x2>;
				bits = <5 8>;
			};

			tsens_s0_p1: s0-p1@1c2 {
				reg = <0x1c2 0x2>;
				bits = <5 6>;
			};

			tsens_s1_p1: s1-p1@1c4 {
				reg = <0x1c4 0x1>;
				bits = <0 6>;
			};

			tsens_s2_p1: s2-p1@1c4 {
				reg = <0x1c4 0x2>;
				bits = <6 6>;
			};

			tsens_s3_p1: s3-p1@1c5 {
				reg = <0x1c5 0x2>;
				bits = <4 6>;
			};

			tsens_s4_p1: s4-p1@1c6 {
				reg = <0x1c6 0x1>;
				bits = <2 6>;
			};

			tsens_s5_p1: s5-p1@1c7 {
				reg = <0x1c7 0x1>;
				bits = <0 6>;
			};

			tsens_s6_p1: s6-p1@1ca {
				reg = <0x1ca 0x2>;
				bits = <4 6>;
			};

			tsens_base2: base2@1cc {
				reg = <0x1cc 0x1>;
				bits = <0 8>;
			};

			tsens_s0_p2: s0-p2@1cd {
				reg = <0x1cd 0x1>;
				bits = <0 6>;
			};

			tsens_s1_p2: s1-p2@1cd {
				reg = <0x1cd 0x2>;
				bits = <6 6>;
			};

			tsens_s2_p2: s2-p2@1ce {
				reg = <0x1ce 0x2>;
				bits = <4 6>;
			};

			tsens_s3_p2: s3-p2@1cf {
				reg = <0x1cf 0x1>;
				bits = <2 6>;
			};

			tsens_s4_p2: s4-p2@446 {
				reg = <0x446 0x2>;
				bits = <4 6>;
			};

			tsens_s5_p2: s5-p2@447 {
				reg = <0x447 0x1>;
				bits = <2 6>;
			};

			tsens_s6_p2: s6-p2@44e {
				reg = <0x44e 0x1>;
				bits = <1 6>;
			};

			tsens_mode: mode@44f {
				reg = <0x44f 0x1>;
				bits = <5 3>;
			};
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		tcsr_mutex: hwlock@fd484000 {
			compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
			reg = <0xfd484000 0x1000>;
			#hwlock-cells = <1>;
		};

		tlmm: pinctrl@fd510000 {
			compatible = "qcom,msm8226-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&tlmm 0 0 117>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			blsp1_i2c1_pins: blsp1-i2c1-state {
				pins = "gpio2", "gpio3";
				function = "blsp_i2c1";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c2_pins: blsp1-i2c2-state {
				pins = "gpio6", "gpio7";
				function = "blsp_i2c2";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c3_pins: blsp1-i2c3-state {
				pins = "gpio10", "gpio11";
				function = "blsp_i2c3";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c4_pins: blsp1-i2c4-state {
				pins = "gpio14", "gpio15";
				function = "blsp_i2c4";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c5_pins: blsp1-i2c5-state {
				pins = "gpio18", "gpio19";
				function = "blsp_i2c5";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c6_pins: blsp1-i2c6-state {
				pins = "gpio22", "gpio23";
				function = "blsp_i2c6";
				drive-strength = <2>;
				bias-disable;
			};

			cci_default: cci-default-state {
				pins = "gpio29", "gpio30";
				function = "cci_i2c0";

				drive-strength = <2>;
				bias-disable;
			};

			cci_sleep: cci-sleep-state {
				pins = "gpio29", "gpio30";
				function = "gpio";

				drive-strength = <2>;
				bias-disable;
			};

			sdhc1_default_state: sdhc1-default-state {
				clk-pins {
					pins = "sdc1_clk";
					drive-strength = <10>;
					bias-disable;
				};

				cmd-data-pins {
					pins = "sdc1_cmd", "sdc1_data";
					drive-strength = <10>;
					bias-pull-up;
				};
			};

			sdhc2_default_state: sdhc2-default-state {
				clk-pins {
					pins = "sdc2_clk";
					drive-strength = <10>;
					bias-disable;
				};

				cmd-data-pins {
					pins = "sdc2_cmd", "sdc2_data";
					drive-strength = <10>;
					bias-pull-up;
				};
			};

			sdhc3_default_state: sdhc3-default-state {
				clk-pins {
					pins = "gpio44";
					function = "sdc3";
					drive-strength = <8>;
					bias-disable;
				};

				cmd-pins {
					pins = "gpio43";
					function = "sdc3";
					drive-strength = <8>;
					bias-pull-up;
				};

				data-pins {
					pins = "gpio39", "gpio40", "gpio41", "gpio42";
					function = "sdc3";
					drive-strength = <8>;
					bias-pull-up;
				};
			};
		};

		mmcc: clock-controller@fd8c0000 {
			compatible = "qcom,mmcc-msm8226";
			reg = <0xfd8c0000 0x6000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;

			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
				 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
				 <&gcc GPLL0_VOTE>,
				 <&gcc GPLL1_VOTE>,
				 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
				 <&mdss_dsi0_phy 1>,
				 <&mdss_dsi0_phy 0>;
			clock-names = "xo",
				      "mmss_gpll0_vote",
				      "gpll0_vote",
				      "gpll1_vote",
				      "gfx3d_clk_src",
				      "dsi0pll",
				      "dsi0pllbyte";
		};

		mdss: display-subsystem@fd900000 {
			compatible = "qcom,mdss";
			reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
			reg-names = "mdss_phys", "vbif_phys";

			power-domains = <&mmcc MDSS_GDSC>;

			clocks = <&mmcc MDSS_AHB_CLK>,
				 <&mmcc MDSS_AXI_CLK>,
				 <&mmcc MDSS_VSYNC_CLK>;
			clock-names = "iface",
				      "bus",
				      "vsync";

			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;
			#interrupt-cells = <1>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			status = "disabled";

			mdss_mdp: display-controller@fd900000 {
				compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
				reg = <0xfd900100 0x22000>;
				reg-names = "mdp_phys";

				interrupt-parent = <&mdss>;
				interrupts = <0>;

				clocks = <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_AXI_CLK>,
					 <&mmcc MDSS_MDP_CLK>,
					 <&mmcc MDSS_VSYNC_CLK>;
				clock-names = "iface",
					      "bus",
					      "core",
					      "vsync";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						mdss_mdp_intf1_out: endpoint {
							remote-endpoint = <&mdss_dsi0_in>;
						};
					};
				};
			};

			mdss_dsi0: dsi@fd922800 {
				compatible = "qcom,msm8226-dsi-ctrl",
					     "qcom,mdss-dsi-ctrl";
				reg = <0xfd922800 0x1f8>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
				interrupts = <4>;

				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
						  <&mmcc PCLK0_CLK_SRC>;
				assigned-clock-parents = <&mdss_dsi0_phy 0>,
							 <&mdss_dsi0_phy 1>;

				clocks = <&mmcc MDSS_MDP_CLK>,
					 <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_AXI_CLK>,
					 <&mmcc MDSS_BYTE0_CLK>,
					 <&mmcc MDSS_PCLK0_CLK>,
					 <&mmcc MDSS_ESC0_CLK>,
					 <&mmcc MMSS_MISC_AHB_CLK>;
				clock-names = "mdp_core",
					      "iface",
					      "bus",
					      "byte",
					      "pixel",
					      "core",
					      "core_mmss";

				phys = <&mdss_dsi0_phy>;

				#address-cells = <1>;
				#size-cells = <0>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						mdss_dsi0_in: endpoint {
							remote-endpoint = <&mdss_mdp_intf1_out>;
						};
					};

					port@1 {
						reg = <1>;
						mdss_dsi0_out: endpoint {
						};
					};
				};
			};

			mdss_dsi0_phy: phy@fd922a00 {
				compatible = "qcom,dsi-phy-28nm-8226";
				reg = <0xfd922a00 0xd4>,
				      <0xfd922b00 0x280>,
				      <0xfd922d80 0x30>;
				reg-names = "dsi_pll",
					    "dsi_phy",
					    "dsi_phy_regulator";

				#clock-cells = <1>;
				#phy-cells = <0>;

				clocks = <&mmcc MDSS_AHB_CLK>,
					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
				clock-names = "iface",
					      "ref";
			};
		};

		cci: cci@fda0c000 {
			compatible = "qcom,msm8226-cci";
			reg = <0xfda0c000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
				 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
				 <&mmcc CAMSS_CCI_CCI_CLK>;
			clock-names = "camss_top_ahb",
				      "cci_ahb",
				      "cci";

			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&cci_default>;
			pinctrl-1 = <&cci_sleep>;

			status = "disabled";

			cci_i2c0: i2c-bus@0 {
				reg = <0>;
				clock-frequency = <400000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gpu: gpu@fdb00000 {
			compatible = "qcom,adreno-305.18", "qcom,adreno";
			reg = <0xfdb00000 0x10000>;
			reg-names = "kgsl_3d0_reg_memory";

			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "kgsl_3d0_irq";

			clocks = <&mmcc OXILI_GFX3D_CLK>,
				 <&mmcc OXILICX_AHB_CLK>,
				 <&mmcc OXILICX_AXI_CLK>;
			clock-names = "core", "iface", "mem_iface";

			sram = <&gmu_sram>;
			power-domains = <&mmcc OXILICX_GDSC>;
			operating-points-v2 = <&gpu_opp_table>;

			status = "disabled";

			gpu_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-450000000 {
					opp-hz = /bits/ 64 <450000000>;
				};

				opp-320000000 {
					opp-hz = /bits/ 64 <320000000>;
				};

				opp-200000000 {
					opp-hz = /bits/ 64 <200000000>;
				};

				opp-19000000 {
					opp-hz = /bits/ 64 <19000000>;
				};
			};
		};

		sram@fdd00000 {
			compatible = "qcom,msm8226-ocmem";
			reg = <0xfdd00000 0x2000>,
			      <0xfec00000 0x20000>;
			reg-names = "ctrl", "mem";
			ranges = <0 0xfec00000 0x20000>;
			clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>;
			clock-names = "core";

			#address-cells = <1>;
			#size-cells = <1>;

			gmu_sram: gmu-sram@0 {
				reg = <0x0 0x20000>;
			};
		};

		adsp: remoteproc@fe200000 {
			compatible = "qcom,msm8226-adsp-pil";
			reg = <0xfe200000 0x100>;

			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

			power-domains = <&rpmpd MSM8226_VDDCX>;
			power-domain-names = "cx";

			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
			clock-names = "xo";

			memory-region = <&adsp_region>;

			qcom,smem-states = <&adsp_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			smd-edge {
				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

				mboxes = <&apcs 8>;
				qcom,smd-edge = <1>;

				label = "lpass";
			};
		};

		sram@fe805000 {
			compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
			reg = <0xfe805000 0x1000>;

			reboot-mode {
				compatible = "syscon-reboot-mode";
				offset = <0x65c>;

				mode-bootloader = <0x77665500>;
				mode-normal = <0x77665501>;
				mode-recovery = <0x77665502>;
			};
		};
	};

	thermal-zones {
		cpu0-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 5>;

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				cpu_alert0: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit0: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu1-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 2>;

			cooling-maps {
				map0 {
					trip = <&cpu_alert1>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				cpu_alert1: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit1: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 2
				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3
				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4
				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1
				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
	};
};