# # CDDL HEADER START # # The contents of this file are subject to the terms of the # Common Development and Distribution License (the "License"). # You may not use this file except in compliance with the License. # # You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE # or http://www.opensolaris.org/os/licensing. # See the License for the specific language governing permissions # and limitations under the License. # # When distributing Covered Code, include this CDDL HEADER in each # file and include the License file at usr/src/OPENSOLARIS.LICENSE. # If applicable, add the following below this CDDL HEADER, with the # fields enclosed by brackets "[]" replaced with your own identifying # information: Portions Copyright [yyyy] [name of copyright owner] # # CDDL HEADER END # # # Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. # # Copyright 2019, Joyent, Inc. # Copyright 2021 Oxide Computer Company # # This Makefile builds # the Intel Core Architecture Performance Counter BackEnd (PCBE). # UTSBASE = ../.. # # The following objects are autogenerated by cpcgen. # CPCGEN_OBJS = \ core_pcbe_cpcgen.o \ core_pcbe_bdw_de.o \ core_pcbe_bdw.o \ core_pcbe_bdx.o \ core_pcbe_bnl.o \ core_pcbe_clx.o \ core_pcbe_glm.o \ core_pcbe_glp.o \ core_pcbe_hsw.o \ core_pcbe_hsx.o \ core_pcbe_icl.o \ core_pcbe_ivb.o \ core_pcbe_ivt.o \ core_pcbe_jkt.o \ core_pcbe_nhm_ep.o \ core_pcbe_nhm_ex.o \ core_pcbe_skl.o \ core_pcbe_skx.o \ core_pcbe_slm.o \ core_pcbe_snb.o \ core_pcbe_snr.o \ core_pcbe_tgl.o \ core_pcbe_wsm_ep_dp.o \ core_pcbe_wsm_ep_sp.o \ core_pcbe_wsm_ex.o CPCGEN_COMMON = core_pcbe_cpcgen.c CPCGEN_CMD = $(CPCGEN) -d $(SRC)/data/perfmon -o . CPCGEN_SRCS = $(CPCGEN_OBJS:%.o=%.c) core_pcbe_cpcgen.h # # Define module and object file sets. # MODULE = pcbe.GenuineIntel.6.15 OBJECTS = $(CORE_PCBE_OBJS:%=$(OBJS_DIR)/%) OBJECTS += $(CPCGEN_OBJS:%=$(OBJS_DIR)/%) ROOTMODULE = $(USR_PCBE_DIR)/$(MODULE) # # This order matches the families declared in uts/intel/sys/x86_archext.h. # SOFTLINKS = \ pcbe.GenuineIntel.6.23 \ pcbe.GenuineIntel.6.29 \ pcbe.GenuineIntel.6.30 \ pcbe.GenuineIntel.6.31 \ pcbe.GenuineIntel.6.26 \ pcbe.GenuineIntel.6.46 \ pcbe.GenuineIntel.6.37 \ pcbe.GenuineIntel.6.44 \ pcbe.GenuineIntel.6.47 \ pcbe.GenuineIntel.6.42 \ pcbe.GenuineIntel.6.45 \ pcbe.GenuineIntel.6.58 \ pcbe.GenuineIntel.6.62 \ pcbe.GenuineIntel.6.60 \ pcbe.GenuineIntel.6.69 \ pcbe.GenuineIntel.6.70 \ pcbe.GenuineIntel.6.63 \ pcbe.GenuineIntel.6.61 \ pcbe.GenuineIntel.6.71 \ pcbe.GenuineIntel.6.79 \ pcbe.GenuineIntel.6.86 \ pcbe.GenuineIntel.6.78 \ pcbe.GenuineIntel.6.85 \ pcbe.GenuineIntel.6.94 \ pcbe.GenuineIntel.6.142 \ pcbe.GenuineIntel.6.158 \ pcbe.GenuineIntel.6.165 \ pcbe.GenuineIntel.6.166 \ pcbe.GenuineIntel.6.28 \ pcbe.GenuineIntel.6.38 \ pcbe.GenuineIntel.6.39 \ pcbe.GenuineIntel.6.53 \ pcbe.GenuineIntel.6.54 \ pcbe.GenuineIntel.6.55 \ pcbe.GenuineIntel.6.77 \ pcbe.GenuineIntel.6.76 \ pcbe.GenuineIntel.6.92 \ pcbe.GenuineIntel.6.95 \ pcbe.GenuineIntel.6.122 \ pcbe.GenuineIntel.6.126 \ pcbe.GenuineIntel.6.134 \ pcbe.GenuineIntel.6.140 \ pcbe.GenuineIntel.6.141 ROOTSOFTLINKS = $(SOFTLINKS:%=$(USR_PCBE_DIR)/%) # # Include common rules. # include $(UTSBASE)/intel/Makefile.intel CERRWARN += $(CNOWARN_UNINIT) CERRWARN += -_gcc=-Wno-unused-variable CPPFLAGS += -I$(UTSBASE)/intel/core_pcbe CLEANFILES += $(CPCGEN_SRCS) # # Define targets. # ALL_TARGET = $(CPCGEN_COMMON) .WAIT $(BINARY) INSTALL_TARGET = $(CPCGEN_COMMON) .WAIT $(BINARY) $(ROOTMODULE) $(ROOTSOFTLINKS) # # Default build targets. # .KEEP_STATE: def: $(DEF_DEPS) all: $(ALL_DEPS) clean: $(CLEAN_DEPS) clobber: $(CLOBBER_DEPS) install: $(INSTALL_DEPS) $(ROOTSOFTLINKS): $(ROOTMODULE) -$(RM) $@; $(SYMLINK) $(MODULE) $@ core_pcbe_cpcgen.c: $(CPCGEN_CMD) -a -H core_pcbe_%.c: $(CPCGEN_COMMON) $(CPCGEN_CMD) -c -p \ $$(echo $@ | \ $(SED) -e 's/core_pcbe_//g' -e 's/_/-/g' -e 's/.c$$//g') $(OBJS_DIR)/%.o: %.c $(COMPILE.c) -I$(SRC)/uts/intel/pcbe/ -o $@ $< $(CTFCONVERT_O) # # Include common targets. # include $(UTSBASE)/intel/Makefile.targ