#define ATC_REG_ATC_NUM_SETS 0x110000UL //ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32
#define ATC_REG_ATC_1_WAY 0x110004UL //ACCESS:RW DataWidth:0x1 Description: If set the ATC will use only one way per set
#define ATC_REG_ATC_FULL_REG 0x110008UL //ACCESS:R DataWidth:0x8 Description: SPA Done FIFO full bit; RCPL FIFO full bit; TCPL FIFO full bit; IREQ full bit; PLKP FIFO full bit; MLKP FIFO full bit; OTB full bit; OIB full bit
#define ATC_REG_ATC_EMPTY_REG 0x11000cUL //ACCESS:R DataWidth:0x8 Description: SPA Done FIFO empty bit; RCPL FIFO empty bit; TCPL FIFO empty bit; IREQ empty bit; PLKP FIFO empty bit; MLKP FIFO empty bit; OTB empty bit; OIB empty bit
#define ATC_REG_ATC_WAIT_IF_MISS 0x110010UL //ACCESS:RW DataWidth:0x1 Description: WaitIfMiss configuration bit
#define ATC_REG_ATC_WAIT_IF_PENDING 0x110014UL //ACCESS:RW DataWidth:0x1 Description: WaitTransPending cofiguration bit
#define ATC_REG_ATC_STALL_SEQ_0 0x110018UL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_STALL_SEQ_1 0x11001cUL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_STALL_SEQ_2 0x110020UL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_STALL_SEQ_3 0x110024UL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_STALL_SEQ_4 0x110028UL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_STALL_SEQ_5 0x11002cUL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_SET_STALL_SEQ_0 0x110030UL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_SET_STALL_SEQ_1 0x110034UL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_SET_STALL_SEQ_2 0x110038UL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_SET_STALL_SEQ_3 0x11003cUL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_SET_STALL_SEQ_4 0x110040UL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_SET_STALL_SEQ_5 0x110044UL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction
#define ATC_REG_ATC_DISABLE_BYPASS 0x110048UL //ACCESS:RW DataWidth:0x1 Description: disables the bypass on the GPA table
#define ATC_REG_ATC_ISSUE_4_CYCLES 0x11004cUL //ACCESS:RW DataWidth:0x1 Description: Issue event once in four cycles (instead of 2)
#define ATC_REG_ATC_IREQ_FIFO_SIZE 0x110050UL //ACCESS:RW DataWidth:0x8 Description: defines the size of the IREQ fifo
#define ATC_REG_ATC_IREQ_ALMOST_FULL_THR 0x110054UL //ACCESS:RW DataWidth:0x8 Description: Debug only: defines the IFIFO almost full threshold. Its size can't be bigger than the Ireq FIFO size
#define ATC_REG_ATC_PIGGYBACKED_TREQ_EN 0x110058UL //ACCESS:RW DataWidth:0x1 Description: Piggybacked treq issue enabled
#define ATC_REG_ATC_WAIT_RESP 0x11005cUL //ACCESS:RW DataWidth:0x1 Description: Allows the ATC to return Wait response
#define ATC_REG_ATC_TREQ_CREDITS 0x110060UL //ACCESS:RW DataWidth:0x6 Description: Number of credits for the treq interface
#define ATC_REG_ATC_ARBITER_PRIO_MLKP 0x110064UL //ACCESS:RW DataWidth:0x2 Description: MLKP prio
#define ATC_REG_ATC_ARBITER_PRIO_PLKP 0x110068UL //ACCESS:RW DataWidth:0x2 Description: PLKP prio
#define ATC_REG_ATC_ARBITER_PRIO_IREQ 0x11006cUL //ACCESS:RW DataWidth:0x2 Description: IREQ prio
#define ATC_REG_ATC_ARBITER_PRIO_TCPL 0x110070UL //ACCESS:RW DataWidth:0x2 Description: TCPL prio
#define ATC_REG_ATC_ARBITER_PRIO_SPAD 0x110074UL //ACCESS:RW DataWidth:0x2 Description: SPAD prio
#define ATC_REG_ATC_ARBITER_PRIO_RCPL 0x110078UL //ACCESS:RW DataWidth:0x2 Description: RCPL prio
#define ATC_REG_ATC_OTB_MAX_ENTRY 0x11007cUL //ACCESS:RW DataWidth:0x5 Description: Defines the number of entries in the OTB when 31 indicates 32 entries (entries count begins in 0)
#define ATC_REG_ATC_CHECK_TAGS 0x110080UL //ACCESS:RW DataWidth:0x1 Description: CheckTags configuration bit - when set the available NPH credits is checked before issuing TREQ
#define ATC_REG_ATC_TAG_THR 0x110084UL //ACCESS:RW DataWidth:0x8 Description: TAG threshold - for the checkTags feature
#define ATC_REG_ATC_ICPL_CREDIT 0x110088UL //ACCESS:RW DataWidth:0x3 Description: Credit value for the ICPL interface
#define ATC_REG_ATC_DIS_MLKP 0x11008cUL //ACCESS:RW DataWidth:0x1 Description: Disables the main lookup interface
#define ATC_REG_ATC_DIS_PLKP 0x110090UL //ACCESS:RW DataWidth:0x1 Description: Disables the pre lookup interface
#define ATC_REG_ATC_DIS_IREQ 0x110094UL //ACCESS:RW DataWidth:0x1 Description: Disables the invalidation request interface
#define ATC_REG_ATC_DIS_TCPL 0x110098UL //ACCESS:RW DataWidth:0x1 Description: Disables the translation completion interface
#define ATC_REG_ATC_DIS_SPAD 0x11009cUL //ACCESS:RW DataWidth:0x1 Description: Disables the spa done interface
#define ATC_REG_ATC_DIS_RCPL 0x1100a0UL //ACCESS:RW DataWidth:0x1 Description: Disables the Read Completion interface
#define ATC_REG_ATC_DIS_LKPRES 0x1100a4UL //ACCESS:RW DataWidth:0x1 Description: Disables the lookup response interface
#define ATC_REG_ATC_DIS_TREQ 0x1100a8UL //ACCESS:RW DataWidth:0x1 Description: Disables the translation request interface
#define ATC_REG_ATC_DIS_ICPL 0x1100acUL //ACCESS:RW DataWidth:0x1 Description: Disables the invalidation completion interface
#define ATC_REG_ATC_SCRUB_CYC 0x1100b0UL //ACCESS:RW DataWidth:0x8 Description: Number of cycles between one scrub event to another
#define ATC_REG_ATC_SCRUB_DIS 0x1100b4UL //ACCESS:RW DataWidth:0x1 Description: Disable bit for the scrubbing event of the GPA table
#define ATC_REG_ATC_INIT_ARRAY 0x1100b8UL //ACCESS:RW DataWidth:0x1 Description: Initiate the ATC array - reset all the valid bits
#define ATC_REG_ATC_INIT_DONE 0x1100bcUL //ACCESS:R DataWidth:0x1 Description: ATC initalization done
#define ATC_REG_ATC_STAT_MLKP_HITS 0x1100c0UL //ACCESS:ST DataWidth:0x20 Description: Number of hits for Main-lookups in the ATC
#define ATC_REG_ATC_STAT_MLKP_NUM 0x1100c4UL //ACCESS:ST DataWidth:0x20 Description: Number of Main lookups in the ATC
#define ATC_REG_ATC_STAT_PLKP_TREQ 0x1100c8UL //ACCESS:ST DataWidth:0x20 Description: Number of treqs issued due to pre-lookup
#define ATC_REG_ATC_STAT_PLKP_NUM 0x1100ccUL //ACCESS:ST DataWidth:0x20 Description: Number of Pre Lookps in the ATC
#define ATC_REG_ATC_STAT_EVICT_NUM 0x1100d0UL //ACCESS:ST DataWidth:0x20 Description: Number of evictions out of the ATC
#define ATC_REG_ATC_STAT_INV_NUM 0x1100d4UL //ACCESS:ST DataWidth:0x20 Description: Number of invalidations handled by the ATC
#define ATC_REG_ATC_STAT_TREQ_NUM 0x1100d8UL //ACCESS:ST DataWidth:0x20 Description: Number of translation requests issued by the ATC
#define ATC_REG_ATC_STAT_ACTIVE 0x1100dcUL //ACCESS:RW DataWidth:0x1 Description: When this signal is set the statistics count is on
#define ATC_REG_ATC_STAT_USDM_LKP_NUM 0x1100e0UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_USDM_HIT_NUM 0x1100e4UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_CSDM_LKP_NUM 0x1100e8UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_CSDM_HIT_NUM 0x1100ecUL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_XSDM_LKP_NUM 0x1100f0UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_XSDM_HIT_NUM 0x1100f4UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_TSDM_LKP_NUM 0x1100f8UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_TSDM_HIT_NUM 0x1100fcUL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_PBF_LKP_NUM 0x110100UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_PBF_HIT_NUM 0x110104UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_QM_LKP_NUM 0x110108UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_QM_HIT_NUM 0x11010cUL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_TM_LKP_NUM 0x110110UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_TM_HIT_NUM 0x110114UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_SRC_LKP_NUM 0x110118UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_SRC_HIT_NUM 0x11011cUL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_CDURD_LKP_NUM 0x110120UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_CDURD_HIT_NUM 0x110124UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_DMAE_LKP_NUM 0x110128UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_DMAE_HIT_NUM 0x11012cUL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_USDM_DP_LKP_NUM 0x110130UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_USDM_DP_HIT_NUM 0x110134UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_HC_LKP_NUM 0x110138UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_HC_HIT_NUM 0x11013cUL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_CDUWR_LKP_NUM 0x110140UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_CDUWR_HIT_NUM 0x110144UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_DBG_LKP_NUM 0x110148UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_DBG_HIT_NUM 0x11014cUL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_L2P_LKP_NUM 0x110150UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_STAT_L2P_HIT_NUM 0x110154UL //ACCESS:ST DataWidth:0x20 Description: Count lookups and hit for the different clients
#define ATC_REG_ATC_GPA_HASH_EN 0x110158UL //ACCESS:RW DataWidth:0x1 Description: enable the use of a hash function for the GPA table; instead of the lsb bits of the address
#define ATC_REG_ATC_GPA_HASH_CRC 0x11015cUL //ACCESS:RW DataWidth:0x1 Description: relevant only if hash_en is set. selects the CRC as hash function for the GPA table; If reset use xor of the FID LS bits with the relevant bits out of the GPA as hash function
#define ATC_REG_ATC_TCPL_LOG_ON_ERROR 0x110160UL //ACCESS:RW DataWidth:0x5 Description: In case of TCPL with error log the relevant data. The seperation for the different errors is: BME clear [0]; Unsupported request [1]; Completer abort/completion timeout [2]; Both R & W bits are reset [3]; Other [4]
#define ATC_REG_ATC_TCPL_DIS_ON_ERROR 0x110164UL //ACCESS:RW DataWidth:0x5 Description: In case of TCPL with error disable the ATC. The seperation for the different errors is: BME clear [0]; Unsupported request [1]; Completer abort/completion timeout [2]; Both R & W bits are reset [3]; Other [4]
#define ATC_REG_ATC_TCPL_ERR_LOG 0x110168UL //ACCESS:R DataWidth:0x16 Description: Data belongs to an erroneous TCPL: [9:0] Func (VF_Valid;VFID;PFID);[10] U bit; [11] W bit; [12] R bit; [13] NS bit; [18:14] OTBEntryID;[21:19] Error code
#define ATC_REG_ATC_TCPL_ERR_ADDR_LSB 0x11016cUL //ACCESS:R DataWidth:0x20 Description: Data belongs to an erroneous TCPL: [31:0]-bits [31:0] of the address
#define ATC_REG_ATC_TCPL_ERR_ADDR_MSB 0x110170UL //ACCESS:R DataWidth:0x14 Description: Data belongs to an erroneous TCPL: [19:0]-bits [51:32] of the address
#define ATC_REG_ATC_TCPL_ERR_LOG_VALID 0x110174UL //ACCESS:R DataWidth:0x1 Description: Indicates valid data at the tcpl error log registers
#define ATC_REG_ATC_ARRAY_ACCESS_ENABLE 0x110178UL //ACCESS:RW DataWidth:0x1 Description: Allows GRC access to the GPA and SPA table
#define ATC_REG_ATC_DURING_FLI 0x11017cUL //ACCESS:R DataWidth:0x1 Description: Indication that the ATC currently handles FLI
#define ATC_REG_ATC_DURING_INV 0x110180UL //ACCESS:R DataWidth:0x1 Description: Indication that the ATC currently handles Any type of invalidation
#define ATC_REG_ATC_FLI_DONE_VF_31_0 0x110184UL //ACCESS:R DataWidth:0x20 Description: Indicates the end of FLI flow for VF 31-0
#define ATC_REG_ATC_FLI_DONE_VF_63_32 0x110188UL //ACCESS:R DataWidth:0x20 Description: Indicates the end of FLI flow for VF 63-32
#define ATC_REG_ATC_FLI_DONE_PF_7_0 0x11018cUL //ACCESS:R DataWidth:0x8 Description: Indicates the end of FLI flow for PF 7-0
#define ATC_REG_ATC_FLI_DONE_CLR_VF_31_0 0x110190UL //ACCESS:RW DataWidth:0x20 Description: Clears the FLI done indication for VF bits 31-0 accordingly
#define ATC_REG_ATC_FLI_DONE_CLR_VF_63_32 0x110194UL //ACCESS:RW DataWidth:0x20 Description: Clears the FLI done indication for VFbits 63-32 accordingly
#define ATC_REG_ATC_FLI_DONE_CLR_PF_7_0 0x110198UL //ACCESS:RW DataWidth:0x8 Description: Clears the FLI done indication for PF bits 7-0 accordingly
#define ATC_REG_DBG_SELECT 0x11019cUL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PXP to the DBG block) - for selecting a line to output to the DBG block.
#define ATC_REG_DBG_BYTE_ENABLE 0x1101a0UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PXP to the DBG block) - for enabling bytes in the selected line (after the select and before the shift)
#define ATC_REG_DBG_SHIFT 0x1101a4UL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from PXP to the DBG block) - for circular right shifting of the selected line (after the enabling)
#define ATC_REG_DBGSYN_ALMOST_FULL_THR 0x1101a8UL //ACCESS:RW DataWidth:0x4 Description: Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed. Its value can't be bigger than the set dbg FIFO size
#define ATC_REG_ATC_ALLOW_LOW_REP_HIGH 0x1101acUL //ACCESS:RW DataWidth:0x1 Description: When set low priority lookup can replace high priority entry; iff the set is full with high prio entries
#define ATC_REG_ATC_DIS_IREQ_EVENT 0x1101b0UL //ACCESS:RW DataWidth:0x1 Description: When set Ireq event won't be selected by the ATC arbiter
#define ATC_REG_ATC_ECO_RESERVED 0x1101b4UL //ACCESS:RW DataWidth:0x1 Description: For future ECOs implementation
#define ATC_REG_ATC_TM 0x1101b8UL //ACCESS:RW DataWidth:0x1e Multi Field Register
#define ATC_ATC_TM_REG_ATC_SPA_TABLE_TM (0x1f<<0)
#define ATC_ATC_TM_REG_ATC_SPA_TABLE_TM_SIZE 0
#define ATC_ATC_TM_REG_ATC_GPA_DATA_W0_TM (0x1f<<5)
#define ATC_ATC_TM_REG_ATC_GPA_DATA_W0_TM_SIZE 5
#define ATC_ATC_TM_REG_ATC_GPA_DATA_W1_TM (0x1f<<10)
#define ATC_ATC_TM_REG_ATC_GPA_DATA_W1_TM_SIZE 10
#define ATC_ATC_TM_REG_ATC_GPA_DATA_W2_TM (0x1f<<15)
#define ATC_ATC_TM_REG_ATC_GPA_DATA_W2_TM_SIZE 15
#define ATC_ATC_TM_REG_ATC_GPA_DATA_W3_TM (0x1f<<20)
#define ATC_ATC_TM_REG_ATC_GPA_DATA_W3_TM_SIZE 20
#define ATC_ATC_TM_REG_ATC_GPA_STATE_TM (0x1f<<25)
#define ATC_ATC_TM_REG_ATC_GPA_STATE_TM_SIZE 25
#define ATC_REG_ATC_INT_STS 0x1101bcUL //ACCESS:R DataWidth:0x6 Description: Interrupt register #0 read
#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND_SIZE 1
#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS_SIZE 2
#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT_SIZE 3
#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR_SIZE 4
#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU_SIZE 5
#define ATC_REG_ATC_INT_STS_CLR 0x1101c0UL //ACCESS:RC DataWidth:0x6 Description: Interrupt register #0 read clear
#define ATC_ATC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define ATC_ATC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define ATC_ATC_INT_STS_CLR_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
#define ATC_ATC_INT_STS_CLR_REG_ATC_TCPL_TO_NOT_PEND_SIZE 1
#define ATC_ATC_INT_STS_CLR_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
#define ATC_ATC_INT_STS_CLR_REG_ATC_GPA_MULTIPLE_HITS_SIZE 2
#define ATC_ATC_INT_STS_CLR_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
#define ATC_ATC_INT_STS_CLR_REG_ATC_RCPL_TO_EMPTY_CNT_SIZE 3
#define ATC_ATC_INT_STS_CLR_REG_ATC_TCPL_ERROR (0x1<<4)
#define ATC_ATC_INT_STS_CLR_REG_ATC_TCPL_ERROR_SIZE 4
#define ATC_ATC_INT_STS_CLR_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
#define ATC_ATC_INT_STS_CLR_REG_ATC_IREQ_LESS_THAN_STU_SIZE 5
#define ATC_REG_ATC_INT_STS_WR 0x1101c4UL //ACCESS:WR DataWidth:0x6 Description: Interrupt register #0 bit set or clear
#define ATC_ATC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define ATC_ATC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define ATC_ATC_INT_STS_WR_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
#define ATC_ATC_INT_STS_WR_REG_ATC_TCPL_TO_NOT_PEND_SIZE 1
#define ATC_ATC_INT_STS_WR_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
#define ATC_ATC_INT_STS_WR_REG_ATC_GPA_MULTIPLE_HITS_SIZE 2
#define ATC_ATC_INT_STS_WR_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
#define ATC_ATC_INT_STS_WR_REG_ATC_RCPL_TO_EMPTY_CNT_SIZE 3
#define ATC_ATC_INT_STS_WR_REG_ATC_TCPL_ERROR (0x1<<4)
#define ATC_ATC_INT_STS_WR_REG_ATC_TCPL_ERROR_SIZE 4
#define ATC_ATC_INT_STS_WR_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
#define ATC_ATC_INT_STS_WR_REG_ATC_IREQ_LESS_THAN_STU_SIZE 5
#define ATC_REG_ATC_INT_MASK 0x1101c8UL //ACCESS:RW DataWidth:0x6 Description: Interrupt mask register #0 read/write
#define ATC_ATC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define ATC_ATC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define ATC_ATC_INT_MASK_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
#define ATC_ATC_INT_MASK_REG_ATC_TCPL_TO_NOT_PEND_SIZE 1
#define ATC_ATC_INT_MASK_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
#define ATC_ATC_INT_MASK_REG_ATC_GPA_MULTIPLE_HITS_SIZE 2
#define ATC_ATC_INT_MASK_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
#define ATC_ATC_INT_MASK_REG_ATC_RCPL_TO_EMPTY_CNT_SIZE 3
#define ATC_ATC_INT_MASK_REG_ATC_TCPL_ERROR (0x1<<4)
#define ATC_ATC_INT_MASK_REG_ATC_TCPL_ERROR_SIZE 4
#define ATC_ATC_INT_MASK_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
#define ATC_ATC_INT_MASK_REG_ATC_IREQ_LESS_THAN_STU_SIZE 5
#define ATC_REG_ATC_PRTY_STS 0x1101ccUL //ACCESS:R DataWidth:0x5 Description: Parity register #0 read
#define ATC_ATC_PRTY_STS_REG_PARITY (0x1<<0)
#define ATC_ATC_PRTY_STS_REG_PARITY_SIZE 0
#define ATC_ATC_PRTY_STS_REG_GPA_TABLE (0x1<<1)
#define ATC_ATC_PRTY_STS_REG_GPA_TABLE_SIZE 1
#define ATC_ATC_PRTY_STS_REG_IREQ_FIFO (0x1<<2)
#define ATC_ATC_PRTY_STS_REG_IREQ_FIFO_SIZE 2
#define ATC_ATC_PRTY_STS_REG_SPA_TABLE (0x1<<3)
#define ATC_ATC_PRTY_STS_REG_SPA_TABLE_SIZE 3
#define ATC_ATC_PRTY_STS_REG_TCPL_FIFO (0x1<<4)
#define ATC_ATC_PRTY_STS_REG_TCPL_FIFO_SIZE 4
#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0UL //ACCESS:RC DataWidth:0x5 Description: Parity register #0 read clear
#define ATC_ATC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define ATC_ATC_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define ATC_ATC_PRTY_STS_CLR_REG_GPA_TABLE (0x1<<1)
#define ATC_ATC_PRTY_STS_CLR_REG_GPA_TABLE_SIZE 1
#define ATC_ATC_PRTY_STS_CLR_REG_IREQ_FIFO (0x1<<2)
#define ATC_ATC_PRTY_STS_CLR_REG_IREQ_FIFO_SIZE 2
#define ATC_ATC_PRTY_STS_CLR_REG_SPA_TABLE (0x1<<3)
#define ATC_ATC_PRTY_STS_CLR_REG_SPA_TABLE_SIZE 3
#define ATC_ATC_PRTY_STS_CLR_REG_TCPL_FIFO (0x1<<4)
#define ATC_ATC_PRTY_STS_CLR_REG_TCPL_FIFO_SIZE 4
#define ATC_REG_ATC_PRTY_STS_WR 0x1101d4UL //ACCESS:WR DataWidth:0x5 Description: Parity register #0 bit set or clear
#define ATC_ATC_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define ATC_ATC_PRTY_STS_WR_REG_PARITY_SIZE 0
#define ATC_ATC_PRTY_STS_WR_REG_GPA_TABLE (0x1<<1)
#define ATC_ATC_PRTY_STS_WR_REG_GPA_TABLE_SIZE 1
#define ATC_ATC_PRTY_STS_WR_REG_IREQ_FIFO (0x1<<2)
#define ATC_ATC_PRTY_STS_WR_REG_IREQ_FIFO_SIZE 2
#define ATC_ATC_PRTY_STS_WR_REG_SPA_TABLE (0x1<<3)
#define ATC_ATC_PRTY_STS_WR_REG_SPA_TABLE_SIZE 3
#define ATC_ATC_PRTY_STS_WR_REG_TCPL_FIFO (0x1<<4)
#define ATC_ATC_PRTY_STS_WR_REG_TCPL_FIFO_SIZE 4
#define ATC_REG_ATC_PRTY_MASK 0x1101d8UL //ACCESS:RW DataWidth:0x5 Description: Parity mask register #0 read/write
#define ATC_ATC_PRTY_MASK_REG_PARITY (0x1<<0)
#define ATC_ATC_PRTY_MASK_REG_PARITY_SIZE 0
#define ATC_ATC_PRTY_MASK_REG_GPA_TABLE (0x1<<1)
#define ATC_ATC_PRTY_MASK_REG_GPA_TABLE_SIZE 1
#define ATC_ATC_PRTY_MASK_REG_IREQ_FIFO (0x1<<2)
#define ATC_ATC_PRTY_MASK_REG_IREQ_FIFO_SIZE 2
#define ATC_ATC_PRTY_MASK_REG_SPA_TABLE (0x1<<3)
#define ATC_ATC_PRTY_MASK_REG_SPA_TABLE_SIZE 3
#define ATC_ATC_PRTY_MASK_REG_TCPL_FIFO (0x1<<4)
#define ATC_ATC_PRTY_MASK_REG_TCPL_FIFO_SIZE 4
#define ATC_REG_ATC_IREQ_FIFO_TM 0x1101dcUL //ACCESS:RW DataWidth:0x8 Description: TM bits of GPA state array
#define ATC_REG_DBG_OUT_DATA_LSB 0x110200UL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that goes to the DBG block.
#define ATC_REG_DBG_OUT_DATA_LSB_SIZE 1
#define ATC_REG_DBG_OUT_DATA_MSB 0x110204UL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that goes to the DBG block.
#define ATC_REG_DBG_OUT_DATA_MSB_SIZE 1
#define ATC_REG_DBG_OUT_FRAME 0x110208UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits that goes to the DBG block. Bit0 is the frame of data byte0; Bit1 is the frame of data byte1; Bit2 is the frame of data byte2; Bit3 is the frame of data byte4
#define ATC_REG_DBG_OUT_FRAME_SIZE 1
#define ATC_REG_DBG_OUT_VALID 0x11020cUL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits that goes to the DBG block. Bit0 validtes data byte0; Bit1 validates data byte1; Bit2 validates data byte2; Bit3 validates data byte4
#define ATC_REG_DBG_OUT_VALID_SIZE 1
#define ATC_REG_ATC_GPA_ARRAY_ACCESS_STATE 0x110800UL //ACCESS:WB DataWidth:0x34 Description: Access the state fields of the GPA table; format is: W3 - {par - [51]; NS bit - [50]; W bit - [49]; R bit - [48]; U bit - [47]; Priority bit - [46]; PLRU - [45]; R-counter - [44:42]; transpend bit - [41]; invpend bit [40]; valid bit[39]}; W2 - {par - [38]; NS bit - [37]; W bit - [36]; R bit - [35]; U bit - [34]; Priority bit - [33]; PLRU - [32]; R-counter - [31:29]; transpend bit - [28]; invpend bit [27]; valid bit[26]}; W1 - {par - [25]; NS bit - [24]; W bit - [23]; R bit - [22]; U bit - [21]; Priority bit - [20]; PLRU - [19]; R-counter - [18:16]; transpend bit - [15]; invpend bit [14]; valid bit[13]}; W0 - {par - [12]; NS bit - [11]; W bit - [10]; R bit - [9]; U bit - [8]; Priority bit - [7]; PLRU - [6]; R-counter - [5:3]; transpend bit - [2]; invpend bit [1]; valid bit[0]}
#define ATC_REG_ATC_GPA_ARRAY_ACCESS_STATE_SIZE 512
#define ATC_REG_ATC_GPA_ARRAY_ACCESS_W0 0x111000UL //ACCESS:WB DataWidth:0x3e Description: Access the GPA table way 0; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[58:53]; PFID-[61:59];Parity[62]
#define ATC_REG_ATC_GPA_ARRAY_ACCESS_W0_SIZE 512
#define ATC_REG_ATC_GPA_ARRAY_ACCESS_W1 0x111800UL //ACCESS:WB DataWidth:0x3e Description: Access the GPA table way 1; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[58:53]; PFID-[61:59];Parity[62]
#define ATC_REG_ATC_GPA_ARRAY_ACCESS_W1_SIZE 512
#define ATC_REG_ATC_GPA_ARRAY_ACCESS_W2 0x112000UL //ACCESS:WB DataWidth:0x3e Description: Access the GPA table way 2; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[58:53]; PFID-[61:59];Parity[62]
#define ATC_REG_ATC_GPA_ARRAY_ACCESS_W2_SIZE 512
#define ATC_REG_ATC_GPA_ARRAY_ACCESS_W3 0x112800UL //ACCESS:WB DataWidth:0x3e Description: Access the GPA table way 3; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[58:53]; PFID-[61:59];Parity[62]
#define ATC_REG_ATC_GPA_ARRAY_ACCESS_W3_SIZE 512
#define ATC_REG_ATC_SPA_ARRAY_ACCESS 0x114000UL //ACCESS:WB DataWidth:0x34 Description: Debug access to the SPA array
#define ATC_REG_ATC_SPA_ARRAY_ACCESS_SIZE 2048
#define ATC_REG_ATC_UNUSED_EMPTY_0 0x1101e0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define ATC_REG_ATC_UNUSED_EMPTY_0_SIZE 8
#define ATC_REG_ATC_UNUSED_EMPTY_1 0x110210UL //ACCESS:R DataWidth:0x20 Unused empty space
#define ATC_REG_ATC_UNUSED_EMPTY_1_SIZE 380
#define ATC_REG_ATC_UNUSED_EMPTY_2 0x113000UL //ACCESS:R DataWidth:0x20 Unused empty space
#define ATC_REG_ATC_UNUSED_EMPTY_2_SIZE 1024
#define ATC_REG_ATC_UNUSED_EMPTY_3 0x116000UL //ACCESS:R DataWidth:0x20 Unused empty space
#define ATC_REG_ATC_UNUSED_EMPTY_3_SIZE 2048
#define BRB1_REG_HEADER_SIZE 0x60000UL //ACCESS:RW DataWidth:0x8 Description: Number of bytes after which new packet message is sent.
#define BRB1_REG_READ_FREE_BLOCK_ERROR_0 0x60004UL //ACCESS:RC DataWidth:0x1 Description: Read client 0: attempt to read from free block.
#define BRB1_REG_READ_FREE_BLOCK_ERROR_10 0x60008UL //ACCESS:RC DataWidth:0x1 Description: Read client 10: attempt to read from free block.
#define BRB1_REG_READ_FREE_BLOCK_ERROR_11 0x6000cUL //ACCESS:RC DataWidth:0x1 Description: Read client 11: attempt to read from free block.
#define BRB1_REG_READ_FREE_BLOCK_ERROR_12 0x60010UL //ACCESS:RC DataWidth:0x1 Description: Read client 12: attempt to read from free block.
#define BRB1_REG_READ_FREE_BLOCK_ERROR_13 0x60014UL //ACCESS:RC DataWidth:0x1 Description: Read client 13: attempt to read from free block.
#define BRB1_REG_READ_FREE_BLOCK_ERROR_14 0x60018UL //ACCESS:RC DataWidth:0x1 Description: Read client 14: attempt to read from free block.
#define BRB1_REG_READ_FREE_BLOCK_ERROR_2 0x6001cUL //ACCESS:RC DataWidth:0x1 Description: Read client 2: attempt to read from free block.
#define BRB1_REG_READ_FREE_BLOCK_ERROR_3 0x60020UL //ACCESS:RC DataWidth:0x1 Description: Read client 3: attempt to read from free block.
#define BRB1_REG_READ_FREE_BLOCK_ERROR_4 0x60024UL //ACCESS:RC DataWidth:0x1 Description: Read client 4: attempt to read from free block.
#define BRB1_REG_READ_LENGTH_ERROR_0 0x60028UL //ACCESS:RC DataWidth:0x1 Description: Read client 0: attempt to read more data than in packet.
#define BRB1_REG_READ_LENGTH_ERROR_10 0x6002cUL //ACCESS:RC DataWidth:0x1 Description: Read client 10: attempt to read more data than in packet.
#define BRB1_REG_READ_LENGTH_ERROR_11 0x60030UL //ACCESS:RC DataWidth:0x1 Description: Read client 11: attempt to read more data than in packet.
#define BRB1_REG_READ_LENGTH_ERROR_12 0x60034UL //ACCESS:RC DataWidth:0x1 Description: Read client 12: attempt to read more data than in packet.
#define BRB1_REG_READ_LENGTH_ERROR_13 0x60038UL //ACCESS:RC DataWidth:0x1 Description: Read client 13: attempt to read more data than in packet.
#define BRB1_REG_READ_LENGTH_ERROR_14 0x6003cUL //ACCESS:RC DataWidth:0x1 Description: Read client 14: attempt to read more data than in packet.
#define BRB1_REG_READ_LENGTH_ERROR_2 0x60040UL //ACCESS:RC DataWidth:0x1 Description: Read client 2: attempt to read more data than in packet.
#define BRB1_REG_READ_LENGTH_ERROR_3 0x60044UL //ACCESS:RC DataWidth:0x1 Description: Read client 3: attempt to read more data than in packet.
#define BRB1_REG_READ_LENGTH_ERROR_4 0x60048UL //ACCESS:RC DataWidth:0x1 Description: Read client 4: attempt to read more data than in packet.
#define BRB1_REG_STOP_INTERFACE_ON_READ_FREE_BLOCK_ERROR 0x6004cUL //ACCESS:RW DataWidth:0x9 Description: stop interface on read from free block. Bit 0 (LSB) for client 0. Bit 1 for client 1 logical 0. Bit 2 for client 1 logical 1. Bit 3 for client 1 logical 2. Bit 4 for client 1 logical 3. Bit 5 for client 1 logical 4. Bit 6 for client 2. Bit 7 for client 3. Bit 8 for client 4.
#define BRB1_REG_STOP_INTERFACE_ON_READ_LENGTH_ERROR 0x60050UL //ACCESS:RW DataWidth:0x9 Description: stop interface on read more data than in packet. Bit 0 (LSB) for client 0. Bit 1 for client 1 logical 0. Bit 2 for client 1 logical 1. Bit 3 for client 1 logical 2. Bit 4 for client 1 logical 3. Bit 5 for client 1 logical 4. Bit 6 for client 2. Bit 7 for client 3. Bit 8 for client 4.
#define BRB1_REG_READ_PRIORITY_0 0x60054UL //ACCESS:RW DataWidth:0x3 Description: Read client 0: Read priority
#define BRB1_REG_READ_PRIORITY_1 0x60058UL //ACCESS:RW DataWidth:0x3 Description: Read client 1: Read priority
#define BRB1_REG_READ_PRIORITY_2 0x6005cUL //ACCESS:RW DataWidth:0x3 Description: Read client 2: Read priority
#define BRB1_REG_READ_PRIORITY_3 0x60060UL //ACCESS:RW DataWidth:0x3 Description: Read client 3: Read priority
#define BRB1_REG_READ_PRIORITY_4 0x60064UL //ACCESS:RW DataWidth:0x3 Description: Read client 4: Read priority
#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068UL //ACCESS:RW DataWidth:0xa Description: Write client 0: Assert pause threshold. Not Functional
#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006cUL //ACCESS:RW DataWidth:0xa Description: Write client 0: Assert pause threshold. Not Functional
#define BRB1_REG_PAUSE_LOW_THRESHOLD_2 0x60070UL //ACCESS:RW DataWidth:0xa Description: Write client 0: Assert pause threshold. Not Functional
#define BRB1_REG_PAUSE_LOW_THRESHOLD_3 0x60074UL //ACCESS:RW DataWidth:0xa Description: Write client 0: Assert pause threshold. Not Functional
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078UL //ACCESS:RW DataWidth:0xa Description: Write client 0: De-assert pause threshold. Not Functional
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007cUL //ACCESS:RW DataWidth:0xa Description: Write client 0: De-assert pause threshold. Not Functional
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_2 0x60080UL //ACCESS:RW DataWidth:0xa Description: Write client 0: De-assert pause threshold. Not Functional
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_3 0x60084UL //ACCESS:RW DataWidth:0xa Description: Write client 0: De-assert pause threshold. Not Functional
#define BRB1_REG_BIG_RAM_INDIRECT 0x60088UL //ACCESS:RW DataWidth:0x2 Description: Indirect memory address
#define BRB1_REG_NUM_OF_FREE_BLOCKS 0x6008cUL //ACCESS:R DataWidth:0x18 Description: The number of free 256-byte blocks.
#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090UL //ACCESS:R DataWidth:0x18 Description: The number of full blocks.
#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094UL //ACCESS:R DataWidth:0x18 Description: The number of full blocks occpied by port.
#define BRB1_REG_PORT_NUM_OCC_BLOCKS_1 0x60098UL //ACCESS:R DataWidth:0x18 Description: The number of full blocks occpied by port.
#define BRB1_REG_PORT_NUM_OCC_BLOCKS_2 0x6009cUL //ACCESS:R DataWidth:0x18 Description: The number of full blocks occpied by port.
#define BRB1_REG_PORT_NUM_OCC_BLOCKS_3 0x600a0UL //ACCESS:R DataWidth:0x18 Description: The number of full blocks occpied by port.
#define BRB1_REG_PORT_NUM_OCC_BLOCKS_4 0x600a4UL //ACCESS:R DataWidth:0x18 Description: The number of full blocks occpied by port.
#define BRB1_REG_FULL_WRC_RC 0x600a8UL //ACCESS:R DataWidth:0xf Description: Full on read clients USDM_DP USDM_CTRL TSDM WRC4 WRC1 WRC0. See remark 5.
#define BRB1_REG_PRS_CRDT 0x600acUL //ACCESS:R DataWidth:0xb Description: Parser credit
#define BRB1_REG_PEND_REQ 0x600b0UL //ACCESS:R DataWidth:0x12 Description: Pending requests. 2 bits per each client. Order is from msb to lsb USDM_DP; USDM_CTRL; TSDM_CTRL; CAC; PRS.
#define BRB1_REG_MAXIMUM_NUMBER_OF_FULL_BLOCKS 0x600b4UL //ACCESS:RC DataWidth:0xb Description: The maximum number of occupied block in the time interval between two RBC reads. This field is cleared-on-read.
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the pause signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bcUL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the pause signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the pause signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the pause signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the write_full signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600ccUL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the write_full signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the write_full signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the write_full signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the write_full signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_SOFT_RESET 0x600dcUL //ACCESS:RW DataWidth:0x1 Description: Reset the design by software.
#define BRB1_REG_PORT_0_GUARANTIED 0x600e0UL //ACCESS:RW DataWidth:0xa Description: The number of blocks guarantied for port 0. Not Functional
#define BRB1_REG_PORT_1_GUARANTIED 0x600e4UL //ACCESS:RW DataWidth:0xa Description: The number of blocks guarantied for port 1. Not Functional
#define BRB1_REG_PORT_2_GUARANTIED 0x600e8UL //ACCESS:RW DataWidth:0xa Description: The number of blocks guarantied for port 2. Not Functional
#define BRB1_REG_PORT_3_GUARANTIED 0x600ecUL //ACCESS:RW DataWidth:0xa Description: The number of blocks guarantied for port 3. Not Functional
#define BRB1_REG_PORT_4_GUARANTIED 0x600f0UL //ACCESS:RW DataWidth:0xa Description: The number of blocks guarantied for port 4. Not Functional
#define BRB1_REG_BRB_SIZE 0x600f4UL //ACCESS:RW DataWidth:0xb Description: The number of blocks in the BRB. Not Functional
#define BRB1_REG_DELTA 0x600f8UL //ACCESS:RW DataWidth:0xa Description: The histeresis value. Not Functional
#define BRB1_REG_INPUT_BUFFER_ALMOST_FULL 0x600fcUL //ACCESS:RW DataWidth:0x4 Description: Number of free entries in the buffer of each write port.
#define BRB1_REG_M_SP_RAM_BL_TM 0x60100UL //ACCESS:RW DataWidth:0x5 Description: TM bits of BL RAM memory
#define BRB1_REG_M_SP_RAM_BR_TM 0x60104UL //ACCESS:RW DataWidth:0x5 Description: TM bits of BR RAM memory
#define BRB1_REG_LRAM_TMA 0x60108UL //ACCESS:RW DataWidth:0x5 Description: TMA port register
#define BRB1_REG_LRAM_TMB 0x6010cUL //ACCESS:RW DataWidth:0x5 Description: TMB port register
#define BRB1_REG_DBG_SELECT 0x60110UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from BRB1 to the DBG block) - for selecting a line to output to the DBG block
#define BRB1_REG_DBG_BYTE_ENABLE 0x60114UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from BRB1 to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define BRB1_REG_DBG_SHIFT 0x60118UL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from BRB1 to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define BRB1_REG_BRB1_INT_STS 0x6011cUL //ACCESS:R DataWidth:0x13 Description: Interrupt register #0 read
#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_0 (0x1<<1)
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_0_SIZE 1
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_10 (0x1<<2)
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_10_SIZE 2
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_11 (0x1<<3)
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_11_SIZE 3
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_12 (0x1<<4)
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_12_SIZE 4
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_13 (0x1<<5)
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_13_SIZE 5
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_14 (0x1<<6)
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_14_SIZE 6
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_2 (0x1<<7)
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_2_SIZE 7
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_3 (0x1<<8)
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_3_SIZE 8
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_4 (0x1<<9)
#define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_4_SIZE 9
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_0 (0x1<<10)
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_0_SIZE 10
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_10 (0x1<<11)
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_10_SIZE 11
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_11 (0x1<<12)
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_11_SIZE 12
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_12 (0x1<<13)
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_12_SIZE 13
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_13 (0x1<<14)
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_13_SIZE 14
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_14 (0x1<<15)
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_14_SIZE 15
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_2 (0x1<<16)
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_2_SIZE 16
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_3 (0x1<<17)
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_3_SIZE 17
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_4 (0x1<<18)
#define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_4_SIZE 18
#define BRB1_REG_BRB1_INT_STS_CLR 0x60120UL //ACCESS:RC DataWidth:0x13 Description: Interrupt register #0 read clear
#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_0 (0x1<<1)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_0_SIZE 1
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_10 (0x1<<2)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_10_SIZE 2
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_11 (0x1<<3)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_11_SIZE 3
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_12 (0x1<<4)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_12_SIZE 4
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_13 (0x1<<5)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_13_SIZE 5
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_14 (0x1<<6)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_14_SIZE 6
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_2 (0x1<<7)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_2_SIZE 7
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_3 (0x1<<8)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_3_SIZE 8
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_4 (0x1<<9)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_4_SIZE 9
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_0 (0x1<<10)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_0_SIZE 10
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_10 (0x1<<11)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_10_SIZE 11
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_11 (0x1<<12)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_11_SIZE 12
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_12 (0x1<<13)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_12_SIZE 13
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_13 (0x1<<14)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_13_SIZE 14
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_14 (0x1<<15)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_14_SIZE 15
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_2 (0x1<<16)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_2_SIZE 16
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_3 (0x1<<17)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_3_SIZE 17
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_4 (0x1<<18)
#define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_4_SIZE 18
#define BRB1_REG_BRB1_INT_STS_WR 0x60124UL //ACCESS:WR DataWidth:0x13 Description: Interrupt register #0 bit set or clear
#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_0 (0x1<<1)
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_0_SIZE 1
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_10 (0x1<<2)
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_10_SIZE 2
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_11 (0x1<<3)
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_11_SIZE 3
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_12 (0x1<<4)
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_12_SIZE 4
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_13 (0x1<<5)
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_13_SIZE 5
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_14 (0x1<<6)
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_14_SIZE 6
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_2 (0x1<<7)
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_2_SIZE 7
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_3 (0x1<<8)
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_3_SIZE 8
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_4 (0x1<<9)
#define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_4_SIZE 9
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_0 (0x1<<10)
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_0_SIZE 10
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_10 (0x1<<11)
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_10_SIZE 11
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_11 (0x1<<12)
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_11_SIZE 12
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_12 (0x1<<13)
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_12_SIZE 13
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_13 (0x1<<14)
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_13_SIZE 14
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_14 (0x1<<15)
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_14_SIZE 15
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_2 (0x1<<16)
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_2_SIZE 16
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_3 (0x1<<17)
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_3_SIZE 17
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_4 (0x1<<18)
#define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_4_SIZE 18
#define BRB1_REG_BRB1_INT_MASK 0x60128UL //ACCESS:RW DataWidth:0x13 Description: Interrupt mask register #0 read/write
#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_0 (0x1<<1)
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_0_SIZE 1
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_10 (0x1<<2)
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_10_SIZE 2
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_11 (0x1<<3)
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_11_SIZE 3
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_12 (0x1<<4)
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_12_SIZE 4
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_13 (0x1<<5)
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_13_SIZE 5
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_14 (0x1<<6)
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_14_SIZE 6
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_2 (0x1<<7)
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_2_SIZE 7
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_3 (0x1<<8)
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_3_SIZE 8
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_4 (0x1<<9)
#define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_4_SIZE 9
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_0 (0x1<<10)
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_0_SIZE 10
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_10 (0x1<<11)
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_10_SIZE 11
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_11 (0x1<<12)
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_11_SIZE 12
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_12 (0x1<<13)
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_12_SIZE 13
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_13 (0x1<<14)
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_13_SIZE 14
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_14 (0x1<<15)
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_14_SIZE 15
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_2 (0x1<<16)
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_2_SIZE 16
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_3 (0x1<<17)
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_3_SIZE 17
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_4 (0x1<<18)
#define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_4_SIZE 18
#define BRB1_REG_BRB1_PRTY_STS 0x6012cUL //ACCESS:R DataWidth:0x4 Description: Parity register #0 read
#define BRB1_BRB1_PRTY_STS_REG_PARITY (0x1<<0)
#define BRB1_BRB1_PRTY_STS_REG_PARITY_SIZE 0
#define BRB1_BRB1_PRTY_STS_REG_BRAM_BL (0x1<<1)
#define BRB1_BRB1_PRTY_STS_REG_BRAM_BL_SIZE 1
#define BRB1_BRB1_PRTY_STS_REG_BRAM_BR (0x1<<2)
#define BRB1_BRB1_PRTY_STS_REG_BRAM_BR_SIZE 2
#define BRB1_BRB1_PRTY_STS_REG_LRAM (0x1<<3)
#define BRB1_BRB1_PRTY_STS_REG_LRAM_SIZE 3
#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130UL //ACCESS:RC DataWidth:0x4 Description: Parity register #0 read clear
#define BRB1_BRB1_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define BRB1_BRB1_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define BRB1_BRB1_PRTY_STS_CLR_REG_BRAM_BL (0x1<<1)
#define BRB1_BRB1_PRTY_STS_CLR_REG_BRAM_BL_SIZE 1
#define BRB1_BRB1_PRTY_STS_CLR_REG_BRAM_BR (0x1<<2)
#define BRB1_BRB1_PRTY_STS_CLR_REG_BRAM_BR_SIZE 2
#define BRB1_BRB1_PRTY_STS_CLR_REG_LRAM (0x1<<3)
#define BRB1_BRB1_PRTY_STS_CLR_REG_LRAM_SIZE 3
#define BRB1_REG_BRB1_PRTY_STS_WR 0x60134UL //ACCESS:WR DataWidth:0x4 Description: Parity register #0 bit set or clear
#define BRB1_BRB1_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define BRB1_BRB1_PRTY_STS_WR_REG_PARITY_SIZE 0
#define BRB1_BRB1_PRTY_STS_WR_REG_BRAM_BL (0x1<<1)
#define BRB1_BRB1_PRTY_STS_WR_REG_BRAM_BL_SIZE 1
#define BRB1_BRB1_PRTY_STS_WR_REG_BRAM_BR (0x1<<2)
#define BRB1_BRB1_PRTY_STS_WR_REG_BRAM_BR_SIZE 2
#define BRB1_BRB1_PRTY_STS_WR_REG_LRAM (0x1<<3)
#define BRB1_BRB1_PRTY_STS_WR_REG_LRAM_SIZE 3
#define BRB1_REG_BRB1_PRTY_MASK 0x60138UL //ACCESS:RW DataWidth:0x4 Description: Parity mask register #0 read/write
#define BRB1_BRB1_PRTY_MASK_REG_PARITY (0x1<<0)
#define BRB1_BRB1_PRTY_MASK_REG_PARITY_SIZE 0
#define BRB1_BRB1_PRTY_MASK_REG_BRAM_BL (0x1<<1)
#define BRB1_BRB1_PRTY_MASK_REG_BRAM_BL_SIZE 1
#define BRB1_BRB1_PRTY_MASK_REG_BRAM_BR (0x1<<2)
#define BRB1_BRB1_PRTY_MASK_REG_BRAM_BR_SIZE 2
#define BRB1_BRB1_PRTY_MASK_REG_LRAM (0x1<<3)
#define BRB1_BRB1_PRTY_MASK_REG_LRAM_SIZE 3
#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013cUL //ACCESS:RW DataWidth:0xa Description: The number of free blocks below which the High_llfc signal to interface #n is asserted. Not Functional
#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_1 0x60140UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks below which the High_llfc signal to interface #n is asserted. Not Functional
#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_2 0x60144UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks below which the High_llfc signal to interface #n is asserted. Not Functional
#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_3 0x60148UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks below which the High_llfc signal to interface #n is asserted. Not Functional
#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014cUL //ACCESS:RW DataWidth:0xa Description: The number of free blocks above which the High_llfc signal to interface #n is de-asserted. Not Functional
#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_1 0x60150UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks above which the High_llfc signal to interface #n is de-asserted. Not Functional
#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_2 0x60154UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks above which the High_llfc signal to interface #n is de-asserted. Not Functional
#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_3 0x60158UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks above which the High_llfc signal to interface #n is de-asserted. Not Functional
#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015cUL //ACCESS:RW DataWidth:0xa Description: The number of free blocks below which the Low_llfc signal to interface #n is asserted. Not Functional
#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_1 0x60160UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks below which the Low_llfc signal to interface #n is asserted. Not Functional
#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_2 0x60164UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks below which the Low_llfc signal to interface #n is asserted. Not Functional
#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_3 0x60168UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks below which the Low_llfc signal to interface #n is asserted. Not Functional
#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016cUL //ACCESS:RW DataWidth:0xa Description: The number of free blocks above which the Low_llfc signal to interface #n is de-asserted. Not Functional
#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_1 0x60170UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks above which the Low_llfc signal to interface #n is de-asserted. Not Functional
#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_2 0x60174UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks above which the Low_llfc signal to interface #n is de-asserted. Not Functional
#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_3 0x60178UL //ACCESS:RW DataWidth:0xa Description: The number of free blocks above which the Low_llfc signal to interface #n is de-asserted. Not Functional
#define BRB1_REG_NUM_OF_LLFC_HIGH_CYCLES_0 0x6017cUL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the llfc high signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_LLFC_HIGH_CYCLES_1 0x60180UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the llfc high signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_LLFC_HIGH_CYCLES_2 0x60184UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the llfc high signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_LLFC_HIGH_CYCLES_3 0x60188UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the llfc high signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_LLFC_LOW_CYCLES_0 0x6018cUL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the llfc low signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_LLFC_LOW_CYCLES_1 0x60190UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the llfc low signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_LLFC_LOW_CYCLES_2 0x60194UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the llfc low signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_NUM_OF_LLFC_LOW_CYCLES_3 0x60198UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the llfc low signal towards MAC #0 was asserted. Not Functional
#define BRB1_REG_M_SP_RAM_BM_TM 0x6019cUL //ACCESS:RW DataWidth:0x5 Description: TM bits of BM RAM memory
#define BRB1_REG_ECO_RESERVED 0x601a0UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO; when bit equal to 1: b0 -disable for parser IF bug 1 fix; b1- enable for state machine bug 1 fix; b2- disable for SDM Ifs bug1 fix; b3 - disable for bug2 fix
#define BRB1_REG_NUM_OF_PAUSE_0_CYCLES_0 0x601acUL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the pause signal towards MAC port class 0 was asserted.
#define BRB1_REG_NUM_OF_PAUSE_1_CYCLES_0 0x601b0UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the pause signal towards MAC port class 1 was asserted.
#define BRB1_REG_NUM_OF_FULL_0_CYCLES_0 0x601b4UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the full signal towards MAC port class 0 was asserted.
#define BRB1_REG_NUM_OF_FULL_1_CYCLES_0 0x601b8UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the full signal towards MAC port class 1 was asserted.
#define BRB1_REG_NUM_OF_FULL_LB_CYCLES 0x601bcUL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the full signal towards LB port was asserted.
#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks below which the pause signal to class 0 is asserted
#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks above which the pause signal to class 0 is de-asserted
#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks below which the pause signal to class 1 is asserted
#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601ccUL //ACCESS:RW DataWidth:0xb Description: The number of free blocks above which the pause signal to class 1 is de-asserted
#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks below which the full signal to class 0 is asserted
#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks above which the full signal to class 0 is de-asserted
#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks below which the full signal to class 1 is asserted
#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dcUL //ACCESS:RW DataWidth:0xb Description: The number of free blocks above which the full signal to class 1 is de-asserted
#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks below which the full signal to the LB port is asserted
#define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks above which the full signal to the LB port is de-asserted
#define BRB1_REG_MAC_GUARANTIED_0 0x601e8UL //ACCESS:RW DataWidth:0xb Description: The number of blocks guarantied for the MAC port. The register is applicable only when per_class_guaranty_mode is reset.
#define BRB1_REG_LB_GUARANTIED 0x601ecUL //ACCESS:RW DataWidth:0xb Description: The number of blocks guarantied for the LB port
#define BRB1_REG_BRB_EMPTY_THRESHOLD 0x601f0UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks above which the brb_empty signal to TSEMI is asserted
#define BRB1_REG_NUM_OF_PAUSE_0_CYCLES_1 0x60210UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the pause signal towards MAC port class 0 was asserted.
#define BRB1_REG_NUM_OF_PAUSE_1_CYCLES_1 0x60214UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the pause signal towards MAC port class 1 was asserted.
#define BRB1_REG_NUM_OF_FULL_0_CYCLES_1 0x60218UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the full signal towards MAC port class 0 was asserted.
#define BRB1_REG_NUM_OF_FULL_1_CYCLES_1 0x6021cUL //ACCESS:ST DataWidth:0x20 Description: The number of cycles that the full signal towards MAC port class 1 was asserted.
#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks below which the pause signal to class 0 is asserted
#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks above which the pause signal to class 0 is de-asserted
#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks below which the pause signal to class 1 is asserted
#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022cUL //ACCESS:RW DataWidth:0xb Description: The number of free blocks above which the pause signal to class 1 is de-asserted
#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks below which the full signal to class 0 is asserted
#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks above which the full signal to class 0 is de-asserted
#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238UL //ACCESS:RW DataWidth:0xb Description: The number of free blocks below which the full signal to class 1 is asserted
#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023cUL //ACCESS:RW DataWidth:0xb Description: The number of free blocks above which the full signal to class 1 is de-asserted
#define BRB1_REG_MAC_GUARANTIED_1 0x60240UL //ACCESS:RW DataWidth:0xb Description: The number of blocks guarantied for the MAC port. The register is applicable only when per_class_guaranty_mode is reset.
#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244UL //ACCESS:RW DataWidth:0xb Description: The number of blocks guarantied for class 0 in MAC 0. The register is applicable only when per_class_guaranty_mode is set.
#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248UL //ACCESS:RW DataWidth:0xb Description: The number of blocks guarantied for class 1 in MAC 0. The register is applicable only when per_class_guaranty_mode is set.
#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024cUL //ACCESS:RW DataWidth:0xb Description: The number of blocks guarantied for class 0in MAC1.The register is applicable only when per_class_guaranty_mode is set.
#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250UL //ACCESS:RW DataWidth:0xb Description: The number of blocks guarantied for class 1 in MAC 1. The register is applicable only when per_class_guaranty_mode is set.
#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254UL //ACCESS:RW DataWidth:0xb Description: The hysteresis on the guarantied buffer space for class 0 in MAC 1 before signaling XON. The register is applicable only when per_class_guaranty_mode is set.
#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258UL //ACCESS:RW DataWidth:0xb Description: The hysteresis on the guarantied buffer space for class 1in MAC 0 before signaling XON. The register is applicable only when per_class_guaranty_mode is set.
#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025cUL //ACCESS:RW DataWidth:0xb Description: The hysteresis on the guarantied buffer space for class 0 in MAC 1 before signaling XON. The register is applicable only when per_class_guaranty_mode is set.
#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260UL //ACCESS:RW DataWidth:0xb Description: The hysteresis on the guarantied buffer space for class 1 in MAC 1 before signaling XON. The register is applicable only when per_class_guaranty_mode is set.
#define BRB1_REG_LB_GUARANTIED_HYST 0x60264UL //ACCESS:RW DataWidth:0xb Description: The hysteresis on the guarantied buffer space for the Lb port before signaling XON.
#define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268UL //ACCESS:RW DataWidth:0x1 Description: Indicates if to use per-class guaranty mode (new mode) or per-MAC guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC mode). 1=per-class guaranty mode (new mode).
#define BRB1_REG_EMPTY_BACKWARD_MODE 0x6027cUL //ACCESS:RW DataWidth:0x1 Description: When reset then brb_empty signal will be set according to new E3_B0 formula. When set it will be used an old formula
#define BRB1_REG_SF_MODE_EN 0x60280UL //ACCESS:RW DataWidth:0x5 Description: Store and forward enable mode per port (b0 - mac port 0; b1 - mac port 1; b4 - LB port ). When it is set then NPM notification to parser will be transmitted after EOP inputs to BRB. When it is reset then it will be transmitted after header_size bytes or EOP inputs to BRTB.
#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200UL //ACCESS:RW DataWidth:0xb Description: At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning - following reset the first rbc access to this reg must be write; there can be no more rbc writes after the first one; there can be any number of rbc read following the first write; rbc access not following these rules will result in hang condition.
#define BRB1_REG_FREE_LIST_PRS_CRDT_SIZE 3
#define BRB1_REG_PORT_0_CLASS_0_NUM_OCC_BLOCKS 0x6026cUL //ACCESS:R DataWidth:0xb Description: The number of full blocks occpied by port0 class0 .
#define BRB1_REG_PORT_0_CLASS_0_NUM_OCC_BLOCKS_SIZE 1
#define BRB1_REG_PORT_0_CLASS_1_NUM_OCC_BLOCKS 0x60270UL //ACCESS:R DataWidth:0xb Description: The number of full blocks occpied by port0 class0 .
#define BRB1_REG_PORT_0_CLASS_1_NUM_OCC_BLOCKS_SIZE 1
#define BRB1_REG_PORT_1_CLASS_0_NUM_OCC_BLOCKS 0x60274UL //ACCESS:R DataWidth:0xb Description: The number of full blocks occpied by port0 class0 .
#define BRB1_REG_PORT_1_CLASS_0_NUM_OCC_BLOCKS_SIZE 1
#define BRB1_REG_PORT_1_CLASS_1_NUM_OCC_BLOCKS 0x60278UL //ACCESS:R DataWidth:0xb Description: The number of full blocks occpied by port0 class0 .
#define BRB1_REG_PORT_1_CLASS_1_NUM_OCC_BLOCKS_SIZE 1
#define BRB1_REG_LL_RAM 0x61000UL //ACCESS:RW DataWidth:0x18 Description: LL RAM data.
#define BRB1_REG_LL_RAM_SIZE 1024
#define BRB1_REG_BIG_RAM 0x70000UL //ACCESS:WB DataWidth:0x100 Description: Big RAM data; addressing uses 2 IND bits in item 33 as most significant bits.
#define BRB1_REG_BIG_RAM_SIZE 16384
#define BRB1_REG_BRB1_UNUSED_EMPTY_0 0x601a4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define BRB1_REG_BRB1_UNUSED_EMPTY_0_SIZE 2
#define BRB1_REG_BRB1_UNUSED_EMPTY_1 0x601f4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define BRB1_REG_BRB1_UNUSED_EMPTY_1_SIZE 3
#define BRB1_REG_BRB1_UNUSED_EMPTY_2 0x60284UL //ACCESS:R DataWidth:0x20 Unused empty space
#define BRB1_REG_BRB1_UNUSED_EMPTY_2_SIZE 863
#define BRB1_REG_BRB1_UNUSED_EMPTY_3 0x62000UL //ACCESS:R DataWidth:0x20 Unused empty space
#define BRB1_REG_BRB1_UNUSED_EMPTY_3_SIZE 14336
#define CCM_REG_INIT 0xd0000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0. For debug purposes only.
#define CCM_REG_CCM_STORM0_IFEN 0xd0004UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_CCM_STORM1_IFEN 0xd0008UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_CCM_CQM_IFEN 0xd000cUL //ACCESS:RW DataWidth:0x1 Description: CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_STORM_CCM_IFEN 0xd0010UL //ACCESS:RW DataWidth:0x1 Description: STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_CQM_CCM_IFEN 0xd0014UL //ACCESS:RW DataWidth:0x1 Description: QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_CSDM_IFEN 0xd0018UL //ACCESS:RW DataWidth:0x1 Description: Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_TSEM_IFEN 0xd001cUL //ACCESS:RW DataWidth:0x1 Description: Input tsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_XSEM_IFEN 0xd0020UL //ACCESS:RW DataWidth:0x1 Description: Input xsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_USEM_IFEN 0xd0024UL //ACCESS:RW DataWidth:0x1 Description: Input usem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_PBF_IFEN 0xd0028UL //ACCESS:RW DataWidth:0x1 Description: Input pbf Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_CDU_AG_WR_IFEN 0xd002cUL //ACCESS:RW DataWidth:0x1 Description: CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_CDU_AG_RD_IFEN 0xd0030UL //ACCESS:RW DataWidth:0x1 Description: CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_CDU_SM_WR_IFEN 0xd0034UL //ACCESS:RW DataWidth:0x1 Description: CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_CDU_SM_RD_IFEN 0xd0038UL //ACCESS:RW DataWidth:0x1 Description: CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_CCM_CFC_IFEN 0xd003cUL //ACCESS:RW DataWidth:0x1 Description: CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define CCM_REG_XX_MAX_LL_SZ 0xd0040UL //ACCESS:RW DataWidth:0x6 Description: Maximum link list size per connection in the XX protection.
#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044UL //ACCESS:RW DataWidth:0x8 Description: The Event ID; sent to the STORM in case of XX overflow.
#define CCM_REG_XX_MAX_NUM 0xd0048UL //ACCESS:RW DataWidth:0x5 Description: The maximum number of connections in the XX protection.
#define CCM_REG_N_SM_CTX_LD_0 0xd004cUL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_1 0xd0050UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_2 0xd0054UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_3 0xd0058UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_4 0xd005cUL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_5 0xd0060UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_6 0xd0064UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_7 0xd0068UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_8 0xd006cUL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_9 0xd0070UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_10 0xd0074UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_11 0xd0078UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_12 0xd007cUL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_13 0xd0080UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_14 0xd0084UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_N_SM_CTX_LD_15 0xd0088UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16).
#define CCM_REG_CQM_CCM_HDR_P 0xd008cUL //ACCESS:RW DataWidth:0x1c Description: The CM header value for QM request (primary).
#define CCM_REG_CQM_CCM_HDR_S 0xd0090UL //ACCESS:RW DataWidth:0x1c Description: The CM header value for QM request (secondary).
#define CCM_REG_ERR_CCM_HDR 0xd0094UL //ACCESS:RW DataWidth:0x1c Description: The CM header for QM formatting in case of an error in the QM inputs.
#define CCM_REG_ERR_EVNT_ID 0xd0098UL //ACCESS:RW DataWidth:0x8 Description: The Event ID in case the input message ErrorFlg is set.
#define CCM_REG_STORM_WEIGHT 0xd009cUL //ACCESS:RW DataWidth:0x3 Description: The weight of the STORM input in the WRR (Weighted Round robin) mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2 (more prioritised);etc.
#define CCM_REG_TSEM_WEIGHT 0xd00a0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input tsem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define CCM_REG_XSEM_WEIGHT 0xd00a4UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input xsem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define CCM_REG_USEM_WEIGHT 0xd00a8UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input usem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define CCM_REG_PBF_WEIGHT 0xd00acUL //ACCESS:RW DataWidth:0x3 Description: The weight of the input pbf in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define CCM_REG_CP_WEIGHT 0xd00b0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the CP input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define CCM_REG_CSDM_WEIGHT 0xd00b4UL //ACCESS:RW DataWidth:0x3 Description: The weight of the SDM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define CCM_REG_CQM_P_WEIGHT 0xd00b8UL //ACCESS:RW DataWidth:0x3 Description: The weight of the QM (primary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define CCM_REG_CQM_S_WEIGHT 0xd00bcUL //ACCESS:RW DataWidth:0x3 Description: The weight of the QM (secondary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define CCM_REG_CCM_CQM_USE_Q 0xd00c0UL //ACCESS:RW DataWidth:0x1 Description: If set the Q index; received from the QM is inserted to event ID. Otherwise 0 is inserted.
#define CCM_REG_CCM_REG0_SZ 0xd00c4UL //ACCESS:RW DataWidth:0x3 Description: The size of AG context region 0 in REG-pairs. Designates the MS REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). Is used to determine the number of the AG context REG-pairs written back; when the input message Reg1WbFlg isn't set.
#define CCM_REG_CNT_AUX1_Q 0xd00c8UL //ACCESS:RW DataWidth:0x2 Description: Auxillary counter flag Q number 1.
#define CCM_REG_CNT_AUX2_Q 0xd00ccUL //ACCESS:RW DataWidth:0x2 Description: Auxillary counter flag Q number 2.
#define CCM_REG_CNT_AUX3_Q 0xd00d0UL //ACCESS:RW DataWidth:0x2 Description: Auxillary counter flag Q number 3.
#define CCM_REG_CNT_AUX4_Q 0xd00d4UL //ACCESS:RW DataWidth:0x2 Description: Auxillary counter flag Q number 4.
#define CCM_REG_CNT_AUX5_Q 0xd00d8UL //ACCESS:RW DataWidth:0x2 Description: Auxillary counter flag Q number 5.
#define CCM_REG_CNT_AUX6_Q 0xd00dcUL //ACCESS:RW DataWidth:0x2 Description: Auxillary counter flag Q number 6.
#define CCM_REG_SLOW_PATH_INV_CNT_FLG_Q 0xd00e0UL //ACCESS:RW DataWidth:0x2 Description: Slow path invalid counter flag Q number.
#define CCM_REG_RST_RCVD_FLG_Q 0xd00e4UL //ACCESS:RW DataWidth:0x2 Description: RST received flag Q number.
#define CCM_REG_AUX1_FLG_Q 0xd00e8UL //ACCESS:RW DataWidth:0x2 Description: Aux 1 flag Q number.
#define CCM_REG_AUX2_FLG_Q 0xd00ecUL //ACCESS:RW DataWidth:0x2 Description: Aux 2 flag Q number.
#define CCM_REG_URSE_CNT_FLG_Q 0xd00f0UL //ACCESS:RW DataWidth:0x2 Description: ULP Rx SE counter flag.
#define CCM_REG_URINV_CNT_FLG_Q 0xd00f4UL //ACCESS:RW DataWidth:0x2 Description: ULP Rx Invalide counter flag.
#define CCM_REG_REL_SEQ_Q 0xd00f8UL //ACCESS:RW DataWidth:0x2 Description: Release sequence decision Q index.
#define CCM_REG_HQ_PROD_Q 0xd00fcUL //ACCESS:RW DataWidth:0x2 Description: HQ producer index.
#define CCM_REG_ORQ_UR_CONS_Q 0xd0100UL //ACCESS:RW DataWidth:0x2 Description: ORQ ULP Rx consumer index.
#define CCM_REG_RQ_UR_CONS_Q 0xd0104UL //ACCESS:RW DataWidth:0x2 Description: RQ consumer updated by ULP Rx index.
#define CCM_REG_INV_DONE_Q 0xd0108UL //ACCESS:RW DataWidth:0x2 Description: General flags index.
#define CCM_REG_AUX1_Q 0xd010cUL //ACCESS:RW DataWidth:0x2 Description: Auxillary flag Q number 1 index.
#define CCM_REG_AUX2_Q 0xd0110UL //ACCESS:RW DataWidth:0x2 Description: Auxillary flag Q number 2 index.
#define CCM_REG_SM_CTX0_TM 0xd014cUL //ACCESS:RW DataWidth:0x5 Description: Debug only. TM bits of STORM context.LSB.
#define CCM_REG_AG_CTX0_TM 0xd0150UL //ACCESS:RW DataWidth:0x5 Description: Debug only. TM bits of AG context.
#define CCM_REG_AG_CTX1_TM 0xd0154UL //ACCESS:RW DataWidth:0x5 Description: Debug only. TM bits of AG context.
#define CCM_REG_AG_CTX2_TM 0xd0158UL //ACCESS:RW DataWidth:0x5 Description: Debug only. TM bits of AG context.
#define CCM_REG_GR_ARB_TYPE 0xd015cUL //ACCESS:RW DataWidth:0x1 Description: Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; ~ccm_registers_gr_ld0_pr.gr_ld0_pr and ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and outputs to STORM: aggregation; load FIC0; load FIC1 and store.
#define CCM_REG_GR_AG_PR 0xd0160UL //ACCESS:RW DataWidth:0x2 Description: Aggregation channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed; that the Store channel priority is the compliment to 4 of the rest priorities - Aggregation channel; Load (FIC0) channel and Load (FIC1).
#define CCM_REG_GR_LD0_PR 0xd0164UL //ACCESS:RW DataWidth:0x2 Description: Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed; that the Store channel priority is the compliment to 4 of the rest priorities - Aggregation channel; Load (FIC0) channel and Load (FIC1).
#define CCM_REG_GR_LD1_PR 0xd0168UL //ACCESS:RW DataWidth:0x2 Description: Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed; that the Store channel priority is the compliment to 4 of the rest priorities - Aggregation channel; Load (FIC0) channel and Load (FIC1).
#define CCM_REG_STORM_LENGTH_MIS 0xd016cUL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the STORM interface is detected.
#define CCM_REG_CSDM_LENGTH_MIS 0xd0170UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the SDM interface is detected.
#define CCM_REG_TSEM_LENGTH_MIS 0xd0174UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the tsem interface is detected.
#define CCM_REG_XSEM_LENGTH_MIS 0xd0178UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the xsem interface is detected.
#define CCM_REG_USEM_LENGTH_MIS 0xd017cUL //ACCESS:RC DataWidth:0x1 Description: Set when message length mismatch (relative to last indication) at the usem interface is detected.
#define CCM_REG_PBF_LENGTH_MIS 0xd0180UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the pbf interface is detected.
#define CCM_REG_XX_FREE 0xd0184UL //ACCESS:R DataWidth:0x7 Description: Used to read the value of XX protection Free counter.
#define CCM_REG_CAM_OCCUP 0xd0188UL //ACCESS:R DataWidth:0x5 Description: Used to read the value of the XX protection CAM occupancy counter.
#define CCM_REG_UNLOCK_MISS 0xd018cUL //ACCESS:RC DataWidth:0x1 Description: Error; indicating the LCID to be unlocked from XX protection doesn't exist in LCID CAM.
#define CCM_REG_CQM_GLB_USE_CNTR 0xd0190UL //ACCESS:R DataWidth:0x1a Description: Used to read the QM global usage counter - the counter of QM requests still pending in the QM.
#define CCM_REG_CP_BUF_EMPTY 0xd0194UL //ACCESS:R DataWidth:0x1 Description: Indication of CP buffer is empty.
#define CCM_REG_CP_BUF_STATUS 0xd0198UL //ACCESS:R DataWidth:0x5 Description: CP buffer status.
#define CCM_REG_XX_OVFL_CNTR 0xd019cUL //ACCESS:ST DataWidth:0x10 Description: Counter of XX 0verflow occurencies.
#define CCM_REG_STORM_MSG_CNTR 0xd01a0UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the STORM input.
#define CCM_REG_CSDM_MSG_CNTR 0xd01a4UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input SDM.
#define CCM_REG_TSEM_MSG_CNTR 0xd01a8UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input tsem.
#define CCM_REG_XSEM_MSG_CNTR 0xd01acUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input xsem.
#define CCM_REG_USEM_MSG_CNTR 0xd01b0UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input usem.
#define CCM_REG_PBF_MSG_CNTR 0xd01b4UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input pbf.
#define CCM_REG_CP_MSG_CNTR 0xd01b8UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the CP input.
#define CCM_REG_CQM_P_MSG_CNTR 0xd01bcUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the QM input (primary).
#define CCM_REG_CQM_S_MSG_CNTR 0xd01c0UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the QM input (secondary).
#define CCM_REG_STORM_OUT_CNTR 0xd01c4UL //ACCESS:ST DataWidth:0x18 Description: Counter of the output messages at FIC0 and FIC1 interfaces.
#define CCM_REG_CQM_OUT_CNTR 0xd01c8UL //ACCESS:ST DataWidth:0x18 Description: Counter of the output QM commands.
#define CCM_REG_DBG_SELECT 0xd01ccUL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from CCM to the DBG block) - for selecting a line to output to the DBG block.
#define CCM_REG_DBG_BYTE_ENABLE 0xd01d0UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from CCM to the DBG block) - for enabling bytes in the selected line (after the select; before the shift).
#define CCM_REG_DBG_SHIFT 0xd01d4UL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from CCM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define CCM_REG_CCM_INT_STS 0xd01d8UL //ACCESS:R DataWidth:0xb Description: Interrupt register #0 read
#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define CCM_CCM_INT_STS_REG_XX_UQ_ERR (0x1<<1)
#define CCM_CCM_INT_STS_REG_XX_UQ_ERR_SIZE 1
#define CCM_CCM_INT_STS_REG_STORM_ERR (0x1<<2)
#define CCM_CCM_INT_STS_REG_STORM_ERR_SIZE 2
#define CCM_CCM_INT_STS_REG_CSDM_ERR (0x1<<3)
#define CCM_CCM_INT_STS_REG_CSDM_ERR_SIZE 3
#define CCM_CCM_INT_STS_REG_TSEM_ERR (0x1<<4)
#define CCM_CCM_INT_STS_REG_TSEM_ERR_SIZE 4
#define CCM_CCM_INT_STS_REG_XSEM_ERR (0x1<<5)
#define CCM_CCM_INT_STS_REG_XSEM_ERR_SIZE 5
#define CCM_CCM_INT_STS_REG_USEM_ERR (0x1<<6)
#define CCM_CCM_INT_STS_REG_USEM_ERR_SIZE 6
#define CCM_CCM_INT_STS_REG_PBF_ERR (0x1<<7)
#define CCM_CCM_INT_STS_REG_PBF_ERR_SIZE 7
#define CCM_CCM_INT_STS_REG_CP0_ERR (0x1<<8)
#define CCM_CCM_INT_STS_REG_CP0_ERR_SIZE 8
#define CCM_CCM_INT_STS_REG_CP1_ERR (0x1<<9)
#define CCM_CCM_INT_STS_REG_CP1_ERR_SIZE 9
#define CCM_CCM_INT_STS_REG_UM_ERR (0x1<<10)
#define CCM_CCM_INT_STS_REG_UM_ERR_SIZE 10
#define CCM_REG_CCM_INT_STS_CLR 0xd01dcUL //ACCESS:RC DataWidth:0xb Description: Interrupt register #0 read clear
#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define CCM_CCM_INT_STS_CLR_REG_XX_UQ_ERR (0x1<<1)
#define CCM_CCM_INT_STS_CLR_REG_XX_UQ_ERR_SIZE 1
#define CCM_CCM_INT_STS_CLR_REG_STORM_ERR (0x1<<2)
#define CCM_CCM_INT_STS_CLR_REG_STORM_ERR_SIZE 2
#define CCM_CCM_INT_STS_CLR_REG_CSDM_ERR (0x1<<3)
#define CCM_CCM_INT_STS_CLR_REG_CSDM_ERR_SIZE 3
#define CCM_CCM_INT_STS_CLR_REG_TSEM_ERR (0x1<<4)
#define CCM_CCM_INT_STS_CLR_REG_TSEM_ERR_SIZE 4
#define CCM_CCM_INT_STS_CLR_REG_XSEM_ERR (0x1<<5)
#define CCM_CCM_INT_STS_CLR_REG_XSEM_ERR_SIZE 5
#define CCM_CCM_INT_STS_CLR_REG_USEM_ERR (0x1<<6)
#define CCM_CCM_INT_STS_CLR_REG_USEM_ERR_SIZE 6
#define CCM_CCM_INT_STS_CLR_REG_PBF_ERR (0x1<<7)
#define CCM_CCM_INT_STS_CLR_REG_PBF_ERR_SIZE 7
#define CCM_CCM_INT_STS_CLR_REG_CP0_ERR (0x1<<8)
#define CCM_CCM_INT_STS_CLR_REG_CP0_ERR_SIZE 8
#define CCM_CCM_INT_STS_CLR_REG_CP1_ERR (0x1<<9)
#define CCM_CCM_INT_STS_CLR_REG_CP1_ERR_SIZE 9
#define CCM_CCM_INT_STS_CLR_REG_UM_ERR (0x1<<10)
#define CCM_CCM_INT_STS_CLR_REG_UM_ERR_SIZE 10
#define CCM_REG_CCM_INT_STS_WR 0xd01e0UL //ACCESS:WR DataWidth:0xb Description: Interrupt register #0 bit set or clear
#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define CCM_CCM_INT_STS_WR_REG_XX_UQ_ERR (0x1<<1)
#define CCM_CCM_INT_STS_WR_REG_XX_UQ_ERR_SIZE 1
#define CCM_CCM_INT_STS_WR_REG_STORM_ERR (0x1<<2)
#define CCM_CCM_INT_STS_WR_REG_STORM_ERR_SIZE 2
#define CCM_CCM_INT_STS_WR_REG_CSDM_ERR (0x1<<3)
#define CCM_CCM_INT_STS_WR_REG_CSDM_ERR_SIZE 3
#define CCM_CCM_INT_STS_WR_REG_TSEM_ERR (0x1<<4)
#define CCM_CCM_INT_STS_WR_REG_TSEM_ERR_SIZE 4
#define CCM_CCM_INT_STS_WR_REG_XSEM_ERR (0x1<<5)
#define CCM_CCM_INT_STS_WR_REG_XSEM_ERR_SIZE 5
#define CCM_CCM_INT_STS_WR_REG_USEM_ERR (0x1<<6)
#define CCM_CCM_INT_STS_WR_REG_USEM_ERR_SIZE 6
#define CCM_CCM_INT_STS_WR_REG_PBF_ERR (0x1<<7)
#define CCM_CCM_INT_STS_WR_REG_PBF_ERR_SIZE 7
#define CCM_CCM_INT_STS_WR_REG_CP0_ERR (0x1<<8)
#define CCM_CCM_INT_STS_WR_REG_CP0_ERR_SIZE 8
#define CCM_CCM_INT_STS_WR_REG_CP1_ERR (0x1<<9)
#define CCM_CCM_INT_STS_WR_REG_CP1_ERR_SIZE 9
#define CCM_CCM_INT_STS_WR_REG_UM_ERR (0x1<<10)
#define CCM_CCM_INT_STS_WR_REG_UM_ERR_SIZE 10
#define CCM_REG_CCM_INT_MASK 0xd01e4UL //ACCESS:RW DataWidth:0xb Description: Interrupt mask register #0 read/write
#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define CCM_CCM_INT_MASK_REG_XX_UQ_ERR (0x1<<1)
#define CCM_CCM_INT_MASK_REG_XX_UQ_ERR_SIZE 1
#define CCM_CCM_INT_MASK_REG_STORM_ERR (0x1<<2)
#define CCM_CCM_INT_MASK_REG_STORM_ERR_SIZE 2
#define CCM_CCM_INT_MASK_REG_CSDM_ERR (0x1<<3)
#define CCM_CCM_INT_MASK_REG_CSDM_ERR_SIZE 3
#define CCM_CCM_INT_MASK_REG_TSEM_ERR (0x1<<4)
#define CCM_CCM_INT_MASK_REG_TSEM_ERR_SIZE 4
#define CCM_CCM_INT_MASK_REG_XSEM_ERR (0x1<<5)
#define CCM_CCM_INT_MASK_REG_XSEM_ERR_SIZE 5
#define CCM_CCM_INT_MASK_REG_USEM_ERR (0x1<<6)
#define CCM_CCM_INT_MASK_REG_USEM_ERR_SIZE 6
#define CCM_CCM_INT_MASK_REG_PBF_ERR (0x1<<7)
#define CCM_CCM_INT_MASK_REG_PBF_ERR_SIZE 7
#define CCM_CCM_INT_MASK_REG_CP0_ERR (0x1<<8)
#define CCM_CCM_INT_MASK_REG_CP0_ERR_SIZE 8
#define CCM_CCM_INT_MASK_REG_CP1_ERR (0x1<<9)
#define CCM_CCM_INT_MASK_REG_CP1_ERR_SIZE 9
#define CCM_CCM_INT_MASK_REG_UM_ERR (0x1<<10)
#define CCM_CCM_INT_MASK_REG_UM_ERR_SIZE 10
#define CCM_REG_CCM_PRTY_STS 0xd01e8UL //ACCESS:R DataWidth:0x1b Description: Parity register #0 read
#define CCM_CCM_PRTY_STS_REG_PARITY (0x1<<0)
#define CCM_CCM_PRTY_STS_REG_PARITY_SIZE 0
#define CCM_CCM_PRTY_STS_REG_XT_PRTY (0x1<<1)
#define CCM_CCM_PRTY_STS_REG_XT_PRTY_SIZE 1
#define CCM_CCM_PRTY_STS_REG_DT_PRTY (0x1<<2)
#define CCM_CCM_PRTY_STS_REG_DT_PRTY_SIZE 2
#define CCM_CCM_PRTY_STS_REG_PM_PRTY0 (0x1<<3)
#define CCM_CCM_PRTY_STS_REG_PM_PRTY0_SIZE 3
#define CCM_CCM_PRTY_STS_REG_PM_PRTY1 (0x1<<4)
#define CCM_CCM_PRTY_STS_REG_PM_PRTY1_SIZE 4
#define CCM_CCM_PRTY_STS_REG_UQ_PRTY (0x1<<5)
#define CCM_CCM_PRTY_STS_REG_UQ_PRTY_SIZE 5
#define CCM_CCM_PRTY_STS_REG_AG_PRTY0 (0x1<<6)
#define CCM_CCM_PRTY_STS_REG_AG_PRTY0_SIZE 6
#define CCM_CCM_PRTY_STS_REG_AG_PRTY1 (0x1<<7)
#define CCM_CCM_PRTY_STS_REG_AG_PRTY1_SIZE 7
#define CCM_CCM_PRTY_STS_REG_AG_PRTY2 (0x1<<8)
#define CCM_CCM_PRTY_STS_REG_AG_PRTY2_SIZE 8
#define CCM_CCM_PRTY_STS_REG_AG_PRTY3 (0x1<<9)
#define CCM_CCM_PRTY_STS_REG_AG_PRTY3_SIZE 9
#define CCM_CCM_PRTY_STS_REG_AG_PRTY4 (0x1<<10)
#define CCM_CCM_PRTY_STS_REG_AG_PRTY4_SIZE 10
#define CCM_CCM_PRTY_STS_REG_AG_PRTY5 (0x1<<11)
#define CCM_CCM_PRTY_STS_REG_AG_PRTY5_SIZE 11
#define CCM_CCM_PRTY_STS_REG_AG_PRTY6 (0x1<<12)
#define CCM_CCM_PRTY_STS_REG_AG_PRTY6_SIZE 12
#define CCM_CCM_PRTY_STS_REG_AG_PRTY7 (0x1<<13)
#define CCM_CCM_PRTY_STS_REG_AG_PRTY7_SIZE 13
#define CCM_CCM_PRTY_STS_REG_SM_PRTY0 (0x1<<14)
#define CCM_CCM_PRTY_STS_REG_SM_PRTY0_SIZE 14
#define CCM_CCM_PRTY_STS_REG_SM_PRTY1 (0x1<<15)
#define CCM_CCM_PRTY_STS_REG_SM_PRTY1_SIZE 15
#define CCM_CCM_PRTY_STS_REG_SM_PRTY2 (0x1<<16)
#define CCM_CCM_PRTY_STS_REG_SM_PRTY2_SIZE 16
#define CCM_CCM_PRTY_STS_REG_SM_PRTY3 (0x1<<17)
#define CCM_CCM_PRTY_STS_REG_SM_PRTY3_SIZE 17
#define CCM_CCM_PRTY_STS_REG_STORM_PRTY (0x1<<18)
#define CCM_CCM_PRTY_STS_REG_STORM_PRTY_SIZE 18
#define CCM_CCM_PRTY_STS_REG_CSDM_PRTY (0x1<<19)
#define CCM_CCM_PRTY_STS_REG_CSDM_PRTY_SIZE 19
#define CCM_CCM_PRTY_STS_REG_TSEM_PRTY (0x1<<20)
#define CCM_CCM_PRTY_STS_REG_TSEM_PRTY_SIZE 20
#define CCM_CCM_PRTY_STS_REG_XSEM_PRTY (0x1<<21)
#define CCM_CCM_PRTY_STS_REG_XSEM_PRTY_SIZE 21
#define CCM_CCM_PRTY_STS_REG_USEM_PRTY (0x1<<22)
#define CCM_CCM_PRTY_STS_REG_USEM_PRTY_SIZE 22
#define CCM_CCM_PRTY_STS_REG_PBF_PRTY (0x1<<23)
#define CCM_CCM_PRTY_STS_REG_PBF_PRTY_SIZE 23
#define CCM_CCM_PRTY_STS_REG_CP0_PRTY (0x1<<24)
#define CCM_CCM_PRTY_STS_REG_CP0_PRTY_SIZE 24
#define CCM_CCM_PRTY_STS_REG_CP1_PRTY (0x1<<25)
#define CCM_CCM_PRTY_STS_REG_CP1_PRTY_SIZE 25
#define CCM_CCM_PRTY_STS_REG_UM_PRTY (0x1<<26)
#define CCM_CCM_PRTY_STS_REG_UM_PRTY_SIZE 26
#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ecUL //ACCESS:RC DataWidth:0x1b Description: Parity register #0 read clear
#define CCM_CCM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define CCM_CCM_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define CCM_CCM_PRTY_STS_CLR_REG_XT_PRTY (0x1<<1)
#define CCM_CCM_PRTY_STS_CLR_REG_XT_PRTY_SIZE 1
#define CCM_CCM_PRTY_STS_CLR_REG_DT_PRTY (0x1<<2)
#define CCM_CCM_PRTY_STS_CLR_REG_DT_PRTY_SIZE 2
#define CCM_CCM_PRTY_STS_CLR_REG_PM_PRTY0 (0x1<<3)
#define CCM_CCM_PRTY_STS_CLR_REG_PM_PRTY0_SIZE 3
#define CCM_CCM_PRTY_STS_CLR_REG_PM_PRTY1 (0x1<<4)
#define CCM_CCM_PRTY_STS_CLR_REG_PM_PRTY1_SIZE 4
#define CCM_CCM_PRTY_STS_CLR_REG_UQ_PRTY (0x1<<5)
#define CCM_CCM_PRTY_STS_CLR_REG_UQ_PRTY_SIZE 5
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY0 (0x1<<6)
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY0_SIZE 6
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY1 (0x1<<7)
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY1_SIZE 7
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY2 (0x1<<8)
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY2_SIZE 8
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY3 (0x1<<9)
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY3_SIZE 9
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY4 (0x1<<10)
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY4_SIZE 10
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY5 (0x1<<11)
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY5_SIZE 11
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY6 (0x1<<12)
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY6_SIZE 12
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY7 (0x1<<13)
#define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY7_SIZE 13
#define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY0 (0x1<<14)
#define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY0_SIZE 14
#define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY1 (0x1<<15)
#define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY1_SIZE 15
#define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY2 (0x1<<16)
#define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY2_SIZE 16
#define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY3 (0x1<<17)
#define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY3_SIZE 17
#define CCM_CCM_PRTY_STS_CLR_REG_STORM_PRTY (0x1<<18)
#define CCM_CCM_PRTY_STS_CLR_REG_STORM_PRTY_SIZE 18
#define CCM_CCM_PRTY_STS_CLR_REG_CSDM_PRTY (0x1<<19)
#define CCM_CCM_PRTY_STS_CLR_REG_CSDM_PRTY_SIZE 19
#define CCM_CCM_PRTY_STS_CLR_REG_TSEM_PRTY (0x1<<20)
#define CCM_CCM_PRTY_STS_CLR_REG_TSEM_PRTY_SIZE 20
#define CCM_CCM_PRTY_STS_CLR_REG_XSEM_PRTY (0x1<<21)
#define CCM_CCM_PRTY_STS_CLR_REG_XSEM_PRTY_SIZE 21
#define CCM_CCM_PRTY_STS_CLR_REG_USEM_PRTY (0x1<<22)
#define CCM_CCM_PRTY_STS_CLR_REG_USEM_PRTY_SIZE 22
#define CCM_CCM_PRTY_STS_CLR_REG_PBF_PRTY (0x1<<23)
#define CCM_CCM_PRTY_STS_CLR_REG_PBF_PRTY_SIZE 23
#define CCM_CCM_PRTY_STS_CLR_REG_CP0_PRTY (0x1<<24)
#define CCM_CCM_PRTY_STS_CLR_REG_CP0_PRTY_SIZE 24
#define CCM_CCM_PRTY_STS_CLR_REG_CP1_PRTY (0x1<<25)
#define CCM_CCM_PRTY_STS_CLR_REG_CP1_PRTY_SIZE 25
#define CCM_CCM_PRTY_STS_CLR_REG_UM_PRTY (0x1<<26)
#define CCM_CCM_PRTY_STS_CLR_REG_UM_PRTY_SIZE 26
#define CCM_REG_CCM_PRTY_STS_WR 0xd01f0UL //ACCESS:WR DataWidth:0x1b Description: Parity register #0 bit set or clear
#define CCM_CCM_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define CCM_CCM_PRTY_STS_WR_REG_PARITY_SIZE 0
#define CCM_CCM_PRTY_STS_WR_REG_XT_PRTY (0x1<<1)
#define CCM_CCM_PRTY_STS_WR_REG_XT_PRTY_SIZE 1
#define CCM_CCM_PRTY_STS_WR_REG_DT_PRTY (0x1<<2)
#define CCM_CCM_PRTY_STS_WR_REG_DT_PRTY_SIZE 2
#define CCM_CCM_PRTY_STS_WR_REG_PM_PRTY0 (0x1<<3)
#define CCM_CCM_PRTY_STS_WR_REG_PM_PRTY0_SIZE 3
#define CCM_CCM_PRTY_STS_WR_REG_PM_PRTY1 (0x1<<4)
#define CCM_CCM_PRTY_STS_WR_REG_PM_PRTY1_SIZE 4
#define CCM_CCM_PRTY_STS_WR_REG_UQ_PRTY (0x1<<5)
#define CCM_CCM_PRTY_STS_WR_REG_UQ_PRTY_SIZE 5
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY0 (0x1<<6)
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY0_SIZE 6
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY1 (0x1<<7)
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY1_SIZE 7
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY2 (0x1<<8)
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY2_SIZE 8
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY3 (0x1<<9)
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY3_SIZE 9
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY4 (0x1<<10)
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY4_SIZE 10
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY5 (0x1<<11)
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY5_SIZE 11
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY6 (0x1<<12)
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY6_SIZE 12
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY7 (0x1<<13)
#define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY7_SIZE 13
#define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY0 (0x1<<14)
#define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY0_SIZE 14
#define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY1 (0x1<<15)
#define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY1_SIZE 15
#define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY2 (0x1<<16)
#define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY2_SIZE 16
#define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY3 (0x1<<17)
#define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY3_SIZE 17
#define CCM_CCM_PRTY_STS_WR_REG_STORM_PRTY (0x1<<18)
#define CCM_CCM_PRTY_STS_WR_REG_STORM_PRTY_SIZE 18
#define CCM_CCM_PRTY_STS_WR_REG_CSDM_PRTY (0x1<<19)
#define CCM_CCM_PRTY_STS_WR_REG_CSDM_PRTY_SIZE 19
#define CCM_CCM_PRTY_STS_WR_REG_TSEM_PRTY (0x1<<20)
#define CCM_CCM_PRTY_STS_WR_REG_TSEM_PRTY_SIZE 20
#define CCM_CCM_PRTY_STS_WR_REG_XSEM_PRTY (0x1<<21)
#define CCM_CCM_PRTY_STS_WR_REG_XSEM_PRTY_SIZE 21
#define CCM_CCM_PRTY_STS_WR_REG_USEM_PRTY (0x1<<22)
#define CCM_CCM_PRTY_STS_WR_REG_USEM_PRTY_SIZE 22
#define CCM_CCM_PRTY_STS_WR_REG_PBF_PRTY (0x1<<23)
#define CCM_CCM_PRTY_STS_WR_REG_PBF_PRTY_SIZE 23
#define CCM_CCM_PRTY_STS_WR_REG_CP0_PRTY (0x1<<24)
#define CCM_CCM_PRTY_STS_WR_REG_CP0_PRTY_SIZE 24
#define CCM_CCM_PRTY_STS_WR_REG_CP1_PRTY (0x1<<25)
#define CCM_CCM_PRTY_STS_WR_REG_CP1_PRTY_SIZE 25
#define CCM_CCM_PRTY_STS_WR_REG_UM_PRTY (0x1<<26)
#define CCM_CCM_PRTY_STS_WR_REG_UM_PRTY_SIZE 26
#define CCM_REG_CCM_PRTY_MASK 0xd01f4UL //ACCESS:RW DataWidth:0x1b Description: Parity mask register #0 read/write
#define CCM_CCM_PRTY_MASK_REG_PARITY (0x1<<0)
#define CCM_CCM_PRTY_MASK_REG_PARITY_SIZE 0
#define CCM_CCM_PRTY_MASK_REG_XT_PRTY (0x1<<1)
#define CCM_CCM_PRTY_MASK_REG_XT_PRTY_SIZE 1
#define CCM_CCM_PRTY_MASK_REG_DT_PRTY (0x1<<2)
#define CCM_CCM_PRTY_MASK_REG_DT_PRTY_SIZE 2
#define CCM_CCM_PRTY_MASK_REG_PM_PRTY0 (0x1<<3)
#define CCM_CCM_PRTY_MASK_REG_PM_PRTY0_SIZE 3
#define CCM_CCM_PRTY_MASK_REG_PM_PRTY1 (0x1<<4)
#define CCM_CCM_PRTY_MASK_REG_PM_PRTY1_SIZE 4
#define CCM_CCM_PRTY_MASK_REG_UQ_PRTY (0x1<<5)
#define CCM_CCM_PRTY_MASK_REG_UQ_PRTY_SIZE 5
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY0 (0x1<<6)
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY0_SIZE 6
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY1 (0x1<<7)
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY1_SIZE 7
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY2 (0x1<<8)
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY2_SIZE 8
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY3 (0x1<<9)
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY3_SIZE 9
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY4 (0x1<<10)
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY4_SIZE 10
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY5 (0x1<<11)
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY5_SIZE 11
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY6 (0x1<<12)
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY6_SIZE 12
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY7 (0x1<<13)
#define CCM_CCM_PRTY_MASK_REG_AG_PRTY7_SIZE 13
#define CCM_CCM_PRTY_MASK_REG_SM_PRTY0 (0x1<<14)
#define CCM_CCM_PRTY_MASK_REG_SM_PRTY0_SIZE 14
#define CCM_CCM_PRTY_MASK_REG_SM_PRTY1 (0x1<<15)
#define CCM_CCM_PRTY_MASK_REG_SM_PRTY1_SIZE 15
#define CCM_CCM_PRTY_MASK_REG_SM_PRTY2 (0x1<<16)
#define CCM_CCM_PRTY_MASK_REG_SM_PRTY2_SIZE 16
#define CCM_CCM_PRTY_MASK_REG_SM_PRTY3 (0x1<<17)
#define CCM_CCM_PRTY_MASK_REG_SM_PRTY3_SIZE 17
#define CCM_CCM_PRTY_MASK_REG_STORM_PRTY (0x1<<18)
#define CCM_CCM_PRTY_MASK_REG_STORM_PRTY_SIZE 18
#define CCM_CCM_PRTY_MASK_REG_CSDM_PRTY (0x1<<19)
#define CCM_CCM_PRTY_MASK_REG_CSDM_PRTY_SIZE 19
#define CCM_CCM_PRTY_MASK_REG_TSEM_PRTY (0x1<<20)
#define CCM_CCM_PRTY_MASK_REG_TSEM_PRTY_SIZE 20
#define CCM_CCM_PRTY_MASK_REG_XSEM_PRTY (0x1<<21)
#define CCM_CCM_PRTY_MASK_REG_XSEM_PRTY_SIZE 21
#define CCM_CCM_PRTY_MASK_REG_USEM_PRTY (0x1<<22)
#define CCM_CCM_PRTY_MASK_REG_USEM_PRTY_SIZE 22
#define CCM_CCM_PRTY_MASK_REG_PBF_PRTY (0x1<<23)
#define CCM_CCM_PRTY_MASK_REG_PBF_PRTY_SIZE 23
#define CCM_CCM_PRTY_MASK_REG_CP0_PRTY (0x1<<24)
#define CCM_CCM_PRTY_MASK_REG_CP0_PRTY_SIZE 24
#define CCM_CCM_PRTY_MASK_REG_CP1_PRTY (0x1<<25)
#define CCM_CCM_PRTY_MASK_REG_CP1_PRTY_SIZE 25
#define CCM_CCM_PRTY_MASK_REG_UM_PRTY (0x1<<26)
#define CCM_CCM_PRTY_MASK_REG_UM_PRTY_SIZE 26
#define CCM_REG_SM_CTX1_TM 0xd01f8UL //ACCESS:RW DataWidth:0x5 Description: Debug only. TM bits of STORM context. MSB.
#define CCM_REG_ECO_RESERVED 0xd01fcUL //ACCESS:RW DataWidth:0x8 Description: chicken bits
#define CCM_REG_IS_UM_TM 0xd0800UL //ACCESS:RW DataWidth:0x2 Description: Debug only. TM bits of input stage UM buffer.
#define CCM_REG_IS_STORM_TM 0xd0804UL //ACCESS:RW DataWidth:0x2 Description: Debug only. TM bits of input stage STORM buffer.
#define CCM_REG_PM_RAM_TM 0xd0808UL //ACCESS:RW DataWidth:0x2 Description: Debug only. TM bits of Pending Messages RAM.
#define CCM_REG_IS_USEM_TM 0xd080cUL //ACCESS:RW DataWidth:0x2 Description: Debug only. TM bits of USEM input stage..
#define CCM_REG_UM_FIC1_FORCE 0xd0818UL //ACCESS:RW DataWidth:0x1 Description: 0-messages unlocked from Pending messages RAM go to the FIC for which they were designated in input message; 1-messages unlocked from Pending messages RAM are forced to FIC1 whether they were destined to FIC0 or FIC1 in original message.
#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 0 with QOS equal 0 port index 0.
#define CCM_REG_QOS_PHYS_QNUM0_0_SIZE 1
#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 0 with QOS equal 0 port index 1.
#define CCM_REG_QOS_PHYS_QNUM0_1_SIZE 1
#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011cUL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 0 with QOS equal 1 port index 0.
#define CCM_REG_QOS_PHYS_QNUM1_0_SIZE 1
#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 0 with QOS equal 1 per port index 1.
#define CCM_REG_QOS_PHYS_QNUM1_1_SIZE 1
#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 0 with QOS equal 2 port index 0.
#define CCM_REG_QOS_PHYS_QNUM2_0_SIZE 1
#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 0 with QOS equal 2 port index 1.
#define CCM_REG_QOS_PHYS_QNUM2_1_SIZE 1
#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012cUL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 0 with QOS equal 3 port index 0.
#define CCM_REG_QOS_PHYS_QNUM3_0_SIZE 1
#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 0 with QOS equal 3 port index 1.
#define CCM_REG_QOS_PHYS_QNUM3_1_SIZE 1
#define CCM_REG_PHYS_QNUM1_0 0xd0134UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 1 per port index.
#define CCM_REG_PHYS_QNUM1_0_SIZE 1
#define CCM_REG_PHYS_QNUM1_1 0xd0138UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 1 per port index.
#define CCM_REG_PHYS_QNUM1_1_SIZE 1
#define CCM_REG_PHYS_QNUM2_0 0xd013cUL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 2 per port index.
#define CCM_REG_PHYS_QNUM2_0_SIZE 1
#define CCM_REG_PHYS_QNUM2_1 0xd0140UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 2 per port index.
#define CCM_REG_PHYS_QNUM2_1_SIZE 1
#define CCM_REG_PHYS_QNUM3_0 0xd0144UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 3 per port index.
#define CCM_REG_PHYS_QNUM3_0_SIZE 1
#define CCM_REG_PHYS_QNUM3_1 0xd0148UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number of queue number 3 per port index.
#define CCM_REG_PHYS_QNUM3_1_SIZE 1
#define CCM_REG_CAM_OCCUP_ST 0xd0200UL //ACCESS:RW DataWidth:0x5 Description: XX protection LCID CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.
#define CCM_REG_CAM_OCCUP_ST_SIZE 1
#define CCM_REG_CFC_INIT_CRD 0xd0204UL //ACCESS:RW DataWidth:0x4 Description: CFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 1 at start-up.
#define CCM_REG_CFC_INIT_CRD_SIZE 1
#define CCM_REG_CP_MSG 0xd0208UL //ACCESS:W DataWidth:0x20 Description: Indirect access to write the CP message.
#define CCM_REG_CP_MSG_SIZE 1
#define CCM_REG_CQM_INIT_CRD 0xd020cUL //ACCESS:RW DataWidth:0x6 Description: QM output initial credit. Max credit available - 32. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 32 at start-up.
#define CCM_REG_CQM_INIT_CRD_SIZE 1
#define CCM_REG_FIC0_INIT_CRD 0xd0210UL //ACCESS:RW DataWidth:0x8 Description: FIC0 output initial credit. Max credit available - 255. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up.
#define CCM_REG_FIC0_INIT_CRD_SIZE 1
#define CCM_REG_FIC1_INIT_CRD 0xd0214UL //ACCESS:RW DataWidth:0x8 Description: FIC1 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up.
#define CCM_REG_FIC1_INIT_CRD_SIZE 1
#define CCM_REG_GLB_CNT_STICKY 0xd0218UL //ACCESS:RW DataWidth:0x1a Description: QM global usage counter maximum sticky value.
#define CCM_REG_GLB_CNT_STICKY_SIZE 1
#define CCM_REG_LL_SZ_STICKY 0xd021cUL //ACCESS:RW DataWidth:0x6 Description: XX protection Link List maximum value ever reached sticky value for any connection. The write to the register is performed by the XX internal circuitry.
#define CCM_REG_LL_SZ_STICKY_SIZE 1
#define CCM_REG_XX_INIT_CRD 0xd0220UL //ACCESS:RW DataWidth:0x6 Description: Initial value for the credit counter; responsible for fulfilling of the Input Stage XX protection buffer by the XX protection pending messages. Max credit available - 127. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to maximum XX protected message size - 2 at start-up.
#define CCM_REG_XX_INIT_CRD_SIZE 1
#define CCM_REG_XX_MSG_NUM 0xd0224UL //ACCESS:RW DataWidth:0x7 Description: The maximum number of pending messages; which may be stored in XX protection. At write the ~ccm_registers_xx_free.xx_free counter is also written.
#define CCM_REG_XX_MSG_NUM_SIZE 1
#define CCM_REG_LCID_CAM_0 0xd0228UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_0_SIZE 1
#define CCM_REG_LCID_CAM_1 0xd022cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_1_SIZE 1
#define CCM_REG_LCID_CAM_2 0xd0230UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_2_SIZE 1
#define CCM_REG_LCID_CAM_3 0xd0234UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_3_SIZE 1
#define CCM_REG_LCID_CAM_4 0xd0238UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_4_SIZE 1
#define CCM_REG_LCID_CAM_5 0xd023cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_5_SIZE 1
#define CCM_REG_LCID_CAM_6 0xd0240UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_6_SIZE 1
#define CCM_REG_LCID_CAM_7 0xd0244UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_7_SIZE 1
#define CCM_REG_LCID_CAM_8 0xd0248UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_8_SIZE 1
#define CCM_REG_LCID_CAM_9 0xd024cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_9_SIZE 1
#define CCM_REG_LCID_CAM_10 0xd0250UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_10_SIZE 1
#define CCM_REG_LCID_CAM_11 0xd0254UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_11_SIZE 1
#define CCM_REG_LCID_CAM_12 0xd0258UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_12_SIZE 1
#define CCM_REG_LCID_CAM_13 0xd025cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_13_SIZE 1
#define CCM_REG_LCID_CAM_14 0xd0260UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_14_SIZE 1
#define CCM_REG_LCID_CAM_15 0xd0264UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_15_SIZE 1
#define CCM_REG_LCID_CAM_16 0xd0268UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_16_SIZE 1
#define CCM_REG_LCID_CAM_17 0xd026cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define CCM_REG_LCID_CAM_17_SIZE 1
#define CCM_REG_XX_TABLE 0xd0280UL //ACCESS:RW DataWidth:0x12 Description: Indirect access to the XX table of the XX protection mechanism. The fields are: [5:0] - tail pointer;[11:6] - Link List size;[17:12] - header pointer.
#define CCM_REG_XX_TABLE_SIZE 18
#define CCM_REG_XX_DESCR_TABLE 0xd0300UL //ACCESS:RW DataWidth:0x13 Description: Indirect access to the descriptor table of the XX protection mechanism. The fields are: [5:0] - message length; [12:6] - message pointer;[18:13] - next pointer.
#define CCM_REG_XX_DESCR_TABLE_SIZE 24
#define CCM_REG_XX_PEND_MSG 0xd0400UL //ACCESS:RW DataWidth:0x20 Description: Debug only. Indirect access to the Pending messages RAM of the XX protection mechanism. Bits [7:1] stand for row number; bit [0] stand for one of 2 REGs in the row.
#define CCM_REG_XX_PEND_MSG_SIZE 144
#define CCM_REG_AG_CTX 0xd4000UL //ACCESS:RW DataWidth:0x20 Description: Indirect access to AG context with 32-bits granularity. The bits [11:8] of the address should be the offset within the accessed LCID context; the bits [7:0] are the accessed LCID.Example: to write to REG3 LCID100. The RBC address should be 12'h364.
#define CCM_REG_AG_CTX_SIZE 2560
#define CCM_REG_STORM_CTX 0xd8000UL //ACCESS:RW DataWidth:0x20 Description: Indirect access to STORM context with 32-bits granularity. The bits [12:8] of the address should be the offset within the accessed LCID context; the bits [7:0] are the accessed LCID.Example: to write to REG10 LCID100. The RBC address should be 13'ha64.
#define CCM_REG_STORM_CTX_SIZE 8192
#define CCM_REG_DT_TM 0xd0810UL //ACCESS:R DataWidth:0x2 Description: Debug only. TM bits of Descriptor table.
#define CCM_REG_DT_TM_SIZE 2
#define CCM_REG_CCM_UNUSED_EMPTY_0 0xd0270UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CCM_REG_CCM_UNUSED_EMPTY_0_SIZE 4
#define CCM_REG_CCM_UNUSED_EMPTY_1 0xd081cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define CCM_REG_CCM_UNUSED_EMPTY_1_SIZE 3577
#define CDU_REG_CDU_CHK_MASK0 0x101000UL //ACCESS:RW DataWidth:0x18 Multi Field Register
#define CDU_CDU_CHK_MASK0_REG_CHECK_EN0 (0x3f<<0)
#define CDU_CDU_CHK_MASK0_REG_CHECK_EN0_SIZE 0
#define CDU_CDU_CHK_MASK0_REG_CHECK_EN1 (0x3f<<6)
#define CDU_CDU_CHK_MASK0_REG_CHECK_EN1_SIZE 6
#define CDU_CDU_CHK_MASK0_REG_CHECK_EN2 (0x3f<<12)
#define CDU_CDU_CHK_MASK0_REG_CHECK_EN2_SIZE 12
#define CDU_CDU_CHK_MASK0_REG_CHECK_EN3 (0x3f<<18)
#define CDU_CDU_CHK_MASK0_REG_CHECK_EN3_SIZE 18
#define CDU_REG_CDU_CHK_MASK1 0x101004UL //ACCESS:RW DataWidth:0x18 Multi Field Register
#define CDU_CDU_CHK_MASK1_REG_CHECK_EN4 (0x3f<<0)
#define CDU_CDU_CHK_MASK1_REG_CHECK_EN4_SIZE 0
#define CDU_CDU_CHK_MASK1_REG_CHECK_EN5 (0x3f<<6)
#define CDU_CDU_CHK_MASK1_REG_CHECK_EN5_SIZE 6
#define CDU_CDU_CHK_MASK1_REG_CHECK_EN6 (0x3f<<12)
#define CDU_CDU_CHK_MASK1_REG_CHECK_EN6_SIZE 12
#define CDU_CDU_CHK_MASK1_REG_CHECK_EN7 (0x3f<<18)
#define CDU_CDU_CHK_MASK1_REG_CHECK_EN7_SIZE 18
#define CDU_REG_CDU_CONTROL0 0x101008UL //ACCESS:RW DataWidth:0x9 Multi Field Register
#define CDU_CDU_CONTROL0_REG_PXP_ACTIVE (0x1<<0)
#define CDU_CDU_CONTROL0_REG_PXP_ACTIVE_SIZE 0
#define CDU_CDU_CONTROL0_REG_L1TT_SP (0x1<<1)
#define CDU_CDU_CONTROL0_REG_L1TT_SP_SIZE 1
#define CDU_CDU_CONTROL0_REG_MATT_SP (0x1<<2)
#define CDU_CDU_CONTROL0_REG_MATT_SP_SIZE 2
#define CDU_CDU_CONTROL0_REG_DISABLE_DIVIDER (0x1<<3)
#define CDU_CDU_CONTROL0_REG_DISABLE_DIVIDER_SIZE 3
#define CDU_CDU_CONTROL0_REG_MASK_ECC (0x1<<4)
#define CDU_CDU_CONTROL0_REG_MASK_ECC_SIZE 4
#define CDU_CDU_CONTROL0_REG_LDRESP_ADDR_DIS (0x1<<5)
#define CDU_CDU_CONTROL0_REG_LDRESP_ADDR_DIS_SIZE 5
#define CDU_CDU_CONTROL0_REG_DISABLE_INPUTS (0x1<<6)
#define CDU_CDU_CONTROL0_REG_DISABLE_INPUTS_SIZE 6
#define CDU_CDU_CONTROL0_REG_DISABLE_OUTPUTS (0x1<<7)
#define CDU_CDU_CONTROL0_REG_DISABLE_OUTPUTS_SIZE 7
#define CDU_CDU_CONTROL0_REG_MASK_PCIE (0x1<<8)
#define CDU_CDU_CONTROL0_REG_MASK_PCIE_SIZE 8
#define CDU_REG_CDU_CONTROL1 0x10100cUL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define CDU_CDU_CONTROL1_REG_LDBUF_THRESH (0x1f<<0)
#define CDU_CDU_CONTROL1_REG_LDBUF_THRESH_SIZE 0
#define CDU_CDU_CONTROL1_REG_WBBUF_THRESH (0x1f<<5)
#define CDU_CDU_CONTROL1_REG_WBBUF_THRESH_SIZE 5
#define CDU_CDU_CONTROL1_REG_WBDP_RDTHRESH (0x1f<<10)
#define CDU_CDU_CONTROL1_REG_WBDP_RDTHRESH_SIZE 10
#define CDU_CDU_CONTROL1_REG_LDDPRELAX (0x1<<15)
#define CDU_CDU_CONTROL1_REG_LDDPRELAX_SIZE 15
#define CDU_CDU_CONTROL1_REG_LDL1REQ_INTERGAP (0x1f<<16)
#define CDU_CDU_CONTROL1_REG_LDL1REQ_INTERGAP_SIZE 16
#define CDU_CDU_CONTROL1_REG_WBDPRELAX (0x1<<21)
#define CDU_CDU_CONTROL1_REG_WBDPRELAX_SIZE 21
#define CDU_CDU_CONTROL1_REG_WBL1REQ_INTERGAP (0x1f<<22)
#define CDU_CDU_CONTROL1_REG_WBL1REQ_INTERGAP_SIZE 22
#define CDU_REG_CDU_DEBUG 0x101010UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define CDU_CDU_DEBUG_REG_MASK_LD_EOP_ERR (0x1<<0)
#define CDU_CDU_DEBUG_REG_MASK_LD_EOP_ERR_SIZE 0
#define CDU_CDU_DEBUG_REG_DISABLE_MERGE (0x1<<1)
#define CDU_CDU_DEBUG_REG_DISABLE_MERGE_SIZE 1
#define CDU_CDU_DEBUG_REG_PXP_INIT_LDCREDIT (0x7<<2)
#define CDU_CDU_DEBUG_REG_PXP_INIT_LDCREDIT_SIZE 2
#define CDU_CDU_DEBUG_REG_PXP_INIT_LDCREDIT_SET (0x1<<5)
#define CDU_CDU_DEBUG_REG_PXP_INIT_LDCREDIT_SET_SIZE 5
#define CDU_CDU_DEBUG_REG_PXP_INIT_WBCREDIT (0x7<<6)
#define CDU_CDU_DEBUG_REG_PXP_INIT_WBCREDIT_SIZE 6
#define CDU_CDU_DEBUG_REG_PXP_INIT_WBCREDIT_SET (0x1<<9)
#define CDU_CDU_DEBUG_REG_PXP_INIT_WBCREDIT_SET_SIZE 9
#define CDU_REG_LD_L1_NUM_ERROR_DATA 0x101018UL //ACCESS:RC DataWidth:0x14 Description: logging of error data in case of a CDU load error:{iqcc_l1_regions;iqcc_l1_type;iqcc_l1_lcid}
#define CDU_REG_WB_L1_NUM_ERROR_DATA 0x10101cUL //ACCESS:RC DataWidth:0x14 Description: logging of error data in case of a CDU load error:{iqcc_l1_regions;iqcc_l1_type;iqcc_l1_lcid}
#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define CDU_CDU_GLOBAL_PARAMS_REG_CONTEXT_SIZE (0xfff<<0)
#define CDU_CDU_GLOBAL_PARAMS_REG_CONTEXT_SIZE_SIZE 0
#define CDU_CDU_GLOBAL_PARAMS_REG_BLOCK_WASTE (0xfff<<12)
#define CDU_CDU_GLOBAL_PARAMS_REG_BLOCK_WASTE_SIZE 12
#define CDU_CDU_GLOBAL_PARAMS_REG_NCIB (0xff<<24)
#define CDU_CDU_GLOBAL_PARAMS_REG_NCIB_SIZE 24
#define CDU_REG_DBG_SELECT 0x101024UL //ACCESS:RW DataWidth:0x8 Description: For dbgmux usage (debug data that goes from CDU to the DBG block) - for selecting a line to output to the DBG block
#define CDU_REG_DBG_BYTE_ENABLE 0x101028UL //ACCESS:RW DataWidth:0x8 Description: For dbgmux usage (debug data that goes from CDU to the DBG block) - for enabling bytes in the selected line (after the select and before the shift)
#define CDU_REG_DBG_SHIFT 0x10102cUL //ACCESS:RW DataWidth:0x3 Description: For dbgmux usage (debug data that goes from CDU to the DBG block) - for circular right shifting of the selected line (after the enabling)
#define CDU_REG_CDU_INT_STS 0x101030UL //ACCESS:R DataWidth:0x7 Description: Interrupt register #0 read
#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define CDU_CDU_INT_STS_REG_EOP_ERROR (0x1<<1)
#define CDU_CDU_INT_STS_REG_EOP_ERROR_SIZE 1
#define CDU_CDU_INT_STS_REG_LD_L1_NUM_ERROR (0x1<<2)
#define CDU_CDU_INT_STS_REG_LD_L1_NUM_ERROR_SIZE 2
#define CDU_CDU_INT_STS_REG_WB_L1_NUM_ERROR (0x1<<3)
#define CDU_CDU_INT_STS_REG_WB_L1_NUM_ERROR_SIZE 3
#define CDU_CDU_INT_STS_REG_BVALID_ERROR (0x1<<4)
#define CDU_CDU_INT_STS_REG_BVALID_ERROR_SIZE 4
#define CDU_CDU_INT_STS_REG_LDOFFSET_ERROR (0x1<<5)
#define CDU_CDU_INT_STS_REG_LDOFFSET_ERROR_SIZE 5
#define CDU_CDU_INT_STS_REG_WBOFFSET_ERROR (0x1<<6)
#define CDU_CDU_INT_STS_REG_WBOFFSET_ERROR_SIZE 6
#define CDU_REG_CDU_INT_STS_CLR 0x101034UL //ACCESS:RC DataWidth:0x7 Description: Interrupt register #0 read clear
#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define CDU_CDU_INT_STS_CLR_REG_EOP_ERROR (0x1<<1)
#define CDU_CDU_INT_STS_CLR_REG_EOP_ERROR_SIZE 1
#define CDU_CDU_INT_STS_CLR_REG_LD_L1_NUM_ERROR (0x1<<2)
#define CDU_CDU_INT_STS_CLR_REG_LD_L1_NUM_ERROR_SIZE 2
#define CDU_CDU_INT_STS_CLR_REG_WB_L1_NUM_ERROR (0x1<<3)
#define CDU_CDU_INT_STS_CLR_REG_WB_L1_NUM_ERROR_SIZE 3
#define CDU_CDU_INT_STS_CLR_REG_BVALID_ERROR (0x1<<4)
#define CDU_CDU_INT_STS_CLR_REG_BVALID_ERROR_SIZE 4
#define CDU_CDU_INT_STS_CLR_REG_LDOFFSET_ERROR (0x1<<5)
#define CDU_CDU_INT_STS_CLR_REG_LDOFFSET_ERROR_SIZE 5
#define CDU_CDU_INT_STS_CLR_REG_WBOFFSET_ERROR (0x1<<6)
#define CDU_CDU_INT_STS_CLR_REG_WBOFFSET_ERROR_SIZE 6
#define CDU_REG_CDU_INT_STS_WR 0x101038UL //ACCESS:WR DataWidth:0x7 Description: Interrupt register #0 bit set or clear
#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define CDU_CDU_INT_STS_WR_REG_EOP_ERROR (0x1<<1)
#define CDU_CDU_INT_STS_WR_REG_EOP_ERROR_SIZE 1
#define CDU_CDU_INT_STS_WR_REG_LD_L1_NUM_ERROR (0x1<<2)
#define CDU_CDU_INT_STS_WR_REG_LD_L1_NUM_ERROR_SIZE 2
#define CDU_CDU_INT_STS_WR_REG_WB_L1_NUM_ERROR (0x1<<3)
#define CDU_CDU_INT_STS_WR_REG_WB_L1_NUM_ERROR_SIZE 3
#define CDU_CDU_INT_STS_WR_REG_BVALID_ERROR (0x1<<4)
#define CDU_CDU_INT_STS_WR_REG_BVALID_ERROR_SIZE 4
#define CDU_CDU_INT_STS_WR_REG_LDOFFSET_ERROR (0x1<<5)
#define CDU_CDU_INT_STS_WR_REG_LDOFFSET_ERROR_SIZE 5
#define CDU_CDU_INT_STS_WR_REG_WBOFFSET_ERROR (0x1<<6)
#define CDU_CDU_INT_STS_WR_REG_WBOFFSET_ERROR_SIZE 6
#define CDU_REG_CDU_INT_MASK 0x10103cUL //ACCESS:RW DataWidth:0x7 Description: Interrupt mask register #0 read/write
#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define CDU_CDU_INT_MASK_REG_EOP_ERROR (0x1<<1)
#define CDU_CDU_INT_MASK_REG_EOP_ERROR_SIZE 1
#define CDU_CDU_INT_MASK_REG_LD_L1_NUM_ERROR (0x1<<2)
#define CDU_CDU_INT_MASK_REG_LD_L1_NUM_ERROR_SIZE 2
#define CDU_CDU_INT_MASK_REG_WB_L1_NUM_ERROR (0x1<<3)
#define CDU_CDU_INT_MASK_REG_WB_L1_NUM_ERROR_SIZE 3
#define CDU_CDU_INT_MASK_REG_BVALID_ERROR (0x1<<4)
#define CDU_CDU_INT_MASK_REG_BVALID_ERROR_SIZE 4
#define CDU_CDU_INT_MASK_REG_LDOFFSET_ERROR (0x1<<5)
#define CDU_CDU_INT_MASK_REG_LDOFFSET_ERROR_SIZE 5
#define CDU_CDU_INT_MASK_REG_WBOFFSET_ERROR (0x1<<6)
#define CDU_CDU_INT_MASK_REG_WBOFFSET_ERROR_SIZE 6
#define CDU_REG_CDU_PRTY_STS 0x101040UL //ACCESS:R DataWidth:0x5 Description: Parity register #0 read
#define CDU_CDU_PRTY_STS_REG_PARITY (0x1<<0)
#define CDU_CDU_PRTY_STS_REG_PARITY_SIZE 0
#define CDU_CDU_PRTY_STS_REG_CDUWBBUF_PAR_ERR (0x1<<1)
#define CDU_CDU_PRTY_STS_REG_CDUWBBUF_PAR_ERR_SIZE 1
#define CDU_CDU_PRTY_STS_REG_CDULDBUF_PAR_ERR (0x1<<2)
#define CDU_CDU_PRTY_STS_REG_CDULDBUF_PAR_ERR_SIZE 2
#define CDU_CDU_PRTY_STS_REG_MATT_PAR_ERR (0x1<<3)
#define CDU_CDU_PRTY_STS_REG_MATT_PAR_ERR_SIZE 3
#define CDU_CDU_PRTY_STS_REG_L1TT_PAR_ERR (0x1<<4)
#define CDU_CDU_PRTY_STS_REG_L1TT_PAR_ERR_SIZE 4
#define CDU_REG_CDU_PRTY_STS_CLR 0x101044UL //ACCESS:RC DataWidth:0x5 Description: Parity register #0 read clear
#define CDU_CDU_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define CDU_CDU_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define CDU_CDU_PRTY_STS_CLR_REG_CDUWBBUF_PAR_ERR (0x1<<1)
#define CDU_CDU_PRTY_STS_CLR_REG_CDUWBBUF_PAR_ERR_SIZE 1
#define CDU_CDU_PRTY_STS_CLR_REG_CDULDBUF_PAR_ERR (0x1<<2)
#define CDU_CDU_PRTY_STS_CLR_REG_CDULDBUF_PAR_ERR_SIZE 2
#define CDU_CDU_PRTY_STS_CLR_REG_MATT_PAR_ERR (0x1<<3)
#define CDU_CDU_PRTY_STS_CLR_REG_MATT_PAR_ERR_SIZE 3
#define CDU_CDU_PRTY_STS_CLR_REG_L1TT_PAR_ERR (0x1<<4)
#define CDU_CDU_PRTY_STS_CLR_REG_L1TT_PAR_ERR_SIZE 4
#define CDU_REG_CDU_PRTY_STS_WR 0x101048UL //ACCESS:WR DataWidth:0x5 Description: Parity register #0 bit set or clear
#define CDU_CDU_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define CDU_CDU_PRTY_STS_WR_REG_PARITY_SIZE 0
#define CDU_CDU_PRTY_STS_WR_REG_CDUWBBUF_PAR_ERR (0x1<<1)
#define CDU_CDU_PRTY_STS_WR_REG_CDUWBBUF_PAR_ERR_SIZE 1
#define CDU_CDU_PRTY_STS_WR_REG_CDULDBUF_PAR_ERR (0x1<<2)
#define CDU_CDU_PRTY_STS_WR_REG_CDULDBUF_PAR_ERR_SIZE 2
#define CDU_CDU_PRTY_STS_WR_REG_MATT_PAR_ERR (0x1<<3)
#define CDU_CDU_PRTY_STS_WR_REG_MATT_PAR_ERR_SIZE 3
#define CDU_CDU_PRTY_STS_WR_REG_L1TT_PAR_ERR (0x1<<4)
#define CDU_CDU_PRTY_STS_WR_REG_L1TT_PAR_ERR_SIZE 4
#define CDU_REG_CDU_PRTY_MASK 0x10104cUL //ACCESS:RW DataWidth:0x5 Description: Parity mask register #0 read/write
#define CDU_CDU_PRTY_MASK_REG_PARITY (0x1<<0)
#define CDU_CDU_PRTY_MASK_REG_PARITY_SIZE 0
#define CDU_CDU_PRTY_MASK_REG_CDUWBBUF_PAR_ERR (0x1<<1)
#define CDU_CDU_PRTY_MASK_REG_CDUWBBUF_PAR_ERR_SIZE 1
#define CDU_CDU_PRTY_MASK_REG_CDULDBUF_PAR_ERR (0x1<<2)
#define CDU_CDU_PRTY_MASK_REG_CDULDBUF_PAR_ERR_SIZE 2
#define CDU_CDU_PRTY_MASK_REG_MATT_PAR_ERR (0x1<<3)
#define CDU_CDU_PRTY_MASK_REG_MATT_PAR_ERR_SIZE 3
#define CDU_CDU_PRTY_MASK_REG_L1TT_PAR_ERR (0x1<<4)
#define CDU_CDU_PRTY_MASK_REG_L1TT_PAR_ERR_SIZE 4
#define CDU_REG_MF_MODE 0x101050UL //ACCESS:RW DataWidth:0x1 Description: when this bit is set the CDU operates in multifunction mode
#define CDU_REG_MEM_TM_PORTS 0x101054UL //ACCESS:RW DataWidth:0xa Description: TM Bits of memories: matt bits 1:0; l1tt_low0 bits 3:2; l1tt_low1 bits 5:4; l1tt_high0 bits 7:6; l1tt_high1 bits 9:8
#define CDU_REG_ECO_RESERVED 0x101058UL //ACCESS:RW DataWidth:0x8 Description: eco reserved register
#define CDU_REG_CDU_ATC_FLAGS 0x10105cUL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define CDU_CDU_ATC_FLAGS_REG_ATC_FLAGS_WB (0x7<<0)
#define CDU_CDU_ATC_FLAGS_REG_ATC_FLAGS_WB_SIZE 0
#define CDU_CDU_ATC_FLAGS_REG_ATC_FLAGS_LD (0x7<<3)
#define CDU_CDU_ATC_FLAGS_REG_ATC_FLAGS_LD_SIZE 3
#define CDU_REG_ERROR_DATA 0x101014UL //ACCESS:RW DataWidth:0x20 Description: logging of error data in case of a CDU load error: {expected_cid[15:0];expected_type[2:0];expected_region[2:0];active_error;type_error;actual_active;actual_compressed_context};
#define CDU_REG_ERROR_DATA_SIZE 1
#define CDU_REG_MATT 0x101100UL //ACCESS:WB DataWidth:0x18 Description: MATT ram access. each entry has the following format:{RegionLength[11:0];RegionOffset[11:0]}
#define CDU_REG_MATT_SIZE 64
#define CDU_REG_L1TT 0x101800UL //ACCESS:WB DataWidth:0xd8 Description: L1TT ram access. each entry has the following format : {mrege_regions[7:0];offset12[5:0]...offset0[5:0];length12[5:0]...length0[5:0];id12[3:0]...id0[3:0]}
#define CDU_REG_L1TT_SIZE 512
#define CDU_REG_CDU_UNUSED_EMPTY_0 0x101060UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CDU_REG_CDU_UNUSED_EMPTY_0_SIZE 40
#define CDU_REG_CDU_UNUSED_EMPTY_1 0x101200UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CDU_REG_CDU_UNUSED_EMPTY_1_SIZE 384
#define CFC_REG_NUM_LCIDS_EMPTY 0x104000UL //ACCESS:R DataWidth:0x9 Description: Number of Empty LCIDs in Link List Block (not allocated)
#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004UL //ACCESS:R DataWidth:0x9 Description: Number of Arriving LCIDs in Link List Block
#define CFC_REG_NUM_LCIDS_INSIDE 0x104008UL //ACCESS:R DataWidth:0x9 Description: Number of Inside LCIDs in Link List Block
#define CFC_REG_NUM_LCIDS_INA 0x10400cUL //ACCESS:R DataWidth:0x9 Description: Number of Inside not active LCIDs in Link List Block
#define CFC_REG_NUM_LCIDS_INAS 0x104010UL //ACCESS:R DataWidth:0x9 Description: Number of Inside not active latency sensitive LCIDs in Link List Block
#define CFC_REG_NUM_LCIDS_INANS 0x104014UL //ACCESS:R DataWidth:0x9 Description: Number of Inside not active not sensitive LCIDs in Link List Block
#define CFC_REG_NUM_LCIDS_LEAVING 0x104018UL //ACCESS:R DataWidth:0x9 Description: Number of Leaving LCIDs in Link List Block
#define CFC_REG_NUM_LCIDS_IO 0x10401cUL //ACCESS:R DataWidth:0x9 Description: Number of Inside and Outside LCIDs in Link List Block
#define CFC_REG_NUM_LCIDS_ALLOC 0x104020UL //ACCESS:R DataWidth:0x9 Description: Number of allocated LCIDs which are at empty state
#define CFC_REG_LC_BLOCKED 0x104024UL //ACCESS:ST DataWidth:0x20 Description: statistics register that counts cycles in which load context requests were blocked
#define CFC_REG_CONTROL0 0x104028UL //ACCESS:RW DataWidth:0xf Multi Field Register
#define CFC_CONTROL0_REG_WB_THRESHOLD (0xff<<0)
#define CFC_CONTROL0_REG_WB_THRESHOLD_SIZE 0
#define CFC_CONTROL0_REG_STRING_CAM_DISABLE (0x1<<8)
#define CFC_CONTROL0_REG_STRING_CAM_DISABLE_SIZE 8
#define CFC_CONTROL0_REG_CID_CAM_DISABLE (0x1<<9)
#define CFC_CONTROL0_REG_CID_CAM_DISABLE_SIZE 9
#define CFC_CONTROL0_REG_NLOE (0x1<<10)
#define CFC_CONTROL0_REG_NLOE_SIZE 10
#define CFC_CONTROL0_REG_SCAM_SCRUB_HIT_EN (0x1<<11)
#define CFC_CONTROL0_REG_SCAM_SCRUB_HIT_EN_SIZE 11
#define CFC_CONTROL0_REG_SCAM_SCRUB_MISS_EN (0x1<<12)
#define CFC_CONTROL0_REG_SCAM_SCRUB_MISS_EN_SIZE 12
#define CFC_CONTROL0_REG_CCAM_SCRUB_HIT_EN (0x1<<13)
#define CFC_CONTROL0_REG_CCAM_SCRUB_HIT_EN_SIZE 13
#define CFC_CONTROL0_REG_CCAM_SCRUB_MISS_EN (0x1<<14)
#define CFC_CONTROL0_REG_CCAM_SCRUB_MISS_EN_SIZE 14
#define CFC_REG_MASK_REQUESTS 0x10402cUL //ACCESS:RW DataWidth:0x7 Multi Field Register
#define CFC_MASK_REQUESTS_REG_MASK_LCREQ (0x1<<0)
#define CFC_MASK_REQUESTS_REG_MASK_LCREQ_SIZE 0
#define CFC_MASK_REQUESTS_REG_MASK_SEARCH (0x1<<1)
#define CFC_MASK_REQUESTS_REG_MASK_SEARCH_SIZE 1
#define CFC_MASK_REQUESTS_REG_MASK_UPDATE (0x1<<2)
#define CFC_MASK_REQUESTS_REG_MASK_UPDATE_SIZE 2
#define CFC_MASK_REQUESTS_REG_MASK_WB (0x1<<3)
#define CFC_MASK_REQUESTS_REG_MASK_WB_SIZE 3
#define CFC_MASK_REQUESTS_REG_MASK_INACTIVATE (0x1<<4)
#define CFC_MASK_REQUESTS_REG_MASK_INACTIVATE_SIZE 4
#define CFC_MASK_REQUESTS_REG_MASK_CDULDRESP (0x1<<5)
#define CFC_MASK_REQUESTS_REG_MASK_CDULDRESP_SIZE 5
#define CFC_MASK_REQUESTS_REG_MASK_CDUWBRESP (0x1<<6)
#define CFC_MASK_REQUESTS_REG_MASK_CDUWBRESP_SIZE 6
#define CFC_REG_ERROR_DATA1 0x104030UL //ACCESS:R DataWidth:0x19 Description: when the CFC detects an internal error it updates these fields. {error_id[4:0];req_incval[3:0];ac_error_client[3:0];ac_error_lcid;error_id[3:0]}
#define CFC_REG_ERROR_DATA2 0x104034UL //ACCESS:R DataWidth:0x20 Description: {req_cid;req_taskid[7:4];req_type}
#define CFC_REG_ERROR_DATA3 0x104038UL //ACCESS:R DataWidth:0x20 Description: when the CFC detects an internal error it updates these fields. {req_regions;req_lcid;curr_lcid;ac_lcid}
#define CFC_REG_ERROR_VECTOR 0x10403cUL //ACCESS:R DataWidth:0x10 Description: CFC error vector. when the CFC detects an internal error it will set one of these bits. the bit description can be found in CFC specifications
#define CFC_REG_ERROR_MASK 0x104040UL //ACCESS:RW DataWidth:0x10 Description: masking for error logging. if a bit in this field is set then the corresponding bit in #cfc_registers_cfc_error_vector.error_vector will not be set
#define CFC_REG_DISABLE_ON_ERROR 0x104044UL //ACCESS:RW DataWidth:0x10 Description: indicates per error (in #cfc_registers_cfc_error_vector.cfc_error vector) whether the cfc should be disabled upon it
#define CFC_REG_ARBITERS_REG 0x104048UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define CFC_ARBITERS_REG_REG_SP_MARB_RR1 (0x1<<0)
#define CFC_ARBITERS_REG_REG_SP_MARB_RR1_SIZE 0
#define CFC_ARBITERS_REG_REG_SP_LCARB (0x1<<1)
#define CFC_ARBITERS_REG_REG_SP_LCARB_SIZE 1
#define CFC_ARBITERS_REG_REG_SP_MARB_RR2 (0x1<<2)
#define CFC_ARBITERS_REG_REG_SP_MARB_RR2_SIZE 2
#define CFC_ARBITERS_REG_REG_SP_MARB_RR3 (0x1<<3)
#define CFC_ARBITERS_REG_REG_SP_MARB_RR3_SIZE 3
#define CFC_ARBITERS_REG_REG_SP_AC_DEC (0x1<<4)
#define CFC_ARBITERS_REG_REG_SP_AC_DEC_SIZE 4
#define CFC_ARBITERS_REG_REG_SP_AC_INC (0x1<<5)
#define CFC_ARBITERS_REG_REG_SP_AC_INC_SIZE 5
#define CFC_REG_INIT_REG 0x10404cUL //ACCESS:RW DataWidth:0xb Multi Field Register
#define CFC_INIT_REG_REG_AC_INIT (0x1<<0)
#define CFC_INIT_REG_REG_AC_INIT_SIZE 0
#define CFC_INIT_REG_REG_LL_INIT_LAST_LCID (0xff<<1)
#define CFC_INIT_REG_REG_LL_INIT_LAST_LCID_SIZE 1
#define CFC_INIT_REG_REG_LL_INIT (0x1<<9)
#define CFC_INIT_REG_REG_LL_INIT_SIZE 9
#define CFC_INIT_REG_REG_CAM_INIT (0x1<<10)
#define CFC_INIT_REG_REG_CAM_INIT_SIZE 10
#define CFC_REG_DEBUG0 0x104050UL //ACCESS:RW DataWidth:0x1e Multi Field Register
#define CFC_DEBUG0_REG_DISABLE_INPUTS (0x1<<0)
#define CFC_DEBUG0_REG_DISABLE_INPUTS_SIZE 0
#define CFC_DEBUG0_REG_DISABLE_OUTPUTS (0x1<<1)
#define CFC_DEBUG0_REG_DISABLE_OUTPUTS_SIZE 1
#define CFC_DEBUG0_REG_AC_COUNTER_ZERO (0xff<<2)
#define CFC_DEBUG0_REG_AC_COUNTER_ZERO_SIZE 2
#define CFC_DEBUG0_REG_DELAY_CAM_RESP (0x1<<10)
#define CFC_DEBUG0_REG_DELAY_CAM_RESP_SIZE 10
#define CFC_DEBUG0_REG_AC_GRANT_PERIOD (0xf<<11)
#define CFC_DEBUG0_REG_AC_GRANT_PERIOD_SIZE 11
#define CFC_DEBUG0_REG_E_THRESHOLD (0x7<<15)
#define CFC_DEBUG0_REG_E_THRESHOLD_SIZE 15
#define CFC_DEBUG0_REG_INA_THRESHOLD (0x7<<18)
#define CFC_DEBUG0_REG_INA_THRESHOLD_SIZE 18
#define CFC_DEBUG0_REG_INANS_THRESHOLD (0x7<<21)
#define CFC_DEBUG0_REG_INANS_THRESHOLD_SIZE 21
#define CFC_DEBUG0_REG_INAS_THRESHOLD (0x7<<24)
#define CFC_DEBUG0_REG_INAS_THRESHOLD_SIZE 24
#define CFC_DEBUG0_REG_IO_THRESHOLD (0x7<<27)
#define CFC_DEBUG0_REG_IO_THRESHOLD_SIZE 27
#define CFC_REG_DEBUG1 0x104054UL //ACCESS:RW DataWidth:0xd Multi Field Register
#define CFC_DEBUG1_REG_MARB_THRESHOLD (0xf<<0)
#define CFC_DEBUG1_REG_MARB_THRESHOLD_SIZE 0
#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
#define CFC_DEBUG1_REG_MY_VAL_AC (0x1<<5)
#define CFC_DEBUG1_REG_MY_VAL_AC_SIZE 5
#define CFC_DEBUG1_REG_WVAL_AC (0x3<<6)
#define CFC_DEBUG1_REG_WVAL_AC_SIZE 6
#define CFC_DEBUG1_REG_TYPE_FROM_REQ1 (0x1<<8)
#define CFC_DEBUG1_REG_TYPE_FROM_REQ1_SIZE 8
#define CFC_DEBUG1_REG_TYPE_FROM_REQ2 (0x1<<9)
#define CFC_DEBUG1_REG_TYPE_FROM_REQ2_SIZE 9
#define CFC_DEBUG1_REG_SW_RESET (0x1<<10)
#define CFC_DEBUG1_REG_SW_RESET_SIZE 10
#define CFC_DEBUG1_REG_EN_ON_INT_CLR (0x1<<11)
#define CFC_DEBUG1_REG_EN_ON_INT_CLR_SIZE 11
#define CFC_DEBUG1_REG_UPD_CANCEL_DIS (0x1<<12)
#define CFC_DEBUG1_REG_UPD_CANCEL_DIS_SIZE 12
#define CFC_REG_INTERFACES 0x104058UL //ACCESS:RW DataWidth:0x1a Multi Field Register
#define CFC_INTERFACES_REG_LRESP_CREDIT (0x7<<0)
#define CFC_INTERFACES_REG_LRESP_CREDIT_SIZE 0
#define CFC_INTERFACES_REG_LRESP_CREDIT_SET (0x1<<3)
#define CFC_INTERFACES_REG_LRESP_CREDIT_SET_SIZE 3
#define CFC_INTERFACES_REG_PRSRESP_CREDIT (0x7<<4)
#define CFC_INTERFACES_REG_PRSRESP_CREDIT_SIZE 4
#define CFC_INTERFACES_REG_PRSRESP_CREDIT_SET (0x1<<7)
#define CFC_INTERFACES_REG_PRSRESP_CREDIT_SET_SIZE 7
#define CFC_INTERFACES_REG_SEARCH_CREDIT (0x7<<8)
#define CFC_INTERFACES_REG_SEARCH_CREDIT_SIZE 8
#define CFC_INTERFACES_REG_SEARCH_CREDIT_SET (0x1<<11)
#define CFC_INTERFACES_REG_SEARCH_CREDIT_SET_SIZE 11
#define CFC_INTERFACES_REG_CDULD_CREDIT (0xf<<12)
#define CFC_INTERFACES_REG_CDULD_CREDIT_SIZE 12
#define CFC_INTERFACES_REG_CDULD_CREDIT_SET (0x1<<16)
#define CFC_INTERFACES_REG_CDULD_CREDIT_SET_SIZE 16
#define CFC_INTERFACES_REG_CDUWB_CREDIT (0xf<<17)
#define CFC_INTERFACES_REG_CDUWB_CREDIT_SIZE 17
#define CFC_INTERFACES_REG_CDUWB_CREDIT_SET (0x1<<21)
#define CFC_INTERFACES_REG_CDUWB_CREDIT_SET_SIZE 21
#define CFC_INTERFACES_REG_LRESP6_CREDIT (0x7<<22)
#define CFC_INTERFACES_REG_LRESP6_CREDIT_SIZE 22
#define CFC_INTERFACES_REG_LRESP6_CREDIT_SET (0x1<<25)
#define CFC_INTERFACES_REG_LRESP6_CREDIT_SET_SIZE 25
#define CFC_REG_CID_CAM_CONTROL 0x10405cUL //ACCESS:RW DataWidth:0x16 Multi Field Register
#define CFC_CID_CAM_CONTROL_REG_CCAM_MASK_VECTOR (0xfffff<<0)
#define CFC_CID_CAM_CONTROL_REG_CCAM_MASK_VECTOR_SIZE 0
#define CFC_CID_CAM_CONTROL_REG_CCAM_SEARCH (0x1<<20)
#define CFC_CID_CAM_CONTROL_REG_CCAM_SEARCH_SIZE 20
#define CFC_CID_CAM_CONTROL_REG_CAM_125MHZ (0x1<<21)
#define CFC_CID_CAM_CONTROL_REG_CAM_125MHZ_SIZE 21
#define CFC_REG_SCAM_MASK_VECTOR0 0x104060UL //ACCESS:RW DataWidth:0x20 Description: string cam mask[31:0]. this mask is used for searches. 0 means ignore corresponding bit in search.
#define CFC_REG_SCAM_MASK_VECTOR1 0x104064UL //ACCESS:RW DataWidth:0x20 Description: string cam mask[63:32]. this mask is used for searches. 0 means ignore corresponding bit in search.
#define CFC_REG_SCAM_MASK_VECTOR2 0x104068UL //ACCESS:RW DataWidth:0x20 Description: string cam mask[95:64]. this mask is used for searches. 0 means ignore corresponding bit in search.
#define CFC_REG_SCAM_SEARCH 0x10406cUL //ACCESS:RW DataWidth:0x1 Description: when this bit is set writing to the scam will cause a search operation on the written item (written using ~cfc_registers_lcid_string_cam.string_cam interface. the write can be to any address
#define CFC_REG_SEARCH_RESULT 0x104070UL //ACCESS:R DataWidth:0x9 Description: {HIT;LCID}. HIT - if set then previous CAM seach item (either CCAM or SCAM) was found. LCID contains the result in case CAM search item (either CCAM or SCAM) was found
#define CFC_REG_LL_INIT_DONE 0x104074UL //ACCESS:R DataWidth:0x1 Description: indication the initializing the link list by the hardware was done.
#define CFC_REG_AC_INIT_DONE 0x104078UL //ACCESS:R DataWidth:0x1 Description: indication the initializing the activity counter by the hardware was done.
#define CFC_REG_CAM_INIT_DONE 0x10407cUL //ACCESS:R DataWidth:0x1 Description: indication the initializing the cams by the hardware was done.
#define CFC_REG_TASK_COUNTER 0x104080UL //ACCESS:ST DataWidth:0x20 Description: counts number of tasks done by the cfc
#define CFC_REG_LCREQ_WEIGHTS 0x104084UL //ACCESS:RW DataWidth:0x18 Description: {weight_load_client7[2:0] to weight_load_client0[2:0]}. this field allows changing the priorities of the weighted-round-robin arbiter which selects which CFC load client should be served next
#define CFC_REG_LOAD_CONTEXT_HITS_0 0x104088UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context hits
#define CFC_REG_LOAD_CONTEXT_HITS_1 0x10408cUL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context hits
#define CFC_REG_LOAD_CONTEXT_HITS_2 0x104090UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context hits
#define CFC_REG_LOAD_CONTEXT_HITS_3 0x104094UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context hits
#define CFC_REG_LOAD_CONTEXT_HITS_4 0x104098UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context hits
#define CFC_REG_LOAD_CONTEXT_HITS_5 0x10409cUL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context hits
#define CFC_REG_LOAD_CONTEXT_HITS_6 0x1040a0UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context hits
#define CFC_REG_LOAD_CONTEXT_HITS_7 0x1040a4UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context hits
#define CFC_REG_LOAD_CONTEXT_MISSES_0 0x1040a8UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context misses
#define CFC_REG_LOAD_CONTEXT_MISSES_1 0x1040acUL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context misses
#define CFC_REG_LOAD_CONTEXT_MISSES_2 0x1040b0UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context misses
#define CFC_REG_LOAD_CONTEXT_MISSES_3 0x1040b4UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context misses
#define CFC_REG_LOAD_CONTEXT_MISSES_4 0x1040b8UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context misses
#define CFC_REG_LOAD_CONTEXT_MISSES_5 0x1040bcUL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context misses
#define CFC_REG_LOAD_CONTEXT_MISSES_6 0x1040c0UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context misses
#define CFC_REG_LOAD_CONTEXT_MISSES_7 0x1040c4UL //ACCESS:ST DataWidth:0x20 Description: counts for each client the number of load context misses
#define CFC_REG_RFE_SEARCH_HITS 0x1040c8UL //ACCESS:ST DataWidth:0x20 Description: counts the number of RFE serach hits
#define CFC_REG_RFE_SEARCH_MISSES 0x1040ccUL //ACCESS:ST DataWidth:0x20 Description: counts the number of RFE serach misses
#define CFC_REG_CDU_WRITE_BACKS 0x1040d0UL //ACCESS:ST DataWidth:0x20 Description: counts the number of CDU write backs submitted by CFC
#define CFC_REG_CID_CAM_TM 0x1040d4UL //ACCESS:RW DataWidth:0xe Description: TM bits of cid cam memory
#define CFC_REG_STRING_CAM_TM 0x1040d8UL //ACCESS:RW DataWidth:0xe Description: TM bits of string cam memory
#define CFC_REG_LRAM_TM 0x1040dcUL //ACCESS:RW DataWidth:0x5 Description: TM bits of LCID ram memory
#define CFC_REG_LL1_TM 0x1040e0UL //ACCESS:RW DataWidth:0x5 Description: TM bits of LinkList1 memory
#define CFC_REG_LL2_TM 0x1040e4UL //ACCESS:RW DataWidth:0x5 Description: TM bits of LinkList2 memory
#define CFC_REG_DBG_SELECT 0x1040e8UL //ACCESS:RW DataWidth:0x8 Description: For dbgmux usage (debug data that goes from CFC to the DBG block) - for selecting a line to output to the DBG block
#define CFC_REG_DBG_BYTE_ENABLE 0x1040ecUL //ACCESS:RW DataWidth:0x8 Description: For dbgmux usage (debug data that goes from CFC to the DBG block) - for enabling bytes in the selected line (after the select and before the shift)
#define CFC_REG_DBG_SHIFT 0x1040f0UL //ACCESS:RW DataWidth:0x3 Description: For dbgmux usage (debug data that goes from CFC to the DBG block) - for circular right shifting of the selected line (after the enabling)
#define CFC_REG_CCAM_BIST_EN 0x1040f4UL //ACCESS:RW DataWidth:0x1 Description: CID CAM BIST
#define CFC_REG_SCAM_BIST_EN 0x1040f8UL //ACCESS:RW DataWidth:0x1 Description: STRING CAM BIST
#define CFC_REG_CFC_INT_STS 0x1040fcUL //ACCESS:R DataWidth:0x2 Description: Interrupt register #0 read
#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define CFC_CFC_INT_STS_REG_EXE_ERROR (0x1<<1)
#define CFC_CFC_INT_STS_REG_EXE_ERROR_SIZE 1
#define CFC_REG_CFC_INT_STS_CLR 0x104100UL //ACCESS:RC DataWidth:0x2 Description: Interrupt register #0 read clear
#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define CFC_CFC_INT_STS_CLR_REG_EXE_ERROR (0x1<<1)
#define CFC_CFC_INT_STS_CLR_REG_EXE_ERROR_SIZE 1
#define CFC_REG_CFC_INT_STS_WR 0x104104UL //ACCESS:WR DataWidth:0x2 Description: Interrupt register #0 bit set or clear
#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define CFC_CFC_INT_STS_WR_REG_EXE_ERROR (0x1<<1)
#define CFC_CFC_INT_STS_WR_REG_EXE_ERROR_SIZE 1
#define CFC_REG_CFC_INT_MASK 0x104108UL //ACCESS:RW DataWidth:0x2 Description: Interrupt mask register #0 read/write
#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define CFC_CFC_INT_MASK_REG_EXE_ERROR (0x1<<1)
#define CFC_CFC_INT_MASK_REG_EXE_ERROR_SIZE 1
#define CFC_REG_CFC_PRTY_STS 0x10410cUL //ACCESS:R DataWidth:0x6 Description: Parity register #0 read
#define CFC_CFC_PRTY_STS_REG_PARITY (0x1<<0)
#define CFC_CFC_PRTY_STS_REG_PARITY_SIZE 0
#define CFC_CFC_PRTY_STS_REG_LL_PAR_ERR (0x1<<1)
#define CFC_CFC_PRTY_STS_REG_LL_PAR_ERR_SIZE 1
#define CFC_CFC_PRTY_STS_REG_INFORAM_PAR_ERR (0x1<<2)
#define CFC_CFC_PRTY_STS_REG_INFORAM_PAR_ERR_SIZE 2
#define CFC_CFC_PRTY_STS_REG_AC_PAR_ERR (0x1<<3)
#define CFC_CFC_PRTY_STS_REG_AC_PAR_ERR_SIZE 3
#define CFC_CFC_PRTY_STS_REG_CCAM_PAR_ERR (0x1<<4)
#define CFC_CFC_PRTY_STS_REG_CCAM_PAR_ERR_SIZE 4
#define CFC_CFC_PRTY_STS_REG_SCAM_PAR_ERR (0x1<<5)
#define CFC_CFC_PRTY_STS_REG_SCAM_PAR_ERR_SIZE 5
#define CFC_REG_CFC_PRTY_STS_CLR 0x104110UL //ACCESS:RC DataWidth:0x6 Description: Parity register #0 read clear
#define CFC_CFC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define CFC_CFC_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define CFC_CFC_PRTY_STS_CLR_REG_LL_PAR_ERR (0x1<<1)
#define CFC_CFC_PRTY_STS_CLR_REG_LL_PAR_ERR_SIZE 1
#define CFC_CFC_PRTY_STS_CLR_REG_INFORAM_PAR_ERR (0x1<<2)
#define CFC_CFC_PRTY_STS_CLR_REG_INFORAM_PAR_ERR_SIZE 2
#define CFC_CFC_PRTY_STS_CLR_REG_AC_PAR_ERR (0x1<<3)
#define CFC_CFC_PRTY_STS_CLR_REG_AC_PAR_ERR_SIZE 3
#define CFC_CFC_PRTY_STS_CLR_REG_CCAM_PAR_ERR (0x1<<4)
#define CFC_CFC_PRTY_STS_CLR_REG_CCAM_PAR_ERR_SIZE 4
#define CFC_CFC_PRTY_STS_CLR_REG_SCAM_PAR_ERR (0x1<<5)
#define CFC_CFC_PRTY_STS_CLR_REG_SCAM_PAR_ERR_SIZE 5
#define CFC_REG_CFC_PRTY_STS_WR 0x104114UL //ACCESS:WR DataWidth:0x6 Description: Parity register #0 bit set or clear
#define CFC_CFC_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define CFC_CFC_PRTY_STS_WR_REG_PARITY_SIZE 0
#define CFC_CFC_PRTY_STS_WR_REG_LL_PAR_ERR (0x1<<1)
#define CFC_CFC_PRTY_STS_WR_REG_LL_PAR_ERR_SIZE 1
#define CFC_CFC_PRTY_STS_WR_REG_INFORAM_PAR_ERR (0x1<<2)
#define CFC_CFC_PRTY_STS_WR_REG_INFORAM_PAR_ERR_SIZE 2
#define CFC_CFC_PRTY_STS_WR_REG_AC_PAR_ERR (0x1<<3)
#define CFC_CFC_PRTY_STS_WR_REG_AC_PAR_ERR_SIZE 3
#define CFC_CFC_PRTY_STS_WR_REG_CCAM_PAR_ERR (0x1<<4)
#define CFC_CFC_PRTY_STS_WR_REG_CCAM_PAR_ERR_SIZE 4
#define CFC_CFC_PRTY_STS_WR_REG_SCAM_PAR_ERR (0x1<<5)
#define CFC_CFC_PRTY_STS_WR_REG_SCAM_PAR_ERR_SIZE 5
#define CFC_REG_CFC_PRTY_MASK 0x104118UL //ACCESS:RW DataWidth:0x6 Description: Parity mask register #0 read/write
#define CFC_CFC_PRTY_MASK_REG_PARITY (0x1<<0)
#define CFC_CFC_PRTY_MASK_REG_PARITY_SIZE 0
#define CFC_CFC_PRTY_MASK_REG_LL_PAR_ERR (0x1<<1)
#define CFC_CFC_PRTY_MASK_REG_LL_PAR_ERR_SIZE 1
#define CFC_CFC_PRTY_MASK_REG_INFORAM_PAR_ERR (0x1<<2)
#define CFC_CFC_PRTY_MASK_REG_INFORAM_PAR_ERR_SIZE 2
#define CFC_CFC_PRTY_MASK_REG_AC_PAR_ERR (0x1<<3)
#define CFC_CFC_PRTY_MASK_REG_AC_PAR_ERR_SIZE 3
#define CFC_CFC_PRTY_MASK_REG_CCAM_PAR_ERR (0x1<<4)
#define CFC_CFC_PRTY_MASK_REG_CCAM_PAR_ERR_SIZE 4
#define CFC_CFC_PRTY_MASK_REG_SCAM_PAR_ERR (0x1<<5)
#define CFC_CFC_PRTY_MASK_REG_SCAM_PAR_ERR_SIZE 5
#define CFC_REG_EXEC_ERROR_PF 0x10412cUL //ACCESS:R DataWidth:0x3 Description: Debug Only. The PF that generated the last execution error.
#define CFC_REG_TM_AC 0x107000UL //ACCESS:RW DataWidth:0x2 Description: tm bits for ram_256x14
#define CFC_REG_ECO_RESERVED 0x107004UL //ACCESS:RW DataWidth:0x8 Description: eco reserved. bit0: when set use new equation for last_free_lcid using threshold values. Bit1: when clear (default) use the LL_IO pop PFID to recover the correct Not-Empty PF counter.
#define CFC_REG_TM_LL_RAM_PREV 0x107008UL //ACCESS:RW DataWidth:0x2 Description: tm bits for ll_ram_prev
#define CFC_REG_TM_LL_RAM_NEXT 0x10700cUL //ACCESS:RW DataWidth:0x2 Description: tm bits for rll_ram_next
#define CFC_REG_DORQ_MASK_VALERR 0x107010UL //ACCESS:RW DataWidth:0x1 Description: Indicates if DORQ Validation Error (CDU Error#2) is masked (independent of cfc_error_mask)
#define CFC_REG_DORQ_MASK_PCIERR 0x107014UL //ACCESS:RW DataWidth:0x1 Description: Indicates if DORQ PCIe Error (CDU Error#1) is masked (independent of cfc_error_mask)
#define CFC_REG_SCAM_MASK_VECTOR3 0x107018UL //ACCESS:RW DataWidth:0xf Description: string cam mask[110:96]. this mask is used for searches. 0 means ignore corresponding bit in search. (110:99 - Vlan; 98:96-pfid)
#define CFC_REG_INTERFACES2 0x10701cUL //ACCESS:RW DataWidth:0xb Multi Field Register
#define CFC_INTERFACES2_REG_LRESP8_CREDIT (0xf<<0)
#define CFC_INTERFACES2_REG_LRESP8_CREDIT_SIZE 0
#define CFC_INTERFACES2_REG_LRESP8_CREDIT_SET (0x1<<4)
#define CFC_INTERFACES2_REG_LRESP8_CREDIT_SET_SIZE 4
#define CFC_INTERFACES2_REG_CDULD_CREDIT_E3 (0x1f<<5)
#define CFC_INTERFACES2_REG_CDULD_CREDIT_E3_SIZE 5
#define CFC_INTERFACES2_REG_CDULD_CREDIT_SET_E3 (0x1<<10)
#define CFC_INTERFACES2_REG_CDULD_CREDIT_SET_E3_SIZE 10
#define CFC_REG_NEMPTY_SIZE_PF 0x10411cUL //ACCESS:RW DataWidth:0x9 SPLIT:8 Description: the size of the Not Empty Link List is set accordingly per PF
#define CFC_REG_NEMPTY_SIZE_PF_SIZE 1
#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120UL //ACCESS:RW DataWidth:0x9 SPLIT:8 Description: Number of Inside LCIDs in Link List Block per PF
#define CFC_REG_NUM_LCIDS_INSIDE_PF_SIZE 1
#define CFC_REG_WEAK_ENABLE_PF 0x104124UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: This bit when clear will cause a load-cancel response to a load request for PF and set an execution error. Set processes load requests normally.
#define CFC_REG_WEAK_ENABLE_PF_SIZE 1
#define CFC_REG_STRONG_ENABLE_PF 0x104128UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for PF. The PFID that caused the execution error will be stored (exec_error_pf)
#define CFC_REG_STRONG_ENABLE_PF_SIZE 1
#define CFC_REG_SREQ_FULL_STICKY 0x104130UL //ACCESS:RW DataWidth:0x1 Description: The Interface to Searcher Request Queue has reached the maximum value (4)
#define CFC_REG_SREQ_FULL_STICKY_SIZE 1
#define CFC_REG_PRSRESP_FULL_STICKY 0x104134UL //ACCESS:RW DataWidth:0x1 Description: The Interface to Parser Response Queue has reached the maximum value (6)
#define CFC_REG_PRSRESP_FULL_STICKY_SIZE 1
#define CFC_REG_DISABLE_ROBUSTWB_PF 0x104138UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Disable Robust WB change: When an inactivate request is processed do not move the LCID to Inactive state if any of the regions are in error state
#define CFC_REG_DISABLE_ROBUSTWB_PF_SIZE 1
#define CFC_REG_CCAM_BIST_DBG_SEL 0x10413cUL //ACCESS:RW DataWidth:0x8 Description: This registers selects the type of data present on bist_status bus
#define CFC_REG_CCAM_BIST_DBG_SEL_SIZE 1
#define CFC_REG_CCAM_BIST_STATUS 0x104140UL //ACCESS:R DataWidth:0x20 Description: Bist status from CAM
#define CFC_REG_CCAM_BIST_STATUS_SIZE 1
#define CFC_REG_SCAM_BIST_DBG_SEL 0x104144UL //ACCESS:RW DataWidth:0x8 Description: This registers selects the type of data present on bist_status bus
#define CFC_REG_SCAM_BIST_DBG_SEL_SIZE 1
#define CFC_REG_SCAM_BIST_STATUS 0x104148UL //ACCESS:R DataWidth:0x20 Description: Bist status from CAM
#define CFC_REG_SCAM_BIST_STATUS_SIZE 1
#define CFC_REG_DBG_OUT_DATA_LSB 0x10414cUL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from CFC to the DBG block) - The 32 lsb data that goes to the DBG block.
#define CFC_REG_DBG_OUT_DATA_LSB_SIZE 1
#define CFC_REG_DBG_OUT_DATA_MSB 0x104150UL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from CFC to the DBG block) - The 32 msb data that goes to the DBG block.
#define CFC_REG_DBG_OUT_DATA_MSB_SIZE 1
#define CFC_REG_DBG_OUT_FRAME 0x104154UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from CFC to the DBG block) - The 4 frame bits that goes to the DBG block. Bit0 is the frame of data byte0; Bit1 is the frame of data byte1; Bit2 is the frame of data byte2; Bit3 is the frame of data byte4
#define CFC_REG_DBG_OUT_FRAME_SIZE 1
#define CFC_REG_DBG_OUT_VALID 0x104158UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from CFC to the DBG block) - The 4 valid bits that goes to the DBG block. Bit0 validtes data byte0; Bit1 validates data byte1; Bit2 validates data byte2; Bit3 validates data byte4
#define CFC_REG_DBG_OUT_VALID_SIZE 1
#define CFC_REG_CCAM_BIST_DONE 0x104200UL //ACCESS:R DataWidth:0x1 Description: CID CAM BIST
#define CFC_REG_CCAM_BIST_DONE_SIZE 1
#define CFC_REG_CCAM_BIST_GO 0x104204UL //ACCESS:R DataWidth:0x1 Description: CID CAM BIST
#define CFC_REG_CCAM_BIST_GO_SIZE 1
#define CFC_REG_CCAM_S2_STATUS 0x104208UL //ACCESS:R DataWidth:0x20 Description: CID CAM BIST
#define CFC_REG_CCAM_S2_STATUS_SIZE 1
#define CFC_REG_CCAM_S3_STATUS 0x10420cUL //ACCESS:R DataWidth:0x20 Description: CID CAM BIST
#define CFC_REG_CCAM_S3_STATUS_SIZE 1
#define CFC_REG_CCAM_S5_STATUS 0x104210UL //ACCESS:R DataWidth:0x20 Description: CID CAM BIST
#define CFC_REG_CCAM_S5_STATUS_SIZE 1
#define CFC_REG_CCAM_S6_STATUS 0x104214UL //ACCESS:R DataWidth:0x20 Description: CID CAM BIST
#define CFC_REG_CCAM_S6_STATUS_SIZE 1
#define CFC_REG_CCAM_S8_STATUS 0x104218UL //ACCESS:R DataWidth:0x20 Description: CID CAM BIST
#define CFC_REG_CCAM_S8_STATUS_SIZE 1
#define CFC_REG_EMPTY_HEAD 0x10421cUL //ACCESS:RW DataWidth:0xb Description: the head of the empty Link List is set accordingly pfid;head
#define CFC_REG_EMPTY_HEAD_SIZE 1
#define CFC_REG_EMPTY_SIZE 0x104220UL //ACCESS:RW DataWidth:0x9 Description: the size of the empty Link List is set accordingly
#define CFC_REG_EMPTY_SIZE_SIZE 1
#define CFC_REG_EMPTY_TAIL 0x104224UL //ACCESS:RW DataWidth:0xb Description: the tail of the empty Link List is set accordingly pfid;tail
#define CFC_REG_EMPTY_TAIL_SIZE 1
#define CFC_REG_SCAM_BIST_DONE 0x104228UL //ACCESS:R DataWidth:0x1 Description: STRING CAM BIST
#define CFC_REG_SCAM_BIST_DONE_SIZE 1
#define CFC_REG_SCAM_BIST_GO 0x10422cUL //ACCESS:R DataWidth:0x1 Description: STRING CAM BIST
#define CFC_REG_SCAM_BIST_GO_SIZE 1
#define CFC_REG_SCAM_S2_STATUS 0x104230UL //ACCESS:R DataWidth:0x20 Description: STRING CAM BIST
#define CFC_REG_SCAM_S2_STATUS_SIZE 1
#define CFC_REG_SCAM_S3_STATUS 0x104234UL //ACCESS:R DataWidth:0x20 Description: STRING CAM BIST
#define CFC_REG_SCAM_S3_STATUS_SIZE 1
#define CFC_REG_SCAM_S5_STATUS 0x104238UL //ACCESS:R DataWidth:0x20 Description: STRING CAM BIST
#define CFC_REG_SCAM_S5_STATUS_SIZE 1
#define CFC_REG_SCAM_S6_STATUS 0x10423cUL //ACCESS:R DataWidth:0x20 Description: STRING CAM BIST
#define CFC_REG_SCAM_S6_STATUS_SIZE 1
#define CFC_REG_SCAM_S8_STATUS 0x104240UL //ACCESS:R DataWidth:0x20 Description: STRING CAM BIST
#define CFC_REG_SCAM_S8_STATUS_SIZE 1
#define CFC_REG_ACTIVITY_COUNTER 0x104400UL //ACCESS:RW DataWidth:0xd Description: activity counter ram access
#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
#define CFC_REG_CID_CAM 0x104800UL //ACCESS:RW DataWidth:0x15 Description: CID cam access (21:1 - Data;Valid - 0)
#define CFC_REG_CID_CAM_SIZE 256
#define CFC_REG_LINK_LIST 0x104c00UL //ACCESS:RW DataWidth:0x16 Description: Link List ram access; data = {prev_pfid;prev_lcid;next_pfid;next_lcid}
#define CFC_REG_LINK_LIST_SIZE 256
#define CFC_REG_INFO_RAM 0x105000UL //ACCESS:WB DataWidth:0x61 Description: LCID info ram access = {96-vpf;95:93-pfid;92:89-type;88:85-action;84-paddrv;83:20-paddr;19:4-rstates;3-lsf;2:0-lstate}
#define CFC_REG_INFO_RAM_SIZE 1024
#define CFC_REG_STRING_CAM 0x106000UL //ACCESS:WB DataWidth:0x70 Description: String cam access (111:100 - Vlan; 99:97-pfid; 96:1 - Data; 0 - Valid)
#define CFC_REG_STRING_CAM_SIZE 1024
#define CFC_REG_CFC_UNUSED_EMPTY_0 0x10415cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define CFC_REG_CFC_UNUSED_EMPTY_0_SIZE 41
#define CFC_REG_CFC_UNUSED_EMPTY_1 0x104244UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CFC_REG_CFC_UNUSED_EMPTY_1_SIZE 111
#define CFC_REG_CFC_UNUSED_EMPTY_2 0x107020UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CFC_REG_CFC_UNUSED_EMPTY_2_SIZE 1016
#define CSDM_REG_TIMER_TICK 0xc2000UL //ACCESS:RW DataWidth:0x20 Description: Tick for timer counter. Applicable only when ~csdm_registers_timer_tick_enable.timer_tick_enable =1
#define CSDM_REG_TIMERS_TICK_ENABLE 0xc2004UL //ACCESS:RW DataWidth:0x1 Description: Enable for tick counter.
#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the cfc_rsp lcid
#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200cUL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the completion counters.
#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for queue counters
#define CSDM_REG_PCK_END_MSG_START_ADDR 0xc2014UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the packet end message
#define CSDM_REG_COUNTERS_WRAP 0xc2018UL //ACCESS:RW DataWidth:0x1 Description: Indicates if the 204 statistics counters should stop counting when reaching an all-ones value or should wrap-around 0=stop counting 1=wrap-around.
#define CSDM_REG_CMP_COUNTER_MAX0 0xc201cUL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #0
#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #1
#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #2
#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #3
#define CSDM_REG_BRB1_ALMOST_FULL 0xc202cUL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from BRB1 in DMA_RSP block
#define CSDM_REG_PXP_ALMOST_FULL 0xc2030UL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from pxp in DMA_RSP block
#define CSDM_REG_PB_ALMOST_FULL 0xc2034UL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from PB in DMA_RSP block
#define CSDM_REG_AGG_INT_EVENT_0 0xc2038UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 0
#define CSDM_REG_AGG_INT_EVENT_1 0xc203cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 1
#define CSDM_REG_AGG_INT_EVENT_2 0xc2040UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 2
#define CSDM_REG_AGG_INT_EVENT_3 0xc2044UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 3
#define CSDM_REG_AGG_INT_EVENT_4 0xc2048UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 4
#define CSDM_REG_AGG_INT_EVENT_5 0xc204cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 5
#define CSDM_REG_AGG_INT_EVENT_6 0xc2050UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 6
#define CSDM_REG_AGG_INT_EVENT_7 0xc2054UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 7
#define CSDM_REG_AGG_INT_EVENT_8 0xc2058UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 8
#define CSDM_REG_AGG_INT_EVENT_9 0xc205cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 9
#define CSDM_REG_AGG_INT_EVENT_10 0xc2060UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 10
#define CSDM_REG_AGG_INT_EVENT_11 0xc2064UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 11
#define CSDM_REG_AGG_INT_EVENT_12 0xc2068UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 12
#define CSDM_REG_AGG_INT_EVENT_13 0xc206cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 13
#define CSDM_REG_AGG_INT_EVENT_14 0xc2070UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 14
#define CSDM_REG_AGG_INT_EVENT_15 0xc2074UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 15
#define CSDM_REG_AGG_INT_EVENT_16 0xc2078UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 16
#define CSDM_REG_AGG_INT_EVENT_17 0xc207cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 17
#define CSDM_REG_AGG_INT_EVENT_18 0xc2080UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 18
#define CSDM_REG_AGG_INT_EVENT_19 0xc2084UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 19
#define CSDM_REG_AGG_INT_EVENT_20 0xc2088UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 20
#define CSDM_REG_AGG_INT_EVENT_21 0xc208cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 21
#define CSDM_REG_AGG_INT_EVENT_22 0xc2090UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 22
#define CSDM_REG_AGG_INT_EVENT_23 0xc2094UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 23
#define CSDM_REG_AGG_INT_EVENT_24 0xc2098UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 24
#define CSDM_REG_AGG_INT_EVENT_25 0xc209cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 25
#define CSDM_REG_AGG_INT_EVENT_26 0xc20a0UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 26
#define CSDM_REG_AGG_INT_EVENT_27 0xc20a4UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 27
#define CSDM_REG_AGG_INT_EVENT_28 0xc20a8UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 28
#define CSDM_REG_AGG_INT_EVENT_29 0xc20acUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 29
#define CSDM_REG_AGG_INT_EVENT_30 0xc20b0UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 30
#define CSDM_REG_AGG_INT_EVENT_31 0xc20b4UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 31
#define CSDM_REG_AGG_INT_T_0 0xc20b8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 0
#define CSDM_REG_AGG_INT_T_1 0xc20bcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 1
#define CSDM_REG_AGG_INT_T_2 0xc20c0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 2
#define CSDM_REG_AGG_INT_T_3 0xc20c4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 3
#define CSDM_REG_AGG_INT_T_4 0xc20c8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 4
#define CSDM_REG_AGG_INT_T_5 0xc20ccUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 5
#define CSDM_REG_AGG_INT_T_6 0xc20d0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 6
#define CSDM_REG_AGG_INT_T_7 0xc20d4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 7
#define CSDM_REG_AGG_INT_T_8 0xc20d8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 8
#define CSDM_REG_AGG_INT_T_9 0xc20dcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 9
#define CSDM_REG_AGG_INT_T_10 0xc20e0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 10
#define CSDM_REG_AGG_INT_T_11 0xc20e4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 11
#define CSDM_REG_AGG_INT_T_12 0xc20e8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 12
#define CSDM_REG_AGG_INT_T_13 0xc20ecUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 13
#define CSDM_REG_AGG_INT_T_14 0xc20f0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 14
#define CSDM_REG_AGG_INT_T_15 0xc20f4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 15
#define CSDM_REG_AGG_INT_T_16 0xc20f8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 16
#define CSDM_REG_AGG_INT_T_17 0xc20fcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 17
#define CSDM_REG_AGG_INT_T_18 0xc2100UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 18
#define CSDM_REG_AGG_INT_T_19 0xc2104UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 19
#define CSDM_REG_AGG_INT_T_20 0xc2108UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 20
#define CSDM_REG_AGG_INT_T_21 0xc210cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 21
#define CSDM_REG_AGG_INT_T_22 0xc2110UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 22
#define CSDM_REG_AGG_INT_T_23 0xc2114UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 23
#define CSDM_REG_AGG_INT_T_24 0xc2118UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 24
#define CSDM_REG_AGG_INT_T_25 0xc211cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 25
#define CSDM_REG_AGG_INT_T_26 0xc2120UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 26
#define CSDM_REG_AGG_INT_T_27 0xc2124UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 27
#define CSDM_REG_AGG_INT_T_28 0xc2128UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 28
#define CSDM_REG_AGG_INT_T_29 0xc212cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 29
#define CSDM_REG_AGG_INT_T_30 0xc2130UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 30
#define CSDM_REG_AGG_INT_T_31 0xc2134UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 31
#define CSDM_REG_AGG_INT_FIC_0 0xc2138UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 0
#define CSDM_REG_AGG_INT_FIC_1 0xc213cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 1
#define CSDM_REG_AGG_INT_FIC_2 0xc2140UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 2
#define CSDM_REG_AGG_INT_FIC_3 0xc2144UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 3
#define CSDM_REG_AGG_INT_FIC_4 0xc2148UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 4
#define CSDM_REG_AGG_INT_FIC_5 0xc214cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 5
#define CSDM_REG_AGG_INT_FIC_6 0xc2150UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 6
#define CSDM_REG_AGG_INT_FIC_7 0xc2154UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 7
#define CSDM_REG_AGG_INT_FIC_8 0xc2158UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 8
#define CSDM_REG_AGG_INT_FIC_9 0xc215cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 9
#define CSDM_REG_AGG_INT_FIC_10 0xc2160UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 10
#define CSDM_REG_AGG_INT_FIC_11 0xc2164UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 11
#define CSDM_REG_AGG_INT_FIC_12 0xc2168UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 12
#define CSDM_REG_AGG_INT_FIC_13 0xc216cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 13
#define CSDM_REG_AGG_INT_FIC_14 0xc2170UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 14
#define CSDM_REG_AGG_INT_FIC_15 0xc2174UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 15
#define CSDM_REG_AGG_INT_FIC_16 0xc2178UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 16
#define CSDM_REG_AGG_INT_FIC_17 0xc217cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 17
#define CSDM_REG_AGG_INT_FIC_18 0xc2180UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 18
#define CSDM_REG_AGG_INT_FIC_19 0xc2184UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 19
#define CSDM_REG_AGG_INT_FIC_20 0xc2188UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 20
#define CSDM_REG_AGG_INT_FIC_21 0xc218cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 21
#define CSDM_REG_AGG_INT_FIC_22 0xc2190UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 22
#define CSDM_REG_AGG_INT_FIC_23 0xc2194UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 23
#define CSDM_REG_AGG_INT_FIC_24 0xc2198UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 24
#define CSDM_REG_AGG_INT_FIC_25 0xc219cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 25
#define CSDM_REG_AGG_INT_FIC_26 0xc21a0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 26
#define CSDM_REG_AGG_INT_FIC_27 0xc21a4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 27
#define CSDM_REG_AGG_INT_FIC_28 0xc21a8UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 28
#define CSDM_REG_AGG_INT_FIC_29 0xc21acUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 29
#define CSDM_REG_AGG_INT_FIC_30 0xc21b0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 30
#define CSDM_REG_AGG_INT_FIC_31 0xc21b4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 31
#define CSDM_REG_AGG_INT_MODE_0 0xc21b8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_1 0xc21bcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_2 0xc21c0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_3 0xc21c4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_4 0xc21c8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_5 0xc21ccUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_6 0xc21d0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_7 0xc21d4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_8 0xc21d8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_9 0xc21dcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_10 0xc21e0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_11 0xc21e4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_12 0xc21e8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_13 0xc21ecUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_14 0xc21f0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_15 0xc21f4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_16 0xc21f8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (16) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_17 0xc21fcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (17)
#define CSDM_REG_AGG_INT_MODE_18 0xc2200UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_19 0xc2204UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_20 0xc2208UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_21 0xc220cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_22 0xc2210UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_23 0xc2214UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_24 0xc2218UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_25 0xc221cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_26 0xc2220UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_27 0xc2224UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_28 0xc2228UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_29 0xc222cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_30 0xc2230UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_AGG_INT_MODE_31 0xc2234UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define CSDM_REG_ENABLE_IN1 0xc2238UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define CSDM_ENABLE_IN1_REG_EXT_STORE_IN_EN (0x1<<0)
#define CSDM_ENABLE_IN1_REG_EXT_STORE_IN_EN_SIZE 0
#define CSDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN (0x1<<1)
#define CSDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN_SIZE 1
#define CSDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN (0x1<<2)
#define CSDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN_SIZE 2
#define CSDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN (0x1<<3)
#define CSDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN_SIZE 3
#define CSDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN (0x1<<4)
#define CSDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN_SIZE 4
#define CSDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN (0x1<<5)
#define CSDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN_SIZE 5
#define CSDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN (0x1<<6)
#define CSDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN_SIZE 6
#define CSDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN (0x1<<7)
#define CSDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN_SIZE 7
#define CSDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN (0x1<<8)
#define CSDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN_SIZE 8
#define CSDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN (0x1<<9)
#define CSDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN_SIZE 9
#define CSDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN (0x1<<10)
#define CSDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN_SIZE 10
#define CSDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN (0x1<<11)
#define CSDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN_SIZE 11
#define CSDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN (0x1<<12)
#define CSDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN_SIZE 12
#define CSDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN (0x1<<13)
#define CSDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN_SIZE 13
#define CSDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN (0x1<<14)
#define CSDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN_SIZE 14
#define CSDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN (0x1<<15)
#define CSDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN_SIZE 15
#define CSDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN (0x1<<16)
#define CSDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN_SIZE 16
#define CSDM_ENABLE_IN1_REG_PB_DATA_IN_EN (0x1<<17)
#define CSDM_ENABLE_IN1_REG_PB_DATA_IN_EN_SIZE 17
#define CSDM_ENABLE_IN1_REG_PRS_MSG_IN_EN (0x1<<18)
#define CSDM_ENABLE_IN1_REG_PRS_MSG_IN_EN_SIZE 18
#define CSDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN (0x1<<19)
#define CSDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN_SIZE 19
#define CSDM_ENABLE_IN1_REG_PXP_REQ_IN_EN (0x1<<20)
#define CSDM_ENABLE_IN1_REG_PXP_REQ_IN_EN_SIZE 20
#define CSDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN (0x1<<21)
#define CSDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN_SIZE 21
#define CSDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN (0x1<<22)
#define CSDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN_SIZE 22
#define CSDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN (0x1<<23)
#define CSDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN_SIZE 23
#define CSDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN (0x1<<24)
#define CSDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN_SIZE 24
#define CSDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN (0x1<<25)
#define CSDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN_SIZE 25
#define CSDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN (0x1<<26)
#define CSDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN_SIZE 26
#define CSDM_REG_ENABLE_IN2 0xc223cUL //ACCESS:RW DataWidth:0x7 Multi Field Register
#define CSDM_ENABLE_IN2_REG_SDM_ACK_IN_EN (0x1<<0)
#define CSDM_ENABLE_IN2_REG_SDM_ACK_IN_EN_SIZE 0
#define CSDM_ENABLE_IN2_REG_CM_ACK_IN_EN (0x1<<1)
#define CSDM_ENABLE_IN2_REG_CM_ACK_IN_EN_SIZE 1
#define CSDM_ENABLE_IN2_REG_PB_STATUS_IN_EN (0x1<<2)
#define CSDM_ENABLE_IN2_REG_PB_STATUS_IN_EN_SIZE 2
#define CSDM_ENABLE_IN2_REG_PB_FULL_IN_EN (0x1<<3)
#define CSDM_ENABLE_IN2_REG_PB_FULL_IN_EN_SIZE 3
#define CSDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN (0x1<<4)
#define CSDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN_SIZE 4
#define CSDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN (0x1<<5)
#define CSDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN_SIZE 5
#define CSDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN (0x1<<6)
#define CSDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN_SIZE 6
#define CSDM_REG_ENABLE_OUT1 0xc2240UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define CSDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN (0x1<<0)
#define CSDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN_SIZE 0
#define CSDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN (0x1<<1)
#define CSDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN_SIZE 1
#define CSDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN (0x1<<2)
#define CSDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN_SIZE 2
#define CSDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN (0x1<<3)
#define CSDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN_SIZE 3
#define CSDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN (0x1<<4)
#define CSDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN_SIZE 4
#define CSDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN (0x1<<5)
#define CSDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN_SIZE 5
#define CSDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN (0x1<<6)
#define CSDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN_SIZE 6
#define CSDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN (0x1<<7)
#define CSDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN_SIZE 7
#define CSDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN (0x1<<8)
#define CSDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN_SIZE 8
#define CSDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN (0x1<<9)
#define CSDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN_SIZE 9
#define CSDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN (0x1<<10)
#define CSDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN_SIZE 10
#define CSDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN (0x1<<11)
#define CSDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN_SIZE 11
#define CSDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN (0x1<<12)
#define CSDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN_SIZE 12
#define CSDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN (0x1<<13)
#define CSDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN_SIZE 13
#define CSDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN (0x1<<14)
#define CSDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN_SIZE 14
#define CSDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN (0x1<<15)
#define CSDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN_SIZE 15
#define CSDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN (0x1<<16)
#define CSDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN_SIZE 16
#define CSDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN (0x1<<17)
#define CSDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN_SIZE 17
#define CSDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN (0x1<<18)
#define CSDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN_SIZE 18
#define CSDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN (0x1<<19)
#define CSDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN_SIZE 19
#define CSDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN (0x1<<20)
#define CSDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN_SIZE 20
#define CSDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN (0x1<<21)
#define CSDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN_SIZE 21
#define CSDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN (0x1<<22)
#define CSDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN_SIZE 22
#define CSDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN (0x1<<23)
#define CSDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN_SIZE 23
#define CSDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN (0x1<<24)
#define CSDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN_SIZE 24
#define CSDM_ENABLE_OUT1_REG_PB_OUT_EN (0x1<<25)
#define CSDM_ENABLE_OUT1_REG_PB_OUT_EN_SIZE 25
#define CSDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN (0x1<<26)
#define CSDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN_SIZE 26
#define CSDM_REG_ENABLE_OUT2 0xc2244UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define CSDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN (0x1<<0)
#define CSDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN_SIZE 0
#define CSDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN (0x1<<1)
#define CSDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN_SIZE 1
#define CSDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN (0x1<<2)
#define CSDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN_SIZE 2
#define CSDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN (0x1<<3)
#define CSDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN_SIZE 3
#define CSDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN (0x1<<4)
#define CSDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN_SIZE 4
#define CSDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN (0x1<<5)
#define CSDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN_SIZE 5
#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 0
#define CSDM_REG_NUM_OF_Q1_CMD 0xc224cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 1
#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 3
#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 4
#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 5
#define CSDM_REG_NUM_OF_Q6_CMD 0xc225cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 6
#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 7
#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 8
#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 9
#define CSDM_REG_NUM_OF_Q10_CMD 0xc226cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 10
#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 11
#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274UL //ACCESS:ST DataWidth:0x20 Description: The number of packet end messages received from the parser
#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278UL //ACCESS:ST DataWidth:0x20 Description: The number of requests received from the pxp async if
#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227cUL //ACCESS:ST DataWidth:0x20 Description: The number of ACK after placement messages received
#define CSDM_REG_STATISTICS_TM 0xc2280UL //ACCESS:RW DataWidth:0x4 Description: TM bits for statistics sram
#define CSDM_REG_DBG_SELECT 0xc2284UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from CSDM to the DBG block) - for selecting a line to output to the DBG block
#define CSDM_REG_DBG_BYTE_ENABLE 0xc2288UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from CSDM to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define CSDM_REG_DBG_SHIFT 0xc228cUL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from CSDM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define CSDM_REG_CSDM_INT_STS_0 0xc2290UL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define CSDM_CSDM_INT_STS_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define CSDM_CSDM_INT_STS_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define CSDM_CSDM_INT_STS_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define CSDM_CSDM_INT_STS_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define CSDM_CSDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define CSDM_CSDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define CSDM_CSDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define CSDM_CSDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define CSDM_CSDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define CSDM_CSDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define CSDM_CSDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define CSDM_CSDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define CSDM_CSDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define CSDM_CSDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define CSDM_CSDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define CSDM_CSDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define CSDM_CSDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define CSDM_CSDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define CSDM_CSDM_INT_STS_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define CSDM_CSDM_INT_STS_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define CSDM_CSDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define CSDM_CSDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define CSDM_CSDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define CSDM_CSDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define CSDM_CSDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define CSDM_CSDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define CSDM_CSDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define CSDM_CSDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define CSDM_CSDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define CSDM_CSDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define CSDM_CSDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define CSDM_CSDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define CSDM_CSDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define CSDM_CSDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define CSDM_CSDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define CSDM_CSDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define CSDM_CSDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define CSDM_CSDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define CSDM_REG_CSDM_INT_STS_CLR_0 0xc2294UL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define CSDM_CSDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define CSDM_CSDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define CSDM_CSDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define CSDM_CSDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define CSDM_CSDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define CSDM_CSDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define CSDM_CSDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define CSDM_CSDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define CSDM_CSDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define CSDM_CSDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define CSDM_CSDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define CSDM_CSDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define CSDM_CSDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define CSDM_REG_CSDM_INT_STS_WR_0 0xc2298UL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define CSDM_CSDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define CSDM_CSDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define CSDM_CSDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define CSDM_CSDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define CSDM_CSDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define CSDM_CSDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define CSDM_CSDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define CSDM_CSDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define CSDM_CSDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define CSDM_CSDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define CSDM_CSDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define CSDM_CSDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define CSDM_CSDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define CSDM_CSDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define CSDM_CSDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define CSDM_CSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define CSDM_CSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define CSDM_CSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define CSDM_CSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define CSDM_CSDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define CSDM_CSDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define CSDM_REG_CSDM_INT_MASK_0 0xc229cUL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define CSDM_CSDM_INT_MASK_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define CSDM_CSDM_INT_MASK_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define CSDM_CSDM_INT_MASK_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define CSDM_CSDM_INT_MASK_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define CSDM_CSDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define CSDM_CSDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define CSDM_CSDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define CSDM_CSDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define CSDM_CSDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define CSDM_CSDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define CSDM_CSDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define CSDM_CSDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define CSDM_CSDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define CSDM_CSDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define CSDM_CSDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define CSDM_CSDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define CSDM_CSDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define CSDM_CSDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define CSDM_CSDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define CSDM_CSDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define CSDM_CSDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define CSDM_CSDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define CSDM_CSDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define CSDM_CSDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define CSDM_CSDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define CSDM_CSDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define CSDM_CSDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define CSDM_CSDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define CSDM_CSDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define CSDM_CSDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define CSDM_CSDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define CSDM_CSDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define CSDM_CSDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define CSDM_CSDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define CSDM_CSDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define CSDM_CSDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define CSDM_CSDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define CSDM_CSDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define CSDM_REG_CSDM_INT_STS_1 0xc22a0UL //ACCESS:R DataWidth:0xe Description: Interrupt register #1 read
#define CSDM_CSDM_INT_STS_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define CSDM_CSDM_INT_STS_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define CSDM_CSDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define CSDM_CSDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define CSDM_CSDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define CSDM_CSDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define CSDM_CSDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define CSDM_CSDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define CSDM_CSDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define CSDM_CSDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define CSDM_CSDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define CSDM_CSDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define CSDM_CSDM_INT_STS_1_REG_CM_DELAY_ERROR (0x1<<6)
#define CSDM_CSDM_INT_STS_1_REG_CM_DELAY_ERROR_SIZE 6
#define CSDM_CSDM_INT_STS_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define CSDM_CSDM_INT_STS_1_REG_PXP_DELAY_ERROR_SIZE 7
#define CSDM_CSDM_INT_STS_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define CSDM_CSDM_INT_STS_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define CSDM_CSDM_INT_STS_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define CSDM_CSDM_INT_STS_1_REG_TIMER_PEND_ERROR_SIZE 9
#define CSDM_CSDM_INT_STS_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define CSDM_CSDM_INT_STS_1_REG_DORQ_DPM_ERROR_SIZE 10
#define CSDM_CSDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define CSDM_CSDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define CSDM_CSDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define CSDM_CSDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define CSDM_CSDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define CSDM_CSDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define CSDM_REG_CSDM_INT_STS_CLR_1 0xc22a4UL //ACCESS:RC DataWidth:0xe Description: Interrupt register #1 read clear
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define CSDM_CSDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR (0x1<<6)
#define CSDM_CSDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR_SIZE 6
#define CSDM_CSDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define CSDM_CSDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR_SIZE 7
#define CSDM_CSDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define CSDM_CSDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define CSDM_CSDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define CSDM_CSDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR_SIZE 9
#define CSDM_CSDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define CSDM_CSDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR_SIZE 10
#define CSDM_CSDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define CSDM_CSDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define CSDM_CSDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define CSDM_CSDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define CSDM_CSDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define CSDM_CSDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define CSDM_REG_CSDM_INT_STS_WR_1 0xc22a8UL //ACCESS:WR DataWidth:0xe Description: Interrupt register #1 bit set or clear
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define CSDM_CSDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define CSDM_CSDM_INT_STS_WR_1_REG_CM_DELAY_ERROR (0x1<<6)
#define CSDM_CSDM_INT_STS_WR_1_REG_CM_DELAY_ERROR_SIZE 6
#define CSDM_CSDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define CSDM_CSDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR_SIZE 7
#define CSDM_CSDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define CSDM_CSDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define CSDM_CSDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define CSDM_CSDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR_SIZE 9
#define CSDM_CSDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define CSDM_CSDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR_SIZE 10
#define CSDM_CSDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define CSDM_CSDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define CSDM_CSDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define CSDM_CSDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define CSDM_CSDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define CSDM_CSDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define CSDM_REG_CSDM_INT_MASK_1 0xc22acUL //ACCESS:RW DataWidth:0xe Description: Interrupt mask register #1 read/write
#define CSDM_CSDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define CSDM_CSDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define CSDM_CSDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define CSDM_CSDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define CSDM_CSDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define CSDM_CSDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define CSDM_CSDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define CSDM_CSDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define CSDM_CSDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define CSDM_CSDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define CSDM_CSDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define CSDM_CSDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define CSDM_CSDM_INT_MASK_1_REG_CM_DELAY_ERROR (0x1<<6)
#define CSDM_CSDM_INT_MASK_1_REG_CM_DELAY_ERROR_SIZE 6
#define CSDM_CSDM_INT_MASK_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define CSDM_CSDM_INT_MASK_1_REG_PXP_DELAY_ERROR_SIZE 7
#define CSDM_CSDM_INT_MASK_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define CSDM_CSDM_INT_MASK_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define CSDM_CSDM_INT_MASK_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define CSDM_CSDM_INT_MASK_1_REG_TIMER_PEND_ERROR_SIZE 9
#define CSDM_CSDM_INT_MASK_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define CSDM_CSDM_INT_MASK_1_REG_DORQ_DPM_ERROR_SIZE 10
#define CSDM_CSDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define CSDM_CSDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define CSDM_CSDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define CSDM_CSDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define CSDM_CSDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define CSDM_CSDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define CSDM_REG_CSDM_PRTY_STS 0xc22b0UL //ACCESS:R DataWidth:0xb Description: Parity register #0 read
#define CSDM_CSDM_PRTY_STS_REG_PARITY (0x1<<0)
#define CSDM_CSDM_PRTY_STS_REG_PARITY_SIZE 0
#define CSDM_CSDM_PRTY_STS_REG_TIMERS (0x1<<1)
#define CSDM_CSDM_PRTY_STS_REG_TIMERS_SIZE 1
#define CSDM_CSDM_PRTY_STS_REG_INP_QUEUE (0x1<<2)
#define CSDM_CSDM_PRTY_STS_REG_INP_QUEUE_SIZE 2
#define CSDM_CSDM_PRTY_STS_REG_ASYNC_RD_DATA (0x1<<3)
#define CSDM_CSDM_PRTY_STS_REG_ASYNC_RD_DATA_SIZE 3
#define CSDM_CSDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define CSDM_CSDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define CSDM_CSDM_PRTY_STS_REG_BRB1_DP_RD_DATA (0x1<<5)
#define CSDM_CSDM_PRTY_STS_REG_BRB1_DP_RD_DATA_SIZE 5
#define CSDM_CSDM_PRTY_STS_REG_PB_RD_DATA (0x1<<6)
#define CSDM_CSDM_PRTY_STS_REG_PB_RD_DATA_SIZE 6
#define CSDM_CSDM_PRTY_STS_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define CSDM_CSDM_PRTY_STS_REG_PXP_CTRL_RD_DATA_SIZE 7
#define CSDM_CSDM_PRTY_STS_REG_INT_RAM_RD_DATA (0x1<<8)
#define CSDM_CSDM_PRTY_STS_REG_INT_RAM_RD_DATA_SIZE 8
#define CSDM_CSDM_PRTY_STS_REG_STAT_RD_DATA (0x1<<9)
#define CSDM_CSDM_PRTY_STS_REG_STAT_RD_DATA_SIZE 9
#define CSDM_CSDM_PRTY_STS_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define CSDM_CSDM_PRTY_STS_REG_CM_QUEUE_RD_DATA_SIZE 10
#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4UL //ACCESS:RC DataWidth:0xb Description: Parity register #0 read clear
#define CSDM_CSDM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define CSDM_CSDM_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define CSDM_CSDM_PRTY_STS_CLR_REG_TIMERS (0x1<<1)
#define CSDM_CSDM_PRTY_STS_CLR_REG_TIMERS_SIZE 1
#define CSDM_CSDM_PRTY_STS_CLR_REG_INP_QUEUE (0x1<<2)
#define CSDM_CSDM_PRTY_STS_CLR_REG_INP_QUEUE_SIZE 2
#define CSDM_CSDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA (0x1<<3)
#define CSDM_CSDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA_SIZE 3
#define CSDM_CSDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define CSDM_CSDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define CSDM_CSDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA (0x1<<5)
#define CSDM_CSDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA_SIZE 5
#define CSDM_CSDM_PRTY_STS_CLR_REG_PB_RD_DATA (0x1<<6)
#define CSDM_CSDM_PRTY_STS_CLR_REG_PB_RD_DATA_SIZE 6
#define CSDM_CSDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define CSDM_CSDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA_SIZE 7
#define CSDM_CSDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA (0x1<<8)
#define CSDM_CSDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA_SIZE 8
#define CSDM_CSDM_PRTY_STS_CLR_REG_STAT_RD_DATA (0x1<<9)
#define CSDM_CSDM_PRTY_STS_CLR_REG_STAT_RD_DATA_SIZE 9
#define CSDM_CSDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define CSDM_CSDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA_SIZE 10
#define CSDM_REG_CSDM_PRTY_STS_WR 0xc22b8UL //ACCESS:WR DataWidth:0xb Description: Parity register #0 bit set or clear
#define CSDM_CSDM_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define CSDM_CSDM_PRTY_STS_WR_REG_PARITY_SIZE 0
#define CSDM_CSDM_PRTY_STS_WR_REG_TIMERS (0x1<<1)
#define CSDM_CSDM_PRTY_STS_WR_REG_TIMERS_SIZE 1
#define CSDM_CSDM_PRTY_STS_WR_REG_INP_QUEUE (0x1<<2)
#define CSDM_CSDM_PRTY_STS_WR_REG_INP_QUEUE_SIZE 2
#define CSDM_CSDM_PRTY_STS_WR_REG_ASYNC_RD_DATA (0x1<<3)
#define CSDM_CSDM_PRTY_STS_WR_REG_ASYNC_RD_DATA_SIZE 3
#define CSDM_CSDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define CSDM_CSDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define CSDM_CSDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA (0x1<<5)
#define CSDM_CSDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA_SIZE 5
#define CSDM_CSDM_PRTY_STS_WR_REG_PB_RD_DATA (0x1<<6)
#define CSDM_CSDM_PRTY_STS_WR_REG_PB_RD_DATA_SIZE 6
#define CSDM_CSDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define CSDM_CSDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA_SIZE 7
#define CSDM_CSDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA (0x1<<8)
#define CSDM_CSDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA_SIZE 8
#define CSDM_CSDM_PRTY_STS_WR_REG_STAT_RD_DATA (0x1<<9)
#define CSDM_CSDM_PRTY_STS_WR_REG_STAT_RD_DATA_SIZE 9
#define CSDM_CSDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define CSDM_CSDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA_SIZE 10
#define CSDM_REG_CSDM_PRTY_MASK 0xc22bcUL //ACCESS:RW DataWidth:0xb Description: Parity mask register #0 read/write
#define CSDM_CSDM_PRTY_MASK_REG_PARITY (0x1<<0)
#define CSDM_CSDM_PRTY_MASK_REG_PARITY_SIZE 0
#define CSDM_CSDM_PRTY_MASK_REG_TIMERS (0x1<<1)
#define CSDM_CSDM_PRTY_MASK_REG_TIMERS_SIZE 1
#define CSDM_CSDM_PRTY_MASK_REG_INP_QUEUE (0x1<<2)
#define CSDM_CSDM_PRTY_MASK_REG_INP_QUEUE_SIZE 2
#define CSDM_CSDM_PRTY_MASK_REG_ASYNC_RD_DATA (0x1<<3)
#define CSDM_CSDM_PRTY_MASK_REG_ASYNC_RD_DATA_SIZE 3
#define CSDM_CSDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define CSDM_CSDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define CSDM_CSDM_PRTY_MASK_REG_BRB1_DP_RD_DATA (0x1<<5)
#define CSDM_CSDM_PRTY_MASK_REG_BRB1_DP_RD_DATA_SIZE 5
#define CSDM_CSDM_PRTY_MASK_REG_PB_RD_DATA (0x1<<6)
#define CSDM_CSDM_PRTY_MASK_REG_PB_RD_DATA_SIZE 6
#define CSDM_CSDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define CSDM_CSDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA_SIZE 7
#define CSDM_CSDM_PRTY_MASK_REG_INT_RAM_RD_DATA (0x1<<8)
#define CSDM_CSDM_PRTY_MASK_REG_INT_RAM_RD_DATA_SIZE 8
#define CSDM_CSDM_PRTY_MASK_REG_STAT_RD_DATA (0x1<<9)
#define CSDM_CSDM_PRTY_MASK_REG_STAT_RD_DATA_SIZE 9
#define CSDM_CSDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define CSDM_CSDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA_SIZE 10
#define CSDM_REG_CM_QUEUE_TM 0xc22c0UL //ACCESS:RW DataWidth:0x8 Description: TM bits CM_QUEUE
#define CSDM_REG_INP_QUEUE_TM 0xc22c4UL //ACCESS:RW DataWidth:0x8 Description: TM bits INP_QUEUE
#define CSDM_REG_FIFOS_TM 0xc22c8UL //ACCESS:RW DataWidth:0x2 Description: TM bits fifos: PXP_CTRL[1:0]
#define CSDM_REG_TIMERS_TM 0xc22ccUL //ACCESS:RW DataWidth:0x5 Description: TM bits for timers sram
#define CSDM_REG_ECO_RESERVED 0xc22d0UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO
#define CSDM_REG_CMP_COUNTER_MAX4 0xc22d8UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #4
#define CSDM_REG_CMP_COUNTER_MAX5 0xc22dcUL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #5
#define CSDM_REG_CMP_COUNTER_MAX6 0xc22e0UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #6
#define CSDM_REG_CMP_COUNTER_MAX7 0xc22e4UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #7
#define CSDM_REG_AGGREG_INTERRUPT_LSB 0xc2400UL //ACCESS:R DataWidth:0x20 Description: lsb register of aggregated interrupt in sdm_cm block
#define CSDM_REG_AGGREG_INTERRUPT_LSB_SIZE 1
#define CSDM_REG_AGGREG_INTERRUPT_MSB 0xc2404UL //ACCESS:R DataWidth:0x20 Description: msb register of aggregated interrupt in sdm_cm block
#define CSDM_REG_AGGREG_INTERRUPT_MSB_SIZE 1
#define CSDM_REG_ASYNC_HOST_EMPTY 0xc2408UL //ACCESS:R DataWidth:0x1 Description: async fifo empty in sdm_async block
#define CSDM_REG_ASYNC_HOST_EMPTY_SIZE 1
#define CSDM_REG_ASYNC_HOST_FULL 0xc240cUL //ACCESS:R DataWidth:0x1 Description: async fifo full in sdm_async block
#define CSDM_REG_ASYNC_HOST_FULL_SIZE 1
#define CSDM_REG_CFC_LOAD_PEND_EMPTY 0xc2410UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo empty in sdm_dma_dst block
#define CSDM_REG_CFC_LOAD_PEND_EMPTY_SIZE 1
#define CSDM_REG_CFC_LOAD_PEND_FULL 0xc2414UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo full in sdm_cfc block
#define CSDM_REG_CFC_LOAD_PEND_FULL_SIZE 1
#define CSDM_REG_CFC_LOAD_RSP_EMPTY 0xc2418UL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo empty in sdm_dma_dst block
#define CSDM_REG_CFC_LOAD_RSP_EMPTY_SIZE 1
#define CSDM_REG_CFC_LOAD_RSP_FULL 0xc241cUL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo full in sdm_cfcblock
#define CSDM_REG_CFC_LOAD_RSP_FULL_SIZE 1
#define CSDM_REG_CM_DELAY_EMPTY 0xc2420UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo empty in sdm_dma_dst block
#define CSDM_REG_CM_DELAY_EMPTY_SIZE 1
#define CSDM_REG_CM_DELAY_FULL 0xc2424UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo full in sdm_cm block
#define CSDM_REG_CM_DELAY_FULL_SIZE 1
#define CSDM_REG_CM_QUEUE_EMPTY 0xc2428UL //ACCESS:R DataWidth:0x1 Description: cm queue fifo empty in sdm_dma_dst block
#define CSDM_REG_CM_QUEUE_EMPTY_SIZE 1
#define CSDM_REG_CM_QUEUE_FULL 0xc242cUL //ACCESS:R DataWidth:0x1 Description: cm queue fifo full in sdm_cm block
#define CSDM_REG_CM_QUEUE_FULL_SIZE 1
#define CSDM_REG_DELAY_FIFO_EMPTY 0xc2430UL //ACCESS:R DataWidth:0x1 Description: delay FIFO empty in sdm_inp block
#define CSDM_REG_DELAY_FIFO_EMPTY_SIZE 1
#define CSDM_REG_DELAY_FIFO_FULL 0xc2434UL //ACCESS:R DataWidth:0x1 Description: delay FIFO full in sdm_inp block
#define CSDM_REG_DELAY_FIFO_FULL_SIZE 1
#define CSDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY 0xc2438UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo empty in sdm_dma_dst block
#define CSDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY_SIZE 1
#define CSDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL 0xc243cUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo full in sdm_dma_dst block
#define CSDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL_SIZE 1
#define CSDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY 0xc2440UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo empty in sdm_dma_dst block
#define CSDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY_SIZE 1
#define CSDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL 0xc2444UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo full in sdm_dma_dst block
#define CSDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL_SIZE 1
#define CSDM_REG_DST_INT_RAM_IF_FULL 0xc2448UL //ACCESS:R DataWidth:0x1 Description: int_ram if full in sdm_dma_dst block
#define CSDM_REG_DST_INT_RAM_IF_FULL_SIZE 1
#define CSDM_REG_DST_INT_RAM_WAIT_EMPTY 0xc244cUL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo empty in sdm_dma_dst block
#define CSDM_REG_DST_INT_RAM_WAIT_EMPTY_SIZE 1
#define CSDM_REG_DST_INT_RAM_WAIT_FULL 0xc2450UL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo full in sdm_dma_dst block
#define CSDM_REG_DST_INT_RAM_WAIT_FULL_SIZE 1
#define CSDM_REG_DST_NONE_PEND_EMPTY 0xc2454UL //ACCESS:R DataWidth:0x1 Description: none pending fifo empty in sdm_dma_dst block
#define CSDM_REG_DST_NONE_PEND_EMPTY_SIZE 1
#define CSDM_REG_DST_NONE_PEND_FULL 0xc2458UL //ACCESS:R DataWidth:0x1 Description: none pending fifo full in sdm_dma_dst block
#define CSDM_REG_DST_NONE_PEND_FULL_SIZE 1
#define CSDM_REG_DST_PAS_BUF_IF_FULL 0xc245cUL //ACCESS:R DataWidth:0x1 Description: pas_buf if full in sdm_dma_dst block
#define CSDM_REG_DST_PAS_BUF_IF_FULL_SIZE 1
#define CSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0xc2460UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo empty in sdm_dma_dst block
#define CSDM_REG_DST_PAS_BUF_WAIT_EMPTY_SIZE 1
#define CSDM_REG_DST_PAS_BUF_WAIT_FULL 0xc2464UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo full in sdm_dma_dst block
#define CSDM_REG_DST_PAS_BUF_WAIT_FULL_SIZE 1
#define CSDM_REG_DST_PB_IF_FULL 0xc2468UL //ACCESS:R DataWidth:0x1 Description: pb if full in sdm_dma_dst block
#define CSDM_REG_DST_PB_IF_FULL_SIZE 1
#define CSDM_REG_DST_PB_IMMED_EMPTY 0xc246cUL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo empty in sdm_dma_dst block
#define CSDM_REG_DST_PB_IMMED_EMPTY_SIZE 1
#define CSDM_REG_DST_PB_IMMED_FULL 0xc2470UL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo full in sdm_dma_dst block
#define CSDM_REG_DST_PB_IMMED_FULL_SIZE 1
#define CSDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY 0xc2474UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo empty in sdm_dma_dst block
#define CSDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY_SIZE 1
#define CSDM_REG_DST_PXP_CTRL_DST_PEND_FULL 0xc2478UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo full in sdm_dma_dst block
#define CSDM_REG_DST_PXP_CTRL_DST_PEND_FULL_SIZE 1
#define CSDM_REG_DST_PXP_CTRL_IF_FULL 0xc247cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl if full in sdm_dma_dst block
#define CSDM_REG_DST_PXP_CTRL_IF_FULL_SIZE 1
#define CSDM_REG_DST_PXP_CTRL_IMMED_EMPTY 0xc2480UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo empty in sdm_dma_dst block
#define CSDM_REG_DST_PXP_CTRL_IMMED_EMPTY_SIZE 1
#define CSDM_REG_DST_PXP_CTRL_IMMED_FULL 0xc2484UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo full in sdm_dma_dst block
#define CSDM_REG_DST_PXP_CTRL_IMMED_FULL_SIZE 1
#define CSDM_REG_DST_PXP_CTRL_LINK_EMPTY 0xc2488UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list empty in sdm_dma_dst block
#define CSDM_REG_DST_PXP_CTRL_LINK_EMPTY_SIZE 1
#define CSDM_REG_DST_PXP_CTRL_LINK_FULL 0xc248cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list full in sdm_dma_dst block
#define CSDM_REG_DST_PXP_CTRL_LINK_FULL_SIZE 1
#define CSDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY 0xc2490UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo empty in sdm_dma_dst block
#define CSDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY_SIZE 1
#define CSDM_REG_DST_PXP_CTRL_SRC_PEND_FULL 0xc2494UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo full in sdm_dma_dst block
#define CSDM_REG_DST_PXP_CTRL_SRC_PEND_FULL_SIZE 1
#define CSDM_REG_DST_PXP_DP_DST_PEND_EMPTY 0xc2498UL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo empty in sdm_dma_dst block
#define CSDM_REG_DST_PXP_DP_DST_PEND_EMPTY_SIZE 1
#define CSDM_REG_DST_PXP_DP_DST_PEND_FULL 0xc249cUL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo full in sdm_dma_dst block
#define CSDM_REG_DST_PXP_DP_DST_PEND_FULL_SIZE 1
#define CSDM_REG_DST_PXP_DP_IF_FULL 0xc24a0UL //ACCESS:R DataWidth:0x1 Description: pxp_dp if full in sdm_dma_dst block
#define CSDM_REG_DST_PXP_DP_IF_FULL_SIZE 1
#define CSDM_REG_DST_PXP_DP_LINK_EMPTY 0xc24a4UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list empty in sdm_dma_dst block
#define CSDM_REG_DST_PXP_DP_LINK_EMPTY_SIZE 1
#define CSDM_REG_DST_PXP_DP_LINK_FULL 0xc24a8UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list full in sdm_dma_dst block
#define CSDM_REG_DST_PXP_DP_LINK_FULL_SIZE 1
#define CSDM_REG_INIT_CREDIT_CFC_ACDEC 0xc24acUL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC activity counters interface without receiving any ACK
#define CSDM_REG_INIT_CREDIT_CFC_ACDEC_SIZE 1
#define CSDM_REG_INIT_CREDIT_CFC_ACINC 0xc24b0UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC activity counters interface without receiving any ACK.
#define CSDM_REG_INIT_CREDIT_CFC_ACINC_SIZE 1
#define CSDM_REG_INIT_CREDIT_CFC_LOAD 0xc24b4UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC load interface without receiving any ACK.
#define CSDM_REG_INIT_CREDIT_CFC_LOAD_SIZE 1
#define CSDM_REG_INIT_CREDIT_CM 0xc24b8UL //ACCESS:RW DataWidth:0x4 Description: The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block
#define CSDM_REG_INIT_CREDIT_CM_SIZE 1
#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bcUL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the pxp control interface without receiving any ACK.
#define CSDM_REG_INIT_CREDIT_PXP_CTRL_SIZE 1
#define CSDM_REG_INT_RAM_RR_REQ 0xc24c0UL //ACCESS:R DataWidth:0x6 Description: round robin for int_ram arbiter: b0-pas_buf; b1-int_ram;b2-pxp_dp;b3-pxp_ctrl;b4-brb1_ctrl;b5-brb1_dp;
#define CSDM_REG_INT_RAM_RR_REQ_SIZE 1
#define CSDM_REG_OPERATION_GEN 0xc24c4UL //ACCESS:W DataWidth:0x11 Description: Generate an operation after completion; bit-16 is AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and bits 4:0 are the T124Param[4:0]
#define CSDM_REG_OPERATION_GEN_SIZE 1
#define CSDM_REG_PB_FULL 0xc24c8UL //ACCESS:R DataWidth:0x1 Description: UPB IF full in sdm_inp block
#define CSDM_REG_PB_FULL_SIZE 1
#define CSDM_REG_PBF_FULL 0xc24ccUL //ACCESS:R DataWidth:0x1 Description: PBF if full in sdm_inp block
#define CSDM_REG_PBF_FULL_SIZE 1
#define CSDM_REG_PXP_DELAY_EMPTY 0xc24d0UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo empty in sdm_dma_dst block
#define CSDM_REG_PXP_DELAY_EMPTY_SIZE 1
#define CSDM_REG_PXP_DELAY_FULL 0xc24d4UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo full in sdm_cm block
#define CSDM_REG_PXP_DELAY_FULL_SIZE 1
#define CSDM_REG_QM_FULL 0xc24d8UL //ACCESS:R DataWidth:0x1 Description: QM IF full in sdm_inp block
#define CSDM_REG_QM_FULL_SIZE 1
#define CSDM_REG_QUEUE_EMPTY 0xc24dcUL //ACCESS:R DataWidth:0xc Description: Input queue fifo empty in sdm_inp block
#define CSDM_REG_QUEUE_EMPTY_SIZE 1
#define CSDM_REG_QUEUE_FULL 0xc24e0UL //ACCESS:R DataWidth:0xc Description: Input queue fifo full in sdm_inp block
#define CSDM_REG_QUEUE_FULL_SIZE 1
#define CSDM_REG_RR_CNT_COUNTERS_STATUS 0xc24e4UL //ACCESS:R DataWidth:0x15 Description: round robin for all completion counters
#define CSDM_REG_RR_CNT_COUNTERS_STATUS_SIZE 1
#define CSDM_REG_RR_COMPLETE_REQ 0xc24e8UL //ACCESS:R DataWidth:0x7 Description: round robin for all completion requests in sdm_cm block: b0-async b1-nop;b2-pxp_int; b3-timers;b4-dma;b5-grc;b6-rbc
#define CSDM_REG_RR_COMPLETE_REQ_SIZE 1
#define CSDM_REG_RR_PTR_REQ 0xc24ecUL //ACCESS:R DataWidth:0x7 Description: round robin for cm pointer: b0-async; b1-dma_dp; b2 - dma_ctrl; b3-cfc; b4-nop; b5-timers; b6-pxp_int
#define CSDM_REG_RR_PTR_REQ_SIZE 1
#define CSDM_REG_RSP_BRB1_CTRL_IF_FULL 0xc24f0UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl if is full in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_CTRL_IF_FULL_SIZE 1
#define CSDM_REG_RSP_BRB1_CTRL_PEND_EMPTY 0xc24f4UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo empty in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_CTRL_PEND_EMPTY_SIZE 1
#define CSDM_REG_RSP_BRB1_CTRL_PEND_FULL 0xc24f8UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo full in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_CTRL_PEND_FULL_SIZE 1
#define CSDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY 0xc24fcUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo empty in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY_SIZE 1
#define CSDM_REG_RSP_BRB1_CTRL_RDATA_FULL 0xc2500UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo full in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_CTRL_RDATA_FULL_SIZE 1
#define CSDM_REG_RSP_BRB1_DP_DST_EMPTY 0xc2504UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo empty in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_DP_DST_EMPTY_SIZE 1
#define CSDM_REG_RSP_BRB1_DP_DST_FULL 0xc2508UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo full in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_DP_DST_FULL_SIZE 1
#define CSDM_REG_RSP_BRB1_DP_IF_FULL 0xc250cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp if is full in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_DP_IF_FULL_SIZE 1
#define CSDM_REG_RSP_BRB1_DP_PEND_EMPTY 0xc2510UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo empty in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_DP_PEND_EMPTY_SIZE 1
#define CSDM_REG_RSP_BRB1_DP_PEND_FULL 0xc2514UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo full in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_DP_PEND_FULL_SIZE 1
#define CSDM_REG_RSP_BRB1_DP_RDATA_EMPTY 0xc2518UL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo empty in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_DP_RDATA_EMPTY_SIZE 1
#define CSDM_REG_RSP_BRB1_DP_RDATA_FULL 0xc251cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo full in sdm_dma_rsp block
#define CSDM_REG_RSP_BRB1_DP_RDATA_FULL_SIZE 1
#define CSDM_REG_RSP_INT_RAM_PEND_EMPTY 0xc2520UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo empty in sdm_dma_rsp block
#define CSDM_REG_RSP_INT_RAM_PEND_EMPTY_SIZE 1
#define CSDM_REG_RSP_INT_RAM_PEND_FULL 0xc2524UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo full in sdm_dma_rsp block
#define CSDM_REG_RSP_INT_RAM_PEND_FULL_SIZE 1
#define CSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0xc2528UL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo empty in sdm_dma_rsp block
#define CSDM_REG_RSP_INT_RAM_RDATA_EMPTY_SIZE 1
#define CSDM_REG_RSP_INT_RAM_RDATA_FULL 0xc252cUL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo full in sdm_dma_rsp block
#define CSDM_REG_RSP_INT_RAM_RDATA_FULL_SIZE 1
#define CSDM_REG_RSP_PB_IF_FULL 0xc2530UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
#define CSDM_REG_RSP_PB_IF_FULL_SIZE 1
#define CSDM_REG_RSP_PB_PEND_EMPTY 0xc2534UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo empty in sdm_dma_rsp block
#define CSDM_REG_RSP_PB_PEND_EMPTY_SIZE 1
#define CSDM_REG_RSP_PB_PEND_FULL 0xc2538UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo full in sdm_dma_rsp block
#define CSDM_REG_RSP_PB_PEND_FULL_SIZE 1
#define CSDM_REG_RSP_PB_RDATA_EMPTY 0xc253cUL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo empty in sdm_dma_rsp block
#define CSDM_REG_RSP_PB_RDATA_EMPTY_SIZE 1
#define CSDM_REG_RSP_PB_RDATA_FULL 0xc2540UL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo full in sdm_dma_rsp block
#define CSDM_REG_RSP_PB_RDATA_FULL_SIZE 1
#define CSDM_REG_RSP_PXP_CTRL_IF_FULL 0xc2544UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
#define CSDM_REG_RSP_PXP_CTRL_IF_FULL_SIZE 1
#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo empty in sdm_dma_rsp block
#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
#define CSDM_REG_RSP_PXP_CTRL_RDATA_FULL 0xc254cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo full in sdm_dma_rsp block
#define CSDM_REG_RSP_PXP_CTRL_RDATA_FULL_SIZE 1
#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550UL //ACCESS:R DataWidth:0x1 Description: parser fifo empty in sdm_sync block
#define CSDM_REG_SYNC_PARSER_EMPTY_SIZE 1
#define CSDM_REG_SYNC_PARSER_FULL 0xc2554UL //ACCESS:R DataWidth:0x1 Description: parser fifo full in sdm_sync block
#define CSDM_REG_SYNC_PARSER_FULL_SIZE 1
#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558UL //ACCESS:R DataWidth:0x1 Description: parser serial fifo empty in sdm_sync block
#define CSDM_REG_SYNC_SYNC_EMPTY_SIZE 1
#define CSDM_REG_SYNC_SYNC_FULL 0xc255cUL //ACCESS:R DataWidth:0x1 Description: parser serial fifo full in sdm_sync block
#define CSDM_REG_SYNC_SYNC_FULL_SIZE 1
#define CSDM_REG_TIMERS_ADDR_EMPTY 0xc2560UL //ACCESS:R DataWidth:0x1 Description: address FIFO empty in sdm_timers block
#define CSDM_REG_TIMERS_ADDR_EMPTY_SIZE 1
#define CSDM_REG_TIMERS_ADDR_FULL 0xc2564UL //ACCESS:R DataWidth:0x1 Description: address FIFO full in sdm_timers block
#define CSDM_REG_TIMERS_ADDR_FULL_SIZE 1
#define CSDM_REG_TIMERS_PEND_EMPTY 0xc2568UL //ACCESS:R DataWidth:0x1 Description: pending FIFO empty in sdm_timers block
#define CSDM_REG_TIMERS_PEND_EMPTY_SIZE 1
#define CSDM_REG_TIMERS_PEND_FULL 0xc256cUL //ACCESS:R DataWidth:0x1 Description: pending FIFO full in sdm_timers block
#define CSDM_REG_TIMERS_PEND_FULL_SIZE 1
#define CSDM_REG_STATISTICS 0xc2600UL //ACCESS:RW DataWidth:0x20 Description: Statistics memory. Each read from RBC resets the corresponding statistic counter
#define CSDM_REG_STATISTICS_SIZE 48
#define CSDM_REG_TIMERS 0xc2800UL //ACCESS:WB DataWidth:0x34 Description: Debug only. Timers memory.
#define CSDM_REG_TIMERS_SIZE 380
#define CSDM_REG_CM_QUEUE 0xc3000UL //ACCESS:WB DataWidth:0x40 Description: Debug only. CM queue memory.
#define CSDM_REG_CM_QUEUE_SIZE 512
#define CSDM_REG_INP_QUEUE 0xc3800UL //ACCESS:WB DataWidth:0x40 Description: Debug only. Input queue memory.
#define CSDM_REG_INP_QUEUE_SIZE 352
#define CSDM_REG_CSDM_UNUSED_EMPTY_0 0xc22d4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSDM_REG_CSDM_UNUSED_EMPTY_0_SIZE 1
#define CSDM_REG_CSDM_UNUSED_EMPTY_1 0xc22e8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSDM_REG_CSDM_UNUSED_EMPTY_1_SIZE 70
#define CSDM_REG_CSDM_UNUSED_EMPTY_2 0xc2570UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSDM_REG_CSDM_UNUSED_EMPTY_2_SIZE 36
#define CSDM_REG_CSDM_UNUSED_EMPTY_3 0xc2700UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSDM_REG_CSDM_UNUSED_EMPTY_3_SIZE 64
#define CSEM_REG_MSG_NUM_FIC0 0x200000UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that entered through FIC0
#define CSEM_REG_MSG_NUM_FIC1 0x200004UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that entered through FIC1
#define CSEM_REG_MSG_NUM_FOC0 0x200008UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC0
#define CSEM_REG_MSG_NUM_FOC1 0x20000cUL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC1
#define CSEM_REG_MSG_NUM_FOC2 0x200010UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC2
#define CSEM_REG_MSG_NUM_FOC3 0x200014UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC3
#define CSEM_REG_THREAD_INTER_CNT_ENABLE 0x200018UL //ACCESS:RW DataWidth:0x1 Description: Enable for start count of counter ~csem_registers_thread_inter_cnt.thread_inter_cnt
#define CSEM_REG_THREAD_INTER_CNT 0x20001cUL //ACCESS:RW DataWidth:0x10 Description: Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter. This register may be used only when ~csem_registers_thread_inter_cnt_enable.thread_inter_cnt_enable =1
#define CSEM_REG_ARB_ELEMENT0 0x200020UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 0. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2
#define CSEM_REG_ARB_ELEMENT1 0x200024UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 1. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~csem_registers_arb_element0.arb_element0
#define CSEM_REG_ARB_ELEMENT2 0x200028UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 2. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~csem_registers_arb_element0.arb_element0 and ~csem_registers_arb_element1.arb_element1
#define CSEM_REG_ARB_ELEMENT3 0x20002cUL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 3. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2.Could not be equal to register ~csem_registers_arb_element0.arb_element0 and ~csem_registers_arb_element1.arb_element1 and ~csem_registers_arb_element2.arb_element2
#define CSEM_REG_ARB_ELEMENT4 0x200030UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 4. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~csem_registers_arb_element0.arb_element0 and ~csem_registers_arb_element1.arb_element1 and ~csem_registers_arb_element2.arb_element2 and ~csem_registers_arb_element3.arb_element3
#define CSEM_REG_ARB_CYCLE_SIZE 0x200034UL //ACCESS:RW DataWidth:0x5 Description: The number of time_slots in the arbitration cycle
#define CSEM_REG_TS_0_AS 0x200038UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 0
#define CSEM_REG_TS_1_AS 0x20003cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 1
#define CSEM_REG_TS_2_AS 0x200040UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 2
#define CSEM_REG_TS_3_AS 0x200044UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 3
#define CSEM_REG_TS_4_AS 0x200048UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 4
#define CSEM_REG_TS_5_AS 0x20004cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 5
#define CSEM_REG_TS_6_AS 0x200050UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 6
#define CSEM_REG_TS_7_AS 0x200054UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 7
#define CSEM_REG_TS_8_AS 0x200058UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 8
#define CSEM_REG_TS_9_AS 0x20005cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 9
#define CSEM_REG_TS_10_AS 0x200060UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 10
#define CSEM_REG_TS_11_AS 0x200064UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 11
#define CSEM_REG_TS_12_AS 0x200068UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 12
#define CSEM_REG_TS_13_AS 0x20006cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 13
#define CSEM_REG_TS_14_AS 0x200070UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 14
#define CSEM_REG_TS_15_AS 0x200074UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 15
#define CSEM_REG_TS_16_AS 0x200078UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 16
#define CSEM_REG_TS_17_AS 0x20007cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 17
#define CSEM_REG_TS_18_AS 0x200080UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 18
#define CSEM_REG_TS_19_AS 0x200084UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 19
#define CSEM_REG_FIC0_MIN_MSG_LINES 0x200088UL //ACCESS:RW DataWidth:0x6 Description: The minimum number of cycles in a message from FIC0 interfaces after which the message can be sent to the passive register_file. It must be always equal to 2; other way it may cause to deadlock in a chip.
#define CSEM_REG_FIC1_MIN_MSG_LINES 0x20008cUL //ACCESS:RW DataWidth:0x6 Description: The minimum number of cycles in a message from FIC1 interfaces after which the message can be sent to the passive register_file. It must be always equal to 2; other way it may cause to deadlock in a chip.
#define CSEM_REG_PASSIVE_ALM_FULL 0x200090UL //ACCESS:RW DataWidth:0x5 Description: The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted
#define CSEM_REG_SYNC_DRA_WR_ALM_FULL 0x200094UL //ACCESS:RW DataWidth:0x5 Description: Almost full for sync dra_wr fifo (data from DRA to STORM)
#define CSEM_REG_SYNC_RAM_WR_ALM_FULL 0x200098UL //ACCESS:RW DataWidth:0x6 Description: Almost full for sync ram_wr fifo (data from EXT_IF to STORM)
#define CSEM_REG_DBG_ALM_FULL 0x20009cUL //ACCESS:RW DataWidth:0x6 Description: Almost full for slow debug fifo
#define CSEM_REG_EXCEPTION_INT 0x2000a0UL //ACCESS:RW DataWidth:0xf Description: The PRAM address for the interrupt in a case the event ID is bigger then the INT table size. This register is always NA; because this feature is removed
#define CSEM_REG_ENABLE_IN 0x2000a4UL //ACCESS:RW DataWidth:0xf Multi Field Register
#define CSEM_ENABLE_IN_REG_FIC0_ENABLE_IN (0x1<<0)
#define CSEM_ENABLE_IN_REG_FIC0_ENABLE_IN_SIZE 0
#define CSEM_ENABLE_IN_REG_FIC1_ENABLE_IN (0x1<<1)
#define CSEM_ENABLE_IN_REG_FIC1_ENABLE_IN_SIZE 1
#define CSEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN (0x1<<2)
#define CSEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN_SIZE 2
#define CSEM_ENABLE_IN_REG_GENERAL_ENABLE_IN (0x1<<3)
#define CSEM_ENABLE_IN_REG_GENERAL_ENABLE_IN_SIZE 3
#define CSEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN (0x1<<4)
#define CSEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN_SIZE 4
#define CSEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN (0x1<<5)
#define CSEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN_SIZE 5
#define CSEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN (0x1<<6)
#define CSEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN_SIZE 6
#define CSEM_ENABLE_IN_REG_RAM0_ENABLE_IN (0x1<<7)
#define CSEM_ENABLE_IN_REG_RAM0_ENABLE_IN_SIZE 7
#define CSEM_ENABLE_IN_REG_RAM1_ENABLE_IN (0x1<<8)
#define CSEM_ENABLE_IN_REG_RAM1_ENABLE_IN_SIZE 8
#define CSEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN (0x1<<9)
#define CSEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN_SIZE 9
#define CSEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN (0x1<<10)
#define CSEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN_SIZE 10
#define CSEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN (0x1<<11)
#define CSEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN_SIZE 11
#define CSEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN (0x1<<12)
#define CSEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN_SIZE 12
#define CSEM_ENABLE_IN_REG_WAITP_ENABLE_IN (0x1<<13)
#define CSEM_ENABLE_IN_REG_WAITP_ENABLE_IN_SIZE 13
#define CSEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN (0x1<<14)
#define CSEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN_SIZE 14
#define CSEM_REG_ENABLE_OUT 0x2000a8UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define CSEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT (0x1<<0)
#define CSEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT_SIZE 0
#define CSEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT (0x1<<1)
#define CSEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT_SIZE 1
#define CSEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT (0x1<<2)
#define CSEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT_SIZE 2
#define CSEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT (0x1<<3)
#define CSEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT_SIZE 3
#define CSEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT (0x1<<4)
#define CSEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT_SIZE 4
#define CSEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT (0x1<<5)
#define CSEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT_SIZE 5
#define CSEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT (0x1<<6)
#define CSEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT_SIZE 6
#define CSEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT (0x1<<7)
#define CSEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT_SIZE 7
#define CSEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT (0x1<<8)
#define CSEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT_SIZE 8
#define CSEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT (0x1<<9)
#define CSEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT_SIZE 9
#define CSEM_REG_STORM0_H_TM 0x2000acUL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm0_h memory instance
#define CSEM_REG_STORM1_H_TM 0x2000b0UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm1_h memory instance
#define CSEM_REG_STORM0_L_TM 0x2000b4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm0_l memory instance
#define CSEM_REG_STORM1_L_TM 0x2000b8UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm1_l memory instance
#define CSEM_REG_CAM_TM 0x2000bcUL //ACCESS:RW DataWidth:0xe Description: TM bits for cam
#define CSEM_REG_RAM0_TM 0x2000c0UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory ram0_0
#define CSEM_REG_PAS_BUF_LSB_TMA 0x2000c4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_lsb
#define CSEM_REG_PAS_BUF_LSB_TMB 0x2000c8UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_lsb
#define CSEM_REG_PAS_BUF_MSB_TMA 0x2000ccUL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_msb
#define CSEM_REG_PAS_BUF_MSB_TMB 0x2000d0UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_msb
#define CSEM_REG_INT_TABLE_TM 0x2000d4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory int_table
#define CSEM_REG_CLEAR_WAITP 0x2000d8UL //ACCESS:RW DataWidth:0x1 Description: Write 1 to this register will disable waitp from this storm to other storms
#define CSEM_REG_SLOW_DBG_MODE 0x2000dcUL //ACCESS:RW DataWidth:0x3 Description: debug mode for slow debug bus. Applicable only when ~csem_registers_slow_dbg_active.slow_dbg_active =1. If mode =0 thread number; pram address and DRA WR data selected; if mode =1 fin command and DRA RD ; if mode =2 pram address and thread number and fin command and released thread from STORM; if mode =3 STORE data to SDM
#define CSEM_REG_SLOW_DBG_ACTIVE 0x2000e0UL //ACCESS:RW DataWidth:0x1 Description: debug mode is active
#define CSEM_REG_DBG_MSG_SRC 0x2000e4UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~csem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0only FIC-s output to debug bus; 1=both FIC-s and passive buffer.
#define CSEM_REG_DBG_MODE0_CFG 0x2000e8UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~csem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0 all the message output to debug bus; 1=partial message.
#define CSEM_REG_DBG_MODE0_CFG_CYCLE 0x2000ecUL //ACCESS:RW DataWidth:0x5 Description: Applicable only when ~csem_registers_dbg_mode0_cfg.dbg_mode0_cfg =1. If =1 the additional cycles to extract to the debug bus.
#define CSEM_REG_DBG_MODE1_CFG 0x2000f0UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~csem_registers_slow_dbg_mode.slow_dbg_mode =1. If=0 output to debug bus without the data; 1=with the data.
#define CSEM_REG_DBG_EACH_CYLE 0x2000f4UL //ACCESS:RW DataWidth:0x1 Description: If=0 output every cycle full indication or thread status; 1= output only when there is a change.
#define CSEM_REG_DBG_SELECT 0x2000f8UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from USEMI to the DBG block) - for selecting a line to output to the DBG block
#define CSEM_REG_DBG_BYTE_ENABLE 0x2000fcUL //ACCESS:RW DataWidth:0x8 Description: Debug only.For dbgmux usage (debug data that goes from USEM to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define CSEM_REG_DBG_SHIFT 0x200100UL //ACCESS:RW DataWidth:0x3 Description: Debug only.For dbgmux usage (debug data that goes from USEM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define CSEM_REG_CSEM_INT_STS_0 0x200104UL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define CSEM_CSEM_INT_STS_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define CSEM_CSEM_INT_STS_0_REG_FIC0_LAST_ERROR_SIZE 1
#define CSEM_CSEM_INT_STS_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define CSEM_CSEM_INT_STS_0_REG_FIC1_LAST_ERROR_SIZE 2
#define CSEM_CSEM_INT_STS_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define CSEM_CSEM_INT_STS_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define CSEM_CSEM_INT_STS_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define CSEM_CSEM_INT_STS_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define CSEM_CSEM_INT_STS_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define CSEM_CSEM_INT_STS_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define CSEM_CSEM_INT_STS_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define CSEM_CSEM_INT_STS_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define CSEM_CSEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define CSEM_CSEM_INT_STS_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define CSEM_CSEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define CSEM_CSEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define CSEM_CSEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define CSEM_CSEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define CSEM_CSEM_INT_STS_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define CSEM_CSEM_INT_STS_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define CSEM_CSEM_INT_STS_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define CSEM_CSEM_INT_STS_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define CSEM_CSEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define CSEM_CSEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define CSEM_CSEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define CSEM_CSEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define CSEM_CSEM_INT_STS_0_REG_RD_EMPTY_CAM (0x1<<20)
#define CSEM_CSEM_INT_STS_0_REG_RD_EMPTY_CAM_SIZE 20
#define CSEM_CSEM_INT_STS_0_REG_WR_FULL_CAM (0x1<<21)
#define CSEM_CSEM_INT_STS_0_REG_WR_FULL_CAM_SIZE 21
#define CSEM_CSEM_INT_STS_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define CSEM_CSEM_INT_STS_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define CSEM_CSEM_INT_STS_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define CSEM_CSEM_INT_STS_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define CSEM_CSEM_INT_STS_0_REG_CAM_OUT_FIFO (0x1<<24)
#define CSEM_CSEM_INT_STS_0_REG_CAM_OUT_FIFO_SIZE 24
#define CSEM_CSEM_INT_STS_0_REG_FIN_FIFO (0x1<<25)
#define CSEM_CSEM_INT_STS_0_REG_FIN_FIFO_SIZE 25
#define CSEM_CSEM_INT_STS_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define CSEM_CSEM_INT_STS_0_REG_SET0_THREAD_ERROR_SIZE 26
#define CSEM_CSEM_INT_STS_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define CSEM_CSEM_INT_STS_0_REG_SET1_THREAD_ERROR_SIZE 27
#define CSEM_CSEM_INT_STS_0_REG_THREAD_OVERRUN (0x1<<28)
#define CSEM_CSEM_INT_STS_0_REG_THREAD_OVERRUN_SIZE 28
#define CSEM_CSEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define CSEM_CSEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define CSEM_CSEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define CSEM_CSEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define CSEM_REG_CSEM_INT_STS_CLR_0 0x200108UL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR_SIZE 1
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR_SIZE 2
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define CSEM_CSEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define CSEM_CSEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define CSEM_CSEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define CSEM_CSEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define CSEM_CSEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define CSEM_CSEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define CSEM_CSEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define CSEM_CSEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define CSEM_CSEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define CSEM_CSEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define CSEM_CSEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM (0x1<<20)
#define CSEM_CSEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM_SIZE 20
#define CSEM_CSEM_INT_STS_CLR_0_REG_WR_FULL_CAM (0x1<<21)
#define CSEM_CSEM_INT_STS_CLR_0_REG_WR_FULL_CAM_SIZE 21
#define CSEM_CSEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define CSEM_CSEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define CSEM_CSEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define CSEM_CSEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define CSEM_CSEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO (0x1<<24)
#define CSEM_CSEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO_SIZE 24
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIN_FIFO (0x1<<25)
#define CSEM_CSEM_INT_STS_CLR_0_REG_FIN_FIFO_SIZE 25
#define CSEM_CSEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR_SIZE 26
#define CSEM_CSEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR_SIZE 27
#define CSEM_CSEM_INT_STS_CLR_0_REG_THREAD_OVERRUN (0x1<<28)
#define CSEM_CSEM_INT_STS_CLR_0_REG_THREAD_OVERRUN_SIZE 28
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define CSEM_REG_CSEM_INT_STS_WR_0 0x20010cUL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR_SIZE 1
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR_SIZE 2
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define CSEM_CSEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define CSEM_CSEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define CSEM_CSEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define CSEM_CSEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define CSEM_CSEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define CSEM_CSEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define CSEM_CSEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define CSEM_CSEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define CSEM_CSEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define CSEM_CSEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define CSEM_CSEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define CSEM_CSEM_INT_STS_WR_0_REG_RD_EMPTY_CAM (0x1<<20)
#define CSEM_CSEM_INT_STS_WR_0_REG_RD_EMPTY_CAM_SIZE 20
#define CSEM_CSEM_INT_STS_WR_0_REG_WR_FULL_CAM (0x1<<21)
#define CSEM_CSEM_INT_STS_WR_0_REG_WR_FULL_CAM_SIZE 21
#define CSEM_CSEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define CSEM_CSEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define CSEM_CSEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define CSEM_CSEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define CSEM_CSEM_INT_STS_WR_0_REG_CAM_OUT_FIFO (0x1<<24)
#define CSEM_CSEM_INT_STS_WR_0_REG_CAM_OUT_FIFO_SIZE 24
#define CSEM_CSEM_INT_STS_WR_0_REG_FIN_FIFO (0x1<<25)
#define CSEM_CSEM_INT_STS_WR_0_REG_FIN_FIFO_SIZE 25
#define CSEM_CSEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define CSEM_CSEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR_SIZE 26
#define CSEM_CSEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define CSEM_CSEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR_SIZE 27
#define CSEM_CSEM_INT_STS_WR_0_REG_THREAD_OVERRUN (0x1<<28)
#define CSEM_CSEM_INT_STS_WR_0_REG_THREAD_OVERRUN_SIZE 28
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define CSEM_REG_CSEM_INT_MASK_0 0x200110UL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define CSEM_CSEM_INT_MASK_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define CSEM_CSEM_INT_MASK_0_REG_FIC0_LAST_ERROR_SIZE 1
#define CSEM_CSEM_INT_MASK_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define CSEM_CSEM_INT_MASK_0_REG_FIC1_LAST_ERROR_SIZE 2
#define CSEM_CSEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define CSEM_CSEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define CSEM_CSEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define CSEM_CSEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define CSEM_CSEM_INT_MASK_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define CSEM_CSEM_INT_MASK_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define CSEM_CSEM_INT_MASK_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define CSEM_CSEM_INT_MASK_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define CSEM_CSEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define CSEM_CSEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define CSEM_CSEM_INT_MASK_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define CSEM_CSEM_INT_MASK_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define CSEM_CSEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define CSEM_CSEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define CSEM_CSEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define CSEM_CSEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define CSEM_CSEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define CSEM_CSEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define CSEM_CSEM_INT_MASK_0_REG_RD_EMPTY_CAM (0x1<<20)
#define CSEM_CSEM_INT_MASK_0_REG_RD_EMPTY_CAM_SIZE 20
#define CSEM_CSEM_INT_MASK_0_REG_WR_FULL_CAM (0x1<<21)
#define CSEM_CSEM_INT_MASK_0_REG_WR_FULL_CAM_SIZE 21
#define CSEM_CSEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define CSEM_CSEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define CSEM_CSEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define CSEM_CSEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define CSEM_CSEM_INT_MASK_0_REG_CAM_OUT_FIFO (0x1<<24)
#define CSEM_CSEM_INT_MASK_0_REG_CAM_OUT_FIFO_SIZE 24
#define CSEM_CSEM_INT_MASK_0_REG_FIN_FIFO (0x1<<25)
#define CSEM_CSEM_INT_MASK_0_REG_FIN_FIFO_SIZE 25
#define CSEM_CSEM_INT_MASK_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define CSEM_CSEM_INT_MASK_0_REG_SET0_THREAD_ERROR_SIZE 26
#define CSEM_CSEM_INT_MASK_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define CSEM_CSEM_INT_MASK_0_REG_SET1_THREAD_ERROR_SIZE 27
#define CSEM_CSEM_INT_MASK_0_REG_THREAD_OVERRUN (0x1<<28)
#define CSEM_CSEM_INT_MASK_0_REG_THREAD_OVERRUN_SIZE 28
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define CSEM_CSEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define CSEM_REG_CSEM_INT_STS_1 0x200114UL //ACCESS:R DataWidth:0xb Description: Interrupt register #1 read
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define CSEM_CSEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define CSEM_CSEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define CSEM_CSEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define CSEM_CSEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define CSEM_CSEM_INT_STS_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define CSEM_CSEM_INT_STS_1_REG_DBG_FIFO_ERROR_SIZE 9
#define CSEM_CSEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define CSEM_CSEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define CSEM_REG_CSEM_INT_STS_CLR_1 0x200118UL //ACCESS:RC DataWidth:0xb Description: Interrupt register #1 read clear
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define CSEM_CSEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define CSEM_CSEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR_SIZE 9
#define CSEM_CSEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define CSEM_CSEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define CSEM_REG_CSEM_INT_STS_WR_1 0x20011cUL //ACCESS:WR DataWidth:0xb Description: Interrupt register #1 bit set or clear
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define CSEM_CSEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define CSEM_CSEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR_SIZE 9
#define CSEM_CSEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define CSEM_CSEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define CSEM_REG_CSEM_INT_MASK_1 0x200120UL //ACCESS:RW DataWidth:0xb Description: Interrupt mask register #1 read/write
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define CSEM_CSEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define CSEM_CSEM_INT_MASK_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define CSEM_CSEM_INT_MASK_1_REG_DBG_FIFO_ERROR_SIZE 9
#define CSEM_CSEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define CSEM_CSEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define CSEM_REG_CSEM_PRTY_STS_0 0x200124UL //ACCESS:R DataWidth:0x20 Description: Parity register #0 read
#define CSEM_CSEM_PRTY_STS_0_REG_PARITY (0x1<<0)
#define CSEM_CSEM_PRTY_STS_0_REG_PARITY_SIZE 0
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define CSEM_CSEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define CSEM_CSEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define CSEM_CSEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define CSEM_CSEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define CSEM_CSEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define CSEM_CSEM_PRTY_STS_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define CSEM_CSEM_PRTY_STS_0_REG_PAS_FIFO_PARITY_SIZE 10
#define CSEM_CSEM_PRTY_STS_0_REG_PAS_PARITY0 (0x1<<11)
#define CSEM_CSEM_PRTY_STS_0_REG_PAS_PARITY0_SIZE 11
#define CSEM_CSEM_PRTY_STS_0_REG_PAS_PARITY1 (0x1<<12)
#define CSEM_CSEM_PRTY_STS_0_REG_PAS_PARITY1_SIZE 12
#define CSEM_CSEM_PRTY_STS_0_REG_INT_TABLE_PARITY (0x1<<13)
#define CSEM_CSEM_PRTY_STS_0_REG_INT_TABLE_PARITY_SIZE 13
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY0 (0x1<<14)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY0_SIZE 14
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY1 (0x1<<15)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY1_SIZE 15
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY2 (0x1<<16)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY2_SIZE 16
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY3 (0x1<<17)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY3_SIZE 17
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY4 (0x1<<18)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY4_SIZE 18
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY5 (0x1<<19)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY5_SIZE 19
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY6 (0x1<<20)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY6_SIZE 20
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY7 (0x1<<21)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY7_SIZE 21
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY0 (0x1<<22)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY0_SIZE 22
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY1 (0x1<<23)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY1_SIZE 23
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY2 (0x1<<24)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY2_SIZE 24
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY3 (0x1<<25)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY3_SIZE 25
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY4 (0x1<<26)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY4_SIZE 26
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY5 (0x1<<27)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY5_SIZE 27
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY6 (0x1<<28)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY6_SIZE 28
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY7 (0x1<<29)
#define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY7_SIZE 29
#define CSEM_CSEM_PRTY_STS_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define CSEM_CSEM_PRTY_STS_0_REG_PRAM_LOW_PARITY_SIZE 30
#define CSEM_CSEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define CSEM_CSEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128UL //ACCESS:RC DataWidth:0x20 Description: Parity register #0 read clear
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PARITY_SIZE 0
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY_SIZE 10
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PAS_PARITY0 (0x1<<11)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PAS_PARITY0_SIZE 11
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PAS_PARITY1 (0x1<<12)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PAS_PARITY1_SIZE 12
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY (0x1<<13)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY_SIZE 13
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0 (0x1<<14)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0_SIZE 14
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1 (0x1<<15)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1_SIZE 15
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2 (0x1<<16)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2_SIZE 16
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3 (0x1<<17)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3_SIZE 17
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4 (0x1<<18)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4_SIZE 18
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5 (0x1<<19)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5_SIZE 19
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6 (0x1<<20)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6_SIZE 20
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7 (0x1<<21)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7_SIZE 21
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0 (0x1<<22)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0_SIZE 22
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1 (0x1<<23)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1_SIZE 23
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2 (0x1<<24)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2_SIZE 24
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3 (0x1<<25)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3_SIZE 25
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4 (0x1<<26)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4_SIZE 26
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5 (0x1<<27)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5_SIZE 27
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6 (0x1<<28)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6_SIZE 28
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7 (0x1<<29)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7_SIZE 29
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY_SIZE 30
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define CSEM_CSEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define CSEM_REG_CSEM_PRTY_STS_WR_0 0x20012cUL //ACCESS:WR DataWidth:0x20 Description: Parity register #0 bit set or clear
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PARITY_SIZE 0
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define CSEM_CSEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define CSEM_CSEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY_SIZE 10
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PAS_PARITY0 (0x1<<11)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PAS_PARITY0_SIZE 11
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PAS_PARITY1 (0x1<<12)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PAS_PARITY1_SIZE 12
#define CSEM_CSEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY (0x1<<13)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY_SIZE 13
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY0 (0x1<<14)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY0_SIZE 14
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY1 (0x1<<15)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY1_SIZE 15
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY2 (0x1<<16)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY2_SIZE 16
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY3 (0x1<<17)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY3_SIZE 17
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY4 (0x1<<18)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY4_SIZE 18
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY5 (0x1<<19)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY5_SIZE 19
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY6 (0x1<<20)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY6_SIZE 20
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY7 (0x1<<21)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY7_SIZE 21
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY0 (0x1<<22)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY0_SIZE 22
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY1 (0x1<<23)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY1_SIZE 23
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY2 (0x1<<24)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY2_SIZE 24
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY3 (0x1<<25)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY3_SIZE 25
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY4 (0x1<<26)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY4_SIZE 26
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY5 (0x1<<27)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY5_SIZE 27
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY6 (0x1<<28)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY6_SIZE 28
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY7 (0x1<<29)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY7_SIZE 29
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY_SIZE 30
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define CSEM_CSEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130UL //ACCESS:RW DataWidth:0x20 Description: Parity mask register #0 read/write
#define CSEM_CSEM_PRTY_MASK_0_REG_PARITY (0x1<<0)
#define CSEM_CSEM_PRTY_MASK_0_REG_PARITY_SIZE 0
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define CSEM_CSEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define CSEM_CSEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define CSEM_CSEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define CSEM_CSEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define CSEM_CSEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define CSEM_CSEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY_SIZE 10
#define CSEM_CSEM_PRTY_MASK_0_REG_PAS_PARITY0 (0x1<<11)
#define CSEM_CSEM_PRTY_MASK_0_REG_PAS_PARITY0_SIZE 11
#define CSEM_CSEM_PRTY_MASK_0_REG_PAS_PARITY1 (0x1<<12)
#define CSEM_CSEM_PRTY_MASK_0_REG_PAS_PARITY1_SIZE 12
#define CSEM_CSEM_PRTY_MASK_0_REG_INT_TABLE_PARITY (0x1<<13)
#define CSEM_CSEM_PRTY_MASK_0_REG_INT_TABLE_PARITY_SIZE 13
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY0 (0x1<<14)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY0_SIZE 14
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY1 (0x1<<15)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY1_SIZE 15
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY2 (0x1<<16)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY2_SIZE 16
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY3 (0x1<<17)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY3_SIZE 17
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY4 (0x1<<18)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY4_SIZE 18
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY5 (0x1<<19)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY5_SIZE 19
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY6 (0x1<<20)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY6_SIZE 20
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY7 (0x1<<21)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY7_SIZE 21
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY0 (0x1<<22)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY0_SIZE 22
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY1 (0x1<<23)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY1_SIZE 23
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY2 (0x1<<24)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY2_SIZE 24
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY3 (0x1<<25)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY3_SIZE 25
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY4 (0x1<<26)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY4_SIZE 26
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY5 (0x1<<27)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY5_SIZE 27
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY6 (0x1<<28)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY6_SIZE 28
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY7 (0x1<<29)
#define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY7_SIZE 29
#define CSEM_CSEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define CSEM_CSEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY_SIZE 30
#define CSEM_CSEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define CSEM_CSEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define CSEM_REG_CSEM_PRTY_STS_1 0x200134UL //ACCESS:R DataWidth:0x5 Description: Parity register #1 read
#define CSEM_CSEM_PRTY_STS_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define CSEM_CSEM_PRTY_STS_1_REG_SYNC_DBG_PARITY_SIZE 0
#define CSEM_CSEM_PRTY_STS_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define CSEM_CSEM_PRTY_STS_1_REG_SLOW_DBG_PARITY_SIZE 1
#define CSEM_CSEM_PRTY_STS_1_REG_CAM_PARITY (0x1<<2)
#define CSEM_CSEM_PRTY_STS_1_REG_CAM_PARITY_SIZE 2
#define CSEM_CSEM_PRTY_STS_1_REG_STORM_RF0_PARITY (0x1<<3)
#define CSEM_CSEM_PRTY_STS_1_REG_STORM_RF0_PARITY_SIZE 3
#define CSEM_CSEM_PRTY_STS_1_REG_STORM_RF1_PARITY (0x1<<4)
#define CSEM_CSEM_PRTY_STS_1_REG_STORM_RF1_PARITY_SIZE 4
#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138UL //ACCESS:RC DataWidth:0x5 Description: Parity register #1 read clear
#define CSEM_CSEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define CSEM_CSEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY_SIZE 0
#define CSEM_CSEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define CSEM_CSEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY_SIZE 1
#define CSEM_CSEM_PRTY_STS_CLR_1_REG_CAM_PARITY (0x1<<2)
#define CSEM_CSEM_PRTY_STS_CLR_1_REG_CAM_PARITY_SIZE 2
#define CSEM_CSEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY (0x1<<3)
#define CSEM_CSEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY_SIZE 3
#define CSEM_CSEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY (0x1<<4)
#define CSEM_CSEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY_SIZE 4
#define CSEM_REG_CSEM_PRTY_STS_WR_1 0x20013cUL //ACCESS:WR DataWidth:0x5 Description: Parity register #1 bit set or clear
#define CSEM_CSEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define CSEM_CSEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY_SIZE 0
#define CSEM_CSEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define CSEM_CSEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY_SIZE 1
#define CSEM_CSEM_PRTY_STS_WR_1_REG_CAM_PARITY (0x1<<2)
#define CSEM_CSEM_PRTY_STS_WR_1_REG_CAM_PARITY_SIZE 2
#define CSEM_CSEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY (0x1<<3)
#define CSEM_CSEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY_SIZE 3
#define CSEM_CSEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY (0x1<<4)
#define CSEM_CSEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY_SIZE 4
#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140UL //ACCESS:RW DataWidth:0x5 Description: Parity mask register #1 read/write
#define CSEM_CSEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define CSEM_CSEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY_SIZE 0
#define CSEM_CSEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define CSEM_CSEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY_SIZE 1
#define CSEM_CSEM_PRTY_MASK_1_REG_CAM_PARITY (0x1<<2)
#define CSEM_CSEM_PRTY_MASK_1_REG_CAM_PARITY_SIZE 2
#define CSEM_CSEM_PRTY_MASK_1_REG_STORM_RF0_PARITY (0x1<<3)
#define CSEM_CSEM_PRTY_MASK_1_REG_STORM_RF0_PARITY_SIZE 3
#define CSEM_CSEM_PRTY_MASK_1_REG_STORM_RF1_PARITY (0x1<<4)
#define CSEM_CSEM_PRTY_MASK_1_REG_STORM_RF1_PARITY_SIZE 4
#define CSEM_REG_RAM0_TM1 0x20014cUL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory ram0_1
#define CSEM_REG_RAM0_TM2 0x200150UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory ram0_2
#define CSEM_REG_ECO_RESERVED 0x2003a8UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO
#define CSEM_REG_FIFOS_TM 0x2003acUL //ACCESS:RW DataWidth:0xe Description: TM bits for FIC0_LSB [1:0]; FIC0_MSB[3:2]; FIC1_LSB[5:4]; FIC1_MSB[7:6]; DBG_LSB[9:8];DBG_MSB[11:10]; EXT_PAS[13:12]
#define CSEM_REG_ARBITER_REQUEST 0x200200UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2
#define CSEM_REG_ARBITER_REQUEST_SIZE 1
#define CSEM_REG_ARBITER_SELECT 0x200204UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2
#define CSEM_REG_ARBITER_SELECT_SIZE 1
#define CSEM_REG_ARBITER_SLOT 0x200208UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last slot
#define CSEM_REG_ARBITER_SLOT_SIZE 1
#define CSEM_REG_DBG_IF_FULL 0x20020cUL //ACCESS:R DataWidth:0x1 Description: DBG IF is full in sem_slow_ls_dbg
#define CSEM_REG_DBG_IF_FULL_SIZE 1
#define CSEM_REG_DRA_EMPTY 0x200210UL //ACCESS:R DataWidth:0x1 Description: This register is active when FIN FIO is empty and DRA RD FIFO is empty
#define CSEM_REG_DRA_EMPTY_SIZE 1
#define CSEM_REG_EXT_PAS_EMPTY 0x200214UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO empty in sem_slow
#define CSEM_REG_EXT_PAS_EMPTY_SIZE 1
#define CSEM_REG_EXT_PAS_FULL 0x200218UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO Full in sem_slow
#define CSEM_REG_EXT_PAS_FULL_SIZE 1
#define CSEM_REG_EXT_STORE_FREE_ENTRIES 0x20021cUL //ACCESS:R DataWidth:0x6 Description: Number of free entries in the external STORE sync FIFO.
#define CSEM_REG_EXT_STORE_FREE_ENTRIES_SIZE 1
#define CSEM_REG_EXT_STORE_IF_FULL 0x200220UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE IF is full in sem_slow_ls_ext
#define CSEM_REG_EXT_STORE_IF_FULL_SIZE 1
#define CSEM_REG_FIC0_DISABLE 0x200224UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC0 May be updated during run_time by the microcode
#define CSEM_REG_FIC0_DISABLE_SIZE 1
#define CSEM_REG_FIC0_EMPTY 0x200228UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
#define CSEM_REG_FIC0_EMPTY_SIZE 1
#define CSEM_REG_FIC0_FULL 0x20022cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
#define CSEM_REG_FIC0_FULL_SIZE 1
#define CSEM_REG_FIC0_LENGTH 0x200230UL //ACCESS:R DataWidth:0x8 Description: Length from FIC0. Active only with ~csem_registers_fic0_length_error.fic0_length_error interrupt
#define CSEM_REG_FIC0_LENGTH_SIZE 1
#define CSEM_REG_FIC1_DISABLE 0x200234UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC1 May be updated during run_time by the microcode
#define CSEM_REG_FIC1_DISABLE_SIZE 1
#define CSEM_REG_FIC1_EMPTY 0x200238UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
#define CSEM_REG_FIC1_EMPTY_SIZE 1
#define CSEM_REG_FIC1_FULL 0x20023cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
#define CSEM_REG_FIC1_FULL_SIZE 1
#define CSEM_REG_FIC1_LENGTH 0x200240UL //ACCESS:R DataWidth:0x8 Description: Length from FIC1. Active only with ~csem_registers_fic1_length_error.fic1_length_error interrupt
#define CSEM_REG_FIC1_LENGTH_SIZE 1
#define CSEM_REG_GPI_DATA 0x200244UL //ACCESS:R DataWidth:0x18 Description: GPI signals that are inputs to SEMI
#define CSEM_REG_GPI_DATA_SIZE 1
#define CSEM_REG_NUM_OF_THREADS 0x200248UL //ACCESS:R DataWidth:0x6 Description: The number of threads currently active
#define CSEM_REG_NUM_OF_THREADS_SIZE 1
#define CSEM_REG_PAS_DISABLE 0x20024cUL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from the passive buffer May be updated during run_time by the microcode
#define CSEM_REG_PAS_DISABLE_SIZE 1
#define CSEM_REG_PAS_IF_FULL 0x200250UL //ACCESS:R DataWidth:0x1 Description: Full from passive buffer asserted toward SDM
#define CSEM_REG_PAS_IF_FULL_SIZE 1
#define CSEM_REG_RAM0_IF_FULL 0x200254UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM0 IF is full in sem_slow_ls_ram
#define CSEM_REG_RAM0_IF_FULL_SIZE 1
#define CSEM_REG_RAM1_IF_FULL 0x200258UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM1 IF is full in sem_slow_ls_ram
#define CSEM_REG_RAM1_IF_FULL_SIZE 1
#define CSEM_REG_SET0_THREAD_EMPTY 0x20025cUL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is empty in sem_slow_dra_wr
#define CSEM_REG_SET0_THREAD_EMPTY_SIZE 1
#define CSEM_REG_SET0_THREAD_FULL 0x200260UL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is full in sem_slow_dra_wr
#define CSEM_REG_SET0_THREAD_FULL_SIZE 1
#define CSEM_REG_SET1_THREAD_EMPTY 0x200264UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is empty in sem_slow_dra_wr
#define CSEM_REG_SET1_THREAD_EMPTY_SIZE 1
#define CSEM_REG_SET1_THREAD_FULL 0x200268UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is full in sem_slow_dra_wr
#define CSEM_REG_SET1_THREAD_FULL_SIZE 1
#define CSEM_REG_SLEEP_THREADS_VALID 0x20026cUL //ACCESS:R DataWidth:0x14 Description: Valid sleeping threads indication have bit per thread
#define CSEM_REG_SLEEP_THREADS_VALID_SIZE 1
#define CSEM_REG_SLOW_DBG_ALM_EMPTY 0x200270UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg (31 entry inside fifo)
#define CSEM_REG_SLOW_DBG_ALM_EMPTY_SIZE 1
#define CSEM_REG_SLOW_DBG_ALM_FULL 0x200274UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg according to configuration
#define CSEM_REG_SLOW_DBG_ALM_FULL_SIZE 1
#define CSEM_REG_SLOW_DBG_EMPTY 0x200278UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is empty in sem_slow_ls_dbg
#define CSEM_REG_SLOW_DBG_EMPTY_SIZE 1
#define CSEM_REG_SLOW_DBG_FULL 0x20027cUL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is full in sem_slow_ls_dbg
#define CSEM_REG_SLOW_DBG_FULL_SIZE 1
#define CSEM_REG_SLOW_DRA_FIN_EMPTY 0x200280UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is empty in sem_slow_dra_sync
#define CSEM_REG_SLOW_DRA_FIN_EMPTY_SIZE 1
#define CSEM_REG_SLOW_DRA_FIN_FULL 0x200284UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is full in sem_slow_dra_sync (never may be active)
#define CSEM_REG_SLOW_DRA_FIN_FULL_SIZE 1
#define CSEM_REG_SLOW_DRA_INT_EMPTY 0x200288UL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is empty in sem_slow_dra_sync
#define CSEM_REG_SLOW_DRA_INT_EMPTY_SIZE 1
#define CSEM_REG_SLOW_DRA_INT_FULL 0x20028cUL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is full in sem_slow_dra_int
#define CSEM_REG_SLOW_DRA_INT_FULL_SIZE 1
#define CSEM_REG_SLOW_DRA_RD_EMPTY 0x200290UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is empty in sem_slow_dra_sync
#define CSEM_REG_SLOW_DRA_RD_EMPTY_SIZE 1
#define CSEM_REG_SLOW_DRA_RD_FULL 0x200294UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is full in sem_slow_dra_sync
#define CSEM_REG_SLOW_DRA_RD_FULL_SIZE 1
#define CSEM_REG_SLOW_DRA_WR_EMPTY 0x200298UL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is empty in sem_slow_dra_sync
#define CSEM_REG_SLOW_DRA_WR_EMPTY_SIZE 1
#define CSEM_REG_SLOW_DRA_WR_FULL 0x20029cUL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is full in sem_slow_dra_sync
#define CSEM_REG_SLOW_DRA_WR_FULL_SIZE 1
#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is empty in sem_slow_ls_ext
#define CSEM_REG_SLOW_EXT_STORE_EMPTY_SIZE 1
#define CSEM_REG_SLOW_EXT_STORE_FULL 0x2002a4UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is full in sem_slow_ls_ext
#define CSEM_REG_SLOW_EXT_STORE_FULL_SIZE 1
#define CSEM_REG_SLOW_RAM0_RD_EMPTY 0x2002a8UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is empty in sem_slow_ls_ext
#define CSEM_REG_SLOW_RAM0_RD_EMPTY_SIZE 1
#define CSEM_REG_SLOW_RAM0_RD_FULL 0x2002acUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is full in sem_slow_ls_ext
#define CSEM_REG_SLOW_RAM0_RD_FULL_SIZE 1
#define CSEM_REG_SLOW_RAM0_WR_ALM_FULL 0x2002b0UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
#define CSEM_REG_SLOW_RAM0_WR_ALM_FULL_SIZE 1
#define CSEM_REG_SLOW_RAM0_WR_EMPTY 0x2002b4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is empty in sem_slow_ls_ext
#define CSEM_REG_SLOW_RAM0_WR_EMPTY_SIZE 1
#define CSEM_REG_SLOW_RAM0_WR_FULL 0x2002b8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is full in sem_slow_ls_ext
#define CSEM_REG_SLOW_RAM0_WR_FULL_SIZE 1
#define CSEM_REG_SLOW_RAM1_RD_EMPTY 0x2002bcUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is empty in sem_slow_ls_ext
#define CSEM_REG_SLOW_RAM1_RD_EMPTY_SIZE 1
#define CSEM_REG_SLOW_RAM1_RD_FULL 0x2002c0UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is full in sem_slow_ls_ext
#define CSEM_REG_SLOW_RAM1_RD_FULL_SIZE 1
#define CSEM_REG_SLOW_RAM1_WR_ALM_FULL 0x2002c4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
#define CSEM_REG_SLOW_RAM1_WR_ALM_FULL_SIZE 1
#define CSEM_REG_SLOW_RAM1_WR_EMPTY 0x2002c8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is empty in sem_slow_ls_ext
#define CSEM_REG_SLOW_RAM1_WR_EMPTY_SIZE 1
#define CSEM_REG_SLOW_RAM1_WR_FULL 0x2002ccUL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is full in sem_slow_ls_ext
#define CSEM_REG_SLOW_RAM1_WR_FULL_SIZE 1
#define CSEM_REG_SYNC_DBG_EMPTY 0x2002d0UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is empty in sem_slow_ls_sync
#define CSEM_REG_SYNC_DBG_EMPTY_SIZE 1
#define CSEM_REG_SYNC_DBG_FULL 0x2002d4UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is full in sem_slow_ls_sync
#define CSEM_REG_SYNC_DBG_FULL_SIZE 1
#define CSEM_REG_THREAD_ERROR 0x2002d8UL //ACCESS:R DataWidth:0x14 Description: Thread error indication have bit per thread
#define CSEM_REG_THREAD_ERROR_SIZE 1
#define CSEM_REG_THREAD_OVERRUN_NUM 0x2002dcUL //ACCESS:R DataWidth:0x14 Description: Threads are sleeping in passive buffer more than ~csem_registers_thread_inter_cnt.thread_inter_cnt number of cycles
#define CSEM_REG_THREAD_OVERRUN_NUM_SIZE 1
#define CSEM_REG_THREAD_RDY 0x2002e0UL //ACCESS:R DataWidth:0x14 Description: Thread ready indication have bit per thread
#define CSEM_REG_THREAD_RDY_SIZE 1
#define CSEM_REG_THREADS_LIST 0x2002e4UL //ACCESS:RW DataWidth:0x14 Description: List of free threads . There is a bit per thread.
#define CSEM_REG_THREADS_LIST_SIZE 1
#define CSEM_REG_WB_MSB 0x2002e8UL //ACCESS:R DataWidth:0x2 Description: Reset value of this register is right when was not read to ~csem_registers_fic0_fifo.fic0_fifo or ~csem_registers_fic1_fifo.fic1_fifo or ~csem_registers_passive_buffer.passive_buffer. For read from ~csem_registers_passive_buffer.passive_buffer :b0- parity0; b1 parity1. For read from ~csem_registers_fic0_fifo.fic0_fifo and ~csem_registers_fic1_fifo.fic1_fifo :b1=0 data from ~csem_registers_fic0_fifo.fic0_fifo and ~csem_registers_fic1_fifo.fic1_fifo is valid; b1 =1 ~csem_registers_fic0_fifo.fic0_fifo and ~csem_registers_fic1_fifo.fic1_fifo is empty and data from it must be equal to 0; b0 - parity from ~csem_registers_fic0_fifo.fic0_fifo and ~csem_registers_fic1_fifo.fic1_fifo
#define CSEM_REG_WB_MSB_SIZE 1
#define CSEM_REG_FIC0_FIFO 0x200300UL //ACCESS:WB_R DataWidth:0x80 Description: Debug only. FIC0_fifo: b[127:0] data; b128-parity;b129=1- fifo empty;b129=0-data is valid
#define CSEM_REG_FIC0_FIFO_SIZE 4
#define CSEM_REG_FIC1_FIFO 0x200320UL //ACCESS:WB_R DataWidth:0x80 Description: Debug only. FIC1_fifo read for debugging mode; b[127:0] data; b128-parity;
#define CSEM_REG_FIC1_FIFO_SIZE 4
#define CSEM_REG_FIN_COMMAND 0x200340UL //ACCESS:WB_R DataWidth:0x6d Description: last fin command that was read from fifo. Its spelling in ~csem_registers_fin_fifo.fin_fifo register
#define CSEM_REG_FIN_COMMAND_SIZE 4
#define CSEM_REG_FIN_FIFO 0x200360UL //ACCESS:WB_R DataWidth:0x6d Description: Debug only. FIn FIFO. [5:0] start_rp_foc3; [11:6] start_rp_foc2; [17:12] start_rp_foc1; [23:18] start_rp_foc0; [29:24] end_rp_foc3; [35:30] end_rp_foc2; [41:36] end_rp_foc1; [47:42] end_rp_foc0; [53:48] lowest rp; [59:54] highest rp; [65:60] store start rp; [71:66] store end rp; [77:72] load start rp; [83:78] load end rp; [85:84] priority; [101:86] pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid
#define CSEM_REG_FIN_FIFO_SIZE 4
#define CSEM_REG_VFPF_ERR_NUM 0x200380UL //ACCESS:W DataWidth:0x7 Description: VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
#define CSEM_REG_VFPF_ERR_NUM_SIZE 1
#define CSEM_REG_VF_ERR_VECTOR_LSB 0x200388UL //ACCESS:R DataWidth:0x20 Description: VF/PF error bitmap vector [0-31]
#define CSEM_REG_VF_ERR_VECTOR_LSB_SIZE 1
#define CSEM_REG_VF_ERR_VECTOR_MSB 0x200390UL //ACCESS:R DataWidth:0x20 Description: VF/PF error bitmap vector [32-63]
#define CSEM_REG_VF_ERR_VECTOR_MSB_SIZE 1
#define CSEM_REG_PF_ERR_VECTOR 0x200398UL //ACCESS:R DataWidth:0x8 Description: VF/PF error bitmap vector [0-7]
#define CSEM_REG_PF_ERR_VECTOR_SIZE 1
#define CSEM_REG_THREAD_SET_NUM 0x2003a0UL //ACCESS:W DataWidth:0x5 Description: Thread ID. Write thread ID will set ready indication for this thread ID
#define CSEM_REG_THREAD_SET_NUM_SIZE 1
#define CSEM_REG_INT_TABLE 0x200400UL //ACCESS:RW DataWidth:0xf Description: Interrupt table Read and write access to it is not possible in the middle of the work
#define CSEM_REG_INT_TABLE_SIZE 256
#define CSEM_REG_PASSIVE_BUFFER 0x202000UL //ACCESS:WB DataWidth:0x80 Description: Debug only. Passive buffer memory
#define CSEM_REG_PASSIVE_BUFFER_SIZE 2048
#define CSEM_REG_PASSIVE_BUFFER_MSB 0x204000UL //ACCESS:WB DataWidth:0x80 Description: Debug only. Passive buffer memory MSB that starts from row 512 of passive buffer till row 639
#define CSEM_REG_PASSIVE_BUFFER_MSB_SIZE 512
#define CSEM_REG_FAST_MEMORY 0x220000UL //ACCESS:RW DataWidth:0x20 Description: This address space contains all registers and memories that are placed in SEM_FAST block. The SEM_FAST registers are described in appendix B. In order to access the SEM_FAST registers the base address CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each SEM_FAST register offset.
#define CSEM_REG_FAST_MEMORY_SIZE 32768
#define CSEM_REG_PRAM 0x240000UL //ACCESS:WB DataWidth:0x2e Description: pram memory. B45 is parity; b[44:0] - data.
#define CSEM_REG_PRAM_SIZE 65536
#define CSEM_REG_CSEM_UNUSED_EMPTY_0 0x200144UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_0_SIZE 2
#define CSEM_REG_CSEM_UNUSED_EMPTY_1 0x200154UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_1_SIZE 43
#define CSEM_REG_CSEM_UNUSED_EMPTY_2 0x2002ecUL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_2_SIZE 5
#define CSEM_REG_CSEM_UNUSED_EMPTY_3 0x200384UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_3_SIZE 1
#define CSEM_REG_CSEM_UNUSED_EMPTY_4 0x20038cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_4_SIZE 1
#define CSEM_REG_CSEM_UNUSED_EMPTY_5 0x200394UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_5_SIZE 1
#define CSEM_REG_CSEM_UNUSED_EMPTY_6 0x20039cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_6_SIZE 1
#define CSEM_REG_CSEM_UNUSED_EMPTY_7 0x2003a4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_7_SIZE 1
#define CSEM_REG_CSEM_UNUSED_EMPTY_8 0x2003b0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_8_SIZE 20
#define CSEM_REG_CSEM_UNUSED_EMPTY_9 0x200800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_9_SIZE 1536
#define CSEM_REG_CSEM_UNUSED_EMPTY_10 0x204800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define CSEM_REG_CSEM_UNUSED_EMPTY_10_SIZE 28160
#define DBG_REG_CLIENT_ENABLE 0xc000UL //ACCESS:RW DataWidth:0x9 Description: debug only: These bits are enables to client interfaces as follows: 0b000000001 - rx; 0b000000010 - nm; 0b000000100 - ulp; 0b000001000 - tx; 0b000010000 - cpt; 0b000100000 - usem; 0b001000000 - xsem; 0b010000000 - tsem; 0b100000000 - csem;
#define DBG_REG_OUTPUT_ENABLE 0xc004UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define DBG_OUTPUT_ENABLE_REG_PCI_REQ_ENABLE (0x1<<0)
#define DBG_OUTPUT_ENABLE_REG_PCI_REQ_ENABLE_SIZE 0
#define DBG_OUTPUT_ENABLE_REG_PCI_DATA_ENABLE (0x1<<1)
#define DBG_OUTPUT_ENABLE_REG_PCI_DATA_ENABLE_SIZE 1
#define DBG_OUTPUT_ENABLE_REG_NIG_ENABLE (0x1<<2)
#define DBG_OUTPUT_ENABLE_REG_NIG_ENABLE_SIZE 2
#define DBG_REG_CALENDAR_SLOT0 0xc008UL //ACCESS:RW DataWidth:0x4 Description: debug only: These bits are a client index for slot 0 in calendar as follows: 0b0000 - rx; 0b0001 - nm; 0b0010 - ulp; 0b0011 - tx; 0b0100 - cpt; 0b0101 - usem; 0b0110 - xsem; 0b0111 - tsem; 0b1000 - csem; 0b1001 - cpu; 0b1010 - joint HW; 0b1111 - None;
#define DBG_REG_CALENDAR_SLOT1 0xc00cUL //ACCESS:RW DataWidth:0x4 Description: debug only: These bits are a client index for slot 1 in calendar as follows: 0b0000 - rx; 0b0001 - nm; 0b0010 - ulp; 0b0011 - tx; 0b0100 - cpt; 0b0101 - usem; 0b0110 - xsem; 0b0111 - tsem; 0b1000 - csem; 0b1001 - cpu; 0b1010 - joint HW; 0b1111 - None;
#define DBG_REG_CALENDAR_SLOT2 0xc010UL //ACCESS:RW DataWidth:0x4 Description: debug only: These bits are a client index for slot 2 in calendar as follows: 0b0000 - rx; 0b0001 - nm; 0b0010 - ulp; 0b0011 - tx; 0b0100 - cpt; 0b0101 - usem; 0b0110 - xsem; 0b0111 - tsem; 0b1000 - csem; 0b1001 - cpu; 0b1010 - joint HW; 0b1111 - None;
#define DBG_REG_CALENDAR_SLOT3 0xc014UL //ACCESS:RW DataWidth:0x4 Description: debug only: These bits are a client index for slot 3 in calendar as follows: 0b0000 - rx; 0b0001 - nm; 0b0010 - ulp; 0b0011 - tx; 0b0100 - cpt; 0b0101 - usem; 0b0110 - xsem; 0b0111 - tsem; 0b1000 - csem; 0b1001 - cpu; 0b1010 - joint HW; 0b1111 - None;
#define DBG_REG_CALENDAR_SLOT4 0xc018UL //ACCESS:RW DataWidth:0x4 Description: debug only: These bits are a client index for slot 4 in calendar as follows: 0b0000 - rx; 0b0001 - nm; 0b0010 - ulp; 0b0011 - tx; 0b0100 - cpt; 0b0101 - usem; 0b0110 - xsem; 0b0111 - tsem; 0b1000 - csem; 0b1001 - cpu; 0b1010 - joint HW; 0b1111 - None;
#define DBG_REG_CALENDAR_SLOT5 0xc01cUL //ACCESS:RW DataWidth:0x4 Description: debug only: These bits are a client index for slot 5 in calendar as follows: 0b0000 - rx; 0b0001 - nm; 0b0010 - ulp; 0b0011 - tx; 0b0100 - cpt; 0b0101 - usem; 0b0110 - xsem; 0b0111 - tsem; 0b1000 - csem; 0b1001 - cpu; 0b1010 - joint HW; 0b1111 - None;
#define DBG_REG_CALENDAR_SLOT6 0xc020UL //ACCESS:RW DataWidth:0x4 Description: debug only: These bits are a client index for slot 6 in calendar as follows: 0b0000 - rx; 0b0001 - nm; 0b0010 - ulp; 0b0011 - tx; 0b0100 - cpt; 0b0101 - usem; 0b0110 - xsem; 0b0111 - tsem; 0b1000 - csem; 0b1001 - cpu; 0b1010 - joint HW; 0b1111 - None;
#define DBG_REG_CALENDAR_SLOT7 0xc024UL //ACCESS:RW DataWidth:0x4 Description: debug only: These bits are a client index for slot 7 in calendar as follows: 0b0000 - rx; 0b0001 - nm; 0b0010 - ulp; 0b0011 - tx; 0b0100 - cpt; 0b0101 - usem; 0b0110 - xsem; 0b0111 - tsem; 0b1000 - csem; 0b1001 - cpu; 0b1010 - joint HW; 0b1111 - None;
#define DBG_REG_CALENDAR_PACE 0xc028UL //ACCESS:RW DataWidth:0x8 Description: debug only: This bit indicates the calendar pacing which is the number of cycles the calendar stays on the same slot before moving to the next slot to support lower rates (During the number of cycles configured in the #dbg_registers_calendar_pace only one cycle can be valid)
#define DBG_REG_FRAMING_MODE 0xc02cUL //ACCESS:RW DataWidth:0x2 Description: debug only: These bits indicate the framing mode: 0 - tdm (32/64) mode; 1 - 64 bits mode; 2 - 24 bits mode;
#define DBG_REG_DEBUG_TARGET 0xc030UL //ACCESS:RW DataWidth:0x2 Description: debug only: These bits indicates the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI;
#define DBG_REG_FULL_MODE 0xc034UL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicates whether data will be wrapped (oldest data is thrown) or overflowed-one shot (newest data is thrown) as follows: (a) When ~dbg_registers_debug_target=2/0 (PCI/internal buffer): 1 - wrap; 0 - One Shot; (b) When ~dbg_registers_debug_target=1 (NIG): 1 - constant send; 0 - One Shot;
#define DBG_REG_ETHERNET_HDR0 0xc038UL //ACCESS:RW DataWidth:0x20 Description: debug only: These bits indicate the value of the ethernet header: bytes 0:3; The ethernet header is 14 bytes length which are being added at the beginning of the packet in network order
#define DBG_REG_ETHERNET_HDR1 0xc03cUL //ACCESS:RW DataWidth:0x20 Description: debug only: These bits indicate the value of the ethernet header: bytes 4:7; The ethernet header is 14 bytes length which are being added at the beginning of the packet in network order
#define DBG_REG_ETHERNET_HDR2 0xc040UL //ACCESS:RW DataWidth:0x20 Description: debug only: These bits indicate the value of the ethernet header: bytes 8:11; The ethernet header is 14 bytes length which are being added at the beginning of the packet in network order
#define DBG_REG_ETHERNET_HDR3 0xc044UL //ACCESS:RW DataWidth:0x10 Description: debug only: These bits indicate the value of the ethernet header: bytes 12:13; The ethernet header is 14 bytes length which are being added at the beginning of the packet in network order
#define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_LSB 0xc048UL //ACCESS:RW DataWidth:0x20 Description: debug only: LSB of external PCI buffer start address; MUST be configured BEFORE pci_req_credit is configured
#define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_MSB 0xc04cUL //ACCESS:RW DataWidth:0x20 Description: debug only: MSB of external PCI buffer start address; MUST be configured BEFORE pci_req_credit is configured
#define DBG_REG_PCI_EXT_BUFFER_SIZE 0xc050UL //ACCESS:RW DataWidth:0x18 Description: debug only: These bits indicate the value of the external PCI buffer size in 256 Byte chunks (The reset value is for 128 Mbyte buffer)
#define DBG_REG_NIG_DATA_LIMIT_SIZE 0xc054UL //ACCESS:RW DataWidth:0x16 Description: debug only: These bits indicate the max value of 1024 Byte data chunks sent through the NIG (The reset value is for 4M chunks of 1024 data byte each); Relevant only when debug_target=1 (NIG) & full_mode=0 (one-shot)
#define DBG_REG_PCI_VQ_ID 0xc058UL //ACCESS:RW DataWidth:0x5 Description: debug only: This bit is a handle given to the PCI block to refer to this request
#define DBG_REG_CPU_DEBUG_FRAME 0xc05cUL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicate the frame signal of the debug data that arrives from the CPU
#define DBG_REG_CPU_TIMEOUT 0xc060UL //ACCESS:RW DataWidth:0x1 Description: debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty
#define DBG_REG_DBG_BLOCK_ON 0xc064UL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;
#define DBG_REG_NUM_OF_QWORDS_SENT0 0xc068UL //ACCESS:ST DataWidth:0x20 Description: debug only: These bits represent the total number of qwords sent from the dbg block to output interface (NIG/PCI)
#define DBG_REG_TDM64_ENABLE 0xc06cUL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicates tdm working mode as follows: (a) 1 - enables tdm64 mechanism which allows 64 bit of data. In this case the 32 lsb are chosen by the tdm mechanism using slots 0..6 and the 32 msb are taken from the joint HW and are marked as slot number 7; (b) 0 - disables the tdm64 mechanism hence allowing 32 bits of data only; the tdm operation mode allows only the 32 lsb of data. In this case the data is chosen by the tdm mechanism using slots 0..7
#define DBG_REG_IMMEDIATE_ACK 0xc070UL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicates that an immediate ack should be sent to the CPU upon writing to ~dbg_registers_cpu_debug_data and an interrupt will be sent when a new write can be issued (after the data was actually taken); If 0 then the ack will be delayed until a new write can be issued by the CPU (after the data was actually taken)
#define DBG_REG_NO_GRANT_ON_FULL 0xc074UL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicate whether grant will be issued by the dbg block towards the storms in case the internal buffer is almost full as follows: (a) 1 - no grants will be made to the storms when the internal buffer is almost full. When the buffer will be partialy freed (enough for a complete data chunk) then grant is resumed; (b) 0 - grant is supplied every time the matching storms's slot is chosen disregarding the volume status of the internal buffer.
#define DBG_REG_FULL_BUFFER_THR 0xc078UL //ACCESS:RW DataWidth:0x7 Description: debug only: These bits indicate the value of the internal buffer almost full threshold used for deciding when ~dbg_registers_dbg_buffer_full output should go high/low; holds the number of 128 bit free lines in the internal buffer under which the full would go high; not applicable when ~dbg_registers_debug_target=0 (internal buffer) and ~dbg_registers_full_mode=1 (wrap);
#define DBG_REG_PCI_LOGIC_ADDR 0xc07cUL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicates logical/physical address in PCI request as follows: (a) 1 - logical address; (b) 0 - physical address;
#define DBG_REG_PATTERN_RECOGNITION_DISABLE 0xc080UL //ACCESS:RW DataWidth:0x1 Description: debug only: For pattern recognition usage: This bit indicates whether the pattern recognition feature is disabled/enabled as follows: (a) 1 - disabled; (b) 0 - enabled;
#define DBG_REG_PATTERN_RECOGNITION_STORAGE_MODE 0xc084UL //ACCESS:RW DataWidth:0x1 Description: debug only: For pattern recognition usage: This bit indicates the trigger behavior of the pattern recognition feature as follows: (a) 1 - stop debug data storgae when the expected pattern is initially recognized; (b) 0 - start debug data storage when the expected pattern is initially recognized
#define DBG_REG_PATTERN_RECOGNITION_FILTER 0xc088UL //ACCESS:RW DataWidth:0x1 Description: debug only: For pattern recognition usage: This bit indicates whether data is continously stored in the dbg block until/from pattern recognition initial event; or stored only in cycles of a pattern recognition event occurence as follows: (a) 1 - enable continuously data storage after/before first occurence of pattern recognition; (b) 0 - enable data storage only in cycles of a pttern recognition event occurence
#define DBG_REG_DBG_INT_STS 0xc08cUL //ACCESS:R DataWidth:0x2 Description: Interrupt register #0 read
#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define DBG_DBG_INT_STS_REG_CPU_DATA_TAKEN_INTR (0x1<<1)
#define DBG_DBG_INT_STS_REG_CPU_DATA_TAKEN_INTR_SIZE 1
#define DBG_REG_DBG_INT_STS_CLR 0xc090UL //ACCESS:RC DataWidth:0x2 Description: Interrupt register #0 read clear
#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define DBG_DBG_INT_STS_CLR_REG_CPU_DATA_TAKEN_INTR (0x1<<1)
#define DBG_DBG_INT_STS_CLR_REG_CPU_DATA_TAKEN_INTR_SIZE 1
#define DBG_REG_DBG_INT_STS_WR 0xc094UL //ACCESS:WR DataWidth:0x2 Description: Interrupt register #0 bit set or clear
#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define DBG_DBG_INT_STS_WR_REG_CPU_DATA_TAKEN_INTR (0x1<<1)
#define DBG_DBG_INT_STS_WR_REG_CPU_DATA_TAKEN_INTR_SIZE 1
#define DBG_REG_DBG_INT_MASK 0xc098UL //ACCESS:RW DataWidth:0x2 Description: Interrupt mask register #0 read/write
#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define DBG_DBG_INT_MASK_REG_CPU_DATA_TAKEN_INTR (0x1<<1)
#define DBG_DBG_INT_MASK_REG_CPU_DATA_TAKEN_INTR_SIZE 1
#define DBG_REG_DBG_PRTY_STS 0xc09cUL //ACCESS:R DataWidth:0x1 Description: Parity register #0 read
#define DBG_DBG_PRTY_STS_REG_PARITY (0x1<<0)
#define DBG_DBG_PRTY_STS_REG_PARITY_SIZE 0
#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0UL //ACCESS:RC DataWidth:0x1 Description: Parity register #0 read clear
#define DBG_DBG_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define DBG_DBG_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define DBG_REG_DBG_PRTY_STS_WR 0xc0a4UL //ACCESS:WR DataWidth:0x1 Description: Parity register #0 bit set or clear
#define DBG_DBG_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define DBG_DBG_PRTY_STS_WR_REG_PARITY_SIZE 0
#define DBG_REG_DBG_PRTY_MASK 0xc0a8UL //ACCESS:RW DataWidth:0x1 Description: Parity mask register #0 read/write
#define DBG_DBG_PRTY_MASK_REG_PARITY (0x1<<0)
#define DBG_DBG_PRTY_MASK_REG_PARITY_SIZE 0
#define DBG_REG_TRIGGER_ENABLE 0xd010UL //ACCESS:RW DataWidth:0x1 Description: (a) 0 - trigger machine is off (all data will bypass the triggering machine) in this mode trigger_event is never asserted. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode & rcrd_on_window_post_trgr_evnt_mode
#define DBG_REG_TRIGGER_INTERLEAVED_ENABLE 0xd014UL //ACCESS:RW DataWidth:0x1 Description: (a) 0 - triggering interleaved messages is disbaled. (b) 1 - triggering interleaved messages is enabled; will be used for triggering on recorded handler messages. NOTE: triggering is possible on one level depth of interleaved messages; i.e. if message B is interleaved within message A then it is ok; However if message C is interleaved within message B and message B is interleaved within message A this scenario is NOT supported
#define DBG_REG_TRIGGER_STATE_SLOTS_0 0xd018UL //ACCESS:RW DataWidth:0x8 Description: Valid slots for triggering machine in relevant state. Data from clients which are not in those slots will be dropped (not compared). b0 - slot0; b1 - slot1;. . .;b7 - slot7; NOTE: 1. NA when framing mode is tdm64 and trigger_state_valid_seli=1; in that case the only client is the JointHW (upper 32 bits of the calendar) and hence the value of trigger_state_slotsi is disregarded. Each valid cycle will be compared. 2. all set bits MUST contain the same client
#define DBG_REG_TRIGGER_STATE_SLOTS_1 0xd01cUL //ACCESS:RW DataWidth:0x8 Description: Valid slots for triggering machine in relevant state. Data from clients which are not in those slots will be dropped (not compared). b0 - slot0; b1 - slot1;. . .;b7 - slot7; NOTE: 1. NA when framing mode is tdm64 and trigger_state_valid_seli=1; in that case the only client is the JointHW (upper 32 bits of the calendar) and hence the value of trigger_state_slotsi is disregarded. Each valid cycle will be compared. 2. all set bits MUST contain the same client
#define DBG_REG_TRIGGER_STATE_SLOTS_2 0xd020UL //ACCESS:RW DataWidth:0x8 Description: Valid slots for triggering machine in relevant state. Data from clients which are not in those slots will be dropped (not compared). b0 - slot0; b1 - slot1;. . .;b7 - slot7; NOTE: 1. NA when framing mode is tdm64 and trigger_state_valid_seli=1; in that case the only client is the JointHW (upper 32 bits of the calendar) and hence the value of trigger_state_slotsi is disregarded. Each valid cycle will be compared. 2. all set bits MUST contain the same client
#define DBG_REG_TRIGGER_STATE_VALID_SEL_0 0xd024UL //ACCESS:RW DataWidth:0x1 Description: When working in tdm64 mode there are 2 valid signals as follows: (1) Valid[3] - validates data[63:32] (2) Valid[0] - validates data[31:0] (a) 1 - use valid[3] (compared data is data[63:32] in that case); (b) 0 - use valid[0] (compared data is data[31:0] in that case). NOTE: 1. in each state the triggering machine compares the constraints to single data source only (which means that only data[31:0] / data[63:32] will be compared in each state) 2. if 64 bit framing mode OR tdm32 framing mode then this bit is not relevant; in that case only valid[0] & data[31:0]/data[63:0] are referred.
#define DBG_REG_TRIGGER_STATE_VALID_SEL_1 0xd028UL //ACCESS:RW DataWidth:0x1 Description: When working in tdm64 mode there are 2 valid signals as follows: (1) Valid[3] - validates data[63:32] (2) Valid[0] - validates data[31:0] (a) 1 - use valid[3] (compared data is data[63:32] in that case); (b) 0 - use valid[0] (compared data is data[31:0] in that case). NOTE: 1. in each state the triggering machine compares the constraints to single data source only (which means that only data[31:0] / data[63:32] will be compared in each state) 2. if 64 bit framing mode OR tdm32 framing mode then this bit is not relevant; in that case only valid[0] & data[31:0]/data[63:0] are referred.
#define DBG_REG_TRIGGER_STATE_VALID_SEL_2 0xd02cUL //ACCESS:RW DataWidth:0x1 Description: When working in tdm64 mode there are 2 valid signals as follows: (1) Valid[3] - validates data[63:32] (2) Valid[0] - validates data[31:0] (a) 1 - use valid[3] (compared data is data[63:32] in that case); (b) 0 - use valid[0] (compared data is data[31:0] in that case). NOTE: 1. in each state the triggering machine compares the constraints to single data source only (which means that only data[31:0] / data[63:32] will be compared in each state) 2. if 64 bit framing mode OR tdm32 framing mode then this bit is not relevant; in that case only valid[0] & data[31:0]/data[63:0] are referred.
#define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_0 0xd030UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
#define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_1 0xd034UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
#define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_2 0xd038UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_0 0xd03cUL //ACCESS:RW DataWidth:0x2 Description: Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_1 0xd040UL //ACCESS:RW DataWidth:0x2 Description: Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_2 0xd044UL //ACCESS:RW DataWidth:0x2 Description: Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_3 0xd048UL //ACCESS:RW DataWidth:0x2 Description: Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_4 0xd04cUL //ACCESS:RW DataWidth:0x2 Description: Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_5 0xd050UL //ACCESS:RW DataWidth:0x2 Description: Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
#define DBG_REG_TRIGGER_STATE_SET_COUNT_0 0xd054UL //ACCESS:RW DataWidth:0x10 Description: Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA
#define DBG_REG_TRIGGER_STATE_SET_COUNT_1 0xd058UL //ACCESS:RW DataWidth:0x10 Description: Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA
#define DBG_REG_TRIGGER_STATE_SET_COUNT_2 0xd05cUL //ACCESS:RW DataWidth:0x10 Description: Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA
#define DBG_REG_TRIGGER_STATE_SET_COUNT_3 0xd060UL //ACCESS:RW DataWidth:0x10 Description: Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA
#define DBG_REG_TRIGGER_STATE_SET_COUNT_4 0xd064UL //ACCESS:RW DataWidth:0x10 Description: Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA
#define DBG_REG_TRIGGER_STATE_SET_COUNT_5 0xd068UL //ACCESS:RW DataWidth:0x10 Description: Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0 0xd06cUL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_1 0xd070UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_2 0xd074UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_3 0xd078UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_4 0xd07cUL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_5 0xd080UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_6 0xd084UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_7 0xd088UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_8 0xd08cUL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_9 0xd090UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_10 0xd094UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_11 0xd098UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_12 0xd09cUL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_13 0xd0a0UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_14 0xd0a4UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_15 0xd0a8UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_16 0xd0acUL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_17 0xd0b0UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_18 0xd0b4UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_19 0xd0b8UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_20 0xd0bcUL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_21 0xd0c0UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_22 0xd0c4UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_23 0xd0c8UL //ACCESS:RW DataWidth:0x20 Description: The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0 0xd0ccUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_1 0xd0d0UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_2 0xd0d4UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_3 0xd0d8UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_4 0xd0dcUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_5 0xd0e0UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_6 0xd0e4UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_7 0xd0e8UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_8 0xd0ecUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_9 0xd0f0UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_10 0xd0f4UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_11 0xd0f8UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_12 0xd0fcUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_13 0xd100UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_14 0xd104UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_15 0xd108UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_16 0xd10cUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_17 0xd110UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_18 0xd114UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_19 0xd118UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_20 0xd11cUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_21 0xd120UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_22 0xd124UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_23 0xd128UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0 0xd12cUL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_1 0xd130UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_2 0xd134UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_3 0xd138UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_4 0xd13cUL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_5 0xd140UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_6 0xd144UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_7 0xd148UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_8 0xd14cUL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_9 0xd150UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_10 0xd154UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_11 0xd158UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_12 0xd15cUL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_13 0xd160UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_14 0xd164UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_15 0xd168UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_16 0xd16cUL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_17 0xd170UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_18 0xd174UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_19 0xd178UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_20 0xd17cUL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_21 0xd180UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_22 0xd184UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_23 0xd188UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0xd18cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_1 0xd190UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_2 0xd194UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_3 0xd198UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_4 0xd19cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_5 0xd1a0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_6 0xd1a4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_7 0xd1a8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_8 0xd1acUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_9 0xd1b0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_10 0xd1b4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_11 0xd1b8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_12 0xd1bcUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_13 0xd1c0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_14 0xd1c4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_15 0xd1c8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_16 0xd1ccUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_17 0xd1d0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_18 0xd1d4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_19 0xd1d8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_20 0xd1dcUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_21 0xd1e0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_22 0xd1e4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_23 0xd1e8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0 0xd1ecUL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_1 0xd1f0UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_2 0xd1f4UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_3 0xd1f8UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_4 0xd1fcUL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_5 0xd200UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_6 0xd204UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_7 0xd208UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_8 0xd20cUL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_9 0xd210UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_10 0xd214UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_11 0xd218UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_12 0xd21cUL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_13 0xd220UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_14 0xd224UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_15 0xd228UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_16 0xd22cUL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_17 0xd230UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_18 0xd234UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_19 0xd238UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_20 0xd23cUL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_21 0xd240UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_22 0xd244UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_23 0xd248UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between trigger_state_set_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0xd24cUL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_0_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_0 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_0_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_0_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_0_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_0 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_0_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_0_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1 0xd250UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_1_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_1 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_1_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_1_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_1_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_1 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_1_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_1_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2 0xd254UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_2_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_2 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_2_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_2_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_2_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_2 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_2_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_2_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3 0xd258UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_3_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_3 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_3_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_3_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_3_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_3 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_3_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_3_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4 0xd25cUL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_4_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_4 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_4_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_4_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_4_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_4 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_4_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_4_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5 0xd260UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_5_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_5 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_5_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_5_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_5_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_5 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_5_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_5_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6 0xd264UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_6_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_6 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_6_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_6_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_6_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_6 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_6_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_6_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7 0xd268UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_7_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_7 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_7_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_7_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_7_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_7 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_7_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_7_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8 0xd26cUL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_8_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_8 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_8_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_8_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_8_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_8 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_8_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_8_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9 0xd270UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_9_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_9 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_9_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_9_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_9_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_9 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_9_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_9_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10 0xd274UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_10_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_10 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_10_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_10_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_10_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_10 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_10_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_10_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11 0xd278UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_11_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_11 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_11_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_11_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_11_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_11 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_11_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_11_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12 0xd27cUL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_12_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_12 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_12_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_12_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_12_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_12 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_12_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_12_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13 0xd280UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_13_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_13 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_13_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_13_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_13_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_13 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_13_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_13_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14 0xd284UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_14_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_14 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_14_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_14_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_14_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_14 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_14_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_14_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15 0xd288UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_15_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_15 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_15_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_15_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_15_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_15 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_15_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_15_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16 0xd28cUL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_16_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_16 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_16_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_16_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_16_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_16 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_16_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_16_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17 0xd290UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_17_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_17 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_17_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_17_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_17_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_17 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_17_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_17_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18 0xd294UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_18_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_18 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_18_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_18_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_18_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_18 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_18_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_18_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19 0xd298UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_19_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_19 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_19_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_19_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_19_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_19 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_19_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_19_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20 0xd29cUL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_20_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_20 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_20_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_20_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_20_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_20 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_20_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_20_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21 0xd2a0UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_21_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_21 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_21_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_21_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_21_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_21 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_21_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_21_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22 0xd2a4UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_22_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_22 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_22_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_22_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_22_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_22 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_22_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_22_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23 0xd2a8UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_23_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_23 (0x1f<<0)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_23_REG_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_23_SIZE 0
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_23_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_23 (0x1f<<5)
#define DBG_TRIGGER_STATE_SET_CNSTR_RANGE_23_REG_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_23_SIZE 5
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0xd2acUL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_1 0xd2b0UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_2 0xd2b4UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_3 0xd2b8UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_4 0xd2bcUL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_5 0xd2c0UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_6 0xd2c4UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_7 0xd2c8UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_8 0xd2ccUL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_9 0xd2d0UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_10 0xd2d4UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_11 0xd2d8UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_12 0xd2dcUL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_13 0xd2e0UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_14 0xd2e4UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_15 0xd2e8UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_16 0xd2ecUL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_17 0xd2f0UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_18 0xd2f4UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_19 0xd2f8UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_20 0xd2fcUL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_21 0xd300UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_22 0xd304UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_23 0xd308UL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0 0xd30cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_1 0xd310UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_2 0xd314UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_3 0xd318UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_4 0xd31cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_5 0xd320UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_6 0xd324UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_7 0xd328UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_8 0xd32cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_9 0xd330UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_10 0xd334UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_11 0xd338UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_12 0xd33cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_13 0xd340UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_14 0xd344UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_15 0xd348UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_16 0xd34cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_17 0xd350UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_18 0xd354UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_19 0xd358UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_20 0xd35cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_21 0xd360UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_22 0xd364UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_23 0xd368UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_0 0xd36cUL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_1 0xd370UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_2 0xd374UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_3 0xd378UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_4 0xd37cUL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_5 0xd380UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_6 0xd384UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_7 0xd388UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_8 0xd38cUL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_9 0xd390UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_10 0xd394UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_11 0xd398UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_12 0xd39cUL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_13 0xd3a0UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_14 0xd3a4UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_15 0xd3a8UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_16 0xd3acUL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_17 0xd3b0UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_18 0xd3b4UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_19 0xd3b8UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_20 0xd3bcUL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_21 0xd3c0UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_22 0xd3c4UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_23 0xd3c8UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai. (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0 0xd3ccUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_1 0xd3d0UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_2 0xd3d4UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_3 0xd3d8UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_4 0xd3dcUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_5 0xd3e0UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_6 0xd3e4UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_7 0xd3e8UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_8 0xd3ecUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_9 0xd3f0UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_10 0xd3f4UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_11 0xd3f8UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_12 0xd3fcUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_13 0xd400UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_14 0xd404UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_15 0xd408UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_16 0xd40cUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_17 0xd410UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_18 0xd414UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_19 0xd418UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_20 0xd41cUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_21 0xd420UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_22 0xd424UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_23 0xd428UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_0 0xd42cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use trigger_state_valid_seli to determine which frame (frame[0]/frame[3]) signals message boundary (end of message)
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_1 0xd430UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use trigger_state_valid_seli to determine which frame (frame[0]/frame[3]) signals message boundary (end of message)
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_2 0xd434UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use trigger_state_valid_seli to determine which frame (frame[0]/frame[3]) signals message boundary (end of message)
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0xd438UL //ACCESS:RW DataWidth:0x7 Description: Message length-1 in terms of numbers of cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when trigger_state_msg_length_eni = 1
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_1 0xd43cUL //ACCESS:RW DataWidth:0x7 Description: Message length-1 in terms of numbers of cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when trigger_state_msg_length_eni = 1
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_2 0xd440UL //ACCESS:RW DataWidth:0x7 Description: Message length-1 in terms of numbers of cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when trigger_state_msg_length_eni = 1
#define DBG_REG_TRIGGER_INDIRECT0_STATE 0xd444UL //ACCESS:RW DataWidth:0x3 Description: If set then record data in relevant state; If clear then do not record data in relevant state; b0: state0; b1: state1; b2: state2;
#define DBG_REG_TRIGGER_INDIRECT0_OFFSET_0 0xd448UL //ACCESS:RW DataWidth:0x8 Description: The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect0_offseti from the last message will be recorded. NOTE: even offsets are for the 32 lsb as uneven offsets are for the 32 msb. For example offset=0 is for cycle 0 for the 32 lsb; offset=1 is for cycle 0 for the 32 msb; offset=2N is for cycle N for the 32 lsb; offset=2N+1 is for cycle N for the 32 msb;
#define DBG_REG_TRIGGER_INDIRECT0_OFFSET_1 0xd44cUL //ACCESS:RW DataWidth:0x8 Description: The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect0_offseti from the last message will be recorded. NOTE: even offsets are for the 32 lsb as uneven offsets are for the 32 msb. For example offset=0 is for cycle 0 for the 32 lsb; offset=1 is for cycle 0 for the 32 msb; offset=2N is for cycle N for the 32 lsb; offset=2N+1 is for cycle N for the 32 msb;
#define DBG_REG_TRIGGER_INDIRECT0_OFFSET_2 0xd450UL //ACCESS:RW DataWidth:0x8 Description: The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect0_offseti from the last message will be recorded. NOTE: even offsets are for the 32 lsb as uneven offsets are for the 32 msb. For example offset=0 is for cycle 0 for the 32 lsb; offset=1 is for cycle 0 for the 32 msb; offset=2N is for cycle N for the 32 lsb; offset=2N+1 is for cycle N for the 32 msb;
#define DBG_REG_TRIGGER_INDIRECT0_SHIFT_0 0xd454UL //ACCESS:RW DataWidth:0x2 Description: Shift vector (byte resolution) for the data trigger_indirect0_recorded_data The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
#define DBG_REG_TRIGGER_INDIRECT0_SHIFT_1 0xd458UL //ACCESS:RW DataWidth:0x2 Description: Shift vector (byte resolution) for the data trigger_indirect0_recorded_data The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
#define DBG_REG_TRIGGER_INDIRECT0_SHIFT_2 0xd45cUL //ACCESS:RW DataWidth:0x2 Description: Shift vector (byte resolution) for the data trigger_indirect0_recorded_data The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
#define DBG_REG_TRIGGER_INDIRECT0_MASK_0 0xd460UL //ACCESS:RW DataWidth:0x4 Description: If set then the relevant byte will be zeroed; if clear then the relevant byte will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect0_recorded_data; (b) The mask is implemented in byte resolution. (c) b0: byte0; b1: byte1; b2: byte2; b3: byte2 (d) useful when trigger_state_set_cnstr_oprtni > 0 (>/)
#define DBG_REG_TRIGGER_INDIRECT0_MASK_1 0xd464UL //ACCESS:RW DataWidth:0x4 Description: If set then the relevant byte will be zeroed; if clear then the relevant byte will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect0_recorded_data; (b) The mask is implemented in byte resolution. (c) b0: byte0; b1: byte1; b2: byte2; b3: byte2 (d) useful when trigger_state_set_cnstr_oprtni > 0 (>/)
#define DBG_REG_TRIGGER_INDIRECT0_MASK_2 0xd468UL //ACCESS:RW DataWidth:0x4 Description: If set then the relevant byte will be zeroed; if clear then the relevant byte will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect0_recorded_data; (b) The mask is implemented in byte resolution. (c) b0: byte0; b1: byte1; b2: byte2; b3: byte2 (d) useful when trigger_state_set_cnstr_oprtni > 0 (>/)
#define DBG_REG_TRIGGER_INDIRECT1_STATE 0xd46cUL //ACCESS:RW DataWidth:0x3 Description: If set then record data in relevant state; If clear then do not record data in relevant state; b0: state0; b1: state1; b2: state2;
#define DBG_REG_TRIGGER_INDIRECT1_OFFSET_0 0xd470UL //ACCESS:RW DataWidth:0x8 Description: The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect1_offseti from the last message will be recorded. NOTE: even offsets are for the 32 lsb as uneven offsets are for the 32 msb. For example offset=0 is for cycle 0 for the 32 lsb; offset=1 is for cycle 0 for the 32 msb; offset=2N is for cycle N for the 32 lsb; offset=2N+1 is for cycle N for the 32 msb;
#define DBG_REG_TRIGGER_INDIRECT1_OFFSET_1 0xd474UL //ACCESS:RW DataWidth:0x8 Description: The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect1_offseti from the last message will be recorded. NOTE: even offsets are for the 32 lsb as uneven offsets are for the 32 msb. For example offset=0 is for cycle 0 for the 32 lsb; offset=1 is for cycle 0 for the 32 msb; offset=2N is for cycle N for the 32 lsb; offset=2N+1 is for cycle N for the 32 msb;
#define DBG_REG_TRIGGER_INDIRECT1_OFFSET_2 0xd478UL //ACCESS:RW DataWidth:0x8 Description: The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect1_offseti from the last message will be recorded. NOTE: even offsets are for the 32 lsb as uneven offsets are for the 32 msb. For example offset=0 is for cycle 0 for the 32 lsb; offset=1 is for cycle 0 for the 32 msb; offset=2N is for cycle N for the 32 lsb; offset=2N+1 is for cycle N for the 32 msb;
#define DBG_REG_TRIGGER_INDIRECT1_SHIFT_0 0xd47cUL //ACCESS:RW DataWidth:0x2 Description: Shift vector (byte resolution) for the data trigger_indirect1_recorded_data The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
#define DBG_REG_TRIGGER_INDIRECT1_SHIFT_1 0xd480UL //ACCESS:RW DataWidth:0x2 Description: Shift vector (byte resolution) for the data trigger_indirect1_recorded_data The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
#define DBG_REG_TRIGGER_INDIRECT1_SHIFT_2 0xd484UL //ACCESS:RW DataWidth:0x2 Description: Shift vector (byte resolution) for the data trigger_indirect1_recorded_data The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
#define DBG_REG_TRIGGER_INDIRECT1_MASK_0 0xd488UL //ACCESS:RW DataWidth:0x4 Description: If set then the relevant byte will be zeroed; if clear then the relevant byte will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect1_recorded_data; (b) The mask is implemented in byte resolution. (c) b0: byte0; b1: byte1; b2: byte2; b3: byte2 (d) useful when trigger_state_set_cnstr_oprtni > 0 (>/)
#define DBG_REG_TRIGGER_INDIRECT1_MASK_1 0xd48cUL //ACCESS:RW DataWidth:0x4 Description: If set then the relevant byte will be zeroed; if clear then the relevant byte will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect1_recorded_data; (b) The mask is implemented in byte resolution. (c) b0: byte0; b1: byte1; b2: byte2; b3: byte2 (d) useful when trigger_state_set_cnstr_oprtni > 0 (>/)
#define DBG_REG_TRIGGER_INDIRECT1_MASK_2 0xd490UL //ACCESS:RW DataWidth:0x4 Description: If set then the relevant byte will be zeroed; if clear then the relevant byte will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect1_recorded_data; (b) The mask is implemented in byte resolution. (c) b0: byte0; b1: byte1; b2: byte2; b3: byte2 (d) useful when trigger_state_set_cnstr_oprtni > 0 (>/)
#define DBG_REG_FILTER_ENABLE 0xd494UL //ACCESS:RW DataWidth:0x2 Description: (a) 00 - Filter off; in that case all data should be transmitted to the internal buffer without any filtering implemented (data should bypass filtering machine). (b) 01 - Filter on prior (in time domain) to trigger_event (asserted by the triggering machine block) only; When off (after trigger event) - data should be transmitted to the internal buffer without any filtering. in this mode trigger_enable must be set. (c) 10 - Filter on upon trigger_event (asserted by the triggering machine) only. When off (before trigger event) - data should be transmitted to the internal buffer without any filtering. in this mode trigger_enable must be set. (d) 11 - Filter on - constant filtering; in this case the triggering event (asserted by the triggering machine) is irrelevant.
#define DBG_REG_FILTER_SLOTS 0xd498UL //ACCESS:RW DataWidth:0x8 Description: Valid slots for filtering machine. Data from clients which are not in those slots will be dropped (not compared). b0 - slot0; b1 - slot1;. . .;b7 - slot7; NOTE: (1) NA when framing mode is tdm64 and filter_valid_sel=1; in that case the only client is the JointHW (upper 32 bits of the calendar) and hence the value of filter_slots is disregarded. Each valid cycle will be compared. (2) all set bits MUST contain the same client
#define DBG_REG_FILTER_VALID_SEL 0xd49cUL //ACCESS:RW DataWidth:0x1 Description: When working in tdm64 mode there are 2 valid signals as follows: (1) Valid[3] - validates data[63:32] (2) Valid[0] - validates data[31:0] Description: (a) 1 - use valid[3] (compared data is data[63:32] in that case) (b) 0 - use valid[0] (compared data is data[31:0] in that case). NOTE: (1) The filtering machine compares the constraints to single data source only (which means that only data[31:0] / data[63:32] will be compared in each state) (2) if 64 bit framing mode OR tdm32 framing mode then this bit is not relevant; in that case only valid[0] & data[31:0]/data[63:0] are referred.
#define DBG_REG_FILTER_CNSTR_DATA_0 0xd4a0UL //ACCESS:RW DataWidth:0x20 Description: The value that need to be compared. (a) data[31:0] - if filter_cnstr_offseti[0] = 0; OR (b) data[63:32] - if filter_cnstr_offseti[0] = 1
#define DBG_REG_FILTER_CNSTR_DATA_1 0xd4a4UL //ACCESS:RW DataWidth:0x20 Description: The value that need to be compared. (a) data[31:0] - if filter_cnstr_offseti[0] = 0; OR (b) data[63:32] - if filter_cnstr_offseti[0] = 1
#define DBG_REG_FILTER_CNSTR_DATA_2 0xd4a8UL //ACCESS:RW DataWidth:0x20 Description: The value that need to be compared. (a) data[31:0] - if filter_cnstr_offseti[0] = 0; OR (b) data[63:32] - if filter_cnstr_offseti[0] = 1
#define DBG_REG_FILTER_CNSTR_DATA_3 0xd4acUL //ACCESS:RW DataWidth:0x20 Description: The value that need to be compared. (a) data[31:0] - if filter_cnstr_offseti[0] = 0; OR (b) data[63:32] - if filter_cnstr_offseti[0] = 1
#define DBG_REG_FILTER_CNSTR_FRAME_0 0xd4b0UL //ACCESS:RW DataWidth:0x1 Description: The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[0] = 0; OR (b) frame[3] - if filter_cnstr_offseti[0] = 1
#define DBG_REG_FILTER_CNSTR_FRAME_1 0xd4b4UL //ACCESS:RW DataWidth:0x1 Description: The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[0] = 0; OR (b) frame[3] - if filter_cnstr_offseti[0] = 1
#define DBG_REG_FILTER_CNSTR_FRAME_2 0xd4b8UL //ACCESS:RW DataWidth:0x1 Description: The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[0] = 0; OR (b) frame[3] - if filter_cnstr_offseti[0] = 1
#define DBG_REG_FILTER_CNSTR_FRAME_3 0xd4bcUL //ACCESS:RW DataWidth:0x1 Description: The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[0] = 0; OR (b) frame[3] - if filter_cnstr_offseti[0] = 1
#define DBG_REG_FILTER_CNSTR_DATA_MASK_0 0xd4c0UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (filter_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_FILTER_CNSTR_DATA_MASK_1 0xd4c4UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (filter_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_FILTER_CNSTR_DATA_MASK_2 0xd4c8UL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (filter_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_FILTER_CNSTR_DATA_MASK_3 0xd4ccUL //ACCESS:RW DataWidth:0x20 Description: If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal operation (filter_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_FILTER_CNSTR_FRAME_MASK_0 0xd4d0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal operation (trigger_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_FILTER_CNSTR_FRAME_MASK_1 0xd4d4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal operation (trigger_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_FILTER_CNSTR_FRAME_MASK_2 0xd4d8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal operation (trigger_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_FILTER_CNSTR_FRAME_MASK_3 0xd4dcUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal operation (trigger_cnstr_oprtni=000); i.e. not valid for =/>.
#define DBG_REG_FILTER_CNSTR_OFFSET_0 0xd4e0UL //ACCESS:RW DataWidth:0x3 Description: The above value vector (data & frame) should be compared filter_cnstr_offseti / 2 cycles after start of message (0..3 cycles --> valid values: 0..7; The filtering is implemented according to the data on the first 4 cycles only) NOTE: (a) even though the comparison is for the first 4 cycles only; the messages length is up to 128 cycles.
#define DBG_REG_FILTER_CNSTR_OFFSET_1 0xd4e4UL //ACCESS:RW DataWidth:0x3 Description: The above value vector (data & frame) should be compared filter_cnstr_offseti / 2 cycles after start of message (0..3 cycles --> valid values: 0..7; The filtering is implemented according to the data on the first 4 cycles only) NOTE: (a) even though the comparison is for the first 4 cycles only; the messages length is up to 128 cycles.
#define DBG_REG_FILTER_CNSTR_OFFSET_2 0xd4e8UL //ACCESS:RW DataWidth:0x3 Description: The above value vector (data & frame) should be compared filter_cnstr_offseti / 2 cycles after start of message (0..3 cycles --> valid values: 0..7; The filtering is implemented according to the data on the first 4 cycles only) NOTE: (a) even though the comparison is for the first 4 cycles only; the messages length is up to 128 cycles.
#define DBG_REG_FILTER_CNSTR_OFFSET_3 0xd4ecUL //ACCESS:RW DataWidth:0x3 Description: The above value vector (data & frame) should be compared filter_cnstr_offseti / 2 cycles after start of message (0..3 cycles --> valid values: 0..7; The filtering is implemented according to the data on the first 4 cycles only) NOTE: (a) even though the comparison is for the first 4 cycles only; the messages length is up to 128 cycles.
#define DBG_REG_FILTER_CNSTR_OPRTN_0 0xd4f0UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between fliter_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_FILTER_CNSTR_OPRTN_1 0xd4f4UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between fliter_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_FILTER_CNSTR_OPRTN_2 0xd4f8UL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between fliter_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_FILTER_CNSTR_OPRTN_3 0xd4fcUL //ACCESS:RW DataWidth:0x3 Description: The comparison operation that should be implemented between fliter_cnstr_datai and the actual data as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>);
#define DBG_REG_FILTER_CNSTR_RANGE_0 0xd500UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_FILTER_CNSTR_RANGE_0_REG_FILTER_CNSTR_RANGE_WIDTH_0 (0x1f<<0)
#define DBG_FILTER_CNSTR_RANGE_0_REG_FILTER_CNSTR_RANGE_WIDTH_0_SIZE 0
#define DBG_FILTER_CNSTR_RANGE_0_REG_FILTER_CNSTR_RANGE_LSB_0 (0x1f<<5)
#define DBG_FILTER_CNSTR_RANGE_0_REG_FILTER_CNSTR_RANGE_LSB_0_SIZE 5
#define DBG_REG_FILTER_CNSTR_RANGE_1 0xd504UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_FILTER_CNSTR_RANGE_1_REG_FILTER_CNSTR_RANGE_WIDTH_1 (0x1f<<0)
#define DBG_FILTER_CNSTR_RANGE_1_REG_FILTER_CNSTR_RANGE_WIDTH_1_SIZE 0
#define DBG_FILTER_CNSTR_RANGE_1_REG_FILTER_CNSTR_RANGE_LSB_1 (0x1f<<5)
#define DBG_FILTER_CNSTR_RANGE_1_REG_FILTER_CNSTR_RANGE_LSB_1_SIZE 5
#define DBG_REG_FILTER_CNSTR_RANGE_2 0xd508UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_FILTER_CNSTR_RANGE_2_REG_FILTER_CNSTR_RANGE_WIDTH_2 (0x1f<<0)
#define DBG_FILTER_CNSTR_RANGE_2_REG_FILTER_CNSTR_RANGE_WIDTH_2_SIZE 0
#define DBG_FILTER_CNSTR_RANGE_2_REG_FILTER_CNSTR_RANGE_LSB_2 (0x1f<<5)
#define DBG_FILTER_CNSTR_RANGE_2_REG_FILTER_CNSTR_RANGE_LSB_2_SIZE 5
#define DBG_REG_FILTER_CNSTR_RANGE_3 0xd50cUL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_FILTER_CNSTR_RANGE_3_REG_FILTER_CNSTR_RANGE_WIDTH_3 (0x1f<<0)
#define DBG_FILTER_CNSTR_RANGE_3_REG_FILTER_CNSTR_RANGE_WIDTH_3_SIZE 0
#define DBG_FILTER_CNSTR_RANGE_3_REG_FILTER_CNSTR_RANGE_LSB_3 (0x1f<<5)
#define DBG_FILTER_CNSTR_RANGE_3_REG_FILTER_CNSTR_RANGE_LSB_3_SIZE 5
#define DBG_REG_FILTER_CNSTR_MUST_0 0xd510UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_FILTER_CNSTR_MUST_1 0xd514UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_FILTER_CNSTR_MUST_2 0xd518UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_FILTER_CNSTR_MUST_3 0xd51cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
#define DBG_REG_FILTER_CNSTR_INDIRECT_0 0xd520UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the filter_cnstr_datai. (b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine)
#define DBG_REG_FILTER_CNSTR_INDIRECT_1 0xd524UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the filter_cnstr_datai. (b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine)
#define DBG_REG_FILTER_CNSTR_INDIRECT_2 0xd528UL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the filter_cnstr_datai. (b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine)
#define DBG_REG_FILTER_CNSTR_INDIRECT_3 0xd52cUL //ACCESS:RW DataWidth:0x2 Description: (a) 00: direct: use the value which was configured in the filter_cnstr_datai. (b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine)
#define DBG_REG_FILTER_CNSTR_CYCLIC_0 0xd530UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (filter_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_FILTER_CNSTR_CYCLIC_1 0xd534UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (filter_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_FILTER_CNSTR_CYCLIC_2 0xd538UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (filter_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_FILTER_CNSTR_CYCLIC_3 0xd53cUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (filter_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
#define DBG_REG_FILTER_MSG_LENGTH_ENABLE 0xd540UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: use filter_msg_length to determine message boundary. (b) 0: use filter_valid_sel to determine which frame (frame[0]/frame[3]) signals message boundary (end of message)
#define DBG_REG_FILTER_MSG_LENGTH 0xd544UL //ACCESS:RW DataWidth:0x7 Description: Message length-1 in terms of numbers of cycles. NOTE: (a) if for example filter_msg_length=0 then Message length = 1 cycle. (b) if for example filter_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when filter_msg_length_en = 1
#define DBG_REG_RCRD_ON_WINDOW_PRE_TRGR_EVNT_MODE 0xd548UL //ACCESS:RW DataWidth:0x2 Description: Recording mode prior to trigger event: (a) 00 - record from time=0; (b) 01 - record rcrd_on_window_pre_num_chunks chunks (16 lines chunks within the internal buffer) to internal buffer prior to triggering event; (c) 10 - Don't record prior to triggering event (drop data). NOTE: applicable only if trigger_enable=1
#define DBG_REG_RCRD_ON_WINDOW_POST_TRGR_EVNT_MODE 0xd54cUL //ACCESS:RW DataWidth:0x1 Description: Recording mode upon trigger event: (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_num_cycles valid cycles upon the event; (b) 1 - disable recording data upon triggering event. NOTE: applicable only if trigger_enable=1
#define DBG_REG_RCRD_ON_WINDOW_PRE_NUM_CHUNKS 0xd550UL //ACCESS:RW DataWidth:0x3 Description: Number of chunks (chunk = 16 lines of 128 bit each within the internal buffer) that should be recorded to the internal buffer prior to triggering event. NOTE: (1) applicable only when rcrd_on_window_pre_trgr_evnt_mode=01; (2) valid values are 1..7; (3) the data that will be stored in the internal buffer is the most recent data prior to the triggering event. (4) rcrd_on_window_pre_num_chunks represents the maximum number of chunks that will be written to the internal buffer; if from since time=0 until triggering event the amount of driven data is smaller then the amount of the above value the amount of data stored in the internal buffer will be smaller then the above value.
#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0xd554UL //ACCESS:RW DataWidth:0x20 Description: Number of valid cycles that should be recorded upon triggering event. NOTE: (1) applicable only when rcrd_on_window_post_trgr_evnt_mode=0; (2) value of 0xffffffff (maximum value) result in recording of unlimited amount of cycles (infinite amount of cycles).
#define DBG_REG_PCI_FUNC_NUM 0xd558UL //ACCESS:RW DataWidth:0x3 Description: pci function number; for pci request interface
#define DBG_REG_DBG_NM_MBIST1_CNTRL_CMD 0xd55cUL //ACCESS:RW DataWidth:0x5 Description: NA
#define DBG_REG_NM_CLK_MBIST1_CNTRL_DBG_STATUS_0 0xd560UL //ACCESS:R DataWidth:0x20 Description: NA
#define DBG_REG_NM_CLK_MBIST1_CNTRL_DBG_STATUS_1 0xd564UL //ACCESS:R DataWidth:0x20 Description: NA
#define DBG_REG_NM_CLK_CP_MBIST1_CNTRL_DBG_STATUS_0 0xd568UL //ACCESS:R DataWidth:0x20 Description: NA
#define DBG_REG_INTERNAL_BUFFER_LSB_TM 0xd56cUL //ACCESS:RW DataWidth:0x8 Description: tm port for the internal buffer lsb memory instance
#define DBG_REG_INTERNAL_BUFFER_MSB_TM 0xd570UL //ACCESS:RW DataWidth:0x8 Description: tm port for the internal buffer msb memory instance
#define DBG_REG_ECO_RESERVED 0xd574UL //ACCESS:RW DataWidth:0x8 Description: eco reserved register
#define DBG_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD 0xd578UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD 0xd57cUL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD 0xd580UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_3_CNTRL_CMD 0xd584UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_4_CNTRL_CMD 0xd588UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_5_CNTRL_CMD 0xd58cUL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_6_CNTRL_CMD 0xd590UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_7_CNTRL_CMD 0xd594UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_8_CNTRL_CMD 0xd598UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_0_STATUS_0 0xd59cUL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_1_STATUS_0 0xd5a0UL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_2_STATUS_0 0xd5a4UL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_3_STATUS_0 0xd5a8UL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_4_STATUS_0 0xd5acUL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_5_STATUS_0 0xd5b0UL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_6_STATUS_0 0xd5b4UL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_7_STATUS_0 0xd5b8UL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_8_STATUS_0 0xd5bcUL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_9_CNTRL_CMD 0xd5c0UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_9_STATUS_0 0xd5c4UL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_10_CNTRL_CMD 0xd5c8UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_11_CNTRL_CMD 0xd5ccUL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define DBG_REG_CPU_MBIST_MEMCTRL_10_STATUS_0 0xd5d0UL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CPU_MBIST_MEMCTRL_11_STATUS_0 0xd5d4UL //ACCESS:R DataWidth:0x19 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DBG_REG_CALENDAR_OUT_DATA_LOW 0xc100UL //ACCESS:R DataWidth:0x20 Description: debug only: These bits indicate the value of the lower 32 bits of the data output of the calendar
#define DBG_REG_CALENDAR_OUT_DATA_LOW_SIZE 1
#define DBG_REG_CPU_DEBUG_DATA 0xc104UL //ACCESS:RW DataWidth:0x20 Description: debug only: These bits indicate debug data that arrives from the CPU client; if ~dbg_registers_immediate_ack=1 then ack is returned upon the following cycle of write command. In this case ~dbg_registers_cpu_data_taken_intr interrupt anounce that the data slot was taken; If ~dbg_registers_immediate_ack=0 then ack is returned only after the data slot was taken. in this case if the CPU is not configured in the slots then an ack signal will never be returned by the calendar.
#define DBG_REG_CPU_DEBUG_DATA_SIZE 1
#define DBG_REG_FULL_ON_EXT_BUFFER 0xc108UL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates that the external buffer was filled; Relevant only when ~dbg_registers_full_mode=0 (one shot)
#define DBG_REG_FULL_ON_EXT_BUFFER_SIZE 1
#define DBG_REG_FULL_ON_INT_BUFFER 0xc10cUL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates that the internal buffer was filled
#define DBG_REG_FULL_ON_INT_BUFFER_SIZE 1
#define DBG_REG_INTR_BUFFER_RD_PTR 0xc110UL //ACCESS:R DataWidth:0x7 Description: debug only: These bits indicate the value of the read pointer for the internal buffer; The read pointer describes the next address to be read from the internal buffer
#define DBG_REG_INTR_BUFFER_RD_PTR_SIZE 1
#define DBG_REG_INTR_BUFFER_WR_PTR 0xc114UL //ACCESS:R DataWidth:0x7 Description: debug only: These bits indicate the value of the write pointer for the internal buffer; The write pointer describes the last address that was written to the internal buffer. An exception exists after reset when #dbg_registers_intr_buffer_wr_ptr is 0 until first data is written
#define DBG_REG_INTR_BUFFER_WR_PTR_SIZE 1
#define DBG_REG_OVL_ON_EXT_BUFFER 0xc118UL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates that the external buffer was overflowed (newest data was thrown); Relevant only for (a) ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=0 (one shot); or (b) ~dbg_registers_debug_target=1 (NIG) & ~dbg_registers_full_mode=0 (one shot)
#define DBG_REG_OVL_ON_EXT_BUFFER_SIZE 1
#define DBG_REG_OVL_ON_INT_BUFFER 0xc11cUL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates that the internal buffer was overflowed (newest data was thrown); Not relevant if ~dbg_registers_debug_target=0 (internal buffer) & ~dbg_registers_full_mode=1 (wrap);
#define DBG_REG_OVL_ON_INT_BUFFER_SIZE 1
#define DBG_REG_PCI_REQ_CREDIT 0xc120UL //ACCESS:RW DataWidth:0x2 Description: debug only: These bits indicate the credit for PCI request type 4 interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are configured
#define DBG_REG_PCI_REQ_CREDIT_SIZE 1
#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124UL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates wheter indicates that external buffer was wrapped (oldest data was thrown); Relevant only when ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap);
#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128UL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates wheter the internal buffer was wrapped (oldest data was thrown) Relevant only when ~dbg_registers_debug_target=0 (internal buffer)
#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
#define DBG_REG_EXT_BUFFER_RD_PTR 0xc130UL //ACCESS:WB_R DataWidth:0x40 Description: debug only: These bits indicate the value of the read pointer for the external pci buffer; relevant only when ~dbg_registers_debug_target=2 (PCI); The read pointer describes the next address to be read from the external buffer; WB Read Only (write request will not be acknowledged);
#define DBG_REG_EXT_BUFFER_RD_PTR_SIZE 2
#define DBG_REG_EXT_BUFFER_WR_PTR 0xc140UL //ACCESS:WB_R DataWidth:0x40 Description: debug only: These bits indicate the value of the write pointer for the external pci buffer when ~dbg_registers_debug_target=2 (PCI). It describes the next address to write to the external buffer; 1024 Byte Chunks counter when ~dbg_registers_debug_target=1 (NIG) and ~dbg_registers_full_mode=0 (one-shot); WB Read Only (write request will not be acknowledged);
#define DBG_REG_EXT_BUFFER_WR_PTR_SIZE 2
#define DBG_REG_CALENDAR_OUT_DATA 0xc160UL //ACCESS:WB_R DataWidth:0x47 Description: debug only: These bits indicate the value of the data frame and valid output of the calendar; The concatenation is done as follows: bits 63:0 - data; bits 66:64 - frame; bits 70:68 - valid. The reference for the valid/frame is according to the ~dbg_registers_framing_mode as follows: (a) tdm32 mode - bit 68 for valid bit 64 for frame for data bits 31:0; (b) tdm64 mode - bit 68 for valid bit 64 for frame for data bits 31:0; bit 69 for valid; bit 65 for frame for data bits 63:32; (c) 64 bit mode - bit 68 for valid bit 64 for frame for data bits 63:0; (d) 24 bit mode - bit 68 for valid bit 64 for frame for data bits 7:0; bit 69 for valid bit 65 for frame for data bits 15:8; bit 70 for valid bit 66 for frame for data bits 23:16; WB Read Only (write request will not be acknowledged);
#define DBG_REG_CALENDAR_OUT_DATA_SIZE 3
#define DBG_REG_EXPECTED_PATTERN 0xc180UL //ACCESS:WB DataWidth:0x46 Description: debug only: For pattern recognition usage: These bits represent the pattern to be compared with the vector {slot_num[2:0]; frame[2:0]; data[63:0]}; This vector represent the debug data it's slot number and it's frame signals that are going to stored in the internal buffer;
#define DBG_REG_EXPECTED_PATTERN_SIZE 3
#define DBG_REG_EXPECTED_PATTERN_BIT_MASK 0xc1a0UL //ACCESS:WB DataWidth:0x46 Description: debug only: For pattern recognition usage: These bits represent a mask bit vector that refers to the ~dbg_registers_expected_pattern vector as follows: (a) 1 - bit is masked. This bit won't be compared with the ~dbg_registers_expected_pattern referred bit; (b) 0 - bit is enabled. This bit will be compared with the ~dbg_registers_expected_pattern reffered bit;
#define DBG_REG_EXPECTED_PATTERN_BIT_MASK_SIZE 3
#define DBG_REG_INTR_BUFFER 0xc800UL //ACCESS:WB DataWidth:0x80 Description: debug only: Internal buffer of 2KByte buffer
#define DBG_REG_INTR_BUFFER_SIZE 512
#define DBG_REG_INT_BUFFER_WRAP_COUNTER 0xd000UL //ACCESS:R DataWidth:0x20 Description: Number of wraps on internal buffer; NOTE: valid only when debug_target=0 (internal buffer) and full_mode=1 (wrap)
#define DBG_REG_INT_BUFFER_WRAP_COUNTER_SIZE 1
#define DBG_REG_TRIGGER_EVENT 0xd004UL //ACCESS:R DataWidth:0x1 Description: Configured messages sequencing was identified.
#define DBG_REG_TRIGGER_EVENT_SIZE 1
#define DBG_REG_TRIGGER_INDIRECT0_RECORDED_DATA 0xd008UL //ACCESS:R DataWidth:0x20 Description: The data that was recorded trigger_indirect0_offset cycles after start of message (during triggering machine operation in state trigger_indirect0_state); NOTE: CID recording for filtering purpose within the sem must use this register (and NOT trigger_indirect1_recorded_data register)
#define DBG_REG_TRIGGER_INDIRECT0_RECORDED_DATA_SIZE 1
#define DBG_REG_TRIGGER_INDIRECT1_RECORDED_DATA 0xd00cUL //ACCESS:R DataWidth:0x20 Description: The data that was recorded trigger_indirect1_offset cycles after start of message (during triggering machine operation in state trigger_indirect0_state);
#define DBG_REG_TRIGGER_INDIRECT1_RECORDED_DATA_SIZE 1
#define DBG_REG_DBG_UNUSED_EMPTY_0 0xc0acUL //ACCESS:R DataWidth:0x20 Unused empty space
#define DBG_REG_DBG_UNUSED_EMPTY_0_SIZE 21
#define DBG_REG_DBG_UNUSED_EMPTY_1 0xc12cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define DBG_REG_DBG_UNUSED_EMPTY_1_SIZE 1
#define DBG_REG_DBG_UNUSED_EMPTY_2 0xc150UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DBG_REG_DBG_UNUSED_EMPTY_2_SIZE 4
#define DBG_REG_DBG_UNUSED_EMPTY_3 0xc1c0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DBG_REG_DBG_UNUSED_EMPTY_3_SIZE 400
#define DBG_REG_DBG_UNUSED_EMPTY_4 0xd5d8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DBG_REG_DBG_UNUSED_EMPTY_4_SIZE 2698
#define DMAE_REG_INIT 0x102000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
#define DMAE_REG_PCI_IFEN 0x102004UL //ACCESS:RW DataWidth:0x1 Description: DMAE PCI Interface (Request;Read;Write) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all other signals are treated as usual; if 1 - normal activity.
#define DMAE_REG_GRC_IFEN 0x102008UL //ACCESS:RW DataWidth:0x1 Description: DMAE GRC Interface (Target;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define DMAE_REG_RLXD_ORDR 0x10200cUL //ACCESS:RW DataWidth:0x1 Description: Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X relaxed ordering is enabled.
#define DMAE_REG_NO_SNOOP 0x102010UL //ACCESS:RW DataWidth:0x1 Description: 0-PCI type cache snoop protection is required;1-system isn't required to cause processor cache snoop for coherency.
#define DMAE_REG_CRC16I_INIT 0x102014UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-16 initial value is all zeroes; if 1 - the CRC-16 initial value is all ones.
#define DMAE_REG_CRC16_BSWAP 0x102018UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-16 final calculation result isn't byte swapped; if 1 - the CRC-16 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
#define DMAE_REG_CRC16C_INIT 0x10201cUL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c initial value is all ones.
#define DMAE_REG_CRC16T10_INIT 0x102020UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the CRC-16 T10 initial value is all ones.
#define DMAE_REG_CRC32I_INIT 0x102024UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-32 initial value is all zeroes; if 1 - the CRC-32 initial value is all ones.
#define DMAE_REG_CRC32I_BSWAP 0x102028UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
#define DMAE_REG_CRC32C_INIT 0x10202cUL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-32c initial value is all zeroes; if 1 - the CRC-32c initial value is all ones.
#define DMAE_REG_CRC32C_BSWAP 0x102030UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-32c final calculation result isn't byte swapped; if 1 - the CRC-32c final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
#define DMAE_REG_CHKSUM0_FIX 0x102034UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the final checksum equal 0 won't be changed;if 1 - the final checksum equal 0 will be fixed to all ones.
#define DMAE_REG_CMD_TM 0x102038UL //ACCESS:RW DataWidth:0x5 Description: TM bits of Command memory.
#define DMAE_REG_DBG_SELECT 0x10203cUL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from DMAE to the DBG block) - for selecting a line to output to the DBG block.
#define DMAE_REG_DBG_BYTE_ENABLE 0x102040UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from DMAE to the DBG block) - for enabling bytes in the selected line (after the select; before the shift).
#define DMAE_REG_DBG_SHIFT 0x102044UL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from DMAE to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define DMAE_REG_DMAE_INT_STS 0x102048UL //ACCESS:R DataWidth:0x2 Description: Interrupt register #0 read
#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define DMAE_DMAE_INT_STS_REG_PCI_RD_BUF_ERR (0x1<<1)
#define DMAE_DMAE_INT_STS_REG_PCI_RD_BUF_ERR_SIZE 1
#define DMAE_REG_DMAE_INT_STS_CLR 0x10204cUL //ACCESS:RC DataWidth:0x2 Description: Interrupt register #0 read clear
#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define DMAE_DMAE_INT_STS_CLR_REG_PCI_RD_BUF_ERR (0x1<<1)
#define DMAE_DMAE_INT_STS_CLR_REG_PCI_RD_BUF_ERR_SIZE 1
#define DMAE_REG_DMAE_INT_STS_WR 0x102050UL //ACCESS:WR DataWidth:0x2 Description: Interrupt register #0 bit set or clear
#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define DMAE_DMAE_INT_STS_WR_REG_PCI_RD_BUF_ERR (0x1<<1)
#define DMAE_DMAE_INT_STS_WR_REG_PCI_RD_BUF_ERR_SIZE 1
#define DMAE_REG_DMAE_INT_MASK 0x102054UL //ACCESS:RW DataWidth:0x2 Description: Interrupt mask register #0 read/write
#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define DMAE_DMAE_INT_MASK_REG_PCI_RD_BUF_ERR (0x1<<1)
#define DMAE_DMAE_INT_MASK_REG_PCI_RD_BUF_ERR_SIZE 1
#define DMAE_REG_DMAE_PRTY_STS 0x102058UL //ACCESS:R DataWidth:0x4 Description: Parity register #0 read
#define DMAE_DMAE_PRTY_STS_REG_PARITY (0x1<<0)
#define DMAE_DMAE_PRTY_STS_REG_PARITY_SIZE 0
#define DMAE_DMAE_PRTY_STS_REG_PCI_BUF_LOW_PRTY_ERR (0x1<<1)
#define DMAE_DMAE_PRTY_STS_REG_PCI_BUF_LOW_PRTY_ERR_SIZE 1
#define DMAE_DMAE_PRTY_STS_REG_PCI_BUF_HIGH_PRTY_ERR (0x1<<2)
#define DMAE_DMAE_PRTY_STS_REG_PCI_BUF_HIGH_PRTY_ERR_SIZE 2
#define DMAE_DMAE_PRTY_STS_REG_CMD_MEM_PRTY_ERR (0x1<<3)
#define DMAE_DMAE_PRTY_STS_REG_CMD_MEM_PRTY_ERR_SIZE 3
#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205cUL //ACCESS:RC DataWidth:0x4 Description: Parity register #0 read clear
#define DMAE_DMAE_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define DMAE_DMAE_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define DMAE_DMAE_PRTY_STS_CLR_REG_PCI_BUF_LOW_PRTY_ERR (0x1<<1)
#define DMAE_DMAE_PRTY_STS_CLR_REG_PCI_BUF_LOW_PRTY_ERR_SIZE 1
#define DMAE_DMAE_PRTY_STS_CLR_REG_PCI_BUF_HIGH_PRTY_ERR (0x1<<2)
#define DMAE_DMAE_PRTY_STS_CLR_REG_PCI_BUF_HIGH_PRTY_ERR_SIZE 2
#define DMAE_DMAE_PRTY_STS_CLR_REG_CMD_MEM_PRTY_ERR (0x1<<3)
#define DMAE_DMAE_PRTY_STS_CLR_REG_CMD_MEM_PRTY_ERR_SIZE 3
#define DMAE_REG_DMAE_PRTY_STS_WR 0x102060UL //ACCESS:WR DataWidth:0x4 Description: Parity register #0 bit set or clear
#define DMAE_DMAE_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define DMAE_DMAE_PRTY_STS_WR_REG_PARITY_SIZE 0
#define DMAE_DMAE_PRTY_STS_WR_REG_PCI_BUF_LOW_PRTY_ERR (0x1<<1)
#define DMAE_DMAE_PRTY_STS_WR_REG_PCI_BUF_LOW_PRTY_ERR_SIZE 1
#define DMAE_DMAE_PRTY_STS_WR_REG_PCI_BUF_HIGH_PRTY_ERR (0x1<<2)
#define DMAE_DMAE_PRTY_STS_WR_REG_PCI_BUF_HIGH_PRTY_ERR_SIZE 2
#define DMAE_DMAE_PRTY_STS_WR_REG_CMD_MEM_PRTY_ERR (0x1<<3)
#define DMAE_DMAE_PRTY_STS_WR_REG_CMD_MEM_PRTY_ERR_SIZE 3
#define DMAE_REG_DMAE_PRTY_MASK 0x102064UL //ACCESS:RW DataWidth:0x4 Description: Parity mask register #0 read/write
#define DMAE_DMAE_PRTY_MASK_REG_PARITY (0x1<<0)
#define DMAE_DMAE_PRTY_MASK_REG_PARITY_SIZE 0
#define DMAE_DMAE_PRTY_MASK_REG_PCI_BUF_LOW_PRTY_ERR (0x1<<1)
#define DMAE_DMAE_PRTY_MASK_REG_PCI_BUF_LOW_PRTY_ERR_SIZE 1
#define DMAE_DMAE_PRTY_MASK_REG_PCI_BUF_HIGH_PRTY_ERR (0x1<<2)
#define DMAE_DMAE_PRTY_MASK_REG_PCI_BUF_HIGH_PRTY_ERR_SIZE 2
#define DMAE_DMAE_PRTY_MASK_REG_CMD_MEM_PRTY_ERR (0x1<<3)
#define DMAE_DMAE_PRTY_MASK_REG_CMD_MEM_PRTY_ERR_SIZE 3
#define DMAE_REG_ECO_RESERVED 0x102068UL //ACCESS:RW DataWidth:0x8 Description: chicken bits
#define DMAE_REG_RD_ATC_FLAGS 0x10206cUL //ACCESS:RW DataWidth:0x3 Description: Read request ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; ATC Flags[2]:0 - Low Priority; - High Priority
#define DMAE_REG_WR_ATC_FLAGS 0x102070UL //ACCESS:RW DataWidth:0x3 Description: Write request ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; ATC Flags[2]:0 - Low Priority; - High Priority
#define DMAE_REG_PCI_ERR_DISCARD_EN 0x102074UL //ACCESS:RW DataWidth:0x1 Description: When set discards 1- or 2-Dword PCI transaction read in case there is PCI error.
#define DMAE_REG_PCI_ERR_DISCARD_ADDR 0x102078UL //ACCESS:RW DataWidth:0x14 Description: GRC address in case 1- or 2-Dword PCI transaction is discardd due to PCI error and dmae.pci_err_discard set.
#define DMAE_REG_BACKWARD_COMP_EN 0x10207cUL //ACCESS:RW DataWidth:0x1 Description: When set the DMAE will process the commands as in E1.5. 1.The function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0; 4.Completion function=0; 5.Error handling=0
#define DMAE_REG_DMAE_CPT_MBIST1_CNTRL_CMD 0x1020c8UL //ACCESS:RW DataWidth:0x5 Description: N/A
#define DMAE_REG_CPT_CLK_MBIST1_CNTRL_DMAE_STATUS_0 0x1020ccUL //ACCESS:R DataWidth:0x20 Description: N/A
#define DMAE_REG_CPT_CLK_MBIST1_CNTRL_DMAE_STATUS_1 0x1020d0UL //ACCESS:R DataWidth:0x20 Description: N/A
#define DMAE_REG_CPT_CLK_PCI_MBIST1_CNTRL_DMAE_STATUS_0 0x1020d4UL //ACCESS:R DataWidth:0x20 Description: N/A
#define DMAE_REG_CPT_CLK_PCI_MBIST1_CNTRL_DMAE_STATUS_1 0x1020d8UL //ACCESS:R DataWidth:0x20 Description: N/A
#define DMAE_REG_CPT_CLK_PCI_MBIST1_CNTRL_DMAE_STATUS_2 0x1020dcUL //ACCESS:R DataWidth:0x20 Description: N/A
#define DMAE_REG_CPT_CLK_CAM_CID_CAM_MBIST1_CNTRL_DMAE_STATUS_0 0x1020e0UL //ACCESS:R DataWidth:0x20 Description: N/A
#define DMAE_REG_CPT_CLK_CAM_STRING_CAM_MBIST1_CNTRL_DMAE_STATUS_0 0x1020e4UL //ACCESS:R DataWidth:0x20 Description: N/A
#define DMAE_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD 0x1020e8UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define DMAE_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD 0x1020ecUL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define DMAE_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD 0x1020f0UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define DMAE_REG_CPU_MBIST_MEMCTRL_3_CNTRL_CMD 0x1020f4UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define DMAE_REG_CPU_MBIST_MEMCTRL_4_CNTRL_CMD 0x1020f8UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define DMAE_REG_CPU_MBIST_MEMCTRL_5_CNTRL_CMD 0x1020fcUL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define DMAE_REG_CPU_MBIST_MEMCTRL_6_CNTRL_CMD 0x102100UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define DMAE_REG_CPU_MBIST_MEMCTRL_7_CNTRL_CMD 0x102104UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define DMAE_REG_CPU_MBIST_MEMCTRL_8_CNTRL_CMD 0x102108UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define DMAE_REG_CPU_MBIST_MEMCTRL_0_STATUS_0 0x10210cUL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DMAE_REG_CPU_MBIST_MEMCTRL_1_STATUS_0 0x102110UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DMAE_REG_CPU_MBIST_MEMCTRL_2_STATUS_0 0x102114UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DMAE_REG_CPU_MBIST_MEMCTRL_3_STATUS_0 0x102118UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DMAE_REG_CPU_MBIST_MEMCTRL_4_STATUS_0 0x10211cUL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DMAE_REG_CPU_MBIST_MEMCTRL_5_STATUS_0 0x102120UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DMAE_REG_CPU_MBIST_MEMCTRL_6_STATUS_0 0x102124UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DMAE_REG_CPU_MBIST_MEMCTRL_7_STATUS_0 0x102128UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DMAE_REG_CPU_MBIST_MEMCTRL_8_STATUS_0 0x10212cUL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define DMAE_REG_GO_C0 0x102080UL //ACCESS:RW DataWidth:0x1 Description: Command 0 go.
#define DMAE_REG_GO_C0_SIZE 1
#define DMAE_REG_GO_C1 0x102084UL //ACCESS:RW DataWidth:0x1 Description: Command 1 go.
#define DMAE_REG_GO_C1_SIZE 1
#define DMAE_REG_GO_C10 0x102088UL //ACCESS:RW DataWidth:0x1 Description: Command 10 go.
#define DMAE_REG_GO_C10_SIZE 1
#define DMAE_REG_GO_C11 0x10208cUL //ACCESS:RW DataWidth:0x1 Description: Command 11 go.
#define DMAE_REG_GO_C11_SIZE 1
#define DMAE_REG_GO_C12 0x102090UL //ACCESS:RW DataWidth:0x1 Description: Command 12 go.
#define DMAE_REG_GO_C12_SIZE 1
#define DMAE_REG_GO_C13 0x102094UL //ACCESS:RW DataWidth:0x1 Description: Command 13 go.
#define DMAE_REG_GO_C13_SIZE 1
#define DMAE_REG_GO_C14 0x102098UL //ACCESS:RW DataWidth:0x1 Description: Command 14 go.
#define DMAE_REG_GO_C14_SIZE 1
#define DMAE_REG_GO_C15 0x10209cUL //ACCESS:RW DataWidth:0x1 Description: Command 15 go.
#define DMAE_REG_GO_C15_SIZE 1
#define DMAE_REG_GO_C2 0x1020a0UL //ACCESS:RW DataWidth:0x1 Description: Command 2 go.
#define DMAE_REG_GO_C2_SIZE 1
#define DMAE_REG_GO_C3 0x1020a4UL //ACCESS:RW DataWidth:0x1 Description: Command 3 go.
#define DMAE_REG_GO_C3_SIZE 1
#define DMAE_REG_GO_C4 0x1020a8UL //ACCESS:RW DataWidth:0x1 Description: Command 4 go.
#define DMAE_REG_GO_C4_SIZE 1
#define DMAE_REG_GO_C5 0x1020acUL //ACCESS:RW DataWidth:0x1 Description: Command 5 go.
#define DMAE_REG_GO_C5_SIZE 1
#define DMAE_REG_GO_C6 0x1020b0UL //ACCESS:RW DataWidth:0x1 Description: Command 6 go.
#define DMAE_REG_GO_C6_SIZE 1
#define DMAE_REG_GO_C7 0x1020b4UL //ACCESS:RW DataWidth:0x1 Description: Command 7 go.
#define DMAE_REG_GO_C7_SIZE 1
#define DMAE_REG_GO_C8 0x1020b8UL //ACCESS:RW DataWidth:0x1 Description: Command 8 go.
#define DMAE_REG_GO_C8_SIZE 1
#define DMAE_REG_GO_C9 0x1020bcUL //ACCESS:RW DataWidth:0x1 Description: Command 9 go.
#define DMAE_REG_GO_C9_SIZE 1
#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0UL //ACCESS:RW DataWidth:0x4 Description: DMAE- PCI Request Interface initial credit. Write writes the initial value to the credit counter; related to the address. Read returns the current value of the counter.
#define DMAE_REG_PXP_REQ_INIT_CRD_SIZE 1
#define DMAE_REG_CMD_MEM 0x102400UL //ACCESS:RW DataWidth:0x20 Description: Commands memory. The address to command X; row Y is to calculated as 14*X+Y.
#define DMAE_REG_CMD_MEM_SIZE 224
#define DMAE_REG_DMAE_UNUSED_EMPTY_0 0x1020c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DMAE_REG_DMAE_UNUSED_EMPTY_0_SIZE 1
#define DMAE_REG_DMAE_UNUSED_EMPTY_1 0x102130UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DMAE_REG_DMAE_UNUSED_EMPTY_1_SIZE 180
#define DMAE_REG_DMAE_UNUSED_EMPTY_2 0x102800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DMAE_REG_DMAE_UNUSED_EMPTY_2_SIZE 512
#define DORQ_REG_INIT 0x170000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
#define DORQ_REG_IF_EN 0x170004UL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define DORQ_IF_EN_REG_RQ_IFEN (0x1<<0)
#define DORQ_IF_EN_REG_RQ_IFEN_SIZE 0
#define DORQ_IF_EN_REG_CF_IFEN (0x1<<1)
#define DORQ_IF_EN_REG_CF_IFEN_SIZE 1
#define DORQ_IF_EN_REG_RSP_IFEN (0x1<<2)
#define DORQ_IF_EN_REG_RSP_IFEN_SIZE 2
#define DORQ_IF_EN_REG_DPM_IFEN (0x1<<3)
#define DORQ_IF_EN_REG_DPM_IFEN_SIZE 3
#define DORQ_REG_MODE_ACT 0x170008UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define DORQ_MODE_ACT_REG_NORM_MODE_ACT (0x1<<0)
#define DORQ_MODE_ACT_REG_NORM_MODE_ACT_SIZE 0
#define DORQ_MODE_ACT_REG_DPM_MODE_ACT (0x1<<1)
#define DORQ_MODE_ACT_REG_DPM_MODE_ACT_SIZE 1
#define DORQ_REG_NORM_ADDR_MASK 0x17000cUL //ACCESS:RW DataWidth:0x20 Description: The normal mode address mask. Filters a certain amount of MSBits of the address to distinguish the normal mode.
#define DORQ_REG_DPM_ADDR_MASK 0x170010UL //ACCESS:RW DataWidth:0x20 Description: The DPM mode address mask. Filters a certain amount of MSBits of the address to distinguish the DPM mode.
#define DORQ_REG_NORM_ADDR_BASE 0x170014UL //ACCESS:RW DataWidth:0x20 Description: The normal mode base address.
#define DORQ_REG_DPM_ADDR_BASE 0x170018UL //ACCESS:RW DataWidth:0x20 Description: The DPM mode base address.
#define DORQ_REG_NORM_CID_MASK 0x17001cUL //ACCESS:RW DataWidth:0x17 Description: The normal mode CID extraction mask.
#define DORQ_REG_DPM_CID_MASK 0x170020UL //ACCESS:RW DataWidth:0x17 Description: The DPM mode CID extraction mask.
#define DORQ_REG_NORM_CID_BASE 0x170024UL //ACCESS:RW DataWidth:0x17 Description: The normal mode CID base.
#define DORQ_REG_DPM_CID_BASE 0x170028UL //ACCESS:RW DataWidth:0x17 Description: The DPM mode CID base.
#define DORQ_REG_NORM_CID_OFST 0x17002cUL //ACCESS:RW DataWidth:0x5 Description: The normal mode CID extraction offset.
#define DORQ_REG_DPM_CID_OFST 0x170030UL //ACCESS:RW DataWidth:0x5 Description: The DPM mode CID extraction offset.
#define DORQ_REG_QM_AEMPTY_EN 0x170034UL //ACCESS:RW DataWidth:0x1 Description: If 0 - QM almost empty is disregarded; if 1 - QM almost empty is taken into consideration.
#define DORQ_REG_REGN 0x170038UL //ACCESS:RW DataWidth:0x18 Multi Field Register
#define DORQ_REGN_REG_NORM_REGN_TX (0xff<<0)
#define DORQ_REGN_REG_NORM_REGN_TX_SIZE 0
#define DORQ_REGN_REG_REGN_RX (0xff<<8)
#define DORQ_REGN_REG_REGN_RX_SIZE 8
#define DORQ_REGN_REG_SHRT_REGN_TX (0xff<<16)
#define DORQ_REGN_REG_SHRT_REGN_TX_SIZE 16
#define DORQ_REG_OUTST_REQ 0x17003cUL //ACCESS:RW DataWidth:0x4 Description: The number of simultaneous outstanding requests to Context Fetch Interface.
#define DORQ_REG_DPM_WR_TYPE_LOC 0x170040UL //ACCESS:RW DataWidth:0x5 Description: DPM write type location. Selects one of bits of address to differentiate between DPM data and DPM trigger types.
#define DORQ_REG_DPM_CID_ADDR 0x170044UL //ACCESS:RW DataWidth:0x8 Description: The address to write the DPM CID to STORM.
#define DORQ_REG_RSP_INIT_CRD 0x170048UL //ACCESS:RW DataWidth:0x4 Description: The initial credit at the Doorbell Response Interface. The write writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The read reads this written value.
#define DORQ_REG_NORM_CMHEAD_TX 0x17004cUL //ACCESS:RW DataWidth:0x1c Description: TCM Header when only TCP context is loaded.
#define DORQ_REG_CMHEAD_RX 0x170050UL //ACCESS:RW DataWidth:0x1c Description: UCM Header.
#define DORQ_REG_SHRT_CMHEAD 0x170054UL //ACCESS:RW DataWidth:0x1c Description: TCM Header when both ULP and TCP context is loaded.
#define DORQ_REG_ERR_CMHEAD 0x170058UL //ACCESS:RW DataWidth:0x1c Description: The value sent to CM header in the case of CFC load error.
#define DORQ_REG_ERR_EVENT_ID 0x17005cUL //ACCESS:RW DataWidth:0x8 Description: Event ID sent to TCM/UCM.
#define DORQ_REG_SHRT_ACT_CNT 0x170070UL //ACCESS:RW DataWidth:0x4 Description: Initial activity counter value on the load request; when the shortcut is done.
#define DORQ_REG_M_SP_RAM_TM 0x170074UL //ACCESS:RW DataWidth:0x5 Description: TM bits of DORQ memory.
#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078UL //ACCESS:RW DataWidth:0xc Description: The threshold of the DQ FIFO to send the full interrupt.
#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007cUL //ACCESS:RW DataWidth:0xc Description: The threshold of the DQ FIFO to send the almost full interrupt.
#define DORQ_REG_DQ_FREEZE 0x170080UL //ACCESS:RW DataWidth:0x1 Description: When set; the DQ will serve the doorbells; already existing in the queue and will block the Response interface.
#define DORQ_REG_AUTO_FREEZE_EN 0x170084UL //ACCESS:RW DataWidth:0x1 Description: When set; the DQ will automatically stop sending CFC load requests when a doorbell discard interrupt is generated. The freeze mode will remain until the auto_freeze_rel register is set.
#define DORQ_REG_AUTO_DISCARD_EN 0x170088UL //ACCESS:RW DataWidth:0x1 Description: If this register is equal to 1 then the DQ will enter auto discard mode when a doorbell discard interrupt is generated. In this mode all incoming doorbells will be dropped even if the FIFO is not full anymore.
#define DORQ_REG_DB_ADDR0 0x17008cUL //ACCESS:RW DataWidth:0x20 Description: Doorbell address for RBC doorbells (function 0).
#define DORQ_REG_DB_ADDR1 0x170090UL //ACCESS:RW DataWidth:0x20 Description: Doorbell address for RBC doorbells (function 1).
#define DORQ_REG_DBG_SELECT 0x170094UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from DORQ to the DBG block) - for selecting a line to output to the DBG block.
#define DORQ_REG_DBG_BYTE_ENABLE 0x170098UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from DORQ to the DBG block) - for enabling bytes in the selected line (after the select; before the shift).
#define DORQ_REG_DBG_SHIFT 0x17009cUL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from DORQ to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define DORQ_REG_DQ_FILL_LVLL 0x1700a0UL //ACCESS:R DataWidth:0xd Description: Current value of the DQ FIFO fill level according to leading pointer. The range is 0 - 256 FIFO rows; where each row stands for the doorbell.
#define DORQ_REG_DQ_FILL_LVLF 0x1700a4UL //ACCESS:R DataWidth:0xd Description: Current value of the DQ FIFO fill level according to following pointer. The range is 0 - 256 FIFO rows; where each row stands for the doorbell.
#define DORQ_REG_OUTST_REQ_CNT 0x1700a8UL //ACCESS:R DataWidth:0x4 Description: Current value of outstanding requests counter credit.
#define DORQ_REG_RSPA_CRD_CNT 0x1700acUL //ACCESS:R DataWidth:0x4 Description: Current value of response A counter credit. Initial credit is configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd register.
#define DORQ_REG_RSPB_CRD_CNT 0x1700b0UL //ACCESS:R DataWidth:0x4 Description: Current value of response B counter credit. Initial credit is configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd register.
#define DORQ_REG_DQ_FIFO_RDL_PTR 0x1700b4UL //ACCESS:R DataWidth:0xc Description: DQ FIFO read leading pointer.
#define DORQ_REG_DQ_FIFO_RDF_PTR 0x1700b8UL //ACCESS:R DataWidth:0xc Description: DQ FIFO read following pointer.
#define DORQ_REG_DQ_FIFO_WR_PTR 0x1700bcUL //ACCESS:R DataWidth:0xc Description: DQ FIFO write pointer.
#define DORQ_REG_DQ_FULL_ST 0x1700c0UL //ACCESS:R DataWidth:0x1 Description: DQ FIFO full status. Is set; when FIFO filling level is more or equal to full threshold; reset on full clear.
#define DORQ_REG_DB_CNTR 0x1700c4UL //ACCESS:ST DataWidth:0x20 Description: Counts the total number of received doorbells.
#define DORQ_REG_DB_MIS_CNTR 0x1700c8UL //ACCESS:ST DataWidth:0x8 Description: Counts the total number of discarded doorbells in PF mode due to mode or range mismatch
#define DORQ_REG_CFC_ERR_CNTR 0x1700ccUL //ACCESS:ST DataWidth:0x8 Description: Counts the number of CFC load errors.
#define DORQ_REG_DPM_FULL_CNTR 0x1700d0UL //ACCESS:ST DataWidth:0x8 Description: Counts the number DPM tried to wite to STORM when it was full.
#define DORQ_REG_DB_DIS_CNTR0 0x1700d4UL //ACCESS:ST DataWidth:0x10 Description: Doorbell disable counter (function 0).
#define DORQ_REG_DB_DIS_CNTR1 0x1700d8UL //ACCESS:ST DataWidth:0x10 Description: Doorbell disable counter (function 1).
#define DORQ_REG_TYPE_VAL_ERR_ADDR 0x1700dcUL //ACCESS:RC DataWidth:0x20 Description: Keeps the address of the first doorbell; caused the type validation error.
#define DORQ_REG_PRIV_MIN_ADDR0 0x1700e0UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 0.
#define DORQ_REG_PRIV_MIN_ADDR1 0x1700e4UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 1.
#define DORQ_REG_PRIV_MAX_ADDR0 0x1700e8UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 0.
#define DORQ_REG_PRIV_MAX_ADDR1 0x1700ecUL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 1.
#define DORQ_REG_TYPE_MIN_ADDR00 0x1700f0UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 0 conection type 0.
#define DORQ_REG_TYPE_MIN_ADDR01 0x1700f4UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 0 conection type 1.
#define DORQ_REG_TYPE_MIN_ADDR02 0x1700f8UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 0 conection type 2.
#define DORQ_REG_TYPE_MIN_ADDR03 0x1700fcUL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 0 conection type 3.
#define DORQ_REG_TYPE_MIN_ADDR04 0x170100UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 0 conection type 4.
#define DORQ_REG_TYPE_MIN_ADDR05 0x170104UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 0 conection type 5.
#define DORQ_REG_TYPE_MIN_ADDR06 0x170108UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 0 conection type 6.
#define DORQ_REG_TYPE_MIN_ADDR07 0x17010cUL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 0 conection type 7.
#define DORQ_REG_TYPE_MIN_ADDR10 0x170110UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 1 conection type 0.
#define DORQ_REG_TYPE_MIN_ADDR11 0x170114UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 1 conection type 1.
#define DORQ_REG_TYPE_MIN_ADDR12 0x170118UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 1 conection type 2.
#define DORQ_REG_TYPE_MIN_ADDR13 0x17011cUL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 1 conection type 3.
#define DORQ_REG_TYPE_MIN_ADDR14 0x170120UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 1 conection type 4.
#define DORQ_REG_TYPE_MIN_ADDR15 0x170124UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 1 conection type 5.
#define DORQ_REG_TYPE_MIN_ADDR16 0x170128UL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 1 conection type 6.
#define DORQ_REG_TYPE_MIN_ADDR17 0x17012cUL //ACCESS:RW DataWidth:0x20 Description: The minimum level for the type address validation function 1 conection type 7.
#define DORQ_REG_TYPE_MAX_ADDR00 0x170130UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 0 connection type 0.
#define DORQ_REG_TYPE_MAX_ADDR01 0x170134UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 0 connection type 1.
#define DORQ_REG_TYPE_MAX_ADDR02 0x170138UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 0 connection type 2.
#define DORQ_REG_TYPE_MAX_ADDR03 0x17013cUL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 0 connection type 3.
#define DORQ_REG_TYPE_MAX_ADDR04 0x170140UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 0 connection type 4.
#define DORQ_REG_TYPE_MAX_ADDR05 0x170144UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 0 connection type 5.
#define DORQ_REG_TYPE_MAX_ADDR06 0x170148UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 0 connection type 6.
#define DORQ_REG_TYPE_MAX_ADDR07 0x17014cUL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 0 connection type 7.
#define DORQ_REG_TYPE_MAX_ADDR10 0x170150UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 1 connection type 0.
#define DORQ_REG_TYPE_MAX_ADDR11 0x170154UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 1 connection type 1.
#define DORQ_REG_TYPE_MAX_ADDR12 0x170158UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 1 connection type 2.
#define DORQ_REG_TYPE_MAX_ADDR13 0x17015cUL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 1 connection type 3.
#define DORQ_REG_TYPE_MAX_ADDR14 0x170160UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 1 connection type 4.
#define DORQ_REG_TYPE_MAX_ADDR15 0x170164UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 1 connection type 5.
#define DORQ_REG_TYPE_MAX_ADDR16 0x170168UL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 1 connection type 6.
#define DORQ_REG_TYPE_MAX_ADDR17 0x17016cUL //ACCESS:RW DataWidth:0x20 Description: The maximum level for the type address validation function 1 connection type 7.
#define DORQ_REG_TYPE_VAL_ERR_CNTR 0x170170UL //ACCESS:ST DataWidth:0x8 Description: The number of doorbells which failed the PF type validation.
#define DORQ_REG_DORQ_INT_STS 0x170174UL //ACCESS:R DataWidth:0x6 Description: Interrupt register #0 read
#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define DORQ_DORQ_INT_STS_REG_DB_DISCARD (0x1<<1)
#define DORQ_DORQ_INT_STS_REG_DB_DISCARD_SIZE 1
#define DORQ_DORQ_INT_STS_REG_TYPE_VAL_ERR (0x1<<2)
#define DORQ_DORQ_INT_STS_REG_TYPE_VAL_ERR_SIZE 2
#define DORQ_DORQ_INT_STS_REG_DB_COLLISION (0x1<<3)
#define DORQ_DORQ_INT_STS_REG_DB_COLLISION_SIZE 3
#define DORQ_DORQ_INT_STS_REG_DQ_AFULL (0x1<<4)
#define DORQ_DORQ_INT_STS_REG_DQ_AFULL_SIZE 4
#define DORQ_DORQ_INT_STS_REG_VF_TYPE_VAL_ERR (0x1<<5)
#define DORQ_DORQ_INT_STS_REG_VF_TYPE_VAL_ERR_SIZE 5
#define DORQ_REG_DORQ_INT_STS_CLR 0x170178UL //ACCESS:RC DataWidth:0x6 Description: Interrupt register #0 read clear
#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define DORQ_DORQ_INT_STS_CLR_REG_DB_DISCARD (0x1<<1)
#define DORQ_DORQ_INT_STS_CLR_REG_DB_DISCARD_SIZE 1
#define DORQ_DORQ_INT_STS_CLR_REG_TYPE_VAL_ERR (0x1<<2)
#define DORQ_DORQ_INT_STS_CLR_REG_TYPE_VAL_ERR_SIZE 2
#define DORQ_DORQ_INT_STS_CLR_REG_DB_COLLISION (0x1<<3)
#define DORQ_DORQ_INT_STS_CLR_REG_DB_COLLISION_SIZE 3
#define DORQ_DORQ_INT_STS_CLR_REG_DQ_AFULL (0x1<<4)
#define DORQ_DORQ_INT_STS_CLR_REG_DQ_AFULL_SIZE 4
#define DORQ_DORQ_INT_STS_CLR_REG_VF_TYPE_VAL_ERR (0x1<<5)
#define DORQ_DORQ_INT_STS_CLR_REG_VF_TYPE_VAL_ERR_SIZE 5
#define DORQ_REG_DORQ_INT_STS_WR 0x17017cUL //ACCESS:WR DataWidth:0x6 Description: Interrupt register #0 bit set or clear
#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define DORQ_DORQ_INT_STS_WR_REG_DB_DISCARD (0x1<<1)
#define DORQ_DORQ_INT_STS_WR_REG_DB_DISCARD_SIZE 1
#define DORQ_DORQ_INT_STS_WR_REG_TYPE_VAL_ERR (0x1<<2)
#define DORQ_DORQ_INT_STS_WR_REG_TYPE_VAL_ERR_SIZE 2
#define DORQ_DORQ_INT_STS_WR_REG_DB_COLLISION (0x1<<3)
#define DORQ_DORQ_INT_STS_WR_REG_DB_COLLISION_SIZE 3
#define DORQ_DORQ_INT_STS_WR_REG_DQ_AFULL (0x1<<4)
#define DORQ_DORQ_INT_STS_WR_REG_DQ_AFULL_SIZE 4
#define DORQ_DORQ_INT_STS_WR_REG_VF_TYPE_VAL_ERR (0x1<<5)
#define DORQ_DORQ_INT_STS_WR_REG_VF_TYPE_VAL_ERR_SIZE 5
#define DORQ_REG_DORQ_INT_MASK 0x170180UL //ACCESS:RW DataWidth:0x6 Description: Interrupt mask register #0 read/write
#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define DORQ_DORQ_INT_MASK_REG_DB_DISCARD (0x1<<1)
#define DORQ_DORQ_INT_MASK_REG_DB_DISCARD_SIZE 1
#define DORQ_DORQ_INT_MASK_REG_TYPE_VAL_ERR (0x1<<2)
#define DORQ_DORQ_INT_MASK_REG_TYPE_VAL_ERR_SIZE 2
#define DORQ_DORQ_INT_MASK_REG_DB_COLLISION (0x1<<3)
#define DORQ_DORQ_INT_MASK_REG_DB_COLLISION_SIZE 3
#define DORQ_DORQ_INT_MASK_REG_DQ_AFULL (0x1<<4)
#define DORQ_DORQ_INT_MASK_REG_DQ_AFULL_SIZE 4
#define DORQ_DORQ_INT_MASK_REG_VF_TYPE_VAL_ERR (0x1<<5)
#define DORQ_DORQ_INT_MASK_REG_VF_TYPE_VAL_ERR_SIZE 5
#define DORQ_REG_DORQ_PRTY_STS 0x170184UL //ACCESS:R DataWidth:0x2 Description: Parity register #0 read
#define DORQ_DORQ_PRTY_STS_REG_PARITY (0x1<<0)
#define DORQ_DORQ_PRTY_STS_REG_PARITY_SIZE 0
#define DORQ_DORQ_PRTY_STS_REG_DORQ_PRTY (0x1<<1)
#define DORQ_DORQ_PRTY_STS_REG_DORQ_PRTY_SIZE 1
#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188UL //ACCESS:RC DataWidth:0x2 Description: Parity register #0 read clear
#define DORQ_DORQ_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define DORQ_DORQ_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define DORQ_DORQ_PRTY_STS_CLR_REG_DORQ_PRTY (0x1<<1)
#define DORQ_DORQ_PRTY_STS_CLR_REG_DORQ_PRTY_SIZE 1
#define DORQ_REG_DORQ_PRTY_STS_WR 0x17018cUL //ACCESS:WR DataWidth:0x2 Description: Parity register #0 bit set or clear
#define DORQ_DORQ_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define DORQ_DORQ_PRTY_STS_WR_REG_PARITY_SIZE 0
#define DORQ_DORQ_PRTY_STS_WR_REG_DORQ_PRTY (0x1<<1)
#define DORQ_DORQ_PRTY_STS_WR_REG_DORQ_PRTY_SIZE 1
#define DORQ_REG_DORQ_PRTY_MASK 0x170190UL //ACCESS:RW DataWidth:0x2 Description: Parity mask register #0 read/write
#define DORQ_DORQ_PRTY_MASK_REG_PARITY (0x1<<0)
#define DORQ_DORQ_PRTY_MASK_REG_PARITY_SIZE 0
#define DORQ_DORQ_PRTY_MASK_REG_DORQ_PRTY (0x1<<1)
#define DORQ_DORQ_PRTY_MASK_REG_DORQ_PRTY_SIZE 1
#define DORQ_REG_ECO_RESERVED 0x170194UL //ACCESS:RW DataWidth:0x8 Description: chicken bits
#define DORQ_REG_DB_RSP_CNTR 0x1701acUL //ACCESS:R DataWidth:0x20 Description: Counts the number of doorbells sent to XCM or UCM on the response interface.
#define DORQ_REG_DB_FID0 0x1701b0UL //ACCESS:RW DataWidth:0xa Description: FID for RBC doorbells (function 0).
#define DORQ_REG_DB_FID1 0x1701b4UL //ACCESS:RW DataWidth:0xa Description: FID for RBC doorbells (function 1).
#define DORQ_REG_CANCEL_CMHEAD 0x1701c4UL //ACCESS:RW DataWidth:0x1c Description: The value sent to CM header in the case of CFC load cancellation.
#define DORQ_REG_CFC_CANCEL_CNTR 0x1701ccUL //ACCESS:ST DataWidth:0x8 Description: Counts the number of CFC load cancellations.
#define DORQ_REG_VF_DB_MIS_CNTR 0x1701d4UL //ACCESS:ST DataWidth:0x8 Description: Counts the total number of discarded doorbells in VF mode due to range mismatch
#define DORQ_REG_VF_TYPE_VAL_ERR_FID 0x1701d8UL //ACCESS:RC DataWidth:0xa Description: Keeps the FID of the first doorbell that caused a VF type validation error.
#define DORQ_REG_VF_TYPE_VAL_ERR_MCID 0x1701dcUL //ACCESS:RC DataWidth:0x11 Description: Keeps the MCID of the first doorbell that caused a VF type validation error.
#define DORQ_REG_VF_TYPE_VAL_ERR_CNTR 0x1701e0UL //ACCESS:ST DataWidth:0x8 Description: The number of doorbells which failed the VF type validation.
#define DORQ_REG_VF_INDEX_FIX_EN 0x1701e8UL //ACCESS:RW DataWidth:0x1 Description: Chicken bit for VF index fix. If high rf_dorq_func[9:4] maps to VF registers. Otherwise rf_dorq_func[5:0] maps to VF registers.
#define DORQ_REG_VF_TYPE_MASK_0 0x170218UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_1 0x17021cUL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_2 0x170220UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_3 0x170224UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_4 0x170228UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_5 0x17022cUL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_6 0x170230UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_7 0x170234UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_8 0x170238UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_9 0x17023cUL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_10 0x170240UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_11 0x170244UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_12 0x170248UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_13 0x17024cUL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_14 0x170250UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_MASK_15 0x170254UL //ACCESS:RW DataWidth:0xa Description: VF type validation mask value
#define DORQ_REG_VF_TYPE_VALUE_0 0x170258UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_1 0x17025cUL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_2 0x170260UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_3 0x170264UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_4 0x170268UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_5 0x17026cUL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_6 0x170270UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_7 0x170274UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_8 0x170278UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_9 0x17027cUL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_10 0x170280UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_11 0x170284UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_12 0x170288UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_13 0x17028cUL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_14 0x170290UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_VALUE_15 0x170294UL //ACCESS:RW DataWidth:0xa Description: VF type validation comp value
#define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_1 0x17029cUL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_2 0x1702a0UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_3 0x1702a4UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_4 0x1702a8UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_5 0x1702acUL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_6 0x1702b0UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_7 0x1702b4UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_8 0x1702b8UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_9 0x1702bcUL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_10 0x1702c0UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_11 0x1702c4UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_12 0x1702c8UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_13 0x1702ccUL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_14 0x1702d0UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MIN_MCID_15 0x1702d4UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Max MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_1 0x1702dcUL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_2 0x1702e0UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_3 0x1702e4UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_4 0x1702e8UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_5 0x1702ecUL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_6 0x1702f0UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_7 0x1702f4UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_8 0x1702f8UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_9 0x1702fcUL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_10 0x170300UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_11 0x170304UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_12 0x170308UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_13 0x17030cUL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_14 0x170310UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_VF_TYPE_MAX_MCID_15 0x170314UL //ACCESS:RW DataWidth:0x11 Description: VF type validation Min MCID value
#define DORQ_REG_AUTO_FREEZE_ST 0x170318UL //ACCESS:R DataWidth:0x1 Description: When high auto freeze is active and doorbells are not being drained from the FIFO. Cleared when auto_freeze_rel is written.
#define DORQ_REG_AUTO_DISCARD_ST 0x17031cUL //ACCESS:R DataWidth:0x1 Description: When high auto discard is active and all doorbells are dropped before going into the FIFO. Cleared when auto_discard_rel is written.
#define DORQ_REG_PF_DISCARD_STAT_POLL 0x17032cUL //ACCESS:R DataWidth:0x8 Description: Allows all the pf_discard_status bits to be read at once.
#define DORQ_REG_VF_DISCARD_STAT_POLL0 0x170338UL //ACCESS:R DataWidth:0x20 Description: Allows the upper 32 bits of the vf_discard_status bits to be read at once.
#define DORQ_REG_VF_DISCARD_STAT_POLL1 0x17033cUL //ACCESS:R DataWidth:0x20 Description: Allows the lower 32 bits of the vf_discard_status bits to be read at once.
#define DORQ_REG_CM_T_FLAG 0x170344UL //ACCESS:RW DataWidth:0x1 Description: Thread Required bit for error indicating CM messages
#define DORQ_REG_AGG_CMD_0 0x170400UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_1 0x170404UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_2 0x170408UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_3 0x17040cUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_4 0x170410UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_5 0x170414UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_6 0x170418UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_7 0x17041cUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_8 0x170420UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_9 0x170424UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_10 0x170428UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_11 0x17042cUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_12 0x170430UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_13 0x170434UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_14 0x170438UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_15 0x17043cUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_16 0x170440UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_17 0x170444UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_18 0x170448UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_19 0x17044cUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_20 0x170450UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_21 0x170454UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_22 0x170458UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_23 0x17045cUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_24 0x170460UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_25 0x170464UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_26 0x170468UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_27 0x17046cUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_28 0x170470UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_29 0x170474UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_30 0x170478UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_31 0x17047cUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_32 0x170480UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_33 0x170484UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_34 0x170488UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_35 0x17048cUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_36 0x170490UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_37 0x170494UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_38 0x170498UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_39 0x17049cUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_40 0x1704a0UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_41 0x1704a4UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_42 0x1704a8UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_43 0x1704acUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_44 0x1704b0UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_45 0x1704b4UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_46 0x1704b8UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_47 0x1704bcUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_48 0x1704c0UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_49 0x1704c4UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_50 0x1704c8UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_51 0x1704ccUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_52 0x1704d0UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_53 0x1704d4UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_54 0x1704d8UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_55 0x1704dcUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_56 0x1704e0UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_57 0x1704e4UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_58 0x1704e8UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_59 0x1704ecUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_60 0x1704f0UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_61 0x1704f4UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_62 0x1704f8UL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_AGG_CMD_63 0x1704fcUL //ACCESS:RW DataWidth:0x8 Description: Aggregation cmd per {vf_valid; conn type; A; R}
#define DORQ_REG_VF_NORM_ADDR_MASK 0x170198UL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: The normal mode address mask for VF doorbells. Filters a certain amount of MSBits of the address to distinguish the normal mode.
#define DORQ_REG_VF_NORM_ADDR_MASK_SIZE 1
#define DORQ_REG_VF_NORM_ADDR_BASE 0x17019cUL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: The normal mode base address for VF doorbells.
#define DORQ_REG_VF_NORM_ADDR_BASE_SIZE 1
#define DORQ_REG_VF_NORM_CID_BASE 0x1701a0UL //ACCESS:RW DataWidth:0x11 SPLIT:8 Description: The per-VNIC normal mode CID base for VF doorbells.
#define DORQ_REG_VF_NORM_CID_BASE_SIZE 1
#define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4UL //ACCESS:RW DataWidth:0x5 SPLIT:8 Description: The per-VNIC normal CID window size for VF doorbells.
#define DORQ_REG_VF_NORM_CID_WND_SIZE_SIZE 1
#define DORQ_REG_VF_NORM_VF_BASE 0x1701a8UL //ACCESS:RW DataWidth:0x3 SPLIT:8 Description: Starting absolute VFID for each PF
#define DORQ_REG_VF_NORM_VF_BASE_SIZE 1
#define DORQ_REG_DPM_MAX_CID_COUNT 0x1701b8UL //ACCESS:RW DataWidth:0x12 SPLIT:8 Description: Maximum number of PF CID values allowed for DPM mode
#define DORQ_REG_DPM_MAX_CID_COUNT_SIZE 1
#define DORQ_REG_NORM_MAX_CID_COUNT 0x1701bcUL //ACCESS:RW DataWidth:0x12 SPLIT:8 Description: Maximum number of PF CID values allowed for normal mode
#define DORQ_REG_NORM_MAX_CID_COUNT_SIZE 1
#define DORQ_REG_PF_USAGE_CNT 0x1701d0UL //ACCESS:R DataWidth:0xc SPLIT:8 Description: Per-PF usage count.
#define DORQ_REG_PF_USAGE_CNT_SIZE 1
#define DORQ_REG_VF_NORM_MAX_CID_COUNT 0x1701e4UL //ACCESS:RW DataWidth:0x12 SPLIT:8 Description: Maximum number of VF CID values allowed
#define DORQ_REG_VF_NORM_MAX_CID_COUNT_SIZE 1
#define DORQ_REG_MAX_RVFID_SIZE 0x1701ecUL //ACCESS:RW DataWidth:0x3 SPLIT:8 Description: Bit width of largest relative VFID.
#define DORQ_REG_MAX_RVFID_SIZE_SIZE 1
#define DORQ_REG_VF_NORM_CID_OFST 0x1701f4UL //ACCESS:RW DataWidth:0x5 SPLIT:8 Description: The normal mode CID extraction offset for VF doorbells.
#define DORQ_REG_VF_NORM_CID_OFST_SIZE 1
#define DORQ_REG_AUTO_DISCARD_REL 0x170200UL //ACCESS:W DataWidth:0x1 Description: Release the discard mode. Write only.
#define DORQ_REG_AUTO_DISCARD_REL_SIZE 1
#define DORQ_REG_AUTO_FREEZE_REL 0x170204UL //ACCESS:W DataWidth:0x1 Description: Release the freeze mode set by auto freeze. Write only.
#define DORQ_REG_AUTO_FREEZE_REL_SIZE 1
#define DORQ_REG_DB_DATA0 0x170208UL //ACCESS:RW DataWidth:0x20 Description: Doorbell data for RBC doorbells (function 0).
#define DORQ_REG_DB_DATA0_SIZE 1
#define DORQ_REG_DB_DATA1 0x17020cUL //ACCESS:RW DataWidth:0x20 Description: Doorbell data for RBC doorbells (function 1).
#define DORQ_REG_DB_DATA1_SIZE 1
#define DORQ_REG_DQ_FIFO_FULL_CLR 0x170210UL //ACCESS:W DataWidth:0x1 Description: Clears the full interrupt. Functionally write only. The read access is allowed with don't care data.
#define DORQ_REG_DQ_FIFO_FULL_CLR_SIZE 1
#define DORQ_REG_DQ_FILL_LVL_MAX 0x170214UL //ACCESS:RW DataWidth:0xd Description: Sticky value of the maximal DQ FIFO fill level. The range is 0 - 2560 FIFO rows; where each row stands for the doorbell.
#define DORQ_REG_DQ_FILL_LVL_MAX_SIZE 1
#define DORQ_REG_VF_USAGE_CNT 0x170320UL //ACCESS:R DataWidth:0x7 SPLIT:64 Description: Per-VF usage count
#define DORQ_REG_VF_USAGE_CNT_SIZE 1
#define DORQ_REG_PF_DISCARD_STATUS 0x170324UL //ACCESS:R DataWidth:0x1 SPLIT:8 Description: Per-PF register indicating that a doorbell has been dropped for this PF. Cleared when corresponding pf_discard_rel register is written.
#define DORQ_REG_PF_DISCARD_STATUS_SIZE 1
#define DORQ_REG_PF_DISCARD_REL 0x170328UL //ACCESS:W DataWidth:0x1 SPLIT:8 Description: When this register is written the corresponding pf_discard_status register is cleared.
#define DORQ_REG_PF_DISCARD_REL_SIZE 1
#define DORQ_REG_VF_DISCARD_STATUS 0x170330UL //ACCESS:R DataWidth:0x1 SPLIT:64 Description: Per-VF register indicating that a doorbell has been dropped for this VF. Cleared when corresponding vf_discard_rel register is written.
#define DORQ_REG_VF_DISCARD_STATUS_SIZE 1
#define DORQ_REG_VF_DISCARD_REL 0x170334UL //ACCESS:W DataWidth:0x1 SPLIT:64 Description: When this register is written the corresponding vf_discard_status register is cleared.
#define DORQ_REG_VF_DISCARD_REL_SIZE 1
#define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340UL //ACCESS:RW DataWidth:0x7 SPLIT:8 Description: Per-PF VF usage count limit
#define DORQ_REG_VF_USAGE_CT_LIMIT_SIZE 1
#define DORQ_REG_FIFO_CNTR 0x170348UL //ACCESS:RW DataWidth:0x20 Description: Counts all doorbells that enter the FIFO.
#define DORQ_REG_FIFO_CNTR_SIZE 2
#define DORQ_REG_DQ_FIFO 0x178000UL //ACCESS:R DataWidth:0x20 Description: Read access to DQ FIFO. The address will be composed of row number; standing for a specific doorbell - 12 Lsbits and 1 Msbit; which will be 1 to read the wait for done and CID indication and 0 - for all the other indications.
#define DORQ_REG_DQ_FIFO_SIZE 5120
#define DORQ_REG_AGG_CMD0 0x170060UL //ACCESS:R DataWidth:0x8 Description: Aggregation command.
#define DORQ_REG_AGG_CMD0_SIZE 1
#define DORQ_REG_AGG_CMD1 0x170064UL //ACCESS:R DataWidth:0x8 Description: Aggregation command.
#define DORQ_REG_AGG_CMD1_SIZE 1
#define DORQ_REG_AGG_CMD2 0x170068UL //ACCESS:R DataWidth:0x8 Description: Aggregation command.
#define DORQ_REG_AGG_CMD2_SIZE 1
#define DORQ_REG_AGG_CMD3 0x17006cUL //ACCESS:R DataWidth:0x8 Description: Aggregation command.
#define DORQ_REG_AGG_CMD3_SIZE 1
#define DORQ_REG_DORQ_UNUSED_EMPTY_0 0x1701c0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DORQ_REG_DORQ_UNUSED_EMPTY_0_SIZE 1
#define DORQ_REG_DORQ_UNUSED_EMPTY_1 0x1701c8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DORQ_REG_DORQ_UNUSED_EMPTY_1_SIZE 1
#define DORQ_REG_DORQ_UNUSED_EMPTY_2 0x1701f0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DORQ_REG_DORQ_UNUSED_EMPTY_2_SIZE 1
#define DORQ_REG_DORQ_UNUSED_EMPTY_3 0x1701f8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DORQ_REG_DORQ_UNUSED_EMPTY_3_SIZE 2
#define DORQ_REG_DORQ_UNUSED_EMPTY_4 0x170350UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DORQ_REG_DORQ_UNUSED_EMPTY_4_SIZE 44
#define DORQ_REG_DORQ_UNUSED_EMPTY_5 0x170500UL //ACCESS:R DataWidth:0x20 Unused empty space
#define DORQ_REG_DORQ_UNUSED_EMPTY_5_SIZE 7872
#define HC_REG_CONFIG_0 0x108000UL //ACCESS:RW DataWidth:0xd SPLIT:4 Multi Field Register
#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
#define HC_CONFIG_0_REG_BLOCK_DISABLE_0_SIZE 0
#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0_SIZE 1
#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0_SIZE 2
#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
#define HC_CONFIG_0_REG_INT_LINE_EN_0_SIZE 3
#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
#define HC_CONFIG_0_REG_ATTN_BIT_EN_0_SIZE 4
#define HC_CONFIG_0_REG_NOT_DURING_INT_EN_0 (0x1<<5)
#define HC_CONFIG_0_REG_NOT_DURING_INT_EN_0_SIZE 5
#define HC_CONFIG_0_REG_COALESCE_NOW_EN_0 (0x1<<6)
#define HC_CONFIG_0_REG_COALESCE_NOW_EN_0_SIZE 6
#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
#define HC_CONFIG_0_REG_MSI_ATTN_EN_0_SIZE 7
#define HC_CONFIG_0_REG_MSIX_ATTN_EN_0 (0x1<<8)
#define HC_CONFIG_0_REG_MSIX_ATTN_EN_0_SIZE 8
#define HC_CONFIG_0_REG_MAILBOX_COUNTER_0 (0x3<<9)
#define HC_CONFIG_0_REG_MAILBOX_COUNTER_0_SIZE 9
#define HC_CONFIG_0_REG_STATISTIC_COUNTER_EN_0 (0x1<<11)
#define HC_CONFIG_0_REG_STATISTIC_COUNTER_EN_0_SIZE 11
#define HC_CONFIG_0_REG_MSI_MSIX_MEMORY_EN_0 (0x1<<12)
#define HC_CONFIG_0_REG_MSI_MSIX_MEMORY_EN_0_SIZE 12
#define HC_REG_CONFIG_1 0x108004UL //ACCESS:RW DataWidth:0xd SPLIT:4 Multi Field Register
#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
#define HC_CONFIG_1_REG_BLOCK_DISABLE_1_SIZE 0
#define HC_CONFIG_1_REG_SINGLE_ISR_EN_1 (0x1<<1)
#define HC_CONFIG_1_REG_SINGLE_ISR_EN_1_SIZE 1
#define HC_CONFIG_1_REG_MSI_MSIX_INT_EN_1 (0x1<<2)
#define HC_CONFIG_1_REG_MSI_MSIX_INT_EN_1_SIZE 2
#define HC_CONFIG_1_REG_INT_LINE_EN_1 (0x1<<3)
#define HC_CONFIG_1_REG_INT_LINE_EN_1_SIZE 3
#define HC_CONFIG_1_REG_ATTN_BIT_EN_1 (0x1<<4)
#define HC_CONFIG_1_REG_ATTN_BIT_EN_1_SIZE 4
#define HC_CONFIG_1_REG_NOT_DURING_INT_EN_1 (0x1<<5)
#define HC_CONFIG_1_REG_NOT_DURING_INT_EN_1_SIZE 5
#define HC_CONFIG_1_REG_COALESCE_NOW_EN_1 (0x1<<6)
#define HC_CONFIG_1_REG_COALESCE_NOW_EN_1_SIZE 6
#define HC_CONFIG_1_REG_MSI_ATTN_EN_1 (0x1<<7)
#define HC_CONFIG_1_REG_MSI_ATTN_EN_1_SIZE 7
#define HC_CONFIG_1_REG_MSIX_ATTN_EN_1 (0x1<<8)
#define HC_CONFIG_1_REG_MSIX_ATTN_EN_1_SIZE 8
#define HC_CONFIG_1_REG_MAILBOX_COUNTER_1 (0x3<<9)
#define HC_CONFIG_1_REG_MAILBOX_COUNTER_1_SIZE 9
#define HC_CONFIG_1_REG_STATISTIC_COUNTER_EN_1 (0x1<<11)
#define HC_CONFIG_1_REG_STATISTIC_COUNTER_EN_1_SIZE 11
#define HC_CONFIG_1_REG_MSI_MSIX_MEMORY_EN_1 (0x1<<12)
#define HC_CONFIG_1_REG_MSI_MSIX_MEMORY_EN_1_SIZE 12
#define HC_REG_VQID_0 0x108008UL //ACCESS:RW DataWidth:0xa SPLIT:4 Multi Field Register
#define HC_VQID_0_REG_VQID_MSI_MSIX_0 (0x1f<<0)
#define HC_VQID_0_REG_VQID_MSI_MSIX_0_SIZE 0
#define HC_VQID_0_REG_VQID_ATTN_MSG_0 (0x1f<<5)
#define HC_VQID_0_REG_VQID_ATTN_MSG_0_SIZE 5
#define HC_REG_VQID_1 0x10800cUL //ACCESS:RW DataWidth:0xa SPLIT:4 Multi Field Register
#define HC_VQID_1_REG_VQID_MSI_MSIX_1 (0x1f<<0)
#define HC_VQID_1_REG_VQID_MSI_MSIX_1_SIZE 0
#define HC_VQID_1_REG_VQID_ATTN_MSG_1 (0x1f<<5)
#define HC_VQID_1_REG_VQID_ATTN_MSG_1_SIZE 5
#define HC_REG_PCI_CONFIG_0 0x108010UL //ACCESS:RW DataWidth:0x4 SPLIT:4 Multi Field Register
#define HC_PCI_CONFIG_0_REG_MSI_RELAX_0 (0x1<<0)
#define HC_PCI_CONFIG_0_REG_MSI_RELAX_0_SIZE 0
#define HC_PCI_CONFIG_0_REG_MSI_NO_SNOOP_0 (0x1<<1)
#define HC_PCI_CONFIG_0_REG_MSI_NO_SNOOP_0_SIZE 1
#define HC_PCI_CONFIG_0_REG_ATTN_RELAX_0 (0x1<<2)
#define HC_PCI_CONFIG_0_REG_ATTN_RELAX_0_SIZE 2
#define HC_PCI_CONFIG_0_REG_ATTN_NO_SNOOP_0 (0x1<<3)
#define HC_PCI_CONFIG_0_REG_ATTN_NO_SNOOP_0_SIZE 3
#define HC_REG_PCI_CONFIG_1 0x108014UL //ACCESS:RW DataWidth:0x4 SPLIT:4 Multi Field Register
#define HC_PCI_CONFIG_1_REG_MSI_RELAX_1 (0x1<<0)
#define HC_PCI_CONFIG_1_REG_MSI_RELAX_1_SIZE 0
#define HC_PCI_CONFIG_1_REG_MSI_NO_SNOOP_1 (0x1<<1)
#define HC_PCI_CONFIG_1_REG_MSI_NO_SNOOP_1_SIZE 1
#define HC_PCI_CONFIG_1_REG_ATTN_RELAX_1 (0x1<<2)
#define HC_PCI_CONFIG_1_REG_ATTN_RELAX_1_SIZE 2
#define HC_PCI_CONFIG_1_REG_ATTN_NO_SNOOP_1 (0x1<<3)
#define HC_PCI_CONFIG_1_REG_ATTN_NO_SNOOP_1_SIZE 3
#define HC_REG_ATTN_MSG0_ADDR_L 0x108018UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: port 0 lower 32 bits address field for attn messag.
#define HC_REG_ATTN_MSG0_ADDR_H 0x10801cUL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: port 0 higher 32 bits address field for attn messag.
#define HC_REG_ATTN_MSG1_ADDR_L 0x108020UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: port 1 lower 32 bits address field for attn messag.
#define HC_REG_ATTN_MSG1_ADDR_H 0x108024UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: port 1 higher 32 bits address field for attn messag.
#define HC_REG_UC_RAM_ADDR_0 0x108028UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Multi Field Register
#define HC_UC_RAM_ADDR_0_REG_USTORM_0_ADDR (0xffff<<0)
#define HC_UC_RAM_ADDR_0_REG_USTORM_0_ADDR_SIZE 0
#define HC_UC_RAM_ADDR_0_REG_CSTORM_0_ADDR (0xffff<<16)
#define HC_UC_RAM_ADDR_0_REG_CSTORM_0_ADDR_SIZE 16
#define HC_REG_XT_RAM_ADDR_0 0x10802cUL //ACCESS:RW DataWidth:0x20 SPLIT:4 Multi Field Register
#define HC_XT_RAM_ADDR_0_REG_XSTORM_0_ADDR (0xffff<<0)
#define HC_XT_RAM_ADDR_0_REG_XSTORM_0_ADDR_SIZE 0
#define HC_XT_RAM_ADDR_0_REG_TSTORM_0_ADDR (0xffff<<16)
#define HC_XT_RAM_ADDR_0_REG_TSTORM_0_ADDR_SIZE 16
#define HC_REG_UC_RAM_ADDR_1 0x108030UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Multi Field Register
#define HC_UC_RAM_ADDR_1_REG_USTORM_1_ADDR (0xffff<<0)
#define HC_UC_RAM_ADDR_1_REG_USTORM_1_ADDR_SIZE 0
#define HC_UC_RAM_ADDR_1_REG_CSTORM_1_ADDR (0xffff<<16)
#define HC_UC_RAM_ADDR_1_REG_CSTORM_1_ADDR_SIZE 16
#define HC_REG_XT_RAM_ADDR_1 0x108034UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Multi Field Register
#define HC_XT_RAM_ADDR_1_REG_XSTORM_1_ADDR (0xffff<<0)
#define HC_XT_RAM_ADDR_1_REG_XSTORM_1_ADDR_SIZE 0
#define HC_XT_RAM_ADDR_1_REG_TSTORM_1_ADDR (0xffff<<16)
#define HC_XT_RAM_ADDR_1_REG_TSTORM_1_ADDR_SIZE 16
#define HC_REG_ATTN_NUM_P0 0x108038UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: status block number for attn bit msg - function 0;
#define HC_REG_ATTN_NUM_P1 0x10803cUL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: status block number for attn bit msg - function 1
#define HC_REG_LEADING_EDGE_0 0x108040UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: port 0 attn bit condition monitoring; each bit that is set will lock a change fron 0 to 1 in the corresponding attention signals that comes from the AEU
#define HC_REG_TRAILING_EDGE_0 0x108044UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: port 0 attn bit condition monitoring; each bit that is set will lock a change fron 1 to 0 in the corresponding attention signals that comes from the AEU
#define HC_REG_LEADING_EDGE_1 0x108048UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: port 1 attn bit condition monitoring; each bit that is set will lock a change fron 0 to 1 in the corresponding attention signals that comes from the AEU
#define HC_REG_TRAILING_EDGE_1 0x10804cUL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: port 1 attn bit condition monitoring; each bit that is set will lock a change fron 1 to 0 in the corresponding attention signals that comes from the AEU
#define HC_REG_AGG_INT_0 0x108050UL //ACCESS:RW DataWidth:0xa SPLIT:4 Multi Field Register
#define HC_AGG_INT_0_REG_AGG_INT_COALESCE_NOW_0 (0x1f<<0)
#define HC_AGG_INT_0_REG_AGG_INT_COALESCE_NOW_0_SIZE 0
#define HC_AGG_INT_0_REG_AGG_INT_CONSUMER_UPD_0 (0x1f<<5)
#define HC_AGG_INT_0_REG_AGG_INT_CONSUMER_UPD_0_SIZE 5
#define HC_REG_AGG_INT_1 0x108054UL //ACCESS:RW DataWidth:0xa SPLIT:4 Multi Field Register
#define HC_AGG_INT_1_REG_AGG_INT_COALESCE_NOW_1 (0x1f<<0)
#define HC_AGG_INT_1_REG_AGG_INT_COALESCE_NOW_1_SIZE 0
#define HC_AGG_INT_1_REG_AGG_INT_CONSUMER_UPD_1 (0x1f<<5)
#define HC_AGG_INT_1_REG_AGG_INT_CONSUMER_UPD_1_SIZE 5
#define HC_REG_INTERRUPT_A 0x108058UL //ACCESS:R DataWidth:0x1 SPLIT:4 Description: read the interrupt b line value; 0 = asserted; 1= deasserted
#define HC_REG_INTERRUPT_B 0x10805cUL //ACCESS:R DataWidth:0x1 SPLIT:4 Description: read the interrupt a line value; 0 = asserted; 1= deasserted
#define HC_REG_STATISTIC_DIVIDER 0x108060UL //ACCESS:RW DataWidth:0x14 SPLIT:4 Description: Define the time statistic counter timer resolution (period rate of HW and SW intack counters update); minimuv value = 2500
#define HC_REG_COUNERTS_MEM_TM 0x108064UL //ACCESS:RW DataWidth:0x4 SPLIT:4 Description: tm bits for statistic counters memory
#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: UNUSED
#define HC_REG_CSTORM_ADDR_FOR_COALESCE 0x10806cUL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: UNUSED
#define HC_REG_XSTORM_ADDR_FOR_COALESCE 0x108070UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: UNUSED
#define HC_REG_TSTORM_ADDR_FOR_COALESCE 0x108074UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: UNUSED
#define HC_REG_DBG_SELECT 0x108078UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Debug only: For dbgmux usage (debug data that goes from HC to the DBG block) - for selecting a line to output to the DBG block.
#define HC_REG_DBG_BYTE_ENABLE 0x10807cUL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Debug only: For dbgmux usage (debug data that goes from HC to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define HC_REG_DBG_SHIFT 0x108080UL //ACCESS:RW DataWidth:0x3 SPLIT:4 Description: Debug only: For dbgmux usage (debug data that goes from HC to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define HC_REG_HC_INT_STS 0x108084UL //ACCESS:R DataWidth:0x7 Description: Interrupt register #0 read
#define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define HC_HC_INT_STS_REG_FIFO_ERROR (0x1<<1)
#define HC_HC_INT_STS_REG_FIFO_ERROR_SIZE 1
#define HC_HC_INT_STS_REG_MME_IS_BIGGER_THEN_5 (0x1<<2)
#define HC_HC_INT_STS_REG_MME_IS_BIGGER_THEN_5_SIZE 2
#define HC_HC_INT_STS_REG_TMP_STORM_ID_NOT_MATCH (0x1<<3)
#define HC_HC_INT_STS_REG_TMP_STORM_ID_NOT_MATCH_SIZE 3
#define HC_HC_INT_STS_REG_MAIN_MEMORY (0x1<<4)
#define HC_HC_INT_STS_REG_MAIN_MEMORY_SIZE 4
#define HC_HC_INT_STS_REG_STATISTIC_COUNTER_MEMORY (0x1<<5)
#define HC_HC_INT_STS_REG_STATISTIC_COUNTER_MEMORY_SIZE 5
#define HC_HC_INT_STS_REG_CONS_OR_PROD_IDX_TOO_BIG (0x1<<6)
#define HC_HC_INT_STS_REG_CONS_OR_PROD_IDX_TOO_BIG_SIZE 6
#define HC_REG_HC_INT_STS_CLR 0x108088UL //ACCESS:RC DataWidth:0x7 Description: Interrupt register #0 read clear
#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define HC_HC_INT_STS_CLR_REG_FIFO_ERROR (0x1<<1)
#define HC_HC_INT_STS_CLR_REG_FIFO_ERROR_SIZE 1
#define HC_HC_INT_STS_CLR_REG_MME_IS_BIGGER_THEN_5 (0x1<<2)
#define HC_HC_INT_STS_CLR_REG_MME_IS_BIGGER_THEN_5_SIZE 2
#define HC_HC_INT_STS_CLR_REG_TMP_STORM_ID_NOT_MATCH (0x1<<3)
#define HC_HC_INT_STS_CLR_REG_TMP_STORM_ID_NOT_MATCH_SIZE 3
#define HC_HC_INT_STS_CLR_REG_MAIN_MEMORY (0x1<<4)
#define HC_HC_INT_STS_CLR_REG_MAIN_MEMORY_SIZE 4
#define HC_HC_INT_STS_CLR_REG_STATISTIC_COUNTER_MEMORY (0x1<<5)
#define HC_HC_INT_STS_CLR_REG_STATISTIC_COUNTER_MEMORY_SIZE 5
#define HC_HC_INT_STS_CLR_REG_CONS_OR_PROD_IDX_TOO_BIG (0x1<<6)
#define HC_HC_INT_STS_CLR_REG_CONS_OR_PROD_IDX_TOO_BIG_SIZE 6
#define HC_REG_HC_INT_STS_WR 0x10808cUL //ACCESS:WR DataWidth:0x7 Description: Interrupt register #0 bit set or clear
#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define HC_HC_INT_STS_WR_REG_FIFO_ERROR (0x1<<1)
#define HC_HC_INT_STS_WR_REG_FIFO_ERROR_SIZE 1
#define HC_HC_INT_STS_WR_REG_MME_IS_BIGGER_THEN_5 (0x1<<2)
#define HC_HC_INT_STS_WR_REG_MME_IS_BIGGER_THEN_5_SIZE 2
#define HC_HC_INT_STS_WR_REG_TMP_STORM_ID_NOT_MATCH (0x1<<3)
#define HC_HC_INT_STS_WR_REG_TMP_STORM_ID_NOT_MATCH_SIZE 3
#define HC_HC_INT_STS_WR_REG_MAIN_MEMORY (0x1<<4)
#define HC_HC_INT_STS_WR_REG_MAIN_MEMORY_SIZE 4
#define HC_HC_INT_STS_WR_REG_STATISTIC_COUNTER_MEMORY (0x1<<5)
#define HC_HC_INT_STS_WR_REG_STATISTIC_COUNTER_MEMORY_SIZE 5
#define HC_HC_INT_STS_WR_REG_CONS_OR_PROD_IDX_TOO_BIG (0x1<<6)
#define HC_HC_INT_STS_WR_REG_CONS_OR_PROD_IDX_TOO_BIG_SIZE 6
#define HC_REG_HC_INT_MASK 0x108090UL //ACCESS:RW DataWidth:0x7 Description: Interrupt mask register #0 read/write
#define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define HC_HC_INT_MASK_REG_FIFO_ERROR (0x1<<1)
#define HC_HC_INT_MASK_REG_FIFO_ERROR_SIZE 1
#define HC_HC_INT_MASK_REG_MME_IS_BIGGER_THEN_5 (0x1<<2)
#define HC_HC_INT_MASK_REG_MME_IS_BIGGER_THEN_5_SIZE 2
#define HC_HC_INT_MASK_REG_TMP_STORM_ID_NOT_MATCH (0x1<<3)
#define HC_HC_INT_MASK_REG_TMP_STORM_ID_NOT_MATCH_SIZE 3
#define HC_HC_INT_MASK_REG_MAIN_MEMORY (0x1<<4)
#define HC_HC_INT_MASK_REG_MAIN_MEMORY_SIZE 4
#define HC_HC_INT_MASK_REG_STATISTIC_COUNTER_MEMORY (0x1<<5)
#define HC_HC_INT_MASK_REG_STATISTIC_COUNTER_MEMORY_SIZE 5
#define HC_HC_INT_MASK_REG_CONS_OR_PROD_IDX_TOO_BIG (0x1<<6)
#define HC_HC_INT_MASK_REG_CONS_OR_PROD_IDX_TOO_BIG_SIZE 6
#define HC_REG_HC_PRTY_STS 0x108094UL //ACCESS:R DataWidth:0x3 Description: Parity register #0 read
#define HC_HC_PRTY_STS_REG_PARITY (0x1<<0)
#define HC_HC_PRTY_STS_REG_PARITY_SIZE 0
#define HC_HC_PRTY_STS_REG_MAIN_MEMORY (0x1<<1)
#define HC_HC_PRTY_STS_REG_MAIN_MEMORY_SIZE 1
#define HC_HC_PRTY_STS_REG_COUNTERS_MEMORY (0x1<<2)
#define HC_HC_PRTY_STS_REG_COUNTERS_MEMORY_SIZE 2
#define HC_REG_HC_PRTY_STS_CLR 0x108098UL //ACCESS:RC DataWidth:0x3 Description: Parity register #0 read clear
#define HC_HC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define HC_HC_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define HC_HC_PRTY_STS_CLR_REG_MAIN_MEMORY (0x1<<1)
#define HC_HC_PRTY_STS_CLR_REG_MAIN_MEMORY_SIZE 1
#define HC_HC_PRTY_STS_CLR_REG_COUNTERS_MEMORY (0x1<<2)
#define HC_HC_PRTY_STS_CLR_REG_COUNTERS_MEMORY_SIZE 2
#define HC_REG_HC_PRTY_STS_WR 0x10809cUL //ACCESS:WR DataWidth:0x3 Description: Parity register #0 bit set or clear
#define HC_HC_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define HC_HC_PRTY_STS_WR_REG_PARITY_SIZE 0
#define HC_HC_PRTY_STS_WR_REG_MAIN_MEMORY (0x1<<1)
#define HC_HC_PRTY_STS_WR_REG_MAIN_MEMORY_SIZE 1
#define HC_HC_PRTY_STS_WR_REG_COUNTERS_MEMORY (0x1<<2)
#define HC_HC_PRTY_STS_WR_REG_COUNTERS_MEMORY_SIZE 2
#define HC_REG_HC_PRTY_MASK 0x1080a0UL //ACCESS:RW DataWidth:0x3 Description: Parity mask register #0 read/write
#define HC_HC_PRTY_MASK_REG_PARITY (0x1<<0)
#define HC_HC_PRTY_MASK_REG_PARITY_SIZE 0
#define HC_HC_PRTY_MASK_REG_MAIN_MEMORY (0x1<<1)
#define HC_HC_PRTY_MASK_REG_MAIN_MEMORY_SIZE 1
#define HC_HC_PRTY_MASK_REG_COUNTERS_MEMORY (0x1<<2)
#define HC_HC_PRTY_MASK_REG_COUNTERS_MEMORY_SIZE 2
#define HC_REG_FUNC_NUM_P0 0x1080acUL //ACCESS:RW DataWidth:0x3 SPLIT:4 Description: function number for MSI MSIX & Attn message
#define HC_REG_FUNC_NUM_P1 0x1080b0UL //ACCESS:RW DataWidth:0x3 SPLIT:4 Description: function number for MSI MSIX & Attn message
#define HC_REG_AEU_MSI_ATTN_P0 0x1080b4UL //ACCESS:R DataWidth:0x4 Description: read hc_misc_aeu_msi_msix_attn_p0 of all the cores. [0] HC_0; [1] HC_1; [2] HC_2; [3] HC_3
#define HC_REG_AEU_MSI_ATTN_P0_SIZE 1
#define HC_REG_AEU_MSI_ATTN_P1 0x1080b8UL //ACCESS:R DataWidth:0x4 Description: read hc_misc_aeu_msi_msix_attn_p1 of all the cores. [0] HC_0; [1] HC_1; [2] HC_2; [3] HC_4
#define HC_REG_AEU_MSI_ATTN_P1_SIZE 1
#define HC_REG_PXP_REQUESTER_CREDIT 0x1080bcUL //ACCESS:RW DataWidth:0x2 Description: the credit for the PXP requester interface. This register is common for all the HC cores. Only 0ne and two are valid values.
#define HC_REG_PXP_REQUESTER_CREDIT_SIZE 1
#define HC_REG_ATTN_IDX 0x108100UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: attn bits status index for attn bit msg; addr 0 - function 0; addr 1 - functin 1
#define HC_REG_ATTN_IDX_SIZE 2
#define HC_REG_INT_MASK 0x108108UL //ACCESS:RW DataWidth:0x11 SPLIT:4 Description: status block interrupt mask; one in each bit means unmask; zerow in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1 to bit 16- SB_15; addr 0 - port 0; addr 1 - port 1
#define HC_REG_INT_MASK_SIZE 2
#define HC_REG_PBA_BIT 0x108110UL //ACCESS:RW DataWidth:0x11 SPLIT:4 Description: PBA 17 bits adress 0 - port0; address 1 - port 1; bit0 = default SB; bit1 = SB_0; bit2 = SB_1 . . . bit16 = SB_15; Each bit in the vector is updated according with scan procedure for MSI/MSI-X message build and posting according to the following rules: If the pending is set AND For the relevant port MSI-X is enabled AND Block is not disabled (per port indication) AND No full indication from the PCI command transmission interface logic AND (relevant MSI-X function mask bit is set OR relevant MSI-X vector mask bit is set) Then the analogous PBA bit is set; The bit is cleared upon posting an MSI-X message for the analogous pending bit.
#define HC_REG_PBA_BIT_SIZE 2
#define HC_REG_ATTN_BIT 0x108120UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: attention bit and attention acknowledge bits status for port 0 and 1 according to the following address map: addr 0 - attn_bit_0; addr 1 - attn_ack_bit_0; addr 2 - attn_bit_1; addr 3 - attn_ack_bit_1;
#define HC_REG_ATTN_BIT_SIZE 4
#define HC_REG_DEC_CEILING 0x108130UL //ACCESS:W DataWidth:0x1 SPLIT:4 Description: This command register infuence the MSI configuration state machine. This register is write only and has 4 addresses as follow: 0 = dec port 0; 1 = ceiling port 0; 2 = dec port 1; 3 = ceiling port 1;
#define HC_REG_DEC_CEILING_SIZE 4
#define HC_REG_PBA_COMMAND 0x108140UL //ACCESS:W DataWidth:0x1 SPLIT:4 Description: This register is write only and has 4 addresses as follow: 0 = clear all PBA bits port 0; 1 = clear all pending interrupts request port0; 2 = clear all PBA bits port 1; 3 = clear all pending interrupts request port1;there is no meaning for the data in this register
#define HC_REG_PBA_COMMAND_SIZE 4
#define HC_REG_COMMAND_REG 0x108180UL //ACCESS:RW DataWidth:0x1b SPLIT:4 Description: This command register has 16 addresses. Write to these registers active command according to the address. For port 0 the address mapped as follow: 0-interrupt acknowledge ; 1-producer update ; 2-attntion bits update; 3-attntion bits set; 4-attntion bits clear; 5-coalesce now; 6-single_isr_multi_dpc with mask; 7-single isr without mask; For port 1 the address mapped as follow: 8-interrupt acknowledge ; 9-producer update ; 10-attntion bits update; 11-attntion bits set; 12-attntion bits clear; 13-coalesce now; 14-single_isr_multi_dpc with mask; 15-single isr without mask; Read from addresses 0-5 and 8-13 is ignored; Write to addresses 6-7 and 14-15 is ignored; the data bits are mapped as follow: tmp_dis_enable_cmd = data[26:25]; tmp_upd_index_cmd = data[24]; tmp_cmd_storm_index = data[23:21] // according to storm table; tmp_cmd_status_id = data[20:16] // according to status block idx table; tmp_index_val = data[15:0]; tmp_function = according to MSB address. if address match interrupt acknowledge {If (tmp_upd_index_cmd == 1) Update consumer index of (tmp_cmd_storm_index; tmp_cmd_status_id) for function(tmp_function) to be tmp_index_val; Check relevant comparator output; If (comparator output is clr (i.e. Prod==Cons) AND tmp_cmd_storm_index < 4 (STORM update) ) set a request for the following command toward the tmp_cmd_storm_index: aggregate_int (according to tmp_function value will be taken from ~agg_int_consumer_upd_0 or agg_int_consumer_upd_1); address (according to tmp_cmd_status_id and tmp_function ~ustorm_0_addr; ~cstorm_0_addr; ~xstorm_0_addr; ~tstorm_0_addr; ~ustorm_1_addr; ~cstorm_1_addr; ~xstorm_1_addr; ~tstorm_1_addr); STORM index (according to tmp_cmd_storm_index); data = consumer index; If (tmp_dis_enable_cmd == 0) Set bit for SB (tmp_cmd_status_id) for function(tmp_function) Else if (tmp_dis_enable_cmd == 1) Clr bit for SB(tmp_cmd_status_id) for function (tmp_function)} else if address matches producer update { If (tmp_upd_index_cmd == 1) Update producer index of (tmp_cmd_storm_index; tmp_cmd_status_id) for function(tmp_function) to be tmp_index_val; If (tmp_dis_enable_cmd == 0) Set mask bit for SB(tmp_cmd_status_id) for function(tmp_function) Else if (tmp_dis_enable_cmd == 1) Clr mask bit for SB(tmp_cmd_status_id) for function(tmp_function)} else if command address matches attn bit upd register {Attn_bit_ack_reg(tmp_function) = data[15:0]} else if command address matches attn bit set register {attn_bit_ack_reg(tmp_function) |= data[15:0]} else if command address matches attn bit clr register {attn_bit_ack_reg(tmp_function) &= data[31:0]} else if command address matches coalesce now { set a request for the following command toward the tmp_cmd_storm_index: aggregate_int (according to tmp_function value will be taken from ~agg_int_coalesce_now_0 or agg_int_coalesce_now_1); address (according to ~ustorm_addr_for_coalesce; ~cstorm_addr_for_coalesce; ~xstorm_addr_for_coalesce; ~tstorm_addr_for_coalesce); STORM index 4 commands are sent (a command per STORM); data = 0; byte enable = all set} else if command address matches single_isr_multi_dpc with mask register { according to tmp_function ret_value = interrupt vector after mask[16:0]; mask tmp_function interrupt register according to rev_value (every one in ret_value masks relevant interrupt)} else if command address matches single_isr_multi_dpc without mask register {according to tmp_function ret_value = interrupt vector after mask[16:0]}.
#define HC_REG_COMMAND_REG_SIZE 16
#define HC_REG_P0_PROD_CONS 0x108200UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: all producer and consumer of port 0 according to the following addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63; Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons: U/C/X/T/Attn-69/70/71/72/73
#define HC_REG_P0_PROD_CONS_SIZE 74
#define HC_REG_P1_PROD_CONS 0x108400UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: all producer and consumer of port 1according to the following addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63; Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons: U/C/X/T/Attn-69/70/71/72/73
#define HC_REG_P1_PROD_CONS_SIZE 74
#define HC_REG_MAIN_MEMORY 0x108800UL //ACCESS:WB DataWidth:0x40 SPLIT:4 Description: The MSI and MSIX memory; each address has 64 bits of data; the address map is as follows; Port 0: addr 0-33 - MSIX_vector (acording to the following distribution: 0 - default SB MSIX addr; 1 - default SB msix data and mask (mask[32];data[31:0]); 2 - SB_0 MSIX addr; 3 - SB_0 msix data and mask (mask[32];data[31:0]); 4 - SB_1 MSIX addr; 5 - SB_1 msix data and mask (mask[32];data[31:0]);... 32 - SB_16 MSIX addr; 33 - SB_16 msix data and mask (mask[32];data[31:0])); addr 34 - MSI_msg_ctrl; addr 35 - MSI_addr_low; addr 36 - MSI_addr_high ; addr 37 - [63:32] - MSI_mask_bit [31:0] - MSI_data. Port 1: addr 38-71 - MSIX_vector (acording to the following distribution: 38 - default SB MSIX addr; 39 - default SB msix data and mask (mask[32];data[31:0]); 40 - SB_0 MSIX addr; 41 - SB_0 msix data and mask (mask[32];data[31:0]); 42 - SB_1 MSIX addr; 43 - SB_1 msix data and mask (mask[32];data[31:0]);... 70 - SB_16 MSIX addr; 71 - SB_16 msix data and mask (mask[32];data[31:0])); addr 72 - MSI_msg_ctrl; addr 73 - MSI_addr_low; addr 74 - MSI_addr_high ; addr 75 - [63:32] - MSI_mask_bit [31:0] - MSI_data.
#define HC_REG_MAIN_MEMORY_SIZE 152
#define HC_REG_STATISTIC_COUNTERS 0x109000UL //ACCESS:RW DataWidth:0x18 SPLIT:4 Description: all counters acording to the following address: LSB: 0=read; 1= read_clear; 0-71 = HW counters (the inside order is the same as the interrupt table in the spec); 72-219 = SW counters 1 (stops after first consumer upd) the inside order is: 72-103 - U_non_default_p0; 104-135 C_non_defaul_p0;136-145 U/C/X/T/Attn_default_p0; 146-177 U_non_default_p1; 178-209 C_non_defaul_p1;210-219 U/C/X/T/Attn_default_p1 ; 220-367 = SW counters 2 (stops when prod=cons) the inside order is: 220-251 - U_non_default_p0; 252-283 C_non_defaul_p0;284-293 U/C/X/T/Attn_default_p0; 294-325 U_non_default_p1; 326-357 C_non_defaul_p1;358-367 U/C/X/T/Attn_default_p1 ; 368-515 = mailbox counters; (the inside order of the mailbox counter is 368-431 U and C non_default_p0; 432-441 U/C//X/T/Attn_default_p0; 442-505 U and C non_default_p1; 506-515 U/C//X/T/Attn_default_p1)
#define HC_REG_STATISTIC_COUNTERS_SIZE 516
#define HC_REG_HC_UNUSED_EMPTY_0 0x1080a4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define HC_REG_HC_UNUSED_EMPTY_0_SIZE 2
#define HC_REG_HC_UNUSED_EMPTY_1 0x1080c0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define HC_REG_HC_UNUSED_EMPTY_1_SIZE 16
#define HC_REG_HC_UNUSED_EMPTY_2 0x108118UL //ACCESS:R DataWidth:0x20 Unused empty space
#define HC_REG_HC_UNUSED_EMPTY_2_SIZE 2
#define HC_REG_HC_UNUSED_EMPTY_3 0x108150UL //ACCESS:R DataWidth:0x20 Unused empty space
#define HC_REG_HC_UNUSED_EMPTY_3_SIZE 12
#define HC_REG_HC_UNUSED_EMPTY_4 0x1081c0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define HC_REG_HC_UNUSED_EMPTY_4_SIZE 16
#define HC_REG_HC_UNUSED_EMPTY_5 0x108600UL //ACCESS:R DataWidth:0x20 Unused empty space
#define HC_REG_HC_UNUSED_EMPTY_5_SIZE 128
#define HC_REG_HC_UNUSED_EMPTY_6 0x108c00UL //ACCESS:R DataWidth:0x20 Unused empty space
#define HC_REG_HC_UNUSED_EMPTY_6_SIZE 256
#define HC_REG_HC_UNUSED_EMPTY_7 0x10a000UL //ACCESS:R DataWidth:0x20 Unused empty space
#define HC_REG_HC_UNUSED_EMPTY_7_SIZE 2048
#define IGU_REG_BLOCK_CONFIGURATION 0x130000UL //ACCESS:RW DataWidth:0x5 Multi Field Register
#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE_SIZE 0
#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN_SIZE 1
#define IGU_BLOCK_CONFIGURATION_REG_BUS_DWORD_SELECT (0x1<<2)
#define IGU_BLOCK_CONFIGURATION_REG_BUS_DWORD_SELECT_SIZE 2
#define IGU_BLOCK_CONFIGURATION_REG_PORT4MODE_EN (0x1<<3)
#define IGU_BLOCK_CONFIGURATION_REG_PORT4MODE_EN_SIZE 3
#define IGU_BLOCK_CONFIGURATION_REG_TIMER_MASK_EN (0x1<<4)
#define IGU_BLOCK_CONFIGURATION_REG_TIMER_MASK_EN_SIZE 4
#define IGU_REG_MESSAGE_FIELDS 0x130004UL //ACCESS:RW DataWidth:0x1a Multi Field Register
#define IGU_MESSAGE_FIELDS_REG_MSI_MSIX_VQID (0x1f<<0)
#define IGU_MESSAGE_FIELDS_REG_MSI_MSIX_VQID_SIZE 0
#define IGU_MESSAGE_FIELDS_REG_MSI_MSIX_ATC (0x7<<5)
#define IGU_MESSAGE_FIELDS_REG_MSI_MSIX_ATC_SIZE 5
#define IGU_MESSAGE_FIELDS_REG_MSI_MSIX_RO (0x1<<8)
#define IGU_MESSAGE_FIELDS_REG_MSI_MSIX_RO_SIZE 8
#define IGU_MESSAGE_FIELDS_REG_MSI_MSIX_NS (0x1<<9)
#define IGU_MESSAGE_FIELDS_REG_MSI_MSIX_NS_SIZE 9
#define IGU_MESSAGE_FIELDS_REG_MSIX_WRITE_DONE_TYPE (0x1<<10)
#define IGU_MESSAGE_FIELDS_REG_MSIX_WRITE_DONE_TYPE_SIZE 10
#define IGU_MESSAGE_FIELDS_REG_MESSAGE_FIELDS_RESEVED (0xf<<11)
#define IGU_MESSAGE_FIELDS_REG_MESSAGE_FIELDS_RESEVED_SIZE 11
#define IGU_MESSAGE_FIELDS_REG_ATTN_VQID (0x1f<<15)
#define IGU_MESSAGE_FIELDS_REG_ATTN_VQID_SIZE 15
#define IGU_MESSAGE_FIELDS_REG_ATTN_ATC (0x7<<20)
#define IGU_MESSAGE_FIELDS_REG_ATTN_ATC_SIZE 20
#define IGU_MESSAGE_FIELDS_REG_ATTN_RO (0x1<<23)
#define IGU_MESSAGE_FIELDS_REG_ATTN_RO_SIZE 23
#define IGU_MESSAGE_FIELDS_REG_ATTN_NS (0x1<<24)
#define IGU_MESSAGE_FIELDS_REG_ATTN_NS_SIZE 24
#define IGU_MESSAGE_FIELDS_REG_ATTN_WRITE_DONE_TYPE (0x1<<25)
#define IGU_MESSAGE_FIELDS_REG_ATTN_WRITE_DONE_TYPE_SIZE 25
#define IGU_REG_FUNC_WITH_MORE_16_SB_0 0x130008UL //ACCESS:RW DataWidth:0x9 Description: The first function numbers that has more then 16 SBs. [6:0] - function number (if VF - [6] = 0; [5:0] = VFID if PF - [6] = 1; [5:3] = 0; [2:0] = PFID); . [7] reserved. [8] - valid bit. In backward compatible mode - not used. The reset value match 2ports mode operation. in 4ports mode it should be reconfigured.
#define IGU_REG_FUNC_WITH_MORE_16_SB_1 0x13000cUL //ACCESS:RW DataWidth:0x9 Description: The second function numbers that has more then 16 SBs. [6:0] - function number (if VF - [6] = 0; [5:0] = VFID if PF - [6] = 1; [5:3] = 0; [2:0] = PFID); . [7] reserved. [8] - valid bit. In backward compatible mode - not used. The reset value match 2ports mode operation. in 4ports mode it should be reconfigured.
#define IGU_REG_FUNC_WITH_MORE_16_SB_2 0x130010UL //ACCESS:RW DataWidth:0x9 Description: The third function numbers that has more then 16 SBs. [6:0] - function number (if VF - [6] = 0; [5:0] = VFID if PF - [6] = 1; [5:3] = 0; [2:0] = PFID); . [7] reserved. [8] - valid bit. In backward compatible mode - not used. The reset value match 2ports mode operation. in 4ports mode it should be reconfigured.
#define IGU_REG_FUNC_WITH_MORE_16_SB_3 0x130014UL //ACCESS:RW DataWidth:0x9 Description: The forth function numbers that has more then 16 SBs. [6:0] - function number (if VF - [6] = 0; [5:0] = VFID if PF - [6] = 1; [5:3] = 0; [2:0] = PFID); . [7] reserved. [8] - valid bit. In backward compatible mode - not used. The reset value match 2ports mode operation. in 4ports mode it should be reconfigured.
#define IGU_REG_FUNC_WITH_MORE_16_SB_4 0x130018UL //ACCESS:RW DataWidth:0x9 Description: The fifth function numbers that has more then 16 SBs. [6:0] - function number (if VF - [6] = 0; [5:0] = VFID if PF - [6] = 1; [5:3] = 0; [2:0] = PFID); . [7] reserved. [8] - valid bit. In backward compatible mode - not used. The reset value match 2ports mode operation. in 4ports mode it should be reconfigured.
#define IGU_REG_FUNC_WITH_MORE_16_SB_5 0x13001cUL //ACCESS:RW DataWidth:0x9 Description: The sixth function numbers that has more then 16 SBs. [6:0] - function number (if VF - [6] = 0; [5:0] = VFID if PF - [6] = 1; [5:3] = 0; [2:0] = PFID); . [7] reserved. [8] - valid bit. In backward compatible mode - not used. The reset value match 2ports mode operation. in 4ports mode it should be reconfigured.
#define IGU_REG_FUNC_WITH_MORE_16_SB_6 0x130020UL //ACCESS:RW DataWidth:0x9 Description: The seventh function numbers that has more then 16 SBs. [6:0] - function number (if VF - [6] = 0; [5:0] = VFID if PF - [6] = 1; [5:3] = 0; [2:0] = PFID); . [7] reserved. [8] - valid bit. In backward compatible mode - not used. The reset value match 2ports mode operation. in 4ports mode it should be reconfigured.
#define IGU_REG_FUNC_WITH_MORE_16_SB_7 0x130024UL //ACCESS:RW DataWidth:0x9 Description: The eight function numbers that has more then 16 SBs. [6:0] - function number (if VF - [6] = 0; [5:0] = VFID if PF - [6] = 1; [5:3] = 0; [2:0] = PFID); . [7] reserved. [8] - valid bit. In backward compatible mode - not used. The reset value match 2ports mode operation. in 4ports mode it should be reconfigured.
#define IGU_REG_PXP_REQUESTER_INITIAL_CREDIT 0x130028UL //ACCESS:RW DataWidth:0x2 Description: PXP req credit. The max number of outstanding messages to the PXP request. The value can be one or two only.
#define IGU_REG_ATTN_MSG_PENDING 0x13002cUL //ACCESS:R DataWidth:0x8 Description: Debug: messages that wait to be sent; but didnt were sent yet. One bit for each PFID.
#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030UL //ACCESS:R DataWidth:0x4 Description: Debug: [3] - attention write done message is pending (0-no pending; 1-pending). [2:0] = PFID. Pending means attention message was sent; but write done didnt receive.
#define IGU_REG_COMMAND_DEBUG 0x130034UL //ACCESS:RW DataWidth:0x1 Description: Debug only: 0 - FIFO collects eight first error messages; 1 - FIFO collects eight last incoming command.
#define IGU_REG_STATISTIC_EN 0x130038UL //ACCESS:RW DataWidth:0x1 Description: enabling to collect data in the statistic_num_message_sent memory.
#define IGU_REG_TIMER_MASKING_VALUE 0x13003cUL //ACCESS:RW DataWidth:0x20 Description: Number of cycles the timer mask masking the IGU interrupt when a timer mask command arrives. Value must be bigger than 100.
#define IGU_REG_TIMER_MASK_ACTIVE 0x130040UL //ACCESS:R DataWidth:0x1 Description: when set the timer mask is active and the IGU does not send interrupts. When clear the timer mask is inactive.
#define IGU_REG_ERROR_HANDLING_FILTER 0x130044UL //ACCESS:RW DataWidth:0x9 Multi Field Register
#define IGU_ERROR_HANDLING_FILTER_REG_ERROR_HANDLING_FILTER_FID (0x7f<<0)
#define IGU_ERROR_HANDLING_FILTER_REG_ERROR_HANDLING_FILTER_FID_SIZE 0
#define IGU_ERROR_HANDLING_FILTER_REG_ERROR_HANDLING_RESERVED (0x1<<7)
#define IGU_ERROR_HANDLING_FILTER_REG_ERROR_HANDLING_RESERVED_SIZE 7
#define IGU_ERROR_HANDLING_FILTER_REG_ERROR_HANDLING_FILTER_EN (0x1<<8)
#define IGU_ERROR_HANDLING_FILTER_REG_ERROR_HANDLING_FILTER_EN_SIZE 8
#define IGU_REG_MAPPING_FSM 0x130048UL //ACCESS:R DataWidth:0x4 Description: Debug: mapping_fsm
#define IGU_REG_SB_CTRL_FSM 0x13004cUL //ACCESS:R DataWidth:0x4 Description: Debug: sb_ctrl_fsm
#define IGU_REG_INT_HANDLE_FSM 0x130050UL //ACCESS:R DataWidth:0x4 Description: Debug: int_handle_fsm
#define IGU_REG_ATTN_FSM 0x130054UL //ACCESS:R DataWidth:0x4 Description: Debug: attn_fsm
#define IGU_REG_PBA_FSM 0x130058UL //ACCESS:R DataWidth:0x4 Description: Debug: pba_fsm
#define IGU_REG_MSIX_MSG_BUILDER_FSM 0x13005cUL //ACCESS:R DataWidth:0x5 Description: Debug: msix_msg_builder_fsm
#define IGU_REG_MSIX_MEM_FSM 0x130060UL //ACCESS:R DataWidth:0x3 Description: Debug: msix_mem_fsm
#define IGU_REG_CTRL_FSM 0x130064UL //ACCESS:R DataWidth:0x5 Description: Debug: ctrl_fsm
#define IGU_REG_PXP_ARB_FSM 0x130068UL //ACCESS:R DataWidth:0x3 Description: Debug: pxp_arb_fsm
#define IGU_REG_DBG_SELECT 0x13006cUL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from HC to the DBG block) - for selecting a line to output to the DBG block.
#define IGU_REG_DBG_BYTE_ENABLE 0x130070UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from HC to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define IGU_REG_DBG_SHIFT 0x130074UL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from HC to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define IGU_REG_TM 0x130078UL //ACCESS:RW DataWidth:0x18 Multi Field Register
#define IGU_TM_REG_CAM_TM (0x3fff<<0)
#define IGU_TM_REG_CAM_TM_SIZE 0
#define IGU_TM_REG_SB_MEM_TM (0x1f<<14)
#define IGU_TM_REG_SB_MEM_TM_SIZE 14
#define IGU_TM_REG_MSIX_MEM_TM (0x1f<<19)
#define IGU_TM_REG_MSIX_MEM_TM_SIZE 19
#define IGU_REG_CAM_BIST_BDG_DATA 0x13007cUL //ACCESS:RW DataWidth:0x8 Description: Debug: for CAM bist uses
#define IGU_REG_CAM_BIST_STATUS 0x130080UL //ACCESS:R DataWidth:0x20 Description: Debug: for CAM bist uses
#define IGU_REG_CAM_BIST_EN 0x130084UL //ACCESS:RW DataWidth:0x1 Description: Debug: for CAM bist uses
#define IGU_REG_ECO_RESERVED 0x130088UL //ACCESS:RW DataWidth:0x8 Description: reserved for ECO if needed
#define IGU_REG_IGU_INT_STS 0x13008cUL //ACCESS:R DataWidth:0xb Description: Interrupt register #0 read
#define IGU_IGU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define IGU_IGU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define IGU_IGU_INT_STS_REG_CTRL_FIFO_ERROR_ERR (0x1<<1)
#define IGU_IGU_INT_STS_REG_CTRL_FIFO_ERROR_ERR_SIZE 1
#define IGU_IGU_INT_STS_REG_PXP_REQ_LENGTH_TOO_BIG (0x1<<2)
#define IGU_IGU_INT_STS_REG_PXP_REQ_LENGTH_TOO_BIG_SIZE 2
#define IGU_IGU_INT_STS_REG_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3)
#define IGU_IGU_INT_STS_REG_HOST_TRIES2ACCESS_PROD_UPD_SIZE 3
#define IGU_IGU_INT_STS_REG_VF_TRIES2ACC_ATTN_CMD (0x1<<4)
#define IGU_IGU_INT_STS_REG_VF_TRIES2ACC_ATTN_CMD_SIZE 4
#define IGU_IGU_INT_STS_REG_MME_BIGGER_THEN_5 (0x1<<5)
#define IGU_IGU_INT_STS_REG_MME_BIGGER_THEN_5_SIZE 5
#define IGU_IGU_INT_STS_REG_SB_INDEX_IS_NOT_VALID (0x1<<6)
#define IGU_IGU_INT_STS_REG_SB_INDEX_IS_NOT_VALID_SIZE 6
#define IGU_IGU_INT_STS_REG_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7)
#define IGU_IGU_INT_STS_REG_DURIN_INT_READ_WITH_SIMD_DIS_SIZE 7
#define IGU_IGU_INT_STS_REG_CMD_FID_NOT_MATCH (0x1<<8)
#define IGU_IGU_INT_STS_REG_CMD_FID_NOT_MATCH_SIZE 8
#define IGU_IGU_INT_STS_REG_SEGMENT_ACCESS_INVALID (0x1<<9)
#define IGU_IGU_INT_STS_REG_SEGMENT_ACCESS_INVALID_SIZE 9
#define IGU_IGU_INT_STS_REG_ATTN_PROD_ACC (0x1<<10)
#define IGU_IGU_INT_STS_REG_ATTN_PROD_ACC_SIZE 10
#define IGU_REG_IGU_INT_STS_CLR 0x130090UL //ACCESS:RC DataWidth:0xb Description: Interrupt register #0 read clear
#define IGU_IGU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define IGU_IGU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define IGU_IGU_INT_STS_CLR_REG_CTRL_FIFO_ERROR_ERR (0x1<<1)
#define IGU_IGU_INT_STS_CLR_REG_CTRL_FIFO_ERROR_ERR_SIZE 1
#define IGU_IGU_INT_STS_CLR_REG_PXP_REQ_LENGTH_TOO_BIG (0x1<<2)
#define IGU_IGU_INT_STS_CLR_REG_PXP_REQ_LENGTH_TOO_BIG_SIZE 2
#define IGU_IGU_INT_STS_CLR_REG_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3)
#define IGU_IGU_INT_STS_CLR_REG_HOST_TRIES2ACCESS_PROD_UPD_SIZE 3
#define IGU_IGU_INT_STS_CLR_REG_VF_TRIES2ACC_ATTN_CMD (0x1<<4)
#define IGU_IGU_INT_STS_CLR_REG_VF_TRIES2ACC_ATTN_CMD_SIZE 4
#define IGU_IGU_INT_STS_CLR_REG_MME_BIGGER_THEN_5 (0x1<<5)
#define IGU_IGU_INT_STS_CLR_REG_MME_BIGGER_THEN_5_SIZE 5
#define IGU_IGU_INT_STS_CLR_REG_SB_INDEX_IS_NOT_VALID (0x1<<6)
#define IGU_IGU_INT_STS_CLR_REG_SB_INDEX_IS_NOT_VALID_SIZE 6
#define IGU_IGU_INT_STS_CLR_REG_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7)
#define IGU_IGU_INT_STS_CLR_REG_DURIN_INT_READ_WITH_SIMD_DIS_SIZE 7
#define IGU_IGU_INT_STS_CLR_REG_CMD_FID_NOT_MATCH (0x1<<8)
#define IGU_IGU_INT_STS_CLR_REG_CMD_FID_NOT_MATCH_SIZE 8
#define IGU_IGU_INT_STS_CLR_REG_SEGMENT_ACCESS_INVALID (0x1<<9)
#define IGU_IGU_INT_STS_CLR_REG_SEGMENT_ACCESS_INVALID_SIZE 9
#define IGU_IGU_INT_STS_CLR_REG_ATTN_PROD_ACC (0x1<<10)
#define IGU_IGU_INT_STS_CLR_REG_ATTN_PROD_ACC_SIZE 10
#define IGU_REG_IGU_INT_STS_WR 0x130094UL //ACCESS:WR DataWidth:0xb Description: Interrupt register #0 bit set or clear
#define IGU_IGU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define IGU_IGU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define IGU_IGU_INT_STS_WR_REG_CTRL_FIFO_ERROR_ERR (0x1<<1)
#define IGU_IGU_INT_STS_WR_REG_CTRL_FIFO_ERROR_ERR_SIZE 1
#define IGU_IGU_INT_STS_WR_REG_PXP_REQ_LENGTH_TOO_BIG (0x1<<2)
#define IGU_IGU_INT_STS_WR_REG_PXP_REQ_LENGTH_TOO_BIG_SIZE 2
#define IGU_IGU_INT_STS_WR_REG_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3)
#define IGU_IGU_INT_STS_WR_REG_HOST_TRIES2ACCESS_PROD_UPD_SIZE 3
#define IGU_IGU_INT_STS_WR_REG_VF_TRIES2ACC_ATTN_CMD (0x1<<4)
#define IGU_IGU_INT_STS_WR_REG_VF_TRIES2ACC_ATTN_CMD_SIZE 4
#define IGU_IGU_INT_STS_WR_REG_MME_BIGGER_THEN_5 (0x1<<5)
#define IGU_IGU_INT_STS_WR_REG_MME_BIGGER_THEN_5_SIZE 5
#define IGU_IGU_INT_STS_WR_REG_SB_INDEX_IS_NOT_VALID (0x1<<6)
#define IGU_IGU_INT_STS_WR_REG_SB_INDEX_IS_NOT_VALID_SIZE 6
#define IGU_IGU_INT_STS_WR_REG_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7)
#define IGU_IGU_INT_STS_WR_REG_DURIN_INT_READ_WITH_SIMD_DIS_SIZE 7
#define IGU_IGU_INT_STS_WR_REG_CMD_FID_NOT_MATCH (0x1<<8)
#define IGU_IGU_INT_STS_WR_REG_CMD_FID_NOT_MATCH_SIZE 8
#define IGU_IGU_INT_STS_WR_REG_SEGMENT_ACCESS_INVALID (0x1<<9)
#define IGU_IGU_INT_STS_WR_REG_SEGMENT_ACCESS_INVALID_SIZE 9
#define IGU_IGU_INT_STS_WR_REG_ATTN_PROD_ACC (0x1<<10)
#define IGU_IGU_INT_STS_WR_REG_ATTN_PROD_ACC_SIZE 10
#define IGU_REG_IGU_INT_MASK 0x130098UL //ACCESS:RW DataWidth:0xb Description: Interrupt mask register #0 read/write
#define IGU_IGU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define IGU_IGU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define IGU_IGU_INT_MASK_REG_CTRL_FIFO_ERROR_ERR (0x1<<1)
#define IGU_IGU_INT_MASK_REG_CTRL_FIFO_ERROR_ERR_SIZE 1
#define IGU_IGU_INT_MASK_REG_PXP_REQ_LENGTH_TOO_BIG (0x1<<2)
#define IGU_IGU_INT_MASK_REG_PXP_REQ_LENGTH_TOO_BIG_SIZE 2
#define IGU_IGU_INT_MASK_REG_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3)
#define IGU_IGU_INT_MASK_REG_HOST_TRIES2ACCESS_PROD_UPD_SIZE 3
#define IGU_IGU_INT_MASK_REG_VF_TRIES2ACC_ATTN_CMD (0x1<<4)
#define IGU_IGU_INT_MASK_REG_VF_TRIES2ACC_ATTN_CMD_SIZE 4
#define IGU_IGU_INT_MASK_REG_MME_BIGGER_THEN_5 (0x1<<5)
#define IGU_IGU_INT_MASK_REG_MME_BIGGER_THEN_5_SIZE 5
#define IGU_IGU_INT_MASK_REG_SB_INDEX_IS_NOT_VALID (0x1<<6)
#define IGU_IGU_INT_MASK_REG_SB_INDEX_IS_NOT_VALID_SIZE 6
#define IGU_IGU_INT_MASK_REG_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7)
#define IGU_IGU_INT_MASK_REG_DURIN_INT_READ_WITH_SIMD_DIS_SIZE 7
#define IGU_IGU_INT_MASK_REG_CMD_FID_NOT_MATCH (0x1<<8)
#define IGU_IGU_INT_MASK_REG_CMD_FID_NOT_MATCH_SIZE 8
#define IGU_IGU_INT_MASK_REG_SEGMENT_ACCESS_INVALID (0x1<<9)
#define IGU_IGU_INT_MASK_REG_SEGMENT_ACCESS_INVALID_SIZE 9
#define IGU_IGU_INT_MASK_REG_ATTN_PROD_ACC (0x1<<10)
#define IGU_IGU_INT_MASK_REG_ATTN_PROD_ACC_SIZE 10
#define IGU_REG_IGU_PRTY_STS 0x13009cUL //ACCESS:R DataWidth:0xb Description: Parity register #0 read
#define IGU_IGU_PRTY_STS_REG_PARITY (0x1<<0)
#define IGU_IGU_PRTY_STS_REG_PARITY_SIZE 0
#define IGU_IGU_PRTY_STS_REG_CTRL_FIFO_ERROR_PARITY (0x1<<1)
#define IGU_IGU_PRTY_STS_REG_CTRL_FIFO_ERROR_PARITY_SIZE 1
#define IGU_IGU_PRTY_STS_REG_CAM_PARITY (0x1<<2)
#define IGU_IGU_PRTY_STS_REG_CAM_PARITY_SIZE 2
#define IGU_IGU_PRTY_STS_REG_SB_PARITY (0x1<<3)
#define IGU_IGU_PRTY_STS_REG_SB_PARITY_SIZE 3
#define IGU_IGU_PRTY_STS_REG_SB_BEFORE_INT_LOW_PARITY (0x1<<4)
#define IGU_IGU_PRTY_STS_REG_SB_BEFORE_INT_LOW_PARITY_SIZE 4
#define IGU_IGU_PRTY_STS_REG_MASK_LOW_PARITY (0x1<<5)
#define IGU_IGU_PRTY_STS_REG_MASK_LOW_PARITY_SIZE 5
#define IGU_IGU_PRTY_STS_REG_PBA_LOW_PARITY (0x1<<6)
#define IGU_IGU_PRTY_STS_REG_PBA_LOW_PARITY_SIZE 6
#define IGU_IGU_PRTY_STS_REG_MSIX_PARITY (0x1<<7)
#define IGU_IGU_PRTY_STS_REG_MSIX_PARITY_SIZE 7
#define IGU_IGU_PRTY_STS_REG_MSI_PARITY (0x1<<8)
#define IGU_IGU_PRTY_STS_REG_MSI_PARITY_SIZE 8
#define IGU_IGU_PRTY_STS_REG_ATTN_ADDR_PARITY (0x1<<9)
#define IGU_IGU_PRTY_STS_REG_ATTN_ADDR_PARITY_SIZE 9
#define IGU_IGU_PRTY_STS_REG_STATISTIC_PARITY (0x1<<10)
#define IGU_IGU_PRTY_STS_REG_STATISTIC_PARITY_SIZE 10
#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0UL //ACCESS:RC DataWidth:0xb Description: Parity register #0 read clear
#define IGU_IGU_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define IGU_IGU_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define IGU_IGU_PRTY_STS_CLR_REG_CTRL_FIFO_ERROR_PARITY (0x1<<1)
#define IGU_IGU_PRTY_STS_CLR_REG_CTRL_FIFO_ERROR_PARITY_SIZE 1
#define IGU_IGU_PRTY_STS_CLR_REG_CAM_PARITY (0x1<<2)
#define IGU_IGU_PRTY_STS_CLR_REG_CAM_PARITY_SIZE 2
#define IGU_IGU_PRTY_STS_CLR_REG_SB_PARITY (0x1<<3)
#define IGU_IGU_PRTY_STS_CLR_REG_SB_PARITY_SIZE 3
#define IGU_IGU_PRTY_STS_CLR_REG_SB_BEFORE_INT_LOW_PARITY (0x1<<4)
#define IGU_IGU_PRTY_STS_CLR_REG_SB_BEFORE_INT_LOW_PARITY_SIZE 4
#define IGU_IGU_PRTY_STS_CLR_REG_MASK_LOW_PARITY (0x1<<5)
#define IGU_IGU_PRTY_STS_CLR_REG_MASK_LOW_PARITY_SIZE 5
#define IGU_IGU_PRTY_STS_CLR_REG_PBA_LOW_PARITY (0x1<<6)
#define IGU_IGU_PRTY_STS_CLR_REG_PBA_LOW_PARITY_SIZE 6
#define IGU_IGU_PRTY_STS_CLR_REG_MSIX_PARITY (0x1<<7)
#define IGU_IGU_PRTY_STS_CLR_REG_MSIX_PARITY_SIZE 7
#define IGU_IGU_PRTY_STS_CLR_REG_MSI_PARITY (0x1<<8)
#define IGU_IGU_PRTY_STS_CLR_REG_MSI_PARITY_SIZE 8
#define IGU_IGU_PRTY_STS_CLR_REG_ATTN_ADDR_PARITY (0x1<<9)
#define IGU_IGU_PRTY_STS_CLR_REG_ATTN_ADDR_PARITY_SIZE 9
#define IGU_IGU_PRTY_STS_CLR_REG_STATISTIC_PARITY (0x1<<10)
#define IGU_IGU_PRTY_STS_CLR_REG_STATISTIC_PARITY_SIZE 10
#define IGU_REG_IGU_PRTY_STS_WR 0x1300a4UL //ACCESS:WR DataWidth:0xb Description: Parity register #0 bit set or clear
#define IGU_IGU_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define IGU_IGU_PRTY_STS_WR_REG_PARITY_SIZE 0
#define IGU_IGU_PRTY_STS_WR_REG_CTRL_FIFO_ERROR_PARITY (0x1<<1)
#define IGU_IGU_PRTY_STS_WR_REG_CTRL_FIFO_ERROR_PARITY_SIZE 1
#define IGU_IGU_PRTY_STS_WR_REG_CAM_PARITY (0x1<<2)
#define IGU_IGU_PRTY_STS_WR_REG_CAM_PARITY_SIZE 2
#define IGU_IGU_PRTY_STS_WR_REG_SB_PARITY (0x1<<3)
#define IGU_IGU_PRTY_STS_WR_REG_SB_PARITY_SIZE 3
#define IGU_IGU_PRTY_STS_WR_REG_SB_BEFORE_INT_LOW_PARITY (0x1<<4)
#define IGU_IGU_PRTY_STS_WR_REG_SB_BEFORE_INT_LOW_PARITY_SIZE 4
#define IGU_IGU_PRTY_STS_WR_REG_MASK_LOW_PARITY (0x1<<5)
#define IGU_IGU_PRTY_STS_WR_REG_MASK_LOW_PARITY_SIZE 5
#define IGU_IGU_PRTY_STS_WR_REG_PBA_LOW_PARITY (0x1<<6)
#define IGU_IGU_PRTY_STS_WR_REG_PBA_LOW_PARITY_SIZE 6
#define IGU_IGU_PRTY_STS_WR_REG_MSIX_PARITY (0x1<<7)
#define IGU_IGU_PRTY_STS_WR_REG_MSIX_PARITY_SIZE 7
#define IGU_IGU_PRTY_STS_WR_REG_MSI_PARITY (0x1<<8)
#define IGU_IGU_PRTY_STS_WR_REG_MSI_PARITY_SIZE 8
#define IGU_IGU_PRTY_STS_WR_REG_ATTN_ADDR_PARITY (0x1<<9)
#define IGU_IGU_PRTY_STS_WR_REG_ATTN_ADDR_PARITY_SIZE 9
#define IGU_IGU_PRTY_STS_WR_REG_STATISTIC_PARITY (0x1<<10)
#define IGU_IGU_PRTY_STS_WR_REG_STATISTIC_PARITY_SIZE 10
#define IGU_REG_IGU_PRTY_MASK 0x1300a8UL //ACCESS:RW DataWidth:0xb Description: Parity mask register #0 read/write
#define IGU_IGU_PRTY_MASK_REG_PARITY (0x1<<0)
#define IGU_IGU_PRTY_MASK_REG_PARITY_SIZE 0
#define IGU_IGU_PRTY_MASK_REG_CTRL_FIFO_ERROR_PARITY (0x1<<1)
#define IGU_IGU_PRTY_MASK_REG_CTRL_FIFO_ERROR_PARITY_SIZE 1
#define IGU_IGU_PRTY_MASK_REG_CAM_PARITY (0x1<<2)
#define IGU_IGU_PRTY_MASK_REG_CAM_PARITY_SIZE 2
#define IGU_IGU_PRTY_MASK_REG_SB_PARITY (0x1<<3)
#define IGU_IGU_PRTY_MASK_REG_SB_PARITY_SIZE 3
#define IGU_IGU_PRTY_MASK_REG_SB_BEFORE_INT_LOW_PARITY (0x1<<4)
#define IGU_IGU_PRTY_MASK_REG_SB_BEFORE_INT_LOW_PARITY_SIZE 4
#define IGU_IGU_PRTY_MASK_REG_MASK_LOW_PARITY (0x1<<5)
#define IGU_IGU_PRTY_MASK_REG_MASK_LOW_PARITY_SIZE 5
#define IGU_IGU_PRTY_MASK_REG_PBA_LOW_PARITY (0x1<<6)
#define IGU_IGU_PRTY_MASK_REG_PBA_LOW_PARITY_SIZE 6
#define IGU_IGU_PRTY_MASK_REG_MSIX_PARITY (0x1<<7)
#define IGU_IGU_PRTY_MASK_REG_MSIX_PARITY_SIZE 7
#define IGU_IGU_PRTY_MASK_REG_MSI_PARITY (0x1<<8)
#define IGU_IGU_PRTY_MASK_REG_MSI_PARITY_SIZE 8
#define IGU_IGU_PRTY_MASK_REG_ATTN_ADDR_PARITY (0x1<<9)
#define IGU_IGU_PRTY_MASK_REG_ATTN_ADDR_PARITY_SIZE 9
#define IGU_IGU_PRTY_MASK_REG_STATISTIC_PARITY (0x1<<10)
#define IGU_IGU_PRTY_MASK_REG_STATISTIC_PARITY_SIZE 10
#define IGU_REG_INTERRUPT_STATUS 0x130100UL //ACCESS:R DataWidth:0x4 Description: Debug: Interrupt status (active high). PF0 to PF3
#define IGU_REG_INTERRUPT_STATUS_SIZE 1
#define IGU_REG_TRAILING_EDGE_LATCH 0x130104UL //ACCESS:RW DataWidth:0x10 SPLIT:8 Description: Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding attention signals that comes from the AEU
#define IGU_REG_TRAILING_EDGE_LATCH_SIZE 1
#define IGU_REG_ATTENTION_ACK_BITS 0x130108UL //ACCESS:RW DataWidth:0x10 SPLIT:8 Description: 16 bit register with the attention ACK values.These are the same bits as in the attention message.
#define IGU_REG_ATTENTION_ACK_BITS_SIZE 1
#define IGU_REG_ATTENTION_BIT_STATUS_INDEX 0x13010cUL //ACCESS:RW DataWidth:0x10 SPLIT:8 Description: Value of attention bit status index (posted toward the driver as attention bit status index). This are the same value as in the attention message.
#define IGU_REG_ATTENTION_BIT_STATUS_INDEX_SIZE 1
#define IGU_REG_ATTENTION_BITS 0x130110UL //ACCESS:RW DataWidth:0x10 SPLIT:8 Description: 16 bit register with the latched attention values. These are the same bits as in the attention message.
#define IGU_REG_ATTENTION_BITS_SIZE 1
#define IGU_REG_ATTENTION_SIGNAL_P0_STATUS 0x130114UL //ACCESS:R DataWidth:0x10 Description: attention signal status. Reflects the current value of the attention signals from the MISC-AEU port0
#define IGU_REG_ATTENTION_SIGNAL_P0_STATUS_SIZE 1
#define IGU_REG_ATTENTION_SIGNAL_P1_STATUS 0x130118UL //ACCESS:R DataWidth:0x10 Description: attention signal status. Reflects the current value of the attention signals from the MISC-AEU port1
#define IGU_REG_ATTENTION_SIGNAL_P1_STATUS_SIZE 1
#define IGU_REG_ATTN_MSG_ADDR_H 0x13011cUL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: For attention message: Attention bit destination address 32 MSB
#define IGU_REG_ATTN_MSG_ADDR_H_SIZE 1
#define IGU_REG_ATTN_MSG_ADDR_L 0x130120UL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: For attention message: Attention bit destination address 32 LSB. Two Lsbit must be zero.
#define IGU_REG_ATTN_MSG_ADDR_L_SIZE 1
#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124UL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: If block is disabled this register will return zero. If the last command sent to the command_reg_ctrl the 32LSB read value will be written here. If address is PBA: 32 LSB of PBA register (one in each bit means PBA message wasnt sent due to mask). If address = SIMD with mask 64b/32LSB: 32 LSB of the during interrupt register (one in each bit means the appropriate SB is asserted. Every bit that is set will be masked in the mask bit register). If address = SIMD with mask 32MSB: this register will return zero. If address = SIMD without mask 64b: 32 LSB of the during interrupt register (one in each bit means the appropriate SB is asserted). If the command sent to the command_reg_ctrl is write command the data in this register will be used as follows: If address = interrupt acknowledge register: d31 - d27- Reserved; d26:d25 - enable/disable interrupt for status block (0=Disable interrupt for status block; 1=Enable interrupt for status block; 2 or 3 - NOP); d24 - update/nop status index (0 = NOP; 1 - update); d23:d21 - segment access for PF only - 0 - regular; 1 - default; 2 - ATTN; 3-7 - reserved. For VF must be zero; d20 - Reserved; d19:d0 - status block consumer index. If address = producer update: d31 - Cleanup bit command (0 - Nop; 1 - cleanup); d30 - cleanup set/clr - 0-clear 1 - set; d29:d28 - Cleanup type (0-ustorm 0; 1-ustorm1; 2-cstorm0; 3-cstorm1); d27- Reserved; d26:d25 - enable/disable interrupt for status block (0=Disable interrupt for status block; 1=Enable interrupt for status block; 2 or 3 - NOP); d24 - update/nop status index (0 = NOP; 1 - update); d23:d21 - segment access for PF only - 0 - regular; 1 - default; 2 - ATTN; 3-7 - reserved. For VF must be zero; d20 - Reserved; d19:d0 - status block producer index. If address = attention update: d31:d16 - reserved; d15:d0 - new attention ack register value. If address = attention set: d31:d16 - reserved; Attention ack new value = attention ack old value | d15:d0. If address = attention clear: d31:d16 - reserved; Attention ack new value = attention ack old value & d15:d0.
#define IGU_REG_COMMAND_REG_32LSB_DATA_SIZE 1
#define IGU_REG_COMMAND_REG_32MSB_DATA 0x130128UL //ACCESS:WB_R DataWidth:0x20 SPLIT:8 Description: Read only register. If block is disable this register will return zero. If the last command sent to the command_reg_ctrl the 32MSB read value will be written here. If address is PBA: 32 MSB of PBA register (one in each bit means PBA message wasnt sent due to mask). If address = SIMD with mask 64b/32MSB: 32 MSB of the during interrupt register (one in each bit means the appropriate SB is asserted. Every bit that is set will be masked in the mask bit register). If address = SIMD with mask 32LSB: this register will return zero. If address = SIMD without mask 64b: 32 MSB of the during interrupt register (one in each bit means the appropriate SB is asserted).
#define IGU_REG_COMMAND_REG_32MSB_DATA_SIZE 1
#define IGU_REG_COMMAND_REG_CTRL 0x13012cUL //ACCESS:W DataWidth:0x15 SPLIT:8 Description: [11:0] - PXP BAR address; [18:12] - FID (if VF - [18] = 0; [17:12] = VF number; if PF - [18] = 1; [17:15] = 0; [14:12] = PFID); [19] - reserved; [20] command type - 0-read; 1-wr. When writing to this register the command will be executed. On write command the 32 LSB command should be written first (to the command_reg_32lsb_data register) and only then this register. PXP BAR address field: 0x000 - 0x1FF - reserved; 0x200 - PBA ; 0x201 - 0x3FF - reserved; 0x400 - 0x487 - interrupt ack register; 0x488-0x4FF - reserved; 0x500 - 0x587 - producer update; 0x588-0x59F - reserved; 0x5A0 - Attention bits update register; 0x5A1 - Attention bits set register; 0x5A2 - Attention bits clear register; 0x5A3 - SIMD with mask 64b; 0x5A4 - SIMD with mask 32 LSB; 0x5A5 - SIMD with mask 32 MSB; 0x5A6 - SIMD without mask 64b; 0x5A7 - 0x5FF - reserved. The following addresses are write only: interrupt ack register; producer update; Attention bits update register; Attention bits set register; Attention bits clear register. The following addresses are read only: PBA; SIMD with mask 64b; SIMD with mask 32 LSB; SIMD with mask 32 MSB; SIMD without mask 64b. The read data is copied to command_reg_32lsb_data and command_reg_32msb_data registers. On read from reserved addresses the read data will be 0.
#define IGU_REG_COMMAND_REG_CTRL_SIZE 1
#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130UL //ACCESS:R DataWidth:0x1 Description: data availble for error memory. If this bit is clear do not red from error_handling_memory.
#define IGU_REG_ERROR_HANDLING_DATA_VALID_SIZE 1
#define IGU_REG_LEADING_EDGE_LATCH 0x130134UL //ACCESS:RW DataWidth:0x10 SPLIT:8 Description: Attention signals leading edge. attn bit condition monitoring; each bit that is set will lock a change from 0 to 1 in the corresponding attention signals that comes from the AEU
#define IGU_REG_LEADING_EDGE_LATCH_SIZE 1
#define IGU_REG_PBA_STATUS_LSB 0x130138UL //ACCESS:RW DataWidth:0x20 SPLIT:72 Description: 32 lsb of PBA register. 0 - PBA clear 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or vector). The bits order is according to the vector number of each SB in that function. For PF bit 0 is the default SB. bits 31:16 are valid only for functions that appears in func_with_more_16_sb_0..7 registers.
#define IGU_REG_PBA_STATUS_LSB_SIZE 1
#define IGU_REG_PBA_STATUS_MSB 0x13013cUL //ACCESS:RW DataWidth:0x20 SPLIT:72 Description: 32 msb of PBA register. 0 - PBA clear 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or vector). The bits order is according to the vector number of each SB in that function. For PF bit 0 is the default SB.This register is valid only for functions that appears in func_with_more_16_sb_0..7 registers
#define IGU_REG_PBA_STATUS_MSB_SIZE 1
#define IGU_REG_PCI_PF_MSI_EN 0x130140UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: PF MSI enable status. shadow of PCI config register
#define IGU_REG_PCI_PF_MSI_EN_SIZE 1
#define IGU_REG_PCI_PF_MSIX_EN 0x130144UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: PF MSIX enable status. shadow of PCI config register
#define IGU_REG_PCI_PF_MSIX_EN_SIZE 1
#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: PF MSIX function mask status. shadow of PCI config register. 0 - unmasked; 1 - masked
#define IGU_REG_PCI_PF_MSIX_FUNC_MASK_SIZE 1
#define IGU_REG_PCI_VF_MSIX_EN 0x13014cUL //ACCESS:RW DataWidth:0x1 SPLIT:64 Description: VF MSIX enable status. shadow of PCI config register
#define IGU_REG_PCI_VF_MSIX_EN_SIZE 1
#define IGU_REG_PCI_VF_MSIX_FUNC_MASK 0x130150UL //ACCESS:RW DataWidth:0x1 SPLIT:64 Description: VF MSIX function mask status shadow of PCI config register. 0 - unmasked; 1 - masked
#define IGU_REG_PCI_VF_MSIX_FUNC_MASK_SIZE 1
#define IGU_REG_PF_CONFIGURATION 0x130154UL //ACCESS:RW DataWidth:0x6 SPLIT:8 Description: d0 - function enable; d1 - MSI/MSIX enable; d2 - INT enable; d3 - attention enabe; d4 - single ISR mode enable; d5 simd all ones mode - If clear (reset value):If the result of SB_before_mask & ~mask is 0xFFFF_FFFF then the read result will be 0x7FFF_FFFF and the mask will be also 0x7FFF_FFFF. Therefore the interrupt is not de-asserted (the MSB SB is asserted and unmasked). And on the next read from SIMD with mask the result will be 0x8000_0000 and only now the interrupt will be de-asserted. If set: If the result of SB_before_mask & ~mask is 0xFFFF_FFFF then the read result will be 0x7FFF_FFFF but the mask will be 0xFFFF_FFFF. Therefore the interrupt is de-asserted. And on the next read from SIMD with mask the result will be 0x0.
#define IGU_REG_PF_CONFIGURATION_SIZE 1
#define IGU_REG_RESET_MEMORIES 0x130158UL //ACCESS:RW DataWidth:0x6 Description: Write one for each bit will reset the appropriate memory. When the memory reset finished the appropriate bit will be clear. Bit 0 - mapping memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3 - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics;
#define IGU_REG_RESET_MEMORIES_SIZE 1
#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015cUL //ACCESS:RW DataWidth:0x20 SPLIT:72 Description: 32 lsb of SB interrupt before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits order is according to the vector number of each SB in that function. For PF bit 0 is the default SB. bits 31:16 are valid only for functions that appears in func_with_more_16_sb_0..7 registers.
#define IGU_REG_SB_INT_BEFORE_MASK_LSB_SIZE 1
#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160UL //ACCESS:RW DataWidth:0x20 SPLIT:72 Description: 32 msb of SB interrupt before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits order is according to the vector number of each SB in that function. For PF bit 0 is the default SB. This register is valid only for functions that appears in func_with_more_16_sb_0..7 registers
#define IGU_REG_SB_INT_BEFORE_MASK_MSB_SIZE 1
#define IGU_REG_SB_MASK_LSB 0x130164UL //ACCESS:RW DataWidth:0x20 SPLIT:72 Description: 32 lsb of SB mask register. 0 - unmased. 1 - masked. The bits order is according to the vector number of each SB in that function. For PF bit 0 is the default SB. bits 31:16 are valid only for functions that appears in func_with_more_16_sb_0..7 registers.
#define IGU_REG_SB_MASK_LSB_SIZE 1
#define IGU_REG_SB_MASK_MSB 0x130168UL //ACCESS:RW DataWidth:0x20 SPLIT:72 Description: 32 msb of SB mask register. 0 - unmased. 1 - masked. The bits order is according to the vector number of each SB in that function. For PF bit 0 is the default SB. This register is valid only for functions that appears in func_with_more_16_sb_0..7 registers
#define IGU_REG_SB_MASK_MSB_SIZE 1
#define IGU_REG_SILENT_DROP 0x13016cUL //ACCESS:RW DataWidth:0x10 Description: Number of command that were dropped without causing an interrupt due to: read access for WO BAR address; or write access for RO BAR address or any access for reserved address or PCI function error is set and address is not MSIX; PBA or cleanup
#define IGU_REG_SILENT_DROP_SIZE 1
#define IGU_REG_VF_CONFIGURATION 0x130170UL //ACCESS:RW DataWidth:0x8 SPLIT:64 Description: d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enable; d7:d5 parent PF
#define IGU_REG_VF_CONFIGURATION_SIZE 1
#define IGU_REG_ERROR_HANDLING_MEMORY 0x130178UL //ACCESS:WB_R DataWidth:0x40 Description: Do not read from this memory if error_handling_data_valid register is zero. The data is collected in according to the command_debug value. if command_debug is clear it holds the first 8 error commands as follows: {wr_data[31:0]; cmd_addr[12:0]; error_type_d[3:0]; cmd_fid[6:0]; cmd_source; error_source[1:0]; cmd_func_err; cmd_length[2:0]; cmd_wr_n_rd} . if command_debug is set it holds the last 8 commands to the IGU (with and without error) as follows: {wr_data[31:0]; cmd_addr[15:0]; 1b0; cmd_fid[6:0]; cmd_source; error_source[1:0]; cmd_func_err; cmd_length[2:0]; cmd_wr_n_rd}. cmd_source - the source field in PXP command. VFID is encoded: PF? {4b1000; PFID} : {1b0; VFID}. error_source[1:0] - pxp - 0; grc - 1; attn - 2. cmd_func_err - func_err field in PXP command. cmd_length[2:0] - length in PXP command. cmd_wr_n_rd: 0 - read; 1 - write. error_type_d[3:0] :1 - length >1; 2 - command to disable function; 3 - VF command to attn bits. 4 - host tries to update prod. 5 - during read from MIMD function; 6 -segment not match; 7 - attn prod upd; 9 - SB index not valid; 10 - FID + vector num not found; 11 - FID not match; 12 - VF tries to access attn command.
#define IGU_REG_ERROR_HANDLING_MEMORY_SIZE 2
#define IGU_REG_MSI_MEMORY 0x130180UL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: addres 0 - MSI address low (two Lsbit are zero). Address 1 - MSI address high. Address 2 - [15:0] - MSI data; [18:16] MME; [31:19] Reserved
#define IGU_REG_MSI_MEMORY_SIZE 3
#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200UL //ACCESS:WB_R DataWidth:0x20 Description: Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer command. Data valid only in addresses 0-4. all the rest are zero.
#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP_SIZE 5
#define IGU_REG_CSTORM_TYPE_1_SB_CLEANUP 0x130280UL //ACCESS:WB_R DataWidth:0x20 Description: Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer command. Data valid only in addresses 0-4. all the rest are zero.
#define IGU_REG_CSTORM_TYPE_1_SB_CLEANUP_SIZE 5
#define IGU_REG_PENDING_BITS_STATUS 0x130300UL //ACCESS:WB_R DataWidth:0x20 Description: Each bit represent the pending bits status for that SB. 0 = no pending; 1 = pending. Pendings means interrupt was asserted; and write done was not received. Data valid only in addresses 0-4. all the rest are zero.
#define IGU_REG_PENDING_BITS_STATUS_SIZE 5
#define IGU_REG_USTORM_TYPE_0_SB_CLEANUP 0x130380UL //ACCESS:WB_R DataWidth:0x20 Description: Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer command. Data valid only in addresses 0-4. all the rest are zero.
#define IGU_REG_USTORM_TYPE_0_SB_CLEANUP_SIZE 5
#define IGU_REG_USTORM_TYPE_1_SB_CLEANUP 0x130400UL //ACCESS:WB_R DataWidth:0x20 Description: Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer command. Data valid only in addresses 0-4. all the rest are zero.
#define IGU_REG_USTORM_TYPE_1_SB_CLEANUP_SIZE 5
#define IGU_REG_WRITE_DONE_PENDING 0x130480UL //ACCESS:WB_R DataWidth:0x20 Description: Each bit represent write done pending bits status for that SB (MSI/MSIX message was sent and write done was not received yet). 0 = clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero.
#define IGU_REG_WRITE_DONE_PENDING_SIZE 5
#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800UL //ACCESS:RW DataWidth:0xa Description: Number of MSI/MSIX/ATTN messages sent for the function: 0-63 - number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per PF; 68-71 number of ATTN messages per PF
#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT_SIZE 72
#define IGU_REG_MAPPING_MEMORY 0x131000UL //ACCESS:RW DataWidth:0xe Description: mapping CAM; relevant for E2 operating mode only. [0] - valid. [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number);
#define IGU_REG_MAPPING_MEMORY_SIZE 136
#define IGU_REG_PROD_CONS_MEMORY 0x132000UL //ACCESS:RW DataWidth:0x14 Description: producers only. E2 mode: address 0-135 match to the mapping memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod; 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode - In backward compatible mode; for non default SB; each even line in the memory holds the U producer and each odd line hold the C producer. The first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 producers are for the DSB for each PF. each PF has five segments (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods;
#define IGU_REG_PROD_CONS_MEMORY_SIZE 148
#define IGU_REG_MSIX_MEMORY 0x134000UL //ACCESS:WB DataWidth:0x61 Description: [63:0] - MSIX message address (bit [1:0] are always zero); [95:64] - MSIX message data; [96] - MSIX mask bit (0 - unmasked; 1 - masked).Reset value (after reset_memories was set) is MSIX address = 0; MSIX data = 0; MSIX mask bit=1
#define IGU_REG_MSIX_MEMORY_SIZE 544
#define IGU_REG_IGU_UNUSED_EMPTY_0 0x1300acUL //ACCESS:R DataWidth:0x20 Unused empty space
#define IGU_REG_IGU_UNUSED_EMPTY_0_SIZE 21
#define IGU_REG_IGU_UNUSED_EMPTY_1 0x130174UL //ACCESS:R DataWidth:0x20 Unused empty space
#define IGU_REG_IGU_UNUSED_EMPTY_1_SIZE 1
#define IGU_REG_IGU_UNUSED_EMPTY_2 0x130190UL //ACCESS:R DataWidth:0x20 Unused empty space
#define IGU_REG_IGU_UNUSED_EMPTY_2_SIZE 28
#define IGU_REG_IGU_UNUSED_EMPTY_3 0x130500UL //ACCESS:R DataWidth:0x20 Unused empty space
#define IGU_REG_IGU_UNUSED_EMPTY_3_SIZE 192
#define IGU_REG_IGU_UNUSED_EMPTY_4 0x130c00UL //ACCESS:R DataWidth:0x20 Unused empty space
#define IGU_REG_IGU_UNUSED_EMPTY_4_SIZE 256
#define IGU_REG_IGU_UNUSED_EMPTY_5 0x133000UL //ACCESS:R DataWidth:0x20 Unused empty space
#define IGU_REG_IGU_UNUSED_EMPTY_5_SIZE 1024
#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 0; this will set/clr bit 94 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 1; this will set/clr bit 95 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 2; this will set/clr bit 96 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00cUL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 3; this will set/clr bit 97 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 4; this will set/clr bit 98 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 5; this will set/clr bit 99 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 6; this will set/clr bit 100 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01cUL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 7; this will set/clr bit 101 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 8; this will set/clr bit 102 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 9; this will set/clr bit 103 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 10; this will set/clr bit 104 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02cUL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 11; this will set/clr bit 105 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 12; this will set/clr bit 106 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_13 0xa034UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 13; this will set/clr bit 107 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_14 0xa038UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 14; this will set/clr bit 108 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_15 0xa03cUL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 15; this will set/clr bit 109 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_16 0xa040UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 16; this will set/clr bit 110 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_17 0xa044UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 17; this will set/clr bit 111 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_18 0xa048UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 18; this will set/clr bit 112 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04cUL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 19; this will set/clr bit 113 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 20; this will set/clr bit 114 in the aeu 128 bit vector
#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 21; this will set/clr bit 115 in the aeu 128 bit vector
#define MISC_REG_AEU_EVENT_ENABLE 0xa058UL //ACCESS:RW DataWidth:0x1 Description: Event_enable control; when this bit is clear the event enable toward the MCP is masked.
#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060UL //ACCESS:RW DataWidth:0xa Description: [7:0] = mask 8 attention output signals toward IGU function0; [9:8] = reserved. 0 = mask; 1 = unmask
#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064UL //ACCESS:RW DataWidth:0xa Description: [7:0] = mask 8 attention output signals toward IGU function1; [9:8] = reserved. 0 = mask; 1 = unmask
#define MISC_REG_AEU_MASK_ATTN_MCP 0xa068UL //ACCESS:RW DataWidth:0x8 Description: Masks 8 attention output signals toward MCP. Zero = mask; one = unmask
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 0 output0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 0 output0. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 0 output0. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 0 output0.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 0 output1. Mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 0 output1. Mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 0 output1. Mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_1 0xa088UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 0 output1.Mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 0 output2. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_2 0xa090UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 0 output2. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_2 0xa094UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 0 output2. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 0 output2.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 0 output3. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_3 0xa0a0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 0 output3. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_3 0xa0a4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 0 output3. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_3 0xa0a8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 0 output3.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_4 0xa0acUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 0 output4. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_4 0xa0b0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 0 output4. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_4 0xa0b4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 0 output4. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 0 output4.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bcUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 0 output5. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_5 0xa0c0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 0 output5. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_5 0xa0c4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 0 output5. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 0 output5.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0ccUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 0 output6. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_6 0xa0d0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 0 output6. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_6 0xa0d4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 0 output6. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 0 output6.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dcUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 0 output7. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_7 0xa0e0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 0 output7. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_7 0xa0e4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 0 output7. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 0 output7.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ecUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for close the gate nig. Mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for close the gate nig. Mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for close the gate nig. Mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for close the gate nig. Mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fcUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for close the gate pxp. Mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for close the gate pxp. Mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for close the gate pxp. Mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 1 output0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 1 output0. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 1 output0. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 1 output0.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 1 output1. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 1 output1. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 1 output1. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_1 0xa128UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 1 output1.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 1 output2. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_2 0xa130UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 1 output2. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_2 0xa134UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 1 output2. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 1 output2.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 1 output3. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_3 0xa140UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 1 output3. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_3 0xa144UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 1 output3. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_3 0xa148UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 1 output3.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_4 0xa14cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 1 output4. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_4 0xa150UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 1 output4. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_4 0xa154UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 1 output4. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 1 output4.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 1 output5. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_5 0xa160UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 1 output5. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_5 0xa164UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 1 output5. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 1 output5.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 1 output6. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_6 0xa170UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 1 output6. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_6 0xa174UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 1 output6. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 1 output6.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for function 1 output7. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_7 0xa180UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for function 1 output7. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_7 0xa184UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for function 1 output7. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for function 0 output7.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18cUL //ACCESS:RW DataWidth:0x20 Description: unused
#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190UL //ACCESS:RW DataWidth:0x20 Description: unused
#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194UL //ACCESS:RW DataWidth:0x20 Description: unused
#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198UL //ACCESS:RW DataWidth:0x20 Description: unused
#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for close the gate system kill. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for close the gate system kill. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for close the gate system kill. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for close the gate system kill.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0 0xa1acUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for mcp output0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_MCP_OUT_0 0xa1b0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for mcp output0. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_MCP_OUT_0 0xa1b4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for mcp output0. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_MCP_OUT_0 0xa1b8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for mcp output0.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_MCP_OUT_1 0xa1bcUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for mcp output1. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_MCP_OUT_1 0xa1c0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for mcp output1. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_MCP_OUT_1 0xa1c4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for mcp output1. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_MCP_OUT_1 0xa1c8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for mcp output1.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_MCP_OUT_2 0xa1ccUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for mcp output2. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_MCP_OUT_2 0xa1d0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for mcp output2. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_MCP_OUT_2 0xa1d4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for mcp output2. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_MCP_OUT_2 0xa1d8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for mcp output2.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_MCP_OUT_3 0xa1dcUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for mcp output3. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_MCP_OUT_3 0xa1e0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for mcp output3. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_MCP_OUT_3 0xa1e4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for mcp output3. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_MCP_OUT_3 0xa1e8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for mcp output3.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_MCP_OUT_4 0xa1ecUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for mcp output4. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_MCP_OUT_4 0xa1f0UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for mcp output4. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_MCP_OUT_4 0xa1f4UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for mcp output4. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_MCP_OUT_4 0xa1f8UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for mcp output4.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_MCP_OUT_5 0xa1fcUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for mcp output5. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_MCP_OUT_5 0xa200UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for mcp output5. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_MCP_OUT_5 0xa204UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for mcp output5. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_MCP_OUT_5 0xa208UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for mcp output5.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_MCP_OUT_6 0xa20cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for mcp output6. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_MCP_OUT_6 0xa210UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for mcp output6. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_MCP_OUT_6 0xa214UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for mcp output6. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_MCP_OUT_6 0xa218UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for mcp output6.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_ENABLE1_MCP_OUT_7 0xa21cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for enabling the output for mcp output7. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_ENABLE2_MCP_OUT_7 0xa220UL //ACCESS:RW DataWidth:0x20 Description: second 32b for enabling the output for mcp output7. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_ENABLE3_MCP_OUT_7 0xa224UL //ACCESS:RW DataWidth:0x20 Description: third 32b for enabling the output for mcp output7. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_ENABLE4_MCP_OUT_7 0xa228UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for enabling the output for mcp output7.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for inverting the input for function 0; for each bit: 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230UL //ACCESS:RW DataWidth:0x20 Description: second 32b for inverting the input for function 0; for each bit: 0= do not invert; 1= invert. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_INVERTER_3_FUNC_0 0xa234UL //ACCESS:RW DataWidth:0x20 Description: third 32b for inverting the input for function 0; for each bit: 0= do not invert; 1= invert. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_INVERTER_4_FUNC_0 0xa238UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for inverting the input for function 0; for each bit: 0= do not invert; 1= invert.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for inverting the input for function 1; for each bit: 0= do not invert; 1= invert. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240UL //ACCESS:RW DataWidth:0x20 Description: second 32b for inverting the input for function 1; for each bit: 0= do not invert; 1= invert. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_INVERTER_3_FUNC_1 0xa244UL //ACCESS:RW DataWidth:0x20 Description: third 32b for inverting the input for function 1; for each bit: 0= do not invert; 1= invert. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_INVERTER_4_FUNC_1 0xa248UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for inverting the input for function 1; for each bit: 0= do not invert; 1= invert.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_INVERTER_1_MCP 0xa24cUL //ACCESS:RW DataWidth:0x20 Description: first 32b for inverting the input for mcp; for each bit: 0= do not invert; 1= invert. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_INVERTER_2_MCP 0xa250UL //ACCESS:RW DataWidth:0x20 Description: second 32b for inverting the input for mcp; for each bit: 0= do not invert; 1= invert. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_INVERTER_3_MCP 0xa254UL //ACCESS:RW DataWidth:0x20 Description: third 32b for inverting the input for mcp; for each bit: 0= do not invert; 1= invert. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_INVERTER_4_MCP 0xa258UL //ACCESS:RW DataWidth:0x20 Description: fourth 32b for inverting the input for mcp; for each bit: 0= do not invert; 1= invert. mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_WAIT_P 0xa25cUL //ACCESS:RW DataWidth:0x1 Description: when set to one stops all storms
#define MISC_REG_EMAC0 0xa278UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define MISC_EMAC0_REG_EMAC0_SHUTDOWN (0x1<<0)
#define MISC_EMAC0_REG_EMAC0_SHUTDOWN_SIZE 0
#define MISC_EMAC0_REG_EMAC0_PARITY_MODE (0x1<<1)
#define MISC_EMAC0_REG_EMAC0_PARITY_MODE_SIZE 1
#define MISC_REG_EMAC1 0xa27cUL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define MISC_EMAC1_REG_EMAC1_SHUTDOWN (0x1<<0)
#define MISC_EMAC1_REG_EMAC1_SHUTDOWN_SIZE 0
#define MISC_EMAC1_REG_EMAC1_PARITY_MODE (0x1<<1)
#define MISC_EMAC1_REG_EMAC1_PARITY_MODE_SIZE 1
#define MISC_REG_GRC_TIMEOUT_EN 0xa280UL //ACCESS:RW DataWidth:0x1 Description: Setting this bit enables a timer in the GRC block to timeout any access that does not finish within ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is cleared; this timeout is disabled. If this timeout occurs; the GRC shall assert it attention output.
#define MISC_REG_GRC_TIMEOUT_VAL 0xa284UL //ACCESS:RW DataWidth:0xa Description: The count value for the timer in the GRC block.
#define MISC_REG_GRC_DBG_EN 0xa288UL //ACCESS:RW DataWidth:0x1 Description: Debug only: enable the debug mux
#define MISC_REG_PLL_STORM_CTRL_1 0xa294UL //ACCESS:RW DataWidth:0x20 Description: UNUSED for E65
#define MISC_REG_PLL_STORM_CTRL_2 0xa298UL //ACCESS:RW DataWidth:0x20 Description: UNUSED for E65
#define MISC_REG_PLL_STORM_CTRL_3 0xa29cUL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define MISC_PLL_STORM_CTRL_3_REG_PLL_STORM_CTRL_N (0x1ff<<0)
#define MISC_PLL_STORM_CTRL_3_REG_PLL_STORM_CTRL_N_SIZE 0
#define MISC_PLL_STORM_CTRL_3_REG_PLL_STORM_CTRL_M1DIV (0xff<<9)
#define MISC_PLL_STORM_CTRL_3_REG_PLL_STORM_CTRL_M1DIV_SIZE 9
#define MISC_PLL_STORM_CTRL_3_REG_PLL_STORM_CTRL_M2DIV (0xff<<17)
#define MISC_PLL_STORM_CTRL_3_REG_PLL_STORM_CTRL_M2DIV_SIZE 17
#define MISC_PLL_STORM_CTRL_3_REG_PLL_STORM_CTRL_3_RESERVE (0x7f<<25)
#define MISC_PLL_STORM_CTRL_3_REG_PLL_STORM_CTRL_3_RESERVE_SIZE 25
#define MISC_REG_RINGOSC 0xa2b0UL //ACCESS:RW DataWidth:0xe Multi Field Register
#define MISC_RINGOSC_REG_CSEM_RINGOSC_ENABLE (0x1<<0)
#define MISC_RINGOSC_REG_CSEM_RINGOSC_ENABLE_SIZE 0
#define MISC_RINGOSC_REG_CSEM_RINGOSC_SEL0 (0x1<<1)
#define MISC_RINGOSC_REG_CSEM_RINGOSC_SEL0_SIZE 1
#define MISC_RINGOSC_REG_CSEM_RINGOSC_SEL1 (0x1<<2)
#define MISC_RINGOSC_REG_CSEM_RINGOSC_SEL1_SIZE 2
#define MISC_RINGOSC_REG_XSEM_RINGOSC_ENABLE (0x1<<3)
#define MISC_RINGOSC_REG_XSEM_RINGOSC_ENABLE_SIZE 3
#define MISC_RINGOSC_REG_XSEM_RINGOSC_SEL0 (0x1<<4)
#define MISC_RINGOSC_REG_XSEM_RINGOSC_SEL0_SIZE 4
#define MISC_RINGOSC_REG_XSEM_RINGOSC_SEL1 (0x1<<5)
#define MISC_RINGOSC_REG_XSEM_RINGOSC_SEL1_SIZE 5
#define MISC_RINGOSC_REG_TSEM_RINGOSC_ENABLE (0x1<<6)
#define MISC_RINGOSC_REG_TSEM_RINGOSC_ENABLE_SIZE 6
#define MISC_RINGOSC_REG_TSEM_RINGOSC_SEL0 (0x1<<7)
#define MISC_RINGOSC_REG_TSEM_RINGOSC_SEL0_SIZE 7
#define MISC_RINGOSC_REG_TSEM_RINGOSC_SEL1 (0x1<<8)
#define MISC_RINGOSC_REG_TSEM_RINGOSC_SEL1_SIZE 8
#define MISC_RINGOSC_REG_USEM_RINGOSC_ENABLE (0x1<<9)
#define MISC_RINGOSC_REG_USEM_RINGOSC_ENABLE_SIZE 9
#define MISC_RINGOSC_REG_USEM_RINGOSC_SEL0 (0x1<<10)
#define MISC_RINGOSC_REG_USEM_RINGOSC_SEL0_SIZE 10
#define MISC_RINGOSC_REG_USEM_RINGOSC_SEL1 (0x1<<11)
#define MISC_RINGOSC_REG_USEM_RINGOSC_SEL1_SIZE 11
#define MISC_RINGOSC_REG_IFMUX_SEM_RINGOSC_MUX_SEL (0x3<<12)
#define MISC_RINGOSC_REG_IFMUX_SEM_RINGOSC_MUX_SEL_SIZE 12
#define MISC_REG_SHARED_MEM_ADDR 0xa2b4UL //ACCESS:RW DataWidth:0x16 Description: 22 bit GRC address where the scratch-pad of the MCP that is shared with the driver resides
#define MISC_REG_OTP_CTRL_REG_0 0xa2c8UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define MISC_OTP_CTRL_REG_0_REG_FMODE (0x7<<0)
#define MISC_OTP_CTRL_REG_0_REG_FMODE_SIZE 0
#define MISC_OTP_CTRL_REG_0_REG_ENABLE_OTP_0 (0x1<<3)
#define MISC_OTP_CTRL_REG_0_REG_ENABLE_OTP_0_SIZE 3
#define MISC_OTP_CTRL_REG_0_REG_ENABLE_OTP_1 (0x1<<4)
#define MISC_OTP_CTRL_REG_0_REG_ENABLE_OTP_1_SIZE 4
#define MISC_OTP_CTRL_REG_0_REG_ENABLE_OTP_2 (0x1<<5)
#define MISC_OTP_CTRL_REG_0_REG_ENABLE_OTP_2_SIZE 5
#define MISC_OTP_CTRL_REG_0_REG_UNUSED_0 (0x3<<6)
#define MISC_OTP_CTRL_REG_0_REG_UNUSED_0_SIZE 6
#define MISC_OTP_CTRL_REG_0_REG_USEPINS (0x1<<8)
#define MISC_OTP_CTRL_REG_0_REG_USEPINS_SIZE 8
#define MISC_OTP_CTRL_REG_0_REG_PROGSEL (0x1<<9)
#define MISC_OTP_CTRL_REG_0_REG_PROGSEL_SIZE 9
#define MISC_OTP_CTRL_REG_0_REG_PROGSTART (0x1<<10)
#define MISC_OTP_CTRL_REG_0_REG_PROGSTART_SIZE 10
#define MISC_OTP_CTRL_REG_0_REG_UNUSED_1 (0x1f<<11)
#define MISC_OTP_CTRL_REG_0_REG_UNUSED_1_SIZE 11
#define MISC_OTP_CTRL_REG_0_REG_PCOUNT (0x7<<16)
#define MISC_OTP_CTRL_REG_0_REG_PCOUNT_SIZE 16
#define MISC_OTP_CTRL_REG_0_REG_PBYP (0x1<<19)
#define MISC_OTP_CTRL_REG_0_REG_PBYP_SIZE 19
#define MISC_OTP_CTRL_REG_0_REG_VSEL (0xf<<20)
#define MISC_OTP_CTRL_REG_0_REG_VSEL_SIZE 20
#define MISC_OTP_CTRL_REG_0_REG_UNUSED_2 (0x7<<24)
#define MISC_OTP_CTRL_REG_0_REG_UNUSED_2_SIZE 24
#define MISC_OTP_CTRL_REG_0_REG_TM (0x7<<27)
#define MISC_OTP_CTRL_REG_0_REG_TM_SIZE 27
#define MISC_OTP_CTRL_REG_0_REG_SADBYP (0x1<<30)
#define MISC_OTP_CTRL_REG_0_REG_SADBYP_SIZE 30
#define MISC_OTP_CTRL_REG_0_REG_DEBUG (0x1<<31)
#define MISC_OTP_CTRL_REG_0_REG_DEBUG_SIZE 31
#define MISC_REG_OTP_CTRL_REG_1 0xa2ccUL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define MISC_OTP_CTRL_REG_1_REG_OTP_ADDR (0x3ff<<0)
#define MISC_OTP_CTRL_REG_1_REG_OTP_ADDR_SIZE 0
#define MISC_OTP_CTRL_REG_1_REG_UNUSED_3 (0x3f<<10)
#define MISC_OTP_CTRL_REG_1_REG_UNUSED_3_SIZE 10
#define MISC_OTP_CTRL_REG_1_REG_DOSEL (0x1ff<<16)
#define MISC_OTP_CTRL_REG_1_REG_DOSEL_SIZE 16
#define MISC_OTP_CTRL_REG_1_REG_UNUSED_4 (0x7f<<25)
#define MISC_OTP_CTRL_REG_1_REG_UNUSED_4_SIZE 25
#define MISC_REG_SW_TIMER_CFG_1 0xa2d0UL //ACCESS:RW DataWidth:0x6 Description: SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when ~misc_registers_sw_timer_val.sw_timer_val of timer 1 reach zero the register will be reload with ~misc_registers_sw_timer_reload_val_1.sw_timer_reload_val_1) ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the ~misc_registers_sw_timer_val.sw_timer_val of timer 1 reach zero); bit4-5=resolution (Devices except 578xx: 00-10us; 01-100us; 10-1ms; 11- 1us; Device 578xx: 00-6.6us; 01-66us; 10-0.66ms; 11- 0.66us)
#define MISC_REG_SW_TIMER_CFG_2 0xa2d4UL //ACCESS:RW DataWidth:0x6 Description: SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when ~misc_registers_sw_timer_val.sw_timer_val of timer 2 reach zero the register will be reload with ~misc_registers_sw_timer_reload_val_2.sw_timer_reload_val_2) ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the ~misc_registers_sw_timer_val.sw_timer_val of timer 2 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11-1us
#define MISC_REG_SW_TIMER_CFG_3 0xa2d8UL //ACCESS:RW DataWidth:0x6 Description: SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when ~misc_registers_sw_timer_val.sw_timer_val of timer 3 reach zero the register will be reload with ~misc_registers_sw_timer_reload_val_3.sw_timer_reload_val_3) ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the ~misc_registers_sw_timer_val.sw_timer_val of timer 3 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11-1us)
#define MISC_REG_SW_TIMER_CFG_4 0xa2dcUL //ACCESS:RW DataWidth:0x6 Description: SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when ~misc_registers_sw_timer_val.sw_timer_val of timer 4 reach zero the register will be reload with ~misc_registers_sw_timer_reload_val_4.sw_timer_reload_val_4) ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the ~misc_registers_sw_timer_val.sw_timer_val of timer 4 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11-1us)
#define MISC_REG_SW_TIMER_CFG_5 0xa2e0UL //ACCESS:RW DataWidth:0x6 Description: SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when ~misc_registers_sw_timer_val.sw_timer_val of timer 5 reach zero the register will be reload with ~misc_registers_sw_timer_reload_val_5.sw_timer_reload_val_5) ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the ~misc_registers_sw_timer_val.sw_timer_val of timer 5 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11-1us)
#define MISC_REG_SW_TIMER_CFG_6 0xa2e4UL //ACCESS:RW DataWidth:0x6 Description: SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when ~misc_registers_sw_timer_val.sw_timer_val of timer 6 reach zero the register will be reload with ~misc_registers_sw_timer_reload_val_6.sw_timer_reload_val_6) ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the ~misc_registers_sw_timer_val.sw_timer_val of timer 6 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11-1us)
#define MISC_REG_SW_TIMER_CFG_7 0xa2e8UL //ACCESS:RW DataWidth:0x6 Description: SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when ~misc_registers_sw_timer_val.sw_timer_val of timer 7 reach zero the register will be reload with ~misc_registers_sw_timer_reload_val_7.sw_timer_reload_val_7) ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the ~misc_registers_sw_timer_val.sw_timer_val of timer 7 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11-1us)
#define MISC_REG_SW_TIMER_CFG_8 0xa2ecUL //ACCESS:RW DataWidth:0x6 Description: SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when ~misc_registers_sw_timer_val.sw_timer_val of timer 8 reach zero the register will be reload with ~misc_registers_sw_timer_reload_val_8.sw_timer_reload_val_8) ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the ~misc_registers_sw_timer_val.sw_timer_val of timer 8 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11-1us)
#define MISC_REG_SW_TIMER_RELOAD_VAL_1 0xa2f0UL //ACCESS:RW DataWidth:0x20 Description: reload value for counter 1 if reload; the value will be reload if the counter reached zero and the reload bit (~misc_registers_sw_timer_cfg_1.sw_timer_cfg_1[1] ) is set
#define MISC_REG_SW_TIMER_RELOAD_VAL_2 0xa2f4UL //ACCESS:RW DataWidth:0x20 Description: reload value for counter 2 if reload; the value will be reload if the counter reached zero and the reload bit (~misc_registers_sw_timer_cfg_2.sw_timer_cfg_2[1] ) is set
#define MISC_REG_SW_TIMER_RELOAD_VAL_3 0xa2f8UL //ACCESS:RW DataWidth:0x20 Description: reload value for counter 3 if reload; the value will be reload if the counter reached zero and the reload bit (~misc_registers_sw_timer_cfg_3.sw_timer_cfg_3[1] ) is set
#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fcUL //ACCESS:RW DataWidth:0x20 Description: reload value for counter 4 if reload; the value will be reload if the counter reached zero and the reload bit (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set
#define MISC_REG_SW_TIMER_RELOAD_VAL_5 0xa300UL //ACCESS:RW DataWidth:0x20 Description: reload value for counter 5 if reload; the value will be reload if the counter reached zero and the reload bit (~misc_registers_sw_timer_cfg_1.sw_timer_cfg_5[1] ) is set
#define MISC_REG_SW_TIMER_RELOAD_VAL_6 0xa304UL //ACCESS:RW DataWidth:0x20 Description: reload value for counter 6 if reload; the value will be reload if the counter reached zero and the reload bit (~misc_registers_sw_timer_cfg_1.sw_timer_cfg_6[1] ) is set
#define MISC_REG_SW_TIMER_RELOAD_VAL_7 0xa308UL //ACCESS:RW DataWidth:0x20 Description: reload value for counter 1 if reload; the value will be reload if the counter reached zero and the reload bit (~misc_registers_sw_timer_cfg_1.sw_timer_cfg_7[1] ) is set
#define MISC_REG_SW_TIMER_RELOAD_VAL_8 0xa30cUL //ACCESS:RW DataWidth:0x20 Description: reload value for counter 8 if reload; the value will be reload if the counter reached zero and the reload bit (~misc_registers_sw_timer_cfg_1.sw_timer_cfg_8[1] ) is set
#define MISC_REG_SW_TIMER_10US_RESOLUTION 0xa310UL //ACCESS:RW DataWidth:0xc Description: fine tuning for sw 10us timer; max value=3000; min value=2000. the 10us timer is the base counter for all the timers.
#define MISC_REG_GRC_DBG_SELECT 0xa314UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from GRC to the DBG block) - for selecting a line to output to the DBG block.
#define MISC_REG_GRC_DBG_BYTE_ENABLE 0xa318UL //ACCESS:RW DataWidth:0x8 Description: Debug Only: For dbgmux usage (debug data that goes from GRC to the DBG block) - for enabling bytes in the selected line (after the select; before the shift)
#define MISC_REG_GRC_DBG_SHIFT 0xa31cUL //ACCESS:RW DataWidth:0x3 Description: Debug Only: For dbgmux usage (debug data that goes from GRC to the DBG block) - for circular right shifting of the selected line (after the enabling)
#define MISC_REG_DBG_SELECT 0xa320UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from MISC to the DBG block) - for selecting a line to output to the DBG block.
#define MISC_REG_DBG_BYTE_ENABLE 0xa324UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from MISC to the DBG block) - for enabling bytes in the selected line (after the select; before the shift)
#define MISC_REG_DBG_SHIFT 0xa328UL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from MISC to the DBG block) - for circular right shifting of the selected line (after the enabling)
#define MISC_REG_MISC_INT_STS 0xa37cUL //ACCESS:R DataWidth:0x8 Description: Interrupt register #0 read
#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define MISC_MISC_INT_STS_REG_RSV_ACCESS_ATTN (0x1<<1)
#define MISC_MISC_INT_STS_REG_RSV_ACCESS_ATTN_SIZE 1
#define MISC_MISC_INT_STS_REG_TIMEOUT_ATTN (0x1<<2)
#define MISC_MISC_INT_STS_REG_TIMEOUT_ATTN_SIZE 2
#define MISC_MISC_INT_STS_REG_GENERIC_SW (0x1<<3)
#define MISC_MISC_INT_STS_REG_GENERIC_SW_SIZE 3
#define MISC_MISC_INT_STS_REG_RX_LPI_P0 (0x1<<4)
#define MISC_MISC_INT_STS_REG_RX_LPI_P0_SIZE 4
#define MISC_MISC_INT_STS_REG_RX_LPI_P1 (0x1<<5)
#define MISC_MISC_INT_STS_REG_RX_LPI_P1_SIZE 5
#define MISC_MISC_INT_STS_REG_TX_LPI_REQ_P0 (0x1<<6)
#define MISC_MISC_INT_STS_REG_TX_LPI_REQ_P0_SIZE 6
#define MISC_MISC_INT_STS_REG_TX_LPI_REQ_P1 (0x1<<7)
#define MISC_MISC_INT_STS_REG_TX_LPI_REQ_P1_SIZE 7
#define MISC_REG_MISC_INT_STS_CLR 0xa380UL //ACCESS:RC DataWidth:0x8 Description: Interrupt register #0 read clear
#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define MISC_MISC_INT_STS_CLR_REG_RSV_ACCESS_ATTN (0x1<<1)
#define MISC_MISC_INT_STS_CLR_REG_RSV_ACCESS_ATTN_SIZE 1
#define MISC_MISC_INT_STS_CLR_REG_TIMEOUT_ATTN (0x1<<2)
#define MISC_MISC_INT_STS_CLR_REG_TIMEOUT_ATTN_SIZE 2
#define MISC_MISC_INT_STS_CLR_REG_GENERIC_SW (0x1<<3)
#define MISC_MISC_INT_STS_CLR_REG_GENERIC_SW_SIZE 3
#define MISC_MISC_INT_STS_CLR_REG_RX_LPI_P0 (0x1<<4)
#define MISC_MISC_INT_STS_CLR_REG_RX_LPI_P0_SIZE 4
#define MISC_MISC_INT_STS_CLR_REG_RX_LPI_P1 (0x1<<5)
#define MISC_MISC_INT_STS_CLR_REG_RX_LPI_P1_SIZE 5
#define MISC_MISC_INT_STS_CLR_REG_TX_LPI_REQ_P0 (0x1<<6)
#define MISC_MISC_INT_STS_CLR_REG_TX_LPI_REQ_P0_SIZE 6
#define MISC_MISC_INT_STS_CLR_REG_TX_LPI_REQ_P1 (0x1<<7)
#define MISC_MISC_INT_STS_CLR_REG_TX_LPI_REQ_P1_SIZE 7
#define MISC_REG_MISC_INT_STS_WR 0xa384UL //ACCESS:WR DataWidth:0x8 Description: Interrupt register #0 bit set or clear
#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define MISC_MISC_INT_STS_WR_REG_RSV_ACCESS_ATTN (0x1<<1)
#define MISC_MISC_INT_STS_WR_REG_RSV_ACCESS_ATTN_SIZE 1
#define MISC_MISC_INT_STS_WR_REG_TIMEOUT_ATTN (0x1<<2)
#define MISC_MISC_INT_STS_WR_REG_TIMEOUT_ATTN_SIZE 2
#define MISC_MISC_INT_STS_WR_REG_GENERIC_SW (0x1<<3)
#define MISC_MISC_INT_STS_WR_REG_GENERIC_SW_SIZE 3
#define MISC_MISC_INT_STS_WR_REG_RX_LPI_P0 (0x1<<4)
#define MISC_MISC_INT_STS_WR_REG_RX_LPI_P0_SIZE 4
#define MISC_MISC_INT_STS_WR_REG_RX_LPI_P1 (0x1<<5)
#define MISC_MISC_INT_STS_WR_REG_RX_LPI_P1_SIZE 5
#define MISC_MISC_INT_STS_WR_REG_TX_LPI_REQ_P0 (0x1<<6)
#define MISC_MISC_INT_STS_WR_REG_TX_LPI_REQ_P0_SIZE 6
#define MISC_MISC_INT_STS_WR_REG_TX_LPI_REQ_P1 (0x1<<7)
#define MISC_MISC_INT_STS_WR_REG_TX_LPI_REQ_P1_SIZE 7
#define MISC_REG_MISC_INT_MASK 0xa388UL //ACCESS:RW DataWidth:0x8 Description: Interrupt mask register #0 read/write
#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define MISC_MISC_INT_MASK_REG_RSV_ACCESS_ATTN (0x1<<1)
#define MISC_MISC_INT_MASK_REG_RSV_ACCESS_ATTN_SIZE 1
#define MISC_MISC_INT_MASK_REG_TIMEOUT_ATTN (0x1<<2)
#define MISC_MISC_INT_MASK_REG_TIMEOUT_ATTN_SIZE 2
#define MISC_MISC_INT_MASK_REG_GENERIC_SW (0x1<<3)
#define MISC_MISC_INT_MASK_REG_GENERIC_SW_SIZE 3
#define MISC_MISC_INT_MASK_REG_RX_LPI_P0 (0x1<<4)
#define MISC_MISC_INT_MASK_REG_RX_LPI_P0_SIZE 4
#define MISC_MISC_INT_MASK_REG_RX_LPI_P1 (0x1<<5)
#define MISC_MISC_INT_MASK_REG_RX_LPI_P1_SIZE 5
#define MISC_MISC_INT_MASK_REG_TX_LPI_REQ_P0 (0x1<<6)
#define MISC_MISC_INT_MASK_REG_TX_LPI_REQ_P0_SIZE 6
#define MISC_MISC_INT_MASK_REG_TX_LPI_REQ_P1 (0x1<<7)
#define MISC_MISC_INT_MASK_REG_TX_LPI_REQ_P1_SIZE 7
#define MISC_REG_MISC_PRTY_STS 0xa38cUL //ACCESS:R DataWidth:0x1 Description: Parity register #0 read
#define MISC_MISC_PRTY_STS_REG_PARITY (0x1<<0)
#define MISC_MISC_PRTY_STS_REG_PARITY_SIZE 0
#define MISC_REG_MISC_PRTY_STS_CLR 0xa390UL //ACCESS:RC DataWidth:0x1 Description: Parity register #0 read clear
#define MISC_MISC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define MISC_MISC_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define MISC_REG_MISC_PRTY_STS_WR 0xa394UL //ACCESS:WR DataWidth:0x1 Description: Parity register #0 bit set or clear
#define MISC_MISC_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define MISC_MISC_PRTY_STS_WR_REG_PARITY_SIZE 0
#define MISC_REG_MISC_PRTY_MASK 0xa398UL //ACCESS:RW DataWidth:0x1 Description: Parity mask register #0 read/write
#define MISC_MISC_PRTY_MASK_REG_PARITY (0x1<<0)
#define MISC_MISC_PRTY_MASK_REG_PARITY_SIZE 0
#define MISC_REG_AEU_MCP_SCPAD_PERR 0xa3a0UL //ACCESS:R DataWidth:0x2 Description: One in each bit shows that the appropriate MCP scpad parity error occurs.
#define MISC_REG_AEU_MASK_ATTN_FUNC_0_MSB 0xa3acUL //ACCESS:RW DataWidth:0x8 Description: mask 8 MSB attention output signals toward IGU function0; Zero = mask; one = unmask
#define MISC_REG_AEU_MASK_ATTN_FUNC_1_MSB 0xa3b0UL //ACCESS:RW DataWidth:0x8 Description: mask 8 MSB attention output signals toward IGU function1; Zero = mask; one = unmask
#define MISC_REG_GRC_RSV_ATTN 0xa3c0UL //ACCESS:R DataWidth:0x1c Description: this field hold the last information that caused reserved attention. bits [19:0] - address; [22:20] function; [23] reserved; [27:24] the master that caused the attention - according to the following encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = dbu; 8 = dmae
#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4UL //ACCESS:R DataWidth:0x1c Description: this field hold the last information that caused timeout attention. bits [19:0] - address; [22:20] function; [23] reserved; [27:24] the master that caused the attention - according to the following encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = dbu; 8 = dmae
#define MISC_REG_BOND_ID 0xa400UL //ACCESS:R DataWidth:0x20 Description: This field indicates the type of the device. '0' - 2 Ports; '1' - 1 Port. Global register.
#define MISC_REG_CHIP_METAL 0xa404UL //ACCESS:R DataWidth:0x8 Description: These bits indicate the metal revision of the chip. This value starts at 0x00 for each all-layer tape-out and increments by one for each tape-out. Global register.
#define MISC_REG_CHIP_NUM 0xa408UL //ACCESS:R DataWidth:0x10 Description: These bits indicate the part number for the chip. Global register.
#define MISC_REG_CHIP_REV 0xa40cUL //ACCESS:R DataWidth:0x4 Description: These bits indicate the base revision of the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer tape-out. Global register.
#define MISC_REG_CHIP_TEST_REG 0xa410UL //ACCESS:R DataWidth:0x8 Description: These bits indicate the silent revision of the chip. Global register.
#define MISC_REG_LINK_HOLDOFF_SUCCESS 0xa418UL //ACCESS:R DataWidth:0x1 Description: This bit indicates the PCIE link is successfully being held from starting training. Used in conjunction with ~MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ. Global register.
#define MISC_REG_LINK_IN_L23 0xa41cUL //ACCESS:R DataWidth:0x1 Description: When this bit is 1 it indicates that the link is down and PCIE is prepared for operation off of VAUX. Global register.
#define MISC_REG_PCIE_DIS 0xa420UL //ACCESS:R DataWidth:0x1 Description: This bit reports the current state of the PCIE_DIS pin. If this bit is 1 it means that the LOM design has been strapped to support management only. The PCI power will always read as '0' in this state; as if the chip is in Out-Of-Box WOL mode. Global register.
#define MISC_REG_VAUX_PRESENT 0xa428UL //ACCESS:R DataWidth:0x1 Description: 0 - VAUX is not present; 1 - VAUX is present. Global register.
#define MISC_REG_ISOLATION_LOGIC 0xa498UL //ACCESS:R DataWidth:0x1 Description: the isolation between Vaux and Vmain read value. Global register.
#define MISC_REG_LCPLL_MISC_LOCK 0xa49cUL //ACCESS:R DataWidth:0x1 Description: lcpll lock signals. 0-unlocked; 1-locked. Global register.
#define MISC_REG_P0_SERDES_PLL_LOCK 0xa4b0UL //ACCESS:R DataWidth:0x1 Description: serdes port 0 pll lock signals. 0-unlocked; 1-locked
#define MISC_REG_P0_XGXS_PLL_LOCK 0xa4b4UL //ACCESS:R DataWidth:0x1 Description: xgxs port 0 pll lock signals. 0-unlocked; 1-locked
#define MISC_REG_P1_SERDES_PLL_LOCK 0xa4b8UL //ACCESS:R DataWidth:0x1 Description: serdes port 1 pll lock signals. 0-unlocked; 1-locked
#define MISC_REG_P1_XGXS_PLL_LOCK 0xa4bcUL //ACCESS:R DataWidth:0x1 Description: xgxs port 1 pll lock signals. 0-unlocked; 1-locked
#define MISC_REG_PIPE_MISC_PLL_LOCK 0xa4c0UL //ACCESS:R DataWidth:0x8 Description: PCIE SERDES pll lock signals. 0-unlocked; 1-locked. Global register.
#define MISC_REG_PLL_MAIN_CTRL_1 0xa548UL //ACCESS:RW DataWidth:0x20 Description: UNUSED for E65
#define MISC_REG_PLL_MAIN_CTRL_2 0xa550UL //ACCESS:RW DataWidth:0x20 Description: UNUSED for E65
#define MISC_REG_PLL_MAIN_CTRL_3_M1DIV 0xa558UL //ACCESS:RW DataWidth:0x8 Description: UNUSED for E65
#define MISC_REG_PLL_MAIN_CTRL_3_M2DIV 0xa560UL //ACCESS:RW DataWidth:0x8 Description: UNUSED for E65
#define MISC_REG_PLL_MAIN_CTRL_3_N 0xa568UL //ACCESS:RW DataWidth:0x9 Description: UNUSED for E65
#define MISC_REG_AEU_VPD_LATCH_STATUS 0xa5fcUL //ACCESS:R DataWidth:0x8 Description: represent the status of pxpv_misc_vpd0_attn (bit 0) - pxpv_misc_vpd7_attn (bit 7) after latching.
#define MISC_REG_PCIE_HOT_RESET 0xa618UL //ACCESS:R DataWidth:0x1 Description: If set indicate that the pcie_rst_b was asserted without perst assertion. Global register.
#define MISC_REG_AEU_GENERAL_MASK 0xa61cUL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK_SIZE 0
#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK_SIZE 1
#define MISC_AEU_GENERAL_MASK_REG_AEU_SYS_KILL_MASK (0x1<<2)
#define MISC_AEU_GENERAL_MASK_REG_AEU_SYS_KILL_MASK_SIZE 2
#define MISC_REG_ECO_RESERVED 0xa620UL //ACCESS:RW DataWidth:0x20 Description: eco reserved. Global register.
#define MISC_REG_CPU_OTP_STATUS 0xa62cUL //ACCESS:R DataWidth:0x20 Description: [0]: command_done: This bit is set when the state machine has returned to IDLE. This will not be set until the last bit of a WORD program is complete; [1]: wrp_data_ready: Wrapper indicates data is ready; [2]: wrp_bit_dout: single bit otp_dout pointed to by wrp_addr; [3]: wrp_busy: The otp_busy was seen - even if it is done. Useful to tell if the state machine ever left IDLE. For a valid command the otp_wrapper state machine asserts this signal indicating that it is busy in executing the command; [4]: wrp_fail: A FAIL occurred on 1 or more commands; [5]: invalid_prog_req: A program request was sent with the incorrect access mode; [6]: prog_blocked: Programming attempted on a locked row was blocked; [7]: wrp_fdone: OTP is ready to take command. Wait for this signal to go high before issuing any command after POR or auto_reload command; [8]: otp_stby_reg: Indicates that the OTP cell is in standby mode. The only command that is valid during this time is a WAKEUP command; [9]: invalid_command: Indicates that it is wrong command. The command is not in the command list; [10]: wrp_error: Error condition in wrapper SM. Clear it with a reset; [11]: refok: OTP regulator refok signal; [12]: progok: OTP is in Program Enable Mode; [13]: invalid_address: OTP address does not adhere to the requirements of the region that is being accessed; [14]: invlaid_access_mode: OTP access mode is not compatible with the address of the region that is being accessed; [15]: invalid_secure_access: JTAG is blocked accessing secure space; [16]: Otp_ready: Indicates the controller is ready to take commands for OTP access. This needs to be tested for High before any command is initiated for execution (mandatory); [29:17] reserved; [31:30]: state: HW OTP reader block state machine : 0 - idle state; 1 - read state; 2 - finish state; 3- reset state. Global register.
#define MISC_REG_CPU_OTP_READ_DATA 0xa634UL //ACCESS:R DataWidth:0x20 Description: SHARED: Data output from the OTP read data command. Global register.
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688UL //ACCESS:RW DataWidth:0x20 Description: fifth 32b for enabling the output for function 0 output0. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_1 0xa68cUL //ACCESS:RW DataWidth:0x20 Description: fifth 32b for enabling the output for function 0 output1. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_2 0xa690UL //ACCESS:RW DataWidth:0x20 Description: fifth 32b for enabling the output for function 0 output2. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [[6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_3 0xa694UL //ACCESS:RW DataWidth:0x20 Description: fifth 32b for enabling the output for function 0 output3. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_4 0xa698UL //ACCESS:RW DataWidth:0x20 Description: fifth 32b for enabling the output for function 0 output4. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity;[6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_5 0xa69cUL //ACCESS:RW DataWidth:0x20 Description: fifth 32b for enabling the output for function 0 output5. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_6 0xa6a0UL //ACCESS:RW DataWidth:0x20 Description: fifth 32b for enabling the output for function 0 output6. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_7 0xa6a4UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for function 0 output7. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_NIG_0 0xa6a8UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for close the gate nig. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_PXP_0 0xa6acUL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity;[6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for function 1 output0. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_1 0xa6b4UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for function 1 output1. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_2 0xa6b8UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for function 1 output2. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_3 0xa6bcUL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for function 1 output3. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_4 0xa6c0UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for function 1 output4. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_5 0xa6c4UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for function 1 output5. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_6 0xa6c8UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for function 1 output6. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity;[6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_7 0xa6ccUL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for function 1 output7. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity;[6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_PXP_1 0xa6d0UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for close the gate system kill. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity;[6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_MCP_OUT_0 0xa6d4UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for mcp output0. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_MCP_OUT_1 0xa6d8UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for mcp output1. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_MCP_OUT_2 0xa6dcUL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for mcp output2. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_MCP_OUT_3 0xa6e0UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for mcp output3. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_MCP_OUT_4 0xa6e4UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for mcp output4. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_MCP_OUT_5 0xa6e8UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for mcp output5. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity;[6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_MCP_OUT_6 0xa6ecUL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for mcp output6. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_ENABLE5_MCP_OUT_7 0xa6f0UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for enabling the output for mcp output7. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_INVERTER_5_FUNC_0 0xa6f4UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for inverting the input for function 0; Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_INVERTER_5_FUNC_1 0xa6f8UL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for inverting the input for function 1; Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_INVERTER_5_MCP 0xa6fcUL //ACCESS:RW DataWidth:0x20 Description: Fifth 32b for inverting the input for mcp; Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_GRC_RSV_ATTN_FULL_FID 0xa710UL //ACCESS:R DataWidth:0xa Description: Holds the last FID that caused reserved attention. Need to be used in conjunction with ~misc_registers_grc_rsv_attn; where 3 bits of function (3 lsb) are also represented. Bit[2:0] - PFID; bit[3] - VFID valid; bit[9:4] - VFID. Global register.
#define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID 0xa714UL //ACCESS:R DataWidth:0xa Description: Holds the last FID that caused timeout attention. Need to be used in conjunction with ~misc_registers_timeout_attn; where 3 bits of function (3 lsb) are also represented. Bit[2:0] - PFID; bit[3] - VFID valid; bit[9:4] - VFID. Global register.
#define MISC_REG_FUNC_HIDE_PIN 0xa718UL //ACCESS:R DataWidth:0x1 Description: Synchronised value of ifmux_misc_func_hide. Global register.
#define MISC_REG_PORT4MODE_EN 0xa750UL //ACCESS:R DataWidth:0x1 Description: Status of 4 port mode enable input pin.
#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754UL //ACCESS:R DataWidth:0x1 Description: Status of 4 port mode port swap input pin.
#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758UL //ACCESS:R DataWidth:0x1 Description: Status of two port mode path swap input pin.
#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75cUL //ACCESS:R DataWidth:0x1 Description: Status of four port mode path swap input pin.
#define MISC_REG_EXT_PHY_MODE_STRAPS 0xa784UL //ACCESS:R DataWidth:0x4 Description: Status of PHY mode straps {TEST_IN[0];TEST_IN[1];EJTAG_TMS;EJTAG_TDI} input pin (ifmux_misc_ext_phy_mode_straps).
#define MISC_REG_PLL_MAIN_E40_OTP_PDIV 0xa7e0UL //ACCESS:R DataWidth:0x3 Description: Input reference clock pre-divider control (code = divider ratio). 000: divide-by-8; 001: divide-by-1; 010: divide-by-2; 011: divide-by-3; 100: divide-by-4; 101: divide-by-5; 110: divide-by-6; 111: divide-by-7. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_OTP_NDIV_INT 0xa7e4UL //ACCESS:R DataWidth:0xa Description: Feedback divider control (Code = divider ratio). 0000000000: divide-by-1024; 0000000001: XXX; 0000000010: XXX; 0000000111: XXX; 0000001000: divide-by-8; 0000001001: divide-by-9; 0000001010: divide-by-10; 1111111110: divide-by-1022; 1111111111: divide-by-1023. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_OTP_NDIV_FRAC 0xa7e8UL //ACCESS:R DataWidth:0x14 Description: Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_OTP_CH0_MDIV 0xa7ecUL //ACCESS:R DataWidth:0x8 Description: Post-divider ratio for channel-0 (divider ratio = code value). 00000000: 256; 00000001: 1; 00000010: 2; 00000011: 3; : :; 11111101: 253; 11111110: 254; 11111111: 255. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_OTP_CTRL_1 0xa7f0UL //ACCESS:R DataWidth:0x1e Description: PLL configuration control register. [11:0]: dco_ctrl_bypass[11:0]: direct programming of DAC: 000000000000 = MIN VCO clock frequency; : ; 111111111111 = MAX VCO clock frequency; [12]: dco_ctrl_bypass_enable: enable of direct programming of DAC: 0 =normal mode; 1 =DAC programming mode; [13]: stat_reset: reset of phase error measurement: 0 =normal mode; 1 =reset; [16:14]: stat_select[2:0]: select of test output: 000 = 000000000000; 001 = minimum phase error; 010 = maximum phase error; 011 = mean-square phase error; 100 = dac control word; 101 = 000000000000; 110 = 000000000000; 111 = 000000000000; [17]: stat_update: On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout; [18]: refclkout: Enable for o_fref output: 0 = o_fref at logic 0; 1 = o_fref enabled (pre-divider output clock); [19]: AUX_CTRL: ICO current: 0 = normal mode; 1 = Ivco increased by 130 ?A; [20]: VCOdiv2_Post: Enables divide-by-2 for the clock to post-dividers: 0 = normal mode; 1 = VCO divide-by-2 clock feeds post dividers; [22:21]: Stat_mode[1:0]: Statistics Mode: 00 = disabled; 01 = phase error stats; 10 = period stats; 11 = Feedback phase error stats; [24:23]: Pwm_rate[1:0]: Set PWM rate; Vco_div2 == 0; 00 = 4 ( default); 01 = 5; 10 = 2; 11 = 3; Vco_div2 == 1; 00 = 8; 01 = 10; 10 = 4 (default when vco_div2 = 1); 11 = 6; [26:25]: vco_dly[1:0]: Adds selectable delay to VCO_CLK; 00 = nominal delay (default); 01 = One added INV/NAND2 pair; 10 = Two added INV/NAND2 pairs; 11 = Three added INV/NAND2 pairs Hook for engineering tests of the T2D; [27]: VCOdiv2: Divide VCO_CLK into T2D by 2: 0 = T2D run at VCO rate; 1 = T2D runs at VCO/2 rate Must be set to 1 above 3.2 GHz; [28]: fast_lock: Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high; 0 = 256 refclk delay; 1 = 32 refclk delay; [29]: ndiv_relock: Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes; 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode; 1 = Re-enter frequency acquisition state without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_OTP_CTRL_2 0xa7f4UL //ACCESS:R DataWidth:0xa Description: Configuration control register. [2:0]: i_ka[2:0]: Loop gain in frequency acquisition mode; [5:3]: i_ki[2:0]: Gain of P/I loop filter integrator path during fine phase acquisition mode; [9:6]: i_kp[3:0]: Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.
#define MISC_REG_RX_LPI_P0_STAT 0xa8d4UL //ACCESS:RW DataWidth:0x1 Description: local port 0 SERDES is receiving (Rx) LPI status reference value. If local port 0 SERDES is receiving (Rx) LPI status is different from this value the corresponding interrupt is issued.
#define MISC_REG_RX_LPI_P1_STAT 0xa8d8UL //ACCESS:RW DataWidth:0x1 Description: local port 1 SERDES is receiving (Rx) LPI status reference value. If local port 1 SERDES is receiving (Rx) LPI status is different from this value the corresponding interrupt is issued.
#define MISC_REG_TX_LPI_REQ_P0_STAT 0xa8dcUL //ACCESS:RW DataWidth:0x1 Description: local port 0 SERDES should enter (Tx) LPI mode reference value. If local port 0 SERDES should enter (Tx) LPI mode is different from this value the corresponding interrupt is issued.
#define MISC_REG_TX_LPI_REQ_P1_STAT 0xa8e0UL //ACCESS:RW DataWidth:0x1 Description: local port 1 SERDES should enter (Tx) LPI mode reference value. If local port 1 SERDES should enter (Tx) LPI mode is different from this value the corresponding interrupt is issued.
#define MISC_REG_PORT_LANE_MODE 0xa974UL //ACCESS:R DataWidth:0x2 Description: Status of swap mode input pin.
#define MISC_REG_WC0_PLL_LOCK 0xaa20UL //ACCESS:R DataWidth:0x1 Description: WC0 pll lock signals. 0-unlocked; 1-locked.
#define MISC_REG_WC1_PLL_LOCK 0xaa24UL //ACCESS:R DataWidth:0x1 Description: WC1 pll lock signals. 0-unlocked; 1-locked.
#define MISC_REG_WC2_PLL_LOCK 0xaa28UL //ACCESS:R DataWidth:0x1 Description: WC2 pll lock signals. 0-unlocked; 1-locked.
#define MISC_REG_CHIP_TYPE 0xac60UL //ACCESS:R DataWidth:0xe Description: otp_misc_do[100:0] spare bits collection: 13:11- otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72]; 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1].
#define MISC_REG_CHIP_TYPE_57811_MASK (1<<1) //
#define MISC_REG_AEU_PRESET_REF 0xa05cUL //ACCESS:RW DataWidth:0x1 Description: The ref value for PERST signal change detection. Default value is 1 (attention on PERST assertion).
#define MISC_REG_AEU_PRESET_REF_SIZE 1
#define MISC_REG_SCPAD_TM 0xa260UL //ACCESS:RW DataWidth:0x5 Description: tm bits for mcp_scpad memory. Global register.
#define MISC_REG_SCPAD_TM_SIZE 1
#define MISC_REG_RX_TM 0xa264UL //ACCESS:RW DataWidth:0xa Description: tm bits for ump_rx memory. Global register.
#define MISC_REG_RX_TM_SIZE 1
#define MISC_REG_TX_TM 0xa268UL //ACCESS:RW DataWidth:0xa Description: tm bits for ump_tx memory. Global register.
#define MISC_REG_TX_TM_SIZE 1
#define MISC_REG_PARITY_MODE 0xa26cUL //ACCESS:RW DataWidth:0x1 Description: debug only : parity mode to MCP. Setting this bit changes the parity checking on the RAMs from even to odd parity. Global register.
#define MISC_REG_PARITY_MODE_SIZE 1
#define MISC_REG_NIG_WOL_P0 0xa270UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: when set to one indicates WOL is detected by the MCP FW on port 0. this register is multiply per function.
#define MISC_REG_NIG_WOL_P0_SIZE 1
#define MISC_REG_NIG_WOL_P1 0xa274UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: when set to one indicates WOL is detected by the MCP FW on port 1. this register is multiply per function.
#define MISC_REG_NIG_WOL_P1_SIZE 1
#define MISC_REG_UNCOND_ENTER_PLAY_DEAD 0xa28cUL //ACCESS:RW DataWidth:0x1 Description: Writing to this register result with resetting entire chip via the play dead mechanism. Global register.
#define MISC_REG_UNCOND_ENTER_PLAY_DEAD_SIZE 1
#define MISC_REG_COND_ENTER_PLAY_DEAD 0xa290UL //ACCESS:RW DataWidth:0x1 Description: Writing to this register result with resetting entire chip via the play dead mechanism if PERST is asserted. Global register.
#define MISC_REG_COND_ENTER_PLAY_DEAD_SIZE 1
#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0UL //ACCESS:RW DataWidth:0x3 Description: [0]clock storm bypass: 0-select Storm SPLL clock; 1-select external clock; [1]PLL storm reset- Analog reset toward the Storm PLL; [2]PLL storm digital reset- Digital reset toward the Storm PLL. Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_CTRL_4_SIZE 1
#define MISC_REG_LCPLL_CTRL_1 0xa2a4UL //ACCESS:RW DataWidth:0x1c Description: 28 LSB of LCPLL first register; reset val = 521. inside order of the bits is: [2:0] OAC reset value 001) CML output buffer bias control; 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl (reset value 001) Charge pump current control; 111 for 720u; 011 for 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00) Global bias control; When bit 7 is high bias current will be 10 0gh; When bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8] Pll_observe (reset value 010) Bits to control observability. bit 10 is for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted internally). [14] reserved (reset value 0) Reset for VCO sequencer is connected to RESET input directly. [15] capRetry_en (reset value 0) enable retry on cap search failure (inverted). [16] freqMonitor_e (reset value 0) bit to continuously monitor vco freq (inverted). [17] freqDetRestart_en (reset value 0) bit to enable restart when not freq locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable retry on freq det failure(inverted). [19] pllForceFdone_en (reset value 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20] pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0) bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force capPass. [26] capRestart (reset value 0) bit to force cap sequencer to restart. [27] capSelectM_en (reset value 0) bit to enable cap select register bits. Global register.
#define MISC_REG_LCPLL_CTRL_1_SIZE 1
#define MISC_REG_OSCILLATOR 0xa2acUL //ACCESS:RW DataWidth:0xa Description: Debug only. [0] - VMAIN oscillator control enable [1] - VMAIN oscillator control select 0 [2] - VMAIN oscillator control select 1 [3] - VAUX oscillator control enable [4] - VAUX oscillator control select 0 [5] - VAUX oscillator control select 1 [6] - PAD oscillator control enable [7] - PAD oscillator control select 0 [8] - PAD oscillator control select 1 [9] - PAD mux select. Global register.
#define MISC_REG_OSCILLATOR_SIZE 1
#define MISC_REG_SPIO_EVENT_EN 0xa2b8UL //ACCESS:RW DataWidth:0x8 Description: These bits enable the SPIO_INTs to signals event to the IGU/MC. according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; [7:6] reserved. Global register.
#define MISC_REG_SPIO_EVENT_EN_SIZE 1
#define MISC_REG_GPIO_EVENT_EN 0xa2bcUL //ACCESS:RW DataWidth:0x8 Description: These bits enable the GPIO_INTs to signals event to the IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2] p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2; [7] p1_gpio_3; Global register.
#define MISC_REG_GPIO_EVENT_EN_SIZE 1
#define MISC_REG_NVM_WR_EN 0xa2c0UL //ACCESS:RW DataWidth:0x2 Description: These bits control how the write-disable to the NVM block is generated. '0' - PROTECT: This value protects the NVM from any writes. '1' - PCI: This value allows writes only when PCI\_RST\ is high.' 2' - ALLOW: This value allows writes to the NVM using normal NVM commands. '3' - ALLOW2: This value allows writes to the NVM using normal NVM commands. Global register.
#define MISC_REG_NVM_WR_EN_SIZE 1
#define MISC_REG_LINK_HOLDOFF_REQ 0xa2c4UL //ACCESS:RW DataWidth:0x1 Description: This bit is written to a '1' to request that the PCIE link not begin training yet. Software should set this bit; and then check the ~MISC_REGISTERS_LINK_HOLDOFF_SUCCESS.LINK_HOLDOFF_SUCCESS bit. If ~MISC_REGISTERS_LINK_HOLDOFF_SUCCESS.LINK_HOLDOFF_SUCCESS is set; configure the PCIE link and then clear this bit. If ~MISC_REGISTERS_LINK_HOLDOFF_SUCCESS.LINK_HOLDOFF_SUCCESS is not set; the PCIE link has already begun training so it's too late to do any configuration. Global register.
#define MISC_REG_LINK_HOLDOFF_REQ_SIZE 1
#define MISC_REG_VMAIN_POR 0xa32cUL //ACCESS:RW DataWidth:0x2 Description: 0-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be #misc_registers_vmain_por.vmain_por[1]; 1- bypass the Vmain PORBG. If #misc_registers_vmain_por.vmain_por[0] is '1' the output of Vmain POR will be this field. Global register.
#define MISC_REG_VMAIN_POR_SIZE 1
#define MISC_REG_RINGOSC_TOP_0_ENABLE 0xa330UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
#define MISC_REG_RINGOSC_TOP_0_ENABLE_SIZE 1
#define MISC_REG_RINGOSC_TOP_0_SEL0 0xa334UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
#define MISC_REG_RINGOSC_TOP_0_SEL0_SIZE 1
#define MISC_REG_RINGOSC_TOP_0_SEL1 0xa338UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1 . Global register.
#define MISC_REG_RINGOSC_TOP_0_SEL1_SIZE 1
#define MISC_REG_RINGOSC_TOP_1_ENABLE 0xa33cUL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
#define MISC_REG_RINGOSC_TOP_1_ENABLE_SIZE 1
#define MISC_REG_RINGOSC_TOP_1_SEL0 0xa340UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
#define MISC_REG_RINGOSC_TOP_1_SEL0_SIZE 1
#define MISC_REG_RINGOSC_TOP_1_SEL1 0xa344UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1. Global register.
#define MISC_REG_RINGOSC_TOP_1_SEL1_SIZE 1
#define MISC_REG_RINGOSC_TOP_2_ENABLE 0xa348UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
#define MISC_REG_RINGOSC_TOP_2_ENABLE_SIZE 1
#define MISC_REG_RINGOSC_TOP_2_SEL0 0xa34cUL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
#define MISC_REG_RINGOSC_TOP_2_SEL0_SIZE 1
#define MISC_REG_RINGOSC_TOP_2_SEL1 0xa350UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1. Global register.
#define MISC_REG_RINGOSC_TOP_2_SEL1_SIZE 1
#define MISC_REG_RINGOSC_TOP_3_ENABLE 0xa354UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
#define MISC_REG_RINGOSC_TOP_3_ENABLE_SIZE 1
#define MISC_REG_RINGOSC_TOP_3_SEL0 0xa358UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
#define MISC_REG_RINGOSC_TOP_3_SEL0_SIZE 1
#define MISC_REG_RINGOSC_TOP_3_SEL1 0xa35cUL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1. Global register.
#define MISC_REG_RINGOSC_TOP_3_SEL1_SIZE 1
#define MISC_REG_RINGOSC_TOP_4_ENABLE 0xa360UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
#define MISC_REG_RINGOSC_TOP_4_ENABLE_SIZE 1
#define MISC_REG_RINGOSC_TOP_4_SEL0 0xa364UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
#define MISC_REG_RINGOSC_TOP_4_SEL0_SIZE 1
#define MISC_REG_RINGOSC_TOP_4_SEL1 0xa368UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1. Global register.
#define MISC_REG_RINGOSC_TOP_4_SEL1_SIZE 1
#define MISC_REG_RINGOSC_TOP_5_ENABLE 0xa36cUL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
#define MISC_REG_RINGOSC_TOP_5_ENABLE_SIZE 1
#define MISC_REG_RINGOSC_TOP_5_SEL0 0xa370UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
#define MISC_REG_RINGOSC_TOP_5_SEL0_SIZE 1
#define MISC_REG_RINGOSC_TOP_5_SEL1 0xa374UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1. Global register.
#define MISC_REG_RINGOSC_TOP_5_SEL1_SIZE 1
#define MISC_REG_TOP_RINGOSC_MUX_SEL 0xa378UL //ACCESS:RW DataWidth:0x3 Description: Debug only: top ringosc mux select. In debug mode maps the following SEM ring oscillators to TDO output: [0] - CSEM0; [1] - XSEM0; [2] - TSEM0; [3] - USEM0; [4] - CSEM1; [5] - XSEM1; [6] - TSEM1; [7] - USEM1. Global register.
#define MISC_REG_TOP_RINGOSC_MUX_SEL_SIZE 1
#define MISC_REG_PORT_SWAP_EN 0xa39cUL //ACCESS:RW DataWidth:0x1 Description: If set the port swap feature for the GPIOs is controlled by the port swap IO (or by override register). If clear port swap feature for the GPIOs is disabled. Global register.
#define MISC_REG_PORT_SWAP_EN_SIZE 1
#define MISC_REG_SMBIO_ENABLE_GLITCH_FILTER 0xa3a4UL //ACCESS:RW DataWidth:0x1 Description: When set enables the deglitching circuit for the SMBus inputs per I2C requirement. Global register.
#define MISC_REG_SMBIO_ENABLE_GLITCH_FILTER_SIZE 1
#define MISC_REG_SCPAD_EXT_TM 0xa3a8UL //ACCESS:RW DataWidth:0x5 Description: tm bits for mcp_scpad_ext memory. Global register.
#define MISC_REG_SCPAD_EXT_TM_SIZE 1
#define MISC_REG_AEU_CLR_VPD_LATCH_SIGNAL 0xa3b4UL //ACCESS:W DataWidth:0x8 Description: write to this register results with the clear of the latched signals; one in d0 clears pxpv_misc_vpd0_attn; one in d1 clears pxpv_misc_vpd1_attn; one in d2 clears pxpv_misc_vpd2_attn; one in d3 clears pxpv_misc_vpd3_attn; one in d4 clears pxpv_misc_vpd4_attn; one in d5 clears pxpv_misc_vpd5_attn; one in d6 clears pxpv_misc_vpd6_attn; one in d7 clears pxpv_misc_vpd7_attn; read from this register return zero
#define MISC_REG_AEU_CLR_VPD_LATCH_SIGNAL_SIZE 1
#define MISC_REG_MISC_OSC40_CONTROL 0xa3b8UL //ACCESS:RW DataWidth:0x10 Description: Differential Crystal Oscillator control. [5:0] - Enabling o_cmos_p[5:0]. Once the clocks are running; user can turn off unused clock to save power: 0: pd: 1: enable; [6] - Output enabling for o_cmos_p[5:0]: 0: depends on i_resetb &; i_osccntrl[5:0]; 1: output is active; [7] - i_sel_test; Monitor XTAL CMOS output; 0: disable monitor; 1: enable monitor. [8] - i_LPG_sw; Control common mode voltage of xtal core input swing; 0: 600mV; 1: 650mV. [9] - i_sel_cur; Adjust CML current by loading distance; 0: 22mA; 1: 12mA. [12:10] - i_d2c_bias; Adjust the d2c block bias current; 000: 76 uA; 001: 240 uA; 010: 376 uA; 011: 450 uA; 100: 872 uA; 111:1.15 mA; (set 000 for low current mode only). [15:13] - i_bias; Adjust the bias master current; 000: 23 uA; 001: 30 uA; 010: 35 uA; 100: 40 uA; 111: 55 uA. Global register. Reset on POR reset.
#define MISC_REG_MISC_OSC40_CONTROL_SIZE 1
#define MISC_REG_PLL_MAIN_E40_CH0_MDIV 0xa3bcUL //ACCESS:RW DataWidth:0x8 Description: Post-divider ratio for channel-0 (divider ratio = code value). 00000000: 256; 00000001: 1; 00000010: 2; 00000011: 3; : :; 11111101: 253; 11111110: 254; 11111111: 255. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_CH0_MDIV_SIZE 1
#define MISC_REG_DRIVER_CONTROL_7 0xa3c8UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_7_SIZE 2
#define MISC_REG_DRIVER_CONTROL_8 0xa3d0UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_8_SIZE 2
#define MISC_REG_DRIVER_CONTROL_9 0xa3d8UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_9_SIZE 2
#define MISC_REG_DRIVER_CONTROL_10 0xa3e0UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_10_SIZE 2
#define MISC_REG_DRIVER_CONTROL_11 0xa3e8UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_11_SIZE 2
#define MISC_REG_DRIVER_CONTROL_12 0xa3f0UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_12_SIZE 2
#define MISC_REG_DRIVER_CONTROL_13 0xa3f8UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_13_SIZE 2
#define MISC_REG_IPOR_CMD_REG 0xa414UL //ACCESS:RW DataWidth:0x1 Description: Writing this bit as a '1' will cause the chip to do an internal reset exactly like a power-up reset. There is not protection for this request and it may cause any current PCI cycle to lock up. Global register. Reset on hard reset.
#define MISC_REG_IPOR_CMD_REG_SIZE 1
#define MISC_REG_UNPREPARED 0xa424UL //ACCESS:RW DataWidth:0x1 Description: Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare;1-unprepare. Global register. Reset on hard reset.
#define MISC_REG_UNPREPARED_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42cUL //ACCESS:R DataWidth:0x20 Description: read first 32 bit after inversion of function 0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430UL //ACCESS:R DataWidth:0x20 Description: read first 32 bit after inversion of function 1. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434UL //ACCESS:R DataWidth:0x20 Description: read first 32 bit after inversion of mcp. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;
#define MISC_REG_AEU_AFTER_INVERT_1_MCP_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438UL //ACCESS:R DataWidth:0x20 Description: read second 32 bit after inversion of function 0. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43cUL //ACCESS:R DataWidth:0x20 Description: read second 32 bit after inversion of function 1. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440UL //ACCESS:R DataWidth:0x20 Description: read second 32 bit after inversion of mcp. mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
#define MISC_REG_AEU_AFTER_INVERT_2_MCP_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444UL //ACCESS:R DataWidth:0x20 Description: read third 32 bit after inversion of function 0. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448UL //ACCESS:R DataWidth:0x20 Description: read third 32 bit after inversion of function 1. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44cUL //ACCESS:R DataWidth:0x20 Description: read third 32 bit after inversion of mcp. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1;
#define MISC_REG_AEU_AFTER_INVERT_3_MCP_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450UL //ACCESS:R DataWidth:0x20 Description: read fourth 32 bit after inversion of function 0. mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454UL //ACCESS:R DataWidth:0x20 Description: read fourth 32 bit after inversion of function 1. mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458UL //ACCESS:R DataWidth:0x20 Description: read fourth 32 bit after inversion of mcp. mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity;
#define MISC_REG_AEU_AFTER_INVERT_4_MCP_SIZE 1
#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45cUL //ACCESS:W DataWidth:0xe Description: write to this register results with the clear of the latched signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP latch; one in d5 clears GRC Latched timeout attention; one in d6 clears GRC Latched reserved access attention; one in d7 clears Latched rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read from this register return zero
#define MISC_REG_AEU_CLR_LATCH_SIGNAL_SIZE 1
#define MISC_REG_GENERIC_CR_0 0xa460UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by core reset. Global register. Reset on core reset.
#define MISC_REG_GENERIC_CR_0_SIZE 1
#define MISC_REG_GENERIC_CR_1 0xa464UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by core reset. Global register. Reset on core reset.
#define MISC_REG_GENERIC_CR_1_SIZE 1
#define MISC_REG_GENERIC_HW_0 0xa468UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by hard reset. Global register.
#define MISC_REG_GENERIC_HW_0_SIZE 1
#define MISC_REG_GENERIC_HW_1 0xa46cUL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by hard reset. Global register. Reset on hard reset.
#define MISC_REG_GENERIC_HW_1_SIZE 1
#define MISC_REG_GENERIC_POR_0 0xa470UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by por reset. bit 0 is used for Vmain state machine system kill reset. If clear will not reset all the Vmain sm (backward compatible); if set will reset all the Vmain state machine. Global register. Reset on POR reset.
#define MISC_REG_GENERIC_POR_0_SIZE 1
#define MISC_REG_GENERIC_POR_1 0xa474UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by por reset. Global register. Reset on POR reset.
#define MISC_REG_GENERIC_POR_1_SIZE 1
#define MISC_REG_GENERIC_RO_0 0xa478UL //ACCESS:R DataWidth:0x20 Description: Debug only: spare RO register reset by hard reset. Global register.
#define MISC_REG_GENERIC_RO_0_SIZE 1
#define MISC_REG_GENERIC_RO_1 0xa47cUL //ACCESS:R DataWidth:0x20 Description: Debug only: spare RO register reset by hard reset. Global register.
#define MISC_REG_GENERIC_RO_1_SIZE 1
#define MISC_REG_GENERIC_RO_2 0xa480UL //ACCESS:R DataWidth:0x20 Description: Debug only: spare RO register reset by core reset. Global register.
#define MISC_REG_GENERIC_RO_2_SIZE 1
#define MISC_REG_GENERIC_RO_3 0xa484UL //ACCESS:R DataWidth:0x20 Description: Debug only: spare RO register reset by core reset. Global register.
#define MISC_REG_GENERIC_RO_3_SIZE 1
#define MISC_REG_GENERIC_RO_4 0xa488UL //ACCESS:R DataWidth:0x20 Description: Debug only: spare RO register reset by por reset. Global register.
#define MISC_REG_GENERIC_RO_4_SIZE 1
#define MISC_REG_GENERIC_RO_5 0xa48cUL //ACCESS:R DataWidth:0x20 Description: Debug only: spare RO register reset by por reset. Global register.
#define MISC_REG_GENERIC_RO_5_SIZE 1
#define MISC_REG_GPIO 0xa490UL //ACCESS:RW DataWidth:0x20 Description: GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of these bits is written as a '1'; the corresponding GPIO bit will turn off it's drivers and become an input. This is the reset state of all GPIO pins. The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). [23-20] CLR port 1;[19-16] CLR port 0; When any of these bits is written as a '1'; the corresponding GPIO bit will drive low. The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #CLR. (reset value 0). [15-12] SET port 1;[11-8] port 0; SET When any of these bits is written as a '1'; the corresponding GPIO bit will drive high (if it has that capability). The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; RO; These bits indicate the read value of each of the eight GPIO pins. This is the result value of the pin; not the drive value. Writing these bits will have not effect. Global register.
#define MISC_REG_GPIO_SIZE 1
#define MISC_REG_GPIO_INT 0xa494UL //ACCESS:RW DataWidth:0x20 Description: GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a '1' to these bit clears the corresponding bit in the #OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0; Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1; OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input value. When the ~INT_STATE bit is set; this bit indicates the OLD value of the pin such that if ~INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in #OLD_VALUE (reset value 0). Global register.
#define MISC_REG_GPIO_INT_SIZE 1
#define MISC_REG_MAIN_SEQ_BYP_SEL 0xa4a4UL //ACCESS:RW DataWidth:0x5 Description: Debug only. main_sequencer_bypass select. For each bit; when set; the compatible bit in the ~misc_registers_main_seq_byp_val.main_seq_byp_val affects the controls; when reset; the SM affects the controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - unprepared_power_down_detection; Bit 3 - PCIE_reset_b; Bit 4 - sel_vaux_b. Global register. Reset on hard reset.
#define MISC_REG_MAIN_SEQ_BYP_SEL_SIZE 1
#define MISC_REG_MAIN_SEQ_BYP_VAL 0xa4a8UL //ACCESS:RW DataWidth:0x5 Description: Debug only. main_sequencer_bypass values. For each bit; the written value affects the control only if the compatible bit in the ~misc_registers_main_seq_byp_sel.main_seq_byp_val is set; when reset; the SM affects the controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - uprepared_power_down_detection; Bit 3 - PCIE_reset_b; Bit 4 - sel_vaux_b. Global register. Reset on hard reset.
#define MISC_REG_MAIN_SEQ_BYP_VAL_SIZE 1
#define MISC_REG_PLL_MAIN_CTRL_4 0xa4c4UL //ACCESS:RW DataWidth:0x6 Description: bit0 = Controls the glitch-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bit#1 in this regitser); reset (to 0) with hard_rst_b. bit1 =Glichless mux manual setting has affect when bit#0 = 1: 0-select USPLL clock; 1-select 25Mhz (ref clock); Reset (to 0) with hard_rst_b. bit 2 = Analog reset toward the USPLL; Controls the USPLL analog reset control source: 0-management power sequencer output; 1- Analog reset manual setting (bit#3 in this regitser); reset (to 0) with hard_rst_b. bit 3 = Analog reset toward the USPLL; Controls the USPLL analog reset control source: 0-reset de-asserted; 1-reset assertion; reset (to 1) with hard_rst_b. E65 oly:bit 4 = Digital reset toward the USPLL; Controls the USPLL digital reset control source: 0-management power sequencer output; 1- Digital reset manual setting (bit#5 in this regitser); reset (to 0) with hard_rst_b. bit 5 = Digital reset toward the USPLL; Controls the USPLL digital reset control source: 0-reset de-asserted; 1-reset assertion; reset (to 1) with hard_rst_b. The whole register is Global united. Reset on POR reset.
#define MISC_REG_PLL_MAIN_CTRL_4_SIZE 1
#define MISC_REG_PLL_MAIN_MISC_LOCK 0xa4c8UL //ACCESS:R DataWidth:0x1 Description: main pll lock signals. 0-unlocked; 1-locked. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_MISC_LOCK_SIZE 1
#define MISC_REG_PLL_MAIN_OTP_CTRL_1 0xa4ccUL //ACCESS:R DataWidth:0x20 Description: UNUSED for E65
#define MISC_REG_PLL_MAIN_OTP_CTRL_1_SIZE 1
#define MISC_REG_PLL_MAIN_OTP_CTRL_2 0xa4d0UL //ACCESS:R DataWidth:0x3 Description: UNUSED for E65
#define MISC_REG_PLL_MAIN_OTP_CTRL_2_SIZE 1
#define MISC_REG_PLL_MAIN_OTP_CTRL_3_M1DIV 0xa4d4UL //ACCESS:R DataWidth:0x8 Description: UNUSED for E65
#define MISC_REG_PLL_MAIN_OTP_CTRL_3_M1DIV_SIZE 1
#define MISC_REG_PLL_MAIN_OTP_CTRL_3_M2DIV 0xa4d8UL //ACCESS:R DataWidth:0x8 Description: UNUSED for E65
#define MISC_REG_PLL_MAIN_OTP_CTRL_3_M2DIV_SIZE 1
#define MISC_REG_PLL_MAIN_OTP_CTRL_3_N 0xa4dcUL //ACCESS:R DataWidth:0x9 Description: UNUSED for E65
#define MISC_REG_PLL_MAIN_OTP_CTRL_3_N_SIZE 1
#define MISC_REG_PLL_STORM_MISC_LOCK 0xa4e0UL //ACCESS:R DataWidth:0x1 Description: storm pll lock signals. 0-unlocked; 1-locked. Global register.
#define MISC_REG_PLL_STORM_MISC_LOCK_SIZE 1
#define MISC_REG_PWR_ATTN 0xa4e4UL //ACCESS:RW DataWidth:0x1 Description: This bit indicates that a Vmain powerdown event occurred. Write 0 to clear the event. Global register. Reset on hard reset.
#define MISC_REG_PWR_ATTN_SIZE 1
#define MISC_REG_RESET_CONFIG 0xa4e8UL //ACCESS:RW DataWidth:0x20 Description: reset configuration register. inside order of the bits is: [0-1] reserved; [2] rst_pxp_rq_rd_wr_auto_mode (0- no auto deassertion; 1 - auto deassertion);[3] rst_pxp_auto_mode (0- no auto deassertion; 1 - auto deassertion); [4] rst_pxpv_auto_mode (0- no auto deassertion; 1 - auto deassertion); [5] rst_rbcp_auto_mode (0- no auto deassertion; 1 - auto deassertion); [6] reserved; [7] rst_mcp_n_reset_reg_hard_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [8] rst_mcp_n_hard_core_rst_b_auto_mode (0- no auto deassertion; 1 - auto deassertion); [9] rst_mcp_n_reset_cmn_cpu_auto_mode (0- no auto deassertion; 1 - auto deassertion); [10] rst_mcp_n_reset_cmn_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [11-12] reserved; [13] rst_dbg_auto_mode (0- no auto deassertion; 1 - auto deassertion); [14] rst_misc_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [15] rst_dbue_auto_mode (0- no auto deassertion; 1 - auto deassertion); [16] grc_reset_assert_on_core_rst (0 - no; 1 - yes); [17] rst_mcp_n_reset_cmn_cpu_assert_on_core_rst (0 - no; 1 - yes); [18] rst_mcp_n_reset_cmn_core_assert_on_core_rst (0 - no; 1 - yes); [19] rst_rbcn_assert_on_core_rst (0 - no; 1 - yes); [20] rst_dbg_assert_on_core_rst (0 - no; 1 - yes); [21] rst_misc_core_assert_on_core_rst (0 - no; 1 - yes); [22] rst_dbue_assert_on_core_rst (0 - no; 1 - yes); [23] wrappers_iddq_and_rst_signals_assert_on_core_rst (0 - no; 1 - yes); [24] rst_atc_auto_mode (0- no auto deassertion; 1 - auto deassertion);[25] rst_pglc_auto_mode (0- no auto deassertion; 1 - auto deassertion); [26-31] reserved; Global register. Reset on hard reset.
#define MISC_REG_RESET_CONFIG_SIZE 1
#define MISC_REG_SHIFT1_CMD 0xa4ecUL //ACCESS:RW DataWidth:0x20 Description: 31:13 Unused RO;12:8 SHIFT_SELECT Selects the data to be loaded from the OTP into SHIFT_DATA. RW 7:4 Unused RO 3 LOAD_DATA Load a 32-bit word from the 1024-bit parallel bus to SHIFT_DATA as selected by the SHIFT_SELECT bits. RW 2 SHIFT_START Shift 32-bit redundancy data bits into shift chain. RW 1 SHIFT_DONE Indicate SHIFT_START has completed. RW 0 RESET_MODE_N Indicate the shift controller is in RESET_MODE; 0=RESET_MODE; 1=not in RESET_MODE. RO. Global register.
#define MISC_REG_SHIFT1_CMD_SIZE 1
#define MISC_REG_SHIFT1_DATA 0xa4f0UL //ACCESS:RW DataWidth:0x20 Description: In RESET_MODE when SHIFT_START is asserted; this register loads the 32-bit OTP data selected with SHIFT_SELECT. When written to this register this loads wr_data which is used for the next shift. When LOAD_DATA is asserted; this register loads the 32-bit data selected by SHIFT_SELECT. When shift is requested; this data is shifted data out while shifting serial data in. Global register.
#define MISC_REG_SHIFT1_DATA_SIZE 1
#define MISC_REG_SHIFT2_CMD 0xa4f4UL //ACCESS:RW DataWidth:0x20 Description: 31:13 Unused RO 12:8 SHIFT_SELECT Selects the data to be loaded from the OTP into SHIFT_DATA. RW 7:4 Unused RO 3 LOAD_DATA Load a 32-bit word from the 1024-bit parallel bus to SHIFT_DATA as selected by the SHIFT_SELECT bits. RW 2 SHIFT_START Shift 32-bit redundancy data bits into shift chain. RW 1 SHIFT_DONE Indicate SHIFT_START has completed. RW 0 RESET_MODE_N Indicate the shift controller is in RESET_MODE; 0=RESET_MODE; 1=not in RESET_MODE. RO. Global register.
#define MISC_REG_SHIFT2_CMD_SIZE 1
#define MISC_REG_SHIFT2_DATA 0xa4f8UL //ACCESS:RW DataWidth:0x20 Description: In RESET_MODE when SHIFT_START is asserted; this register loads the 32-bit OTP data selected with SHIFT_SELECT. When written to this register this loads wr_data which is used for the next shift. When LOAD_DATA is asserted; this register loads the 32-bit data selected by SHIFT_SELECT. When shift is requested; this data is shifted data out while shifting serial data in. Global register.
#define MISC_REG_SHIFT2_DATA_SIZE 1
#define MISC_REG_SPIO 0xa4fcUL //ACCESS:RW DataWidth:0x20 Description: SPIO. [31-24] FLOAT When any of these bits is written as a '1'; the corresponding SPIO bit will turn off it's drivers and become an input. This is the reset state of all SPIO pins. The read value of these bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits is written as a '1'; the corresponding SPIO bit will drive low. The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of these bits is written as a '1'; the corresponding SPIO bit will drive high (if it has that capability). The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. (reset value 0). [7-0] VALUE RO; These bits indicate the read value of each of the eight SPIO pins. This is the result value of the pin; not the drive value. Writing these bits will have not effect. Each 8 bits field is divided as follows: [0] VAUX Enable; when pulsed low; enables supply from VAUX. (This is an output pin only; the FLOAT field is not applicable for this pin); [1] VAUX Disable; when pulsed low; disables supply form VAUX. (This is an output pin only; FLOAT field is not applicable for this pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to select VAUX supply. (This is an output pin only; it is not controlled by the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT field is not applicable for this pin; only the VALUE fields is relevant - it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP device ID select; read by UMP firmware. Global register.
#define MISC_REG_SPIO_SIZE 1
#define MISC_REG_SPIO_INT 0xa500UL //ACCESS:RW DataWidth:0x20 Description: SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the corresponding bit in the #OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding SPIO input (reset value 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE RO; These bits indicate the old value of the SPIO input value. When the ~INT_STATE bit is set; this bit indicates the OLD value of the pin such that if ~INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE RO; These bits indicate the current SPIO interrupt state for each SPIO pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is set when the SPIO input does not match the current value in #OLD_VALUE (reset value 0). Global register.
#define MISC_REG_SPIO_INT_SIZE 1
#define MISC_REG_STATUS 0xa504UL //ACCESS:R DataWidth:0x20 Description: UNUSED for E65
#define MISC_REG_STATUS_SIZE 1
#define MISC_REG_SW_TIMER_EVENT 0xa508UL //ACCESS:R DataWidth:0x8 Description: the appropriate timer had reach to zero. [0] timer1; [1] timer2; [2] timer3; [3] timer4; [4] timer5; [5] timer6; [6] timer7; [7] timer8
#define MISC_REG_SW_TIMER_EVENT_SIZE 1
#define MISC_REG_VOLTAGE_REGISTER 0xa50cUL //ACCESS:RW DataWidth:0xd Description: bit 0 MDIO_VOLTAGE_SEL; bit 1-4 MAIN_VREG_1_0_SEL; bit 5-8 MNG_VREG_1_0_SEL; bit 9-12 VREG_2_5_SEL;ECO32: bits 1-3 and 5-7 and 9-11 are inverted on the output to Vreg sel (Ex: if bits 1-4 = 0000 the output MAIN_VREG_1_0_SEL = 0111). Reset on POR. Global register.
#define MISC_REG_VOLTAGE_REGISTER_SIZE 1
#define MISC_REG_DRIVER_CONTROL_1 0xa510UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_1_SIZE 2
#define MISC_REG_DRIVER_CONTROL_2 0xa518UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_2_SIZE 2
#define MISC_REG_DRIVER_CONTROL_3 0xa520UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_3_SIZE 2
#define MISC_REG_DRIVER_CONTROL_4 0xa528UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_4_SIZE 2
#define MISC_REG_DRIVER_CONTROL_5 0xa530UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_5_SIZE 2
#define MISC_REG_DRIVER_CONTROL_6 0xa538UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_6_SIZE 2
#define MISC_REG_FUNCTION_HIDE 0xa540UL //ACCESS:RW DataWidth:0x8 Description: Bypass to the FUNC_HIDE pin. Bit 0 - bypass select; Bits[7:1] - bypass value per function (1 - function 1; 2 -function 2; etc.). When bypass select is 0 => the value is selcted depending on FUNC_HIDE pin and 4 port/2 port mode; when bypass select = 1; bypass value is selected. Global register. Reset on hard reset.
#define MISC_REG_FUNCTION_HIDE_SIZE 1
#define MISC_REG_SW_TIMER_EVENT_CLR 0xa570UL //ACCESS:W DataWidth:0x8 Description: write one for the appropriate bit will clear the appropriate event to the AEU (if the attn bit (bit 2) in the ~misc_registers_sw_timer_cfg_1.sw_timer_cfg_1[2]; ~misc_registers_sw_timer_cfg_2.sw_timer_cfg_2[2]; ~misc_registers_sw_timer_cfg_3.sw_timer_cfg_3[2]; ~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[2]; ~misc_registers_sw_timer_cfg_5.sw_timer_cfg_5[2]; ~misc_registers_sw_timer_cfg_6.sw_timer_cfg_6[2]; ~misc_registers_sw_timer_cfg_7.sw_timer_cfg_7[2]; ~misc_registers_sw_timer_cfg_8.sw_timer_cfg_8[2] is set). [0] timer1; [1] timer2; [2] timer3; [3] timer4; [4] timer5; [5] timer6; [6] timer7; [7] timer8
#define MISC_REG_SW_TIMER_EVENT_CLR_SIZE 1
#define MISC_REG_RESET_REG_1 0xa580UL //ACCESS:RW DataWidth:0x20 Description: reset reg#1;write/read one = the specific block is out of reset; write/read zero = the specific block is in reset; addr 0-wr- the write value will be written to the register; addr 1-set - one will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change) ; addr 2-clear - zero will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change); addr 3-ignore; read ignore from all addr except addr 00; inside order of the bits is: [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10] rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15] rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20] rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25] rst_cfc; [26] rst_pxp_hst; [27] rst_pxpv (global register); [28] rst_rbcp; [29] rst_hc; [30] rst_dmae; [31] rst_semi_rtc;
#define MISC_REG_RESET_REG_1_SIZE 3
#define MISC_REG_RESET_REG_2 0xa590UL //ACCESS:RW DataWidth:0x20 Description: reset reg#2;write/read one = the specific block is out of reset; write/read zero = the specific block is in reset; addr 0-wr- the write value will be written to the register; addr 1-set - one will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change) ; addr 2-clear - zero will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change); addr 3-ignore; read ignore from all addr except addr 00; inside order of the bits is: [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc(global register); [5] rst_mcp_n_reset_reg_hard_core (global register); [6] rst_mcp_n_hard_core_rst_b(global register); [7] rst_mcp_n_reset_cmn_cpu(global register); [8] rst_mcp_n_reset_cmn_core(global register); [9] rst_rbcn; [10] rst_dbg; [11] rst_misc_core(global register); [12] rst_dbue (UART)(global register); [13] Pci_resetmdio_n(global register); [14] rst_emac0_hard_core; [15] rst_emac1_hard_core;[16] rst_pxp_rq_rd_wr;[17] rst_atc;[18] rst_cnig;[19] rst_pglc (global register); [20] rst_umac0; [21] rst_umac1; [22] rst_xmac; [23] rst_xmac_soft; [24] rst_mstat0; [25] rst_mstat1; [31:26] reserved
#define MISC_REG_RESET_REG_2_SIZE 3
#define MISC_REG_SW_TIMER_VAL 0xa5c0UL //ACCESS:RW DataWidth:0x20 Description: the value of the counter for sw timers1-8. there are 8 addresses in this register. addres 0 - timer 1; address 1 - timer 2; etc ; address 7 - timer 8
#define MISC_REG_SW_TIMER_VAL_SIZE 8
#define MISC_REG_DRIVER_CONTROL_14 0xa5e0UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_14_SIZE 2
#define MISC_REG_DRIVER_CONTROL_15 0xa5e8UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_15_SIZE 2
#define MISC_REG_DRIVER_CONTROL_16 0xa5f0UL //ACCESS:RW DataWidth:0x20 Description: The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted).
#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600UL //ACCESS:RW DataWidth:0x20 Description: Represent the status of the input vector to the AEU when a system kill occurred. The register is reset in por reset. Mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt. Reset on POR reset.
#define MISC_REG_AEU_SYS_KILL_STATUS_0_SIZE 1
#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604UL //ACCESS:RW DataWidth:0x20 Description: Represent the status of the input vector to the AEU when a system kill occurred. The register is reset in por reset. Mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt. Reset on POR reset.
#define MISC_REG_AEU_SYS_KILL_STATUS_1_SIZE 1
#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608UL //ACCESS:RW DataWidth:0x20 Description: Represent the status of the input vector to the AEU when a system kill occurred. The register is reset in por reset. Mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1. Reset on POR reset.
#define MISC_REG_AEU_SYS_KILL_STATUS_2_SIZE 1
#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60cUL //ACCESS:RW DataWidth:0x20 Description: Represent the status of the input vector to the AEU when a system kill occurred. The register is reset in por reset. Mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity. Reset on POR reset.
#define MISC_REG_AEU_SYS_KILL_STATUS_3_SIZE 1
#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610UL //ACCESS:RW DataWidth:0x1 Description: If set a system kill occurred. Reset on POR reset.
#define MISC_REG_AEU_SYS_KILL_OCCURRED_SIZE 1
#define MISC_REG_AEU_SYS_KILL_BEHAVIOR 0xa614UL //ACCESS:RW DataWidth:0x1 Description: The System Kill enable: 0 - none; 1 - hard reset. Reset on POR reset.
#define MISC_REG_AEU_SYS_KILL_BEHAVIOR_SIZE 1
#define MISC_REG_CPU_OTP_CTRL1 0xa624UL //ACCESS:RW DataWidth:0x20 Description: [0]: start: Rising edge of the signal will execute OTP command. This bit should be kept high during the execution of the command (until the command_done goes high). This bit should be set to Low and high again for the next command execution to start; [5:1]: Command: 0: Read; 1: OTP_ProgEnable (OTP must be put in ProgEnable mode by writing 0xF; 0x4; 0x8; 0xD in sequence with OTP_ProgEnable command before you do any actual write to OTP. Sequence Data is taken from bitsel bus and therefore word_address and wdata do not play any role during this authentication process; 2: OTP_ProgDisable (Disable OTP with this command once you are done with programming); 3: Verify( vsel and tm are used from control bits); 4: Init (vsel and tm are used from strap module); 5: lock_cmd. used to program the lock bits that can not be programmed by using regular program bit and program Word cmd. OTP word address 6 and 7 are allocated for lock bits and to program these bits lock command must be used; 6: stby (Not used in this IP); 7: wakeup (Not used in this IP); 9: Prescreen test. Upon getting a prescrn_cmd; word_addr; and bit_sel; otp_controller keeps reading(simple read) the OTP MEMORY SPACE until it reaches the max word_addr or it finds any programmed bit; 10: Program Bit; 11: Program Word; 12: burnin. Upon getting a burnin_cmd; word_addr; and bit_sel; otp_controller keeps reading(simple read) the OTP MEMORY SPACE. It keeps looping until the cmd is changed from burnin to something else; 13: auto_reload; 14: ovst_read; 15: ovst_prog; [8:6]: rsvd; [9]: wrp_prog_in_debug (debug_mode): wrp_prog_in_debug signal is used to overwrite some strap values; [10]: wrp_read2x (debug_mode): 1 =read 2 redundant fuses from otp; 0=1 fuse; [11]: wrp_read4x (debug_mode): 1 = read 4 redundant fuses from otp; 0 = 1 fuse; [12]: wrp_doublefuse (debug_mode): 1 = program 2 redundant fuses in otp; 0=1 fuse; [13]: wrp_quadfuse (debug_mode): 1 = program 4 redundant fuses from otp; 0=1 fuse; [16:14]: wrp_regc_sel (debug_mode): OTP regulator select levels that control the internal regulator voltage; [17]: wrp_double_word: 1= read/write 2 OTP word; 0= read/write 1 OTP word. If OTP_DOUT_DATA_SIZE >32; wrp_double_word value is ignored because 2 word read/write is prohibited; [18]: Program_verify_flag: Controls pass/fail criteria for fuse_verify with read2x/read4 during programming. For Quad Fuse: If prog_verify_flag =1; all 4 fuses has to be verified and passed individually in order to say that programming of the bit is successful. If prog_verify_flag =0; all 4 fuses has to be verified but if any one of the fuses passes individually then the programming of the bit is successful. For Double Fuse: If prog_verify_flag =1; both fuses has to be verified and passed individually in order to say that programming of the bit is successful. If prog_verify_flag =0; all 4 fuses has to be verified but if any one of the fuses passes individually then the programming of the bit is successful; [19]: wrp_continue_on_fail: 0 = OTP wrapper module stays in PROG_FAIL state forever with prog fail OR until reset is applied (or this bit is made 1). 1= OTP will set the FAIL status and continue to accept commands. Please note that even if this bit is 0; the otp module will not hang and the status indicates that there was programming failure. It is only the wrapper module that hangs. Command_done signal will be asserted even in this condition; [20]: otp_debug_mode: Causes bits [19:5] to be used for direct OTP control - used by the library group for debugging. The bits [19:5] are control bits of the OTP memory that can be programmed using software (CPU interface); [21]: otp_prog_en: Only when otp_prog_en is 1; otp programming from cpu side is enabled. Set this pin to 0 will disable otp programming from cpu side; [23:22]: access_mode: 01= manufacturing area; 10= configuration bits area; 11= ram repair bits area. The modes 01; 10 and 11 are used during prog_bit and prog_word commands. There is no need to set this access mode during read; [24]: burst_start_sel: Used during word program command. 0=data from the OTP memory is sent out; 1= Valid returned for programmed bits is sent out (used to debug the failed bits during burst program); [28:25]: cpu_debug_sel : Select signal used to define if data or debug signals are sent to the o_otp_cpu_data output; [29]: testcol(debug mode): OTP test column Read/write enable mode. Only bit mode programming is used to program the test column. Access mode does not need to be set. Bitsel is ignored. Secure control is bypassed for test column. Prescreen is supported for test column; [30]: read_fout: Fout data will be on rdata bus when this bit is set; [31]: bypass_otp_clk: This bit; if set; replaces i_jtag_otp_clk by i_jtag_ser_clk throughout the JTAG_OTP IP. This control bit affects only CPU transactions. USE_TCK_IN_CPU_MODE define should be used for this bit to be effective. Global register.
#define MISC_REG_CPU_OTP_CTRL1_SIZE 1
#define MISC_REG_CPU_OTP_CTRL2 0xa628UL //ACCESS:RW DataWidth:0x20 Description: [8:0] - wrp_tm (debug_mode): OTP timing margin control ; [16:9] - wrp_vsel (debug_mode): OTP verify select level; [20:17] - wrp_cpc_sel (debug_mode): Charge pump select levels that control the strength (voltage and current) of the OTP internal charge pump; [24:21] - wrp_pcount (debug_mode): Program Pulse count; [25] - Wrp_sadbyp (debug_mode): SenseAmp Delay bypass for OTP; [26] - Wrp_pbyp (debug_mode): OTP cell clock control in debug mode; [27] - Wrp_fuselsel0: Fusesel0 in debugmode; [28] - Cpu_disbale_otp: Disables any command execution through CPU interface; [29] - Unused; [30] - Hw_reader_restart: Restart enable for HW OTP reader block. If it is set then HW OTP reader block starts read from OTP from the beginning. It is applicable only with Otp_select_en = 0; [31] - Otp_select_en: Select enable to OTP block: when set then MISC access to OTP; when reset then HW OTP reader block access to OTP is enabled. Global register.
#define MISC_REG_CPU_OTP_CTRL2_SIZE 1
#define MISC_REG_CPU_OTP_WRITE_DATA 0xa630UL //ACCESS:RW DataWidth:0x20 Description: SHARED: Used to provide write data with burst write command from CPU side. Global register.
#define MISC_REG_CPU_OTP_WRITE_DATA_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700UL //ACCESS:R DataWidth:0x20 Description: Read fifth 32 bit after inversion of function 0. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_1 0xa704UL //ACCESS:R DataWidth:0x20 Description: Read fifth 32 bit after inversion of function 1. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_1_SIZE 1
#define MISC_REG_AEU_AFTER_INVERT_5_MCP 0xa708UL //ACCESS:R DataWidth:0x20 Description: Read fifth 32 bit after inversion of mcp. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved;
#define MISC_REG_AEU_AFTER_INVERT_5_MCP_SIZE 1
#define MISC_REG_AEU_SYS_KILL_STATUS_4 0xa70cUL //ACCESS:RW DataWidth:0x20 Description: Represent the status of the input vector to the AEU when a system kill occurred. The register is reset in por reset. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 parity; [31-10] Reserved; Reset on POR reset.
#define MISC_REG_AEU_SYS_KILL_STATUS_4_SIZE 1
#define MISC_REG_VOLTAGE_REG_OVWR 0xa71cUL //ACCESS:RW DataWidth:0x2 Description: ~misc_registers_volatge_register overwrite. 00 - voltage register defines the value of MDIO_VOLTAGE_SEL (path 0 and path1); 01 - MDIO_VOLTAGE_SEL is forced to 0; 10 - MDIO_VOLTAGE_SEL is forced to 1. Global register. Reset on POR.
#define MISC_REG_VOLTAGE_REG_OVWR_SIZE 1
#define MISC_REG_PORT4MODE_EN_OVWR 0xa720UL //ACCESS:RW DataWidth:0x2 Description: 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 - the port4mode_en output is equal to 4 port mode input pin; if it is 1 - the port4mode_en output is equal to bit[1] of this register; [1] - Overwrite value. If bit[0] of this register is 1 this is the value that receives the port4mode_en output. Reset on Hard reset.
#define MISC_REG_PORT4MODE_EN_OVWR_SIZE 1
#define MISC_REG_SWREG_MGMT_PWRDN 0xa724UL //ACCESS:RW DataWidth:0x1 Description: SW Regulator power down. Reset on POR reset.
#define MISC_REG_SWREG_MGMT_PWRDN_SIZE 1
#define MISC_REG_SWREG_MGMT_CTRL 0xa728UL //ACCESS:RW DataWidth:0x20 Description: SW Regulator management control: [3:0] - ADJ (Softstart oscillator adjustment); [7:4] - ADJ1P2 (Integrator adjustment); [11:8] - NOVL_DELAY1P2 (Non Overlap Delay for external switch drivers on 1.2V regulator); [13:12] - OSC_FREQ (Switching oscillator frequency control); [15:14] rsvd; [17:16] - OVCUR_PROT (Over-current Protection threshold); [19:18] - LDO_CTRL (LDO Control); [22:20] - RAMP1P2 (Ramp current control for 1.2V regulator); [23] - rsvd3; [27:24] - SEL2P5 (selects the voltage of the LDO); [31:28] - VSELECT(Voltage output selection). Reset on POR reset.
#define MISC_REG_SWREG_MGMT_CTRL_SIZE 1
#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72cUL //ACCESS:RW DataWidth:0x2 Description: 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the path_swap output is equal to 2 port mode path swap input pin; if it is 1 - the path_swap output is equal to bit[1] of this register; [1] - Overwrite value. If bit[0] of this register is 1 this is the value that receives the path_swap output. Reset on Hard reset.
#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR_SIZE 1
#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734UL //ACCESS:RW DataWidth:0x2 Description: 4 port port swap overwrite.[0] - Overwrite control; if it is 0 - the port_swap output is equal to 4 port mode port swap input pin; if it is 1 - the port_swap output is equal to bit[1] of this register; [1] - Overwrite value. If bit[0] of this register is 1 this is the value that receives the port_swap output. Reset on Hard reset.
#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR_SIZE 1
#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738UL //ACCESS:RW DataWidth:0x2 Description: 4 port path swap overwrite.[0] - Overwrite control; if it is 0 - the path_swap output is equal to 4 port mode path swap input pin; if it is 1 - the path_swap output is equal to bit[1] of this register; [1] - Overwrite value. If bit[0] of this register is 1 this is the value that receives the path_swap output. Reset on Hard reset.
#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR_SIZE 1
#define MISC_REG_NIG_DBG_VECTOR 0xa74cUL //ACCESS:RW DataWidth:0x1 Description: NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 - NIG1 debug vector is output to IFMUX.
#define MISC_REG_NIG_DBG_VECTOR_SIZE 1
#define MISC_REG_CLK_ENABLE 0xa774UL //ACCESS:RW DataWidth:0xb Description: Clock enable. [0] - clk_nm_e0: If 1 the clock of NM engine0 sub-chip is enabled; if 0 the clock of NM engine0 sub-chip is disabled. [1] - clk_nm_e1: If 1 the clock of NM engine1 sub-chip is enabled; if 0 the clock of NM engine1 sub-chip is disabled. [2] - clk_host: If 1 the clock iof HOST sub-chip is enabled; if 0 the clock of HOST sub-chip is disabled. [3] - clk_e0: If 1 the clock of CPT engine0 sub-chip is enabled; if 0 the clock of CPT engine0 sub-chip is disabled. [4] - clk_e1: If 1 the clock of CPT engine1 sub-chip is enabled; if 0 the clock of CPT engine1 sub-chip is disabled. [5] - clk_st_e0: If 1 the storm clock of engine0 is enabled; if 0 the storm clock of engine0 is disabled. [6] - clk_st_e1: If 1 the storm clock of engine1 is enabled; if 0 the storm clock of engine1 is disabled. [7] - clk_pci_host: If 1 the PCI clock of HOST sub-chip is enabled; if 0 the PCI clock of HOST sub-chip is disabled. [8] - clk_pci_e0: If 1 the PCI clock of CPT engine0 sub-chip is enabled; if 0 the PCI clock of CPT engine0 sub-chip is disabled. [9] - clk_pci_e1: If 1 the PCI clock of CPT engine1 sub-chip is enabled; if 0 the PCI clock of CPT engine1 sub-chip is disabled. [10] - clk_cfg: If 1 the PCI cfg clock is enabled; if 0 the PCI cfg clock is disabled.
#define MISC_REG_CLK_ENABLE_SIZE 1
#define MISC_REG_FOUR_PORT_SHARED_MDIO_EN 0xa778UL //ACCESS:RW DataWidth:0x1 Description: When set this will allow any of the four emacs MDIO masters to initiate MDIO transactions to access XGXS0 or the four external GPHYs. Drives misc_cnig_mux_4port_shared_mdio_en output. Applicable both in 2-port and 4-port mode. Global register.
#define MISC_REG_FOUR_PORT_SHARED_MDIO_EN_SIZE 1
#define MISC_REG_SEL_DBG_IFMUX_TEST 0xa77cUL //ACCESS:RW DataWidth:0x1 Description: NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by NIG; If 1 - path1 gmii/mii emac debug outputs are selected by NIG. Drives output misc_cnig_sel_dbg_ifmux_test.
#define MISC_REG_SEL_DBG_IFMUX_TEST_SIZE 1
#define MISC_REG_EXT_PHY_MODE_STRAPS_OVWR 0xa780UL //ACCESS:RW DataWidth:0x5 Description: PHY mode straps overwrite.[0] - Overwrite control; if it is 0 - the PHY mode straps output (misc_cnig_ext_phy_mode_straps) is equal to {TEST_IN[0];TEST_IN[1];EJTAG_TMS;EJTAG_TDI} input pin (ifmux_misc_ext_phy_mode_straps); if it is 1 - the PHY mode straps output (misc_cnig_ext_phy_mode_straps) is equal to bits[4:1] of this register; [4:1] - Overwrite value. If bit[0] of this register is 1 this is the value that receives the PHY mode straps output (misc_cnig_ext_phy_mode_straps). Global register. Reset on Hard reset.
#define MISC_REG_EXT_PHY_MODE_STRAPS_OVWR_SIZE 1
#define MISC_REG_UNPREPARED_FW 0xa788UL //ACCESS:RW DataWidth:0x1 Description: Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare;1-unprepare. Global register. Reset on hard reset.
#define MISC_REG_UNPREPARED_FW_SIZE 1
#define MISC_REG_UNPREPARED_DR 0xa78cUL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Set by the Driver to remember if one or more of the drivers is/are loaded; 0-prepare;1-unprepare. Reset on hard reset.
#define MISC_REG_UNPREPARED_DR_SIZE 1
#define MISC_REG_CPMU_LP_MCP_EARLY_EXIT_P0 0xa7ccUL //ACCESS:W DataWidth:0x1 Description: MCP (FW) Early EEE LPI Exit. When writing 1 indicates that the MCP (FW) expecting activity in the near future and the SM should begin exiting EEE LPI mode. Clock 25MHz.
#define MISC_REG_CPMU_LP_MCP_EARLY_EXIT_P0_SIZE 1
#define MISC_REG_CPMU_LP_MCP_EARLY_EXIT_P1 0xa7d0UL //ACCESS:W DataWidth:0x1 Description: MCP (FW) Early EEE LPI Exit. When writing 1 indicates that the MCP (FW) expecting activity in the near future and the SM should begin exiting EEE LPI mode. Clock 25MHz.
#define MISC_REG_CPMU_LP_MCP_EARLY_EXIT_P1_SIZE 1
#define MISC_REG_CPMU_LP_MCP_EARLY_EXIT_L1 0xa7d4UL //ACCESS:W DataWidth:0x1 Description: MCP (FW) Early L1 Exit. When writing 1 indicates that the MCP (FW) expecting activity in the near future and the SM should begin exiting L1 mode. Clock 25MHz. Global register.
#define MISC_REG_CPMU_LP_MCP_EARLY_EXIT_L1_SIZE 1
#define MISC_REG_ALT_CLK_SELECT 0xa7d8UL //ACCESS:RW DataWidth:0x1 Description: PCI SERDES alternate clock selector. When 0 - 250MHz. When 1 -25MHz. Global register. Reset on hard reset.
#define MISC_REG_ALT_CLK_SELECT_SIZE 1
#define MISC_REG_MCP_ROM_TM 0xa848UL //ACCESS:RW DataWidth:0x20 Description: mcp_rom_tm. Global register.
#define MISC_REG_MCP_ROM_TM_SIZE 1
#define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84cUL //ACCESS:RW DataWidth:0x1 Description: FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_FW_ENABLE_P0_SIZE 1
#define MISC_REG_CPMU_LP_FW_ENABLE_P1 0xa850UL //ACCESS:RW DataWidth:0x1 Description: FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_FW_ENABLE_P1_SIZE 1
#define MISC_REG_CPMU_LP_FW_ENABLE_L1 0xa854UL //ACCESS:RW DataWidth:0x1 Description: FW L1 Enable. When 1 indicates that L1 mode is enabled by FW. When 0 indicates that the L1 mode is disabled by FW. Clock 25MHz. Global register. Reset on hard reset.
#define MISC_REG_CPMU_LP_FW_ENABLE_L1_SIZE 1
#define MISC_REG_CPMU_LP_DR_ENABLE 0xa858UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Driver EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled by driver. When 0 indicates that the EEE LPI mode is disabled by driver. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_DR_ENABLE_SIZE 1
#define MISC_REG_CPMU_LP_DR_ENABLE_L1 0xa85cUL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Driver L1 Enable. When 1 indicates that L1 mode is enabled by driver. When 0 indicates that the L1 mode is disabled by driver. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_DR_ENABLE_L1_SIZE 1
#define MISC_REG_CPMU_LP_DR_EARLY_EXIT 0xa860UL //ACCESS:W DataWidth:0x1 SPLIT:8 Description: Driver Early EEE LPI Exit. When 1 indicates that the driver expecting activity in the near future and the SM should begin exiting EEE LPI mode. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_DR_EARLY_EXIT_SIZE 1
#define MISC_REG_CPMU_LP_DR_EARLY_EXIT_L1 0xa864UL //ACCESS:W DataWidth:0x1 SPLIT:8 Description: Driver Early L1 Exit. When 1 indicates that the driver expecting activity in the near future and the SM should begin exiting L1 mode. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_DR_EARLY_EXIT_L1_SIZE 1
#define MISC_REG_CPMU_LP_FORCE_REQ_P0 0xa868UL //ACCESS:RW DataWidth:0x1 Description: Force EEE LPI. When 1 indicates to force EEE LPI request to the MACs. When 0 the EEE LPI request is defined based on the normal conditions. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_FORCE_REQ_P0_SIZE 1
#define MISC_REG_CPMU_LP_FORCE_REQ_P1 0xa86cUL //ACCESS:RW DataWidth:0x1 Description: Force EEE LPI. When 1 indicates to force EEE LPI request to the MACs. When 0 the EEE LPI request is defined based on the normal conditions. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_FORCE_REQ_P1_SIZE 1
#define MISC_REG_CPMU_LP_FORCE_REQ_L1 0xa870UL //ACCESS:RW DataWidth:0x1 Description: Force L1. When 1 indicates to force L1 request to the MACs. When 0 the L1 request is defined based on the normal conditions. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_FORCE_REQ_L1_SIZE 1
#define MISC_REG_CPMU_LP_OVERRIDE_SM_P0 0xa874UL //ACCESS:RW DataWidth:0x2 Description: EEE LPI Override. [0] - EEE LPI Override Control. When 1 the SM EEE LPI request is overrode by bit 1. When 0 the SM EEE LPI request is driven by the SM. [1] - EEE LPI Override Value. Indicates the value of EEE LPI request when bit 0 is asserted. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_OVERRIDE_SM_P0_SIZE 1
#define MISC_REG_CPMU_LP_OVERRIDE_SM_P1 0xa878UL //ACCESS:RW DataWidth:0x2 Description: EEE LPI Override. [0] - EEE LPI Override Control. When 1 the SM EEE LPI request is overrode by bit 1. When 0 the SM EEE LPI request is driven by the SM. [1] - EEE LPI Override Value. Indicates the value of EEE LPI request when bit 0 is asserted. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_OVERRIDE_SM_P1_SIZE 1
#define MISC_REG_CPMU_LP_OVERRIDE_SM_L1 0xa87cUL //ACCESS:RW DataWidth:0x2 Description: L1 Override. [0] - L1 Early Exit Override Control. When =1 the SM L1 Early Exit request is overrode by bit 1.When =0 the SM L1 early Exit request is driven by the SM or by the Force bit. [1] - L1 Early Exit Override Value. Indicates the value of L1 Early Exit request when bit 0 is asserted: 1 indicates low power state - L1 early request is driven to 0 (indication to the PCIE CORE that it is ok to go to L1 ASPM). 0 indicates normal power state - L1 early request is driven to 1 (indication to the PCIE CORE to get out L1 ASPM). Clock 25MHz. Global register. Reset on hard reset.
#define MISC_REG_CPMU_LP_OVERRIDE_SM_L1_SIZE 1
#define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880UL //ACCESS:RW DataWidth:0x12 Description: LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that the Vmain SM end state is disabled. When 0 indicates that the Vmain SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that the FW command that all Queues are empty is disabled. When 0 indicates that the FW command that all Queues are empty is enabled. [2] - FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early Exit command is disabled. When 0 indicates that the FW Early Exit command is enabled. This bit applicable only in the EXIT Events Mask registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request indication is disabled. When 0 indicates that the PBF Request indication is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF Request indication is disabled. When 0 indicates that the Tx Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. When 0 indicates that the RX EEE LPI Status indication is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the LPI Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that the Tx Pause indication is disabled. When 0 indicates that the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM IDLE indication is disabled. When 0 indicates that the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 Status indication from the PCIE CORE is disabled. When 0 indicates that the RX EEE LPI Status indication from the PCIE CORE is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 REQ indication is disabled. When =0 indicates that the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This bit is applicable only in the EXIT Events Masks registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). When =0 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_MASK_ENT_P0_SIZE 1
#define MISC_REG_CPMU_LP_MASK_ENT_P1 0xa884UL //ACCESS:RW DataWidth:0x12 Description: EEE LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that the Vmain SM end state is disabled. When 0 indicates that the Vmain SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that the FW command that all Queues are empty is disabled. When 0 indicates that the FW command that all Queues are empty is enabled. [2] - FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early Exit command is disabled. When 0 indicates that the FW Early Exit command is enabled. This bit applicable only in the EXIT Events Mask registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request indication is disabled. When 0 indicates that the PBF Request indication is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF Request indication is disabled. When 0 indicates that the Tx Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. When 0 indicates that the RX EEE LPI Status indication is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that the Tx Pause indication is disabled. When 0 indicates that the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM IDLE indication is disabled. When 0 indicates that the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 Status indication from the PCIE CORE is disabled. When 0 indicates that the RX EEE LPI Status indication from the PCIE CORE is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 REQ indication is disabled. When =0 indicates that the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This bit is applicable only in the EXIT Events Masks registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). When =0 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in the EXIT Events Masks registers.Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_MASK_ENT_P1_SIZE 1
#define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888UL //ACCESS:RW DataWidth:0x12 Description: EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates that the Vmain SM end state is disabled. When 0 indicates that the Vmain SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that the FW command that all Queues are empty is disabled. When 0 indicates that the FW command that all Queues are empty is enabled. [2] - FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early Exit command is disabled. When 0 indicates that the FW Early Exit command is enabled. This bit applicable only in the EXIT Events Mask registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request indication is disabled. When 0 indicates that the PBF Request indication is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF Request indication is disabled. When 0 indicates that the Tx Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. When 0 indicates that the RX LPI Status indication is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that the Tx Pause indication is disabled. When 0 indicates that the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM IDLE indication is disabled. When 0 indicates that the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 Status indication from the PCIE CORE is disabled. When 0 indicates that the RX EEE LPI Status indication from the PCIE CORE is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 REQ indication is disabled. When =0 indicates that the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This bit is applicable only in the EXIT Events Masks registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). When =0 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in the EXIT Events Masks registers.Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_MASK_EXT_P0_SIZE 1
#define MISC_REG_CPMU_LP_MASK_EXT_P1 0xa88cUL //ACCESS:RW DataWidth:0x12 Description: EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates that the Vmain SM end state is disabled. When 0 indicates that the Vmain SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that the FW command that all Queues are empty is disabled. When 0 indicates that the FW command that all Queues are empty is enabled. [2] - FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early Exit command is disabled. When 0 indicates that the FW Early Exit command is enabled. This bit applicable only in the EXIT Events Mask registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request indication is disabled. When 0 indicates that the PBF Request indication is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF Request indication is disabled. When 0 indicates that the Tx Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. When 0 indicates that the RX EEE LPI Status indication is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that the Tx Pause indication is disabled. When 0 indicates that the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM IDLE indication is disabled. When 0 indicates that the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 Status indication from the PCIE CORE is disabled. When 0 indicates that the RX EEE LPI Status indication from the PCIE CORE is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 REQ indication is disabled. When =0 indicates that the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This bit is applicable only in the EXIT Events Masks registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). When =0 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in the EXIT Events Masks registers.Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_MASK_EXT_P1_SIZE 1
#define MISC_REG_CPMU_LP_MASK_ENT_P0_L1 0xa890UL //ACCESS:RW DataWidth:0x12 Description: L1 entry events mask. [0] - Vmain SM Mask. When 1 indicates that the Vmain SM end state is disabled. When 0 indicates that the Vmain SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that the FW command that all Queues are empty is disabled. When 0 indicates that the FW command that all Queues are empty is enabled. [2] - FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early Exit command is disabled. When 0 indicates that the FW Early Exit command is enabled. This bit applicable only in the EXIT Events Mask registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request indication is disabled. When 0 indicates that the PBF Request indication is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF Request indication is disabled. When 0 indicates that the Tx Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. When 0 indicates that the RX EEE LPI Status indication is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that the Tx Pause indication is disabled. When 0 indicates that the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM IDLE indication is disabled. When 0 indicates that the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 Status indication from the PCIE CORE is disabled. When 0 indicates that the RX EEE LPI Status indication from the PCIE CORE is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 REQ indication is disabled. When =0 indicates that the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This bit is applicable only in the EXIT Events Masks registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). When =0 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_MASK_ENT_P0_L1_SIZE 1
#define MISC_REG_CPMU_LP_MASK_ENT_P1_L1 0xa894UL //ACCESS:RW DataWidth:0x12 Description: L1 entry events mask. [0] - Vmain SM Mask. When 1 indicates that the Vmain SM end state is disabled. When 0 indicates that the Vmain SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that the FW command that all Queues are empty is disabled. When 0 indicates that the FW command that all Queues are empty is enabled. [2] - FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early Exit command is disabled. When 0 indicates that the FW Early Exit command is enabled. This bit applicable only in the EXIT Events Mask registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request indication is disabled. When 0 indicates that the PBF Request indication is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF Request indication is disabled. When 0 indicates that the Tx Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. When 0 indicates that the RX EEE LPI Status indication is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that the Tx Pause indication is disabled. When 0 indicates that the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM IDLE indication is disabled. When 0 indicates that the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 Status indication from the PCIE CORE is disabled. When 0 indicates that the RX EEE LPI Status indication from the PCIE CORE is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 REQ indication is disabled. When =0 indicates that the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This bit is applicable only in the EXIT Events Masks registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). When =0 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_MASK_ENT_P1_L1_SIZE 1
#define MISC_REG_CPMU_LP_MASK_EXT_P0_L1 0xa898UL //ACCESS:RW DataWidth:0x12 Description: L1 exit events mask. [0] - Vmain SM Mask. When 1 indicates that the Vmain SM end state is disabled. When 0 indicates that the Vmain SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that the FW command that all Queues are empty is disabled. When 0 indicates that the FW command that all Queues are empty is enabled. [2] - FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early Exit command is disabled. When 0 indicates that the FW Early Exit command is enabled. This bit applicable only in the EXIT Events Mask registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request indication is disabled. When 0 indicates that the PBF Request indication is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF Request indication is disabled. When 0 indicates that the Tx Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. When 0 indicates that the RX LPI Status indication is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that the Tx Pause indication is disabled. When 0 indicates that the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM IDLE indication is disabled. When 0 indicates that the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 Status indication from the PCIE CORE is disabled. When 0 indicates that the RX LPI Status indication from the PCIE CORE is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 REQ indication is disabled. When =0 indicates that the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This bit is applicable only in the EXIT Events Masks registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). When =0 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_MASK_EXT_P0_L1_SIZE 1
#define MISC_REG_CPMU_LP_MASK_EXT_P1_L1 0xa89cUL //ACCESS:RW DataWidth:0x12 Description: L1 exit events mask. [0] - Vmain SM Mask. When 1 indicates that the Vmain SM end state is disabled. When 0 indicates that the Vmain SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that the FW command that all Queues are empty is disabled. When 0 indicates that the FW command that all Queues are empty is enabled. [2] - FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early Exit command is disabled. When 0 indicates that the FW Early Exit command is enabled. This bit applicable only in the EXIT Events Mask registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request indication is disabled. When 0 indicates that the PBF Request indication is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF Request indication is disabled. When 0 indicates that the Tx Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. When 0 indicates that the RX EEE LPI Status indication is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that the Tx Pause indication is disabled. When 0 indicates that the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM IDLE indication is disabled. When 0 indicates that the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 Status indication from the PCIE CORE is disabled. When 0 indicates that the RX LPI Status indication from the PCIE CORE is enabled. In the EXIT Events Masks registers; this bit masks the falling edge detect of the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 REQ indication is disabled. When =0 indicates that the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This bit is applicable only in the EXIT Events Masks registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). When =0 indicates that the L1 Status Falling Edge Detect indication from the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_MASK_EXT_P1_L1_SIZE 1
#define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0UL //ACCESS:RW DataWidth:0x20 Description: EEE LPI Idle Threshold. The threshold value for the idle EEE LPI counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_IDLE_THR_P0_SIZE 1
#define MISC_REG_CPMU_LP_IDLE_THR_P1 0xa8a4UL //ACCESS:RW DataWidth:0x20 Description: EEE LPI Idle Threshold. The threshold value for the idle EEE LPI counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_IDLE_THR_P1_SIZE 1
#define MISC_REG_CPMU_LP_IDLE_THR_L1 0xa8a8UL //ACCESS:RW DataWidth:0x20 Description: L1 Idle Threshold. The threshold value for the idle L1 counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset.
#define MISC_REG_CPMU_LP_IDLE_THR_L1_SIZE 1
#define MISC_REG_CPMU_LP_SM_ST_STAT_P0 0xa8acUL //ACCESS:RW DataWidth:0x2 Description: EEE LPI status. [0] - EEE LPI SM Request Status. When 0 the SM is not in EEE LPI state. When 1 the SM is in EEE LPI state. [1] - EEE LPI Control Request Status. This is the status of the control which is function of the EEE LPI SM; EEE LPI Override register and the EEE LPI Force register. When 0 the Control is not in EEE LPI state. When 1 the Control is in EEE LPI state. Clock 25MHz. Read only register. Reset on hard reset.
#define MISC_REG_CPMU_LP_SM_ST_STAT_P0_SIZE 1
#define MISC_REG_CPMU_LP_SM_ST_STAT_P1 0xa8b0UL //ACCESS:RW DataWidth:0x2 Description: EEE LPI status. [0] - EEE LPI SM Request Status. When 0 the SM is not in EEE LPI state. When 1 the SM is in EEE LPI state. [1] - EEE LPI Control Request Status. This is the status of the control which is function of the EEE LPI SM; EEE LPI Override register and the EEE LPI Force register. When 0 the Control is not in EEE LPI state. When 1 the Control is in EEE LPI state. Clock 25MHz. Read only register. Reset on hard reset.
#define MISC_REG_CPMU_LP_SM_ST_STAT_P1_SIZE 1
#define MISC_REG_CPMU_LP_SM_ST_STAT_L1 0xa8b4UL //ACCESS:RW DataWidth:0x2 Description: L1 status. [0] - L1 SM Request Status. When 0 the SM is not in EEE LPI state. When 1 the SM is in L1 state. [1] - EEE LPI Control Request Status. This is the status of the control which is function of the L1 SM; L1 Override register and the L1 Force register. When 0 the Control is not in L1 state. When 1 the Control is in L1 state. Clock 25MHz. Read only register. Reset on hard reset.
#define MISC_REG_CPMU_LP_SM_ST_STAT_L1_SIZE 1
#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8UL //ACCESS:RW DataWidth:0x10 Description: EEE LPI Entry Events Counter. A statistic counter with the number of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only register. Reset on hard reset.
#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0_SIZE 1
#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bcUL //ACCESS:RW DataWidth:0x10 Description: EEE LPI Entry Events Counter. A statistic counter with the number of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only register. Reset on hard reset.
#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1_SIZE 1
#define MISC_REG_CPMU_LP_SM_ENT_CNT_L1 0xa8c0UL //ACCESS:RW DataWidth:0x10 Description: L1 Entry Events Counter. A statistic counter with the number of counts that the SM entered the L1 state. Clock 25MHz. Read only register. Reset on hard reset.
#define MISC_REG_CPMU_LP_SM_ENT_CNT_L1_SIZE 1
#define MISC_REG_ERSTCLK_CLKSWITCH_BYPASS 0xa8c4UL //ACCESS:RW DataWidth:0x4 Description: eclk switches bypass. When =0 the eclk clkswitchs are functional. When =1 the eclk clkswitchs are bypassed. Bit[0] - port 0 path0;Bit[1] - port 0 path1;Bit[2] - port 1 path0;Bit[3] - port 1 path1. Global register. Reset on PLL reset.
#define MISC_REG_ERSTCLK_CLKSWITCH_BYPASS_SIZE 1
#define MISC_REG_CPMU_LP_OVERRIDE_SM_LTR2_L1 0xa8c8UL //ACCESS:RW DataWidth:0x2 Description: L1 LTR2 Override. [0] - L1 LTR2 Override Control. When =1 the SM LTR2 request is overriden by bit[1].When =0 the SM LTR2 request is driven by the SM or by the Force bit. [1] - LTR Override Value. Indicates the value of the LTR2 request when bit 0 is asserted: 1 indicates low power state - LTR2 request is driven to 1 (indication to the CPU (through PCIE CORE) that it is ok to go to low power state). 0 indicates normal power state - LTR2 request is driven to 0 (indication to the CPU (through PCIE CORE) to come out of low power state). Clock 25MHz. Global register. Reset on hard reset.
#define MISC_REG_CPMU_LP_OVERRIDE_SM_LTR2_L1_SIZE 1
#define MISC_REG_VTMON_CTRL 0xa8ccUL //ACCESS:RW DataWidth:0x10 Description: Volatge/Temperature Monitor control. [15:7] - reserved. [6:3] - 1111: Output code =1023; 1110: Output code =960; 1101: Output code =896; 1100: Output code =832; 1011: Output code =768; 1010: Output code =704; 1001: Output code =640; 1000: Output code =576; 0111: Output code =512; 0110: Output code =448; 0101: Output code =384; 0100: Output code =320; 0011: Output code =256; 0010: Output code =192; 0001: Output code =128; 0000: Output code =64. [2:0] - 111: 1.232 V; 110: 1.226 V; 101: 1.220 V; 100: 1.214 V; 011: 1.208 V; 010: 1.202 V; 001: 1.196 V; 000: 1.190 V. Global register. Reset on POR reset.
#define MISC_REG_VTMON_CTRL_SIZE 1
#define MISC_REG_VTMON_DATA 0xa8d0UL //ACCESS:R DataWidth:0xa Description: Voltage/Temperature Monitor output.Global register. Reset on POR reset.
#define MISC_REG_VTMON_DATA_SIZE 1
#define MISC_REG_VTMON_HOLD 0xa8e4UL //ACCESS:RW DataWidth:0x1 Description: Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value forever. Global register. Reset on POR reset.
#define MISC_REG_VTMON_HOLD_SIZE 1
#define MISC_REG_CPMU_CONN_CNT_P0 0xa8e8UL //ACCESS:RW DataWidth:0x20 Description: Number of Connections. Contains the value of the counter that counts the number of connections.The read order is obligatory: first address 0 read; then address 1 read. When address is 0 the 32 lsbits is read; latch the upper 8 msbits. When the address is 1 the 8 msbits is read; the read is done from the latched register. Read only register. Reset on hard reset.
#define MISC_REG_CPMU_CONN_CNT_P0_SIZE 2
#define MISC_REG_CPMU_CONN_CNT_P1 0xa8f0UL //ACCESS:RW DataWidth:0x20 Description: Number of Connections. Contains the value of the counter that counts the number of connections. The read order is obligatory: first address 0 read; then address 1 read. When address is 0 the 32 lsbits is read; latch the upper 8 msbits. When the address is 1 the 8 msbits is read; the read is done from the latched register. Read only register. Reset on hard reset.
#define MISC_REG_CPMU_CONN_CNT_P1_SIZE 2
#define MISC_REG_VTMON_PWR 0xa8f8UL //ACCESS:RW DataWidth:0x2 Description: Voltage/Temperature Monitor power control. [0] - Voltage/Temperature monitor reset (0 - asserted; 1 - de-asserted); [1] - Voltage/Temperature monitor power down (0 - power down; 1 - power up). Global register. Reset on POR reset.
#define MISC_REG_VTMON_PWR_SIZE 1
#define MISC_REG_VTMON_SEL 0xa8fcUL //ACCESS:RW DataWidth:0x3 Description: Voltage/Temperature Monitor select. [2:0] - 000: Temperature Monitor Enable; 001: Voltage Monitor input; i_VTMON_0p9V; 010: Voltage Monitor input; i_VTMON_2V:0; 011: Voltage Monitor input; i_VTMON_2V:1; 100: Voltage Monitor input; i_VTMON_2V:2; 101: Voltage Monitor input; i_VTMON_4V:0; 110: Voltage Monitor input; i_VTMON_4V:1; 111: Test Mode. Global register. Reset on POR reset.
#define MISC_REG_VTMON_SEL_SIZE 1
#define MISC_REG_PLL_MAIN_E40_CTRL_1 0xa900UL //ACCESS:RW DataWidth:0x1e Description: PLL configuration control register. [11:0]: dco_ctrl_bypass[11:0]: direct programming of DAC: 000000000000 = MIN VCO clock frequency; : ; 111111111111 = MAX VCO clock frequency; [12]: dco_ctrl_bypass_enable: enable of direct programming of DAC: 0 =normal mode; 1 =DAC programming mode; [13]: stat_reset: reset of phase error measurement: 0 =normal mode; 1 =reset; [16:14]: stat_select[2:0]: select of test output: 000 = 000000000000; 001 = minimum phase error; 010 = maximum phase error; 011 = mean-square phase error; 100 = dac control word; 101 = 000000000000; 110 = 000000000000; 111 = 000000000000; [17]: stat_update: On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout; [18]: refclkout: Enable for o_fref output: 0 = o_fref at logic 0; 1 = o_fref enabled (pre-divider output clock); [19]: AUX_CTRL: ICO current: 0 = normal mode; 1 = Ivco increased by 130 ?A; [20]: VCOdiv2_Post: Enables divide-by-2 for the clock to post-dividers: 0 = normal mode; 1 = VCO divide-by-2 clock feeds post dividers; [22:21]: Stat_mode[1:0]: Statistics Mode: 00 = disabled; 01 = phase error stats; 10 = period stats; 11 = Feedback phase error stats; [24:23]: Pwm_rate[1:0]: Set PWM rate; Vco_div2 == 0; 00 = 4 ( default); 01 = 5; 10 = 2; 11 = 3; Vco_div2 == 1; 00 = 8; 01 = 10; 10 = 4 (default when vco_div2 = 1); 11 = 6; [26:25]: vco_dly[1:0]: Adds selectable delay to VCO_CLK; 00 = nominal delay (default); 01 = One added INV/NAND2 pair; 10 = Two added INV/NAND2 pairs; 11 = Three added INV/NAND2 pairs Hook for engineering tests of the T2D; [27]: VCOdiv2: Divide VCO_CLK into T2D by 2: 0 = T2D run at VCO rate; 1 = T2D runs at VCO/2 rate Must be set to 1 above 3.2 GHz; [28]: fast_lock: Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high; 0 = 256 refclk delay; 1 = 32 refclk delay; [29]: ndiv_relock: Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes; 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode; 1 = Re-enter frequency acquisition state without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_CTRL_1_SIZE 1
#define MISC_REG_PLL_MAIN_E40_CTRL_2 0xa904UL //ACCESS:RW DataWidth:0xa Description: Configuration control register. [2:0]: i_ka[2:0]: Loop gain in frequency acquisition mode; [5:3]: i_ki[2:0]: Gain of P/I loop filter integrator path during fine phase acquisition mode; [9:6]: i_kp[3:0]: Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_CTRL_2_SIZE 1
#define MISC_REG_PLL_MAIN_E40_NDIV_FRAC 0xa908UL //ACCESS:RW DataWidth:0x14 Description: Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_NDIV_FRAC_SIZE 1
#define MISC_REG_PLL_MAIN_E40_NDIV_INT 0xa90cUL //ACCESS:RW DataWidth:0xa Description: Feedback divider control (Code = divider ratio). 0000000000: divide-by-1024; 0000000001: XXX; 0000000010: XXX; 0000000111: XXX; 0000001000: divide-by-8; 0000001001: divide-by-9; 0000001010: divide-by-10; 1111111110: divide-by-1022; 1111111111: divide-by-1023. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_NDIV_INT_SIZE 1
#define MISC_REG_PLL_MAIN_E40_PDIV 0xa910UL //ACCESS:RW DataWidth:0x3 Description: Input reference clock pre-divider control (code = divider ratio). 000: divide-by-8; 001: divide-by-1; 010: divide-by-2; 011: divide-by-3; 100: divide-by-4; 101: divide-by-5; 110: divide-by-6; 111: divide-by-7. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_PDIV_SIZE 1
#define MISC_REG_PLL_MAIN_E40_MISC_STATUS 0xa914UL //ACCESS:R DataWidth:0xc Description: STATUS (PLL test) output BUS. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_MISC_STATUS_SIZE 1
#define MISC_REG_PLL_STORM_E40_MISC_STATUS 0xa918UL //ACCESS:R DataWidth:0xc Description: STATUS (PLL test) output BUS. Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_E40_MISC_STATUS_SIZE 1
#define MISC_REG_PLL_STORM_E40_CH0_MDIV 0xa91cUL //ACCESS:RW DataWidth:0x8 Description: Post-divider ratio for channel-0 (divider ratio = code value). 00000000: 256; 00000001: 1; 00000010: 2; 00000011: 3; : :; 11111101: 253; 11111110: 254; 11111111: 255. Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_E40_CH0_MDIV_SIZE 1
#define MISC_REG_PLL_STORM_E40_CTRL_1 0xa920UL //ACCESS:RW DataWidth:0x1e Description: PLL configuration control register. [11:0]: dco_ctrl_bypass[11:0]: direct programming of DAC: 000000000000 = MIN VCO clock frequency; : ; 111111111111 = MAX VCO clock frequency; [12]: dco_ctrl_bypass_enable: enable of direct programming of DAC: 0 =normal mode; 1 =DAC programming mode; [13]: stat_reset: reset of phase error measurement: 0 =normal mode; 1 =reset; [16:14]: stat_select[2:0]: select of test output: 000 = 000000000000; 001 = minimum phase error; 010 = maximum phase error; 011 = mean-square phase error; 100 = dac control word; 101 = 000000000000; 110 = 000000000000; 111 = 000000000000; [17]: stat_update: On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout; [18]: refclkout: Enable for o_fref output: 0 = o_fref at logic 0; 1 = o_fref enabled (pre-divider output clock); [19]: AUX_CTRL: ICO current: 0 = normal mode; 1 = Ivco increased by 130 ?A; [20]: VCOdiv2_Post: Enables divide-by-2 for the clock to post-dividers: 0 = normal mode; 1 = VCO divide-by-2 clock feeds post dividers; [22:21]: Stat_mode[1:0]: Statistics Mode: 00 = disabled; 01 = phase error stats; 10 = period stats; 11 = Feedback phase error stats; [24:23]: Pwm_rate[1:0]: Set PWM rate; Vco_div2 == 0; 00 = 4 ( default); 01 = 5; 10 = 2; 11 = 3; Vco_div2 == 1; 00 = 8; 01 = 10; 10 = 4 (default when vco_div2 = 1); 11 = 6; [26:25]: vco_dly[1:0]: Adds selectable delay to VCO_CLK; 00 = nominal delay (default); 01 = One added INV/NAND2 pair; 10 = Two added INV/NAND2 pairs; 11 = Three added INV/NAND2 pairs Hook for engineering tests of the T2D; [27]: VCOdiv2: Divide VCO_CLK into T2D by 2: 0 = T2D run at VCO rate; 1 = T2D runs at VCO/2 rate Must be set to 1 above 3.2 GHz; [28]: fast_lock: Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high; 0 = 256 refclk delay; 1 = 32 refclk delay; [29]: ndiv_relock: Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes; 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode; 1 = Re-enter frequency acquisition state without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent. Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_E40_CTRL_1_SIZE 1
#define MISC_REG_PLL_STORM_E40_CTRL_2 0xa924UL //ACCESS:RW DataWidth:0xa Description: Configuration control register. [2:0]: i_ka[2:0]: Loop gain in frequency acquisition mode; [5:3]: i_ki[2:0]: Gain of P/I loop filter integrator path during fine phase acquisition mode; [9:6]: i_kp[3:0]: Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_E40_CTRL_2_SIZE 1
#define MISC_REG_PLL_STORM_E40_NDIV_FRAC 0xa928UL //ACCESS:RW DataWidth:0x14 Description: Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_E40_NDIV_FRAC_SIZE 1
#define MISC_REG_PLL_STORM_E40_NDIV_INT 0xa92cUL //ACCESS:RW DataWidth:0xa Description: Feedback divider control (Code = divider ratio). 0000000000: divide-by-1024; 0000000001: XXX; 0000000010: XXX; 0000000111: XXX; 0000001000: divide-by-8; 0000001001: divide-by-9; 0000001010: divide-by-10; 1111111110: divide-by-1022; 1111111111: divide-by-1023. Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_E40_NDIV_INT_SIZE 1
#define MISC_REG_PLL_STORM_E40_PDIV 0xa930UL //ACCESS:RW DataWidth:0x3 Description: Input reference clock pre-divider control (code = divider ratio). 000: divide-by-8; 001: divide-by-1; 010: divide-by-2; 011: divide-by-3; 100: divide-by-4; 101: divide-by-5; 110: divide-by-6; 111: divide-by-7. Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_E40_PDIV_SIZE 1
#define MISC_REG_PWRWDOG_E40_ACCU_RUN 0xa934UL //ACCESS:RW DataWidth:0x1 Description: Power watchdog. When 0 all registers and states are of power watchdog accu sub-module are reset. Global register. Reset on POR.
#define MISC_REG_PWRWDOG_E40_ACCU_RUN_SIZE 1
#define MISC_REG_PWRWDOG_E40_ACCU_SKIP 0xa938UL //ACCESS:RW DataWidth:0x2 Description: Power watchdog. Allows to decimate the good signal to measure for beats. Global register. Reset on POR.
#define MISC_REG_PWRWDOG_E40_ACCU_SKIP_SIZE 1
#define MISC_REG_PWRWDOG_E40_ACCU_SKIP_START 0xa93cUL //ACCESS:RW DataWidth:0x2 Description: Power watchdog. Start value of skip counter. Global register. Reset on POR.
#define MISC_REG_PWRWDOG_E40_ACCU_SKIP_START_SIZE 1
#define MISC_REG_PWRWDOG_E40_CGFG 0xa940UL //ACCESS:RW DataWidth:0x8 Description: Power watchdog configuration. Adjustment of integer delay cgfg[7:4] and fractional delay cgfg[3:0]; valid range [0:191]. Global register. Reset on POR.
#define MISC_REG_PWRWDOG_E40_CGFG_SIZE 1
#define MISC_REG_PWRWDOG_E40_CLEARCFG 0xa944UL //ACCESS:RW DataWidth:0x3 Description: Power watchdog selection of delay chain for the reset pulse; recommended setting is 3b100 for longest pulse; 3b010 will shorten the reset pulse by one inverter+inverting mux delay; 3b001 will shorten the reset pulse by two inverter+inverting mux delays; set clearcfg more or equal than rsel to ensure the ring gets flushed from the previous cycle; reducing the reset pulse length is needed to reach the highest possible operating frequencies.Global register. Reset on POR.
#define MISC_REG_PWRWDOG_E40_CLEARCFG_SIZE 1
#define MISC_REG_PWRWDOG_E40_DATA 0xa948UL //ACCESS:R DataWidth:0xa Description: Power watchdog data.Global register. Reset on POR.
#define MISC_REG_PWRWDOG_E40_DATA_SIZE 1
#define MISC_REG_PWRWDOG_E40_DONE 0xa94cUL //ACCESS:R DataWidth:0x1 Description: Power watchdog done. Global register. Reset on POR.
#define MISC_REG_PWRWDOG_E40_DONE_SIZE 1
#define MISC_REG_PWRWDOG_E40_PWRDN 0xa950UL //ACCESS:RW DataWidth:0x1 Description: Power watchdog power down. 1 - power down; 0 - power up.Global register. Reset on POR.
#define MISC_REG_PWRWDOG_E40_PWRDN_SIZE 1
#define MISC_REG_PWRWDOG_E40_RSEL 0xa954UL //ACCESS:RW DataWidth:0x3 Description: Power watchdog selection of delay setting of ring delay element; recommended setting is 3b100 for longest ring delay; 3b010 will shorten the ring by one inverter+inverting mux; 3b001 will shorten the ring by two inverter+inverting mux cells;Global register. Reset on POR.
#define MISC_REG_PWRWDOG_E40_RSEL_SIZE 1
#define MISC_REG_PWRWDOG_E40_START 0xa958UL //ACCESS:RW DataWidth:0x6 Description: Power watchdog. Sets the number of trips through the ring delay element to start+1; range for start is [-1:31].Global register. Reset on POR.
#define MISC_REG_PWRWDOG_E40_START_SIZE 1
#define MISC_REG_CPU_OTP_CTRL3 0xa95cUL //ACCESS:RW DataWidth:0x20 Description: CPU OTP Control Register. [10:0]: Otp_rom_address: OTP ROM Address; [30:11]: reserved; [31]: Jtag_cpu_mode: This bit must be set to enable access to the OTP ROM interface via GRC registers. If this bit is cleared; access is allowed only through the JTAG interface. Global register.
#define MISC_REG_CPU_OTP_CTRL3_SIZE 1
#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960UL //ACCESS:RW DataWidth:0x2 Description: XMAC PHY port mode. Indicates the number of ports on the Warp Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the XMAC_MP core; and should be changed only while reset is held low. Reset on Hard reset.
#define MISC_REG_XMAC_PHY_PORT_MODE_SIZE 1
#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964UL //ACCESS:RW DataWidth:0x2 Description: XMAC Core port mode. Indicates the number of ports on the system side. This should be less than or equal to phy_port_mode; if some of the ports are not used. This enables reduction of frequency on the core side. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap input for the XMAC_MP core; and should be changed only while reset is held low. Reset on Hard reset.
#define MISC_REG_XMAC_CORE_PORT_MODE_SIZE 1
#define MISC_REG_UMAC0_LPI_TX_DETECT 0xa968UL //ACCESS:R DataWidth:0x1 Description: UMAC0 transmit LPI (Low Power Indication) state. This per port signal is set to 1; whenever the transmit interface is in LPI (Low Power Indication) state and LPI_IDLES are being sent out on the TX Warpcore interface.
#define MISC_REG_UMAC0_LPI_TX_DETECT_SIZE 1
#define MISC_REG_UMAC1_LPI_TX_DETECT 0xa96cUL //ACCESS:R DataWidth:0x1 Description: UMAC1 transmit LPI (Low Power Indication) state. This per port signal is set to 1; whenever the transmit interface is in LPI (Low Power Indication) state and LPI_IDLES are being sent out on the TX Warpcore interface.
#define MISC_REG_UMAC1_LPI_TX_DETECT_SIZE 1
#define MISC_REG_PORT_LANE_MODE_OVWR 0xa978UL //ACCESS:RW DataWidth:0x3 Description: Swap mode. This control is provided by the MISC block through straps and can also changed by F/W override. It is used to select the basic swap modes. The following table defines the swap modes. [0] - Overwrite control; if it is 0 - the swap_mode output is equal to ifmux_swap_mode input pin; if it is 1 - the swap_mode output is equal to bit[2:1] of this register; [2:1] - Overwrite value. If bit[0] of this register is 1 this is the value that receives the swap_mode output. These two bits are: 00 - generic; 01 - special mode 0; 10 - special mode 1; 11 - rsvd. Global register.
#define MISC_REG_PORT_LANE_MODE_OVWR_SIZE 1
#define MISC_REG_GEN_PURP_CR0 0xa97cUL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by core reset.
#define MISC_REG_GEN_PURP_CR0_SIZE 1
#define MISC_REG_GEN_PURP_CR1 0xa980UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by core reset.
#define MISC_REG_GEN_PURP_CR1_SIZE 1
#define MISC_REG_GEN_PURP_CR2 0xa984UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by core reset.
#define MISC_REG_GEN_PURP_CR2_SIZE 1
#define MISC_REG_GEN_PURP_CR3 0xa988UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by core reset.
#define MISC_REG_GEN_PURP_CR3_SIZE 1
#define MISC_REG_GEN_PURP_CRG 0xa98cUL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by core reset. Bit[0]: used for VCCMIN control to select 25MHz clock on XMAC; UMAC and PCIE Serdes. Global register.
#define MISC_REG_GEN_PURP_CRG_SIZE 1
#define MISC_REG_GEN_PURP_HW0 0xa990UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by hard reset.
#define MISC_REG_GEN_PURP_HW0_SIZE 1
#define MISC_REG_GEN_PURP_HW1 0xa994UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by hard reset.
#define MISC_REG_GEN_PURP_HW1_SIZE 1
#define MISC_REG_GEN_PURP_HW2 0xa998UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by hard reset.
#define MISC_REG_GEN_PURP_HW2_SIZE 1
#define MISC_REG_GEN_PURP_HW3 0xa99cUL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by hard reset.
#define MISC_REG_GEN_PURP_HW3_SIZE 1
#define MISC_REG_GEN_PURP_HWG 0xa9a0UL //ACCESS:RW DataWidth:0x20 Description: Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO can not be configured as an output. Each output has its output enable in the MCP register space; but this bit needs to be set to make use of that. Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change the i/o to an output and will drive the TimeSync output. Bit[31:7]: spare. Global register. Reset by hard reset.
#define MISC_REG_GEN_PURP_HWG_SIZE 1
#define MISC_REG_GEN_PURP_POR0 0xa9a4UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by por reset.
#define MISC_REG_GEN_PURP_POR0_SIZE 1
#define MISC_REG_GEN_PURP_POR1 0xa9a8UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by por reset.
#define MISC_REG_GEN_PURP_POR1_SIZE 1
#define MISC_REG_GEN_PURP_POR2 0xa9acUL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by por reset.
#define MISC_REG_GEN_PURP_POR2_SIZE 1
#define MISC_REG_GEN_PURP_POR3 0xa9b0UL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by por reset.
#define MISC_REG_GEN_PURP_POR3_SIZE 1
#define MISC_REG_GEN_PURP_PORG 0xa9b4UL //ACCESS:RW DataWidth:0x20 Description: Debug only: [31:4] - spare RW register reset by por reset; [3] - when 1 reset the Vmain Switching Regulator Controller PMU registers; [2] - when 1 disable the Vmain Switching Regulator Controller; [1] - when 1 reset the Vmgmt Switching Regulator Controller PMU registers; [0] - when 1 disable the Vmgmt Switching Regulator Controller. Global register.
#define MISC_REG_GEN_PURP_PORG_SIZE 1
#define MISC_REG_MDIO_OVERRIDE 0xa9b8UL //ACCESS:RW DataWidth:0x1 Description: MDIO Override. Enables the values on ~misc_registers_mdio_subscription.mdio_subscription to override the hardware mode defined defaults. Global register. Reset on Hard reset.
#define MISC_REG_MDIO_OVERRIDE_SIZE 1
#define MISC_REG_MDIO_SUBSCRIPTION 0xa9bcUL //ACCESS:RW DataWidth:0x20 Description: MDIO Subscription. Is used to configure the subscriptions of on-chip PHY devices and MAC ports to the four MDIO domains. It is only used when ~misc_registers_mdio_override.mdio_override is set. [3:0] - ch0_rr; [7:4] - ch1_rr; [11:8] - ch2_rr; [15:12] - ch3_rr; [19:16] - ch0_phy; [23:20] - ch1_phy; [27:24] - ch2_phy; [31:28] - ch3_phy. Global register. Reset on Hard reset.
#define MISC_REG_MDIO_SUBSCRIPTION_SIZE 1
#define MISC_REG_WC0_CTRL_EXTREMOTEMDIOST 0xa9c0UL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO strap (BRCM mode rarely used); tie to 0. Drives output misc_xgxs0_extremotemdiost. Global register.
#define MISC_REG_WC0_CTRL_EXTREMOTEMDIOST_SIZE 1
#define MISC_REG_WC0_CTRL_MD_DEVAD 0xa9c4UL //ACCESS:RW DataWidth:0x5 Description: Reserved for future XGXS cores which require an md_devad input. Drives output misc_xgxs0_md_devad. Global register.
#define MISC_REG_WC0_CTRL_MD_DEVAD_SIZE 1
#define MISC_REG_WC0_CTRL_MD_ST 0xa9c8UL //ACCESS:RW DataWidth:0x1 Description: MDIO State. This bit defines the LSB of the MDIO state machine in the WarpCore. A logic-1 enables clause 22 and a logic-0 enables clause 45. Drives output misc_xgxs0_md_st. Global register.
#define MISC_REG_WC0_CTRL_MD_ST_SIZE 1
#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9ccUL //ACCESS:RW DataWidth:0x5 Description: MDIO PHY Address. The WC uses this address to determine whether or not it is the recipient of the message on the MDIO interface. The value is compared to the value on ctrl_md_devad. Drives output misc_xgxs0_phy_addr. Global register.
#define MISC_REG_WC0_CTRL_PHY_ADDR_SIZE 1
#define MISC_REG_WC0_CTRL_PLL_BYPASS 0xa9d0UL //ACCESS:RW DataWidth:0x1 Description: Phase-locked-loop Bypass. Drives output misc_xgxs0_pll_bypass. Global register.
#define MISC_REG_WC0_CTRL_PLL_BYPASS_SIZE 1
#define MISC_REG_WC0_CTRL_REMOTEMDIOEN 0xa9d4UL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO enable. Drives output misc_xgxs0_remotemdioen. Global register.
#define MISC_REG_WC0_CTRL_REMOTEMDIOEN_SIZE 1
#define MISC_REG_WC1_CTRL_EXTREMOTEMDIOST 0xa9d8UL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO strap (BRCM mode rarely used); tie to 0. Drives output misc_xgxs1_extremotemdiost. Global register.
#define MISC_REG_WC1_CTRL_EXTREMOTEMDIOST_SIZE 1
#define MISC_REG_WC1_CTRL_MD_DEVAD 0xa9dcUL //ACCESS:RW DataWidth:0x5 Description: Reserved for future XGXS cores which require an md_devad input. Drives output misc_xgxs1_md_devad. Global register.
#define MISC_REG_WC1_CTRL_MD_DEVAD_SIZE 1
#define MISC_REG_WC1_CTRL_MD_ST 0xa9e0UL //ACCESS:RW DataWidth:0x1 Description: MDIO State. This bit defines the LSB of the MDIO state machine in the WarpCore. A logic-1 enables clause 22 and a logic-0 enables clause 45. Drives output misc_xgxs1_md_st. Global register.
#define MISC_REG_WC1_CTRL_MD_ST_SIZE 1
#define MISC_REG_WC1_CTRL_PHY_ADDR 0xa9e4UL //ACCESS:RW DataWidth:0x5 Description: MDIO PHY Address. The W C uses this address to determine whether or not it is the recipient of the message on the MDIO interface. The value is compared to the value on ctrl_md_devad. Drives output misc_xgxs1_phy_addr. Global register.
#define MISC_REG_WC1_CTRL_PHY_ADDR_SIZE 1
#define MISC_REG_WC1_CTRL_PLL_BYPASS 0xa9e8UL //ACCESS:RW DataWidth:0x1 Description: Phase-locked-loop Bypass. Drives output misc_xgxs1_pll_bypass. Global register.
#define MISC_REG_WC1_CTRL_PLL_BYPASS_SIZE 1
#define MISC_REG_WC1_CTRL_REMOTEMDIOEN 0xa9ecUL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO enable. Drives output misc_xgxs1_remotemdioen. Global register.
#define MISC_REG_WC1_CTRL_REMOTEMDIOEN_SIZE 1
#define MISC_REG_WC2_CTRL_EXTREMOTEMDIOST 0xa9f0UL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO strap (BRCM mode rarely used); tie to 0. Drives output misc_serdes0_extremotemdiost. Global register.
#define MISC_REG_WC2_CTRL_EXTREMOTEMDIOST_SIZE 1
#define MISC_REG_WC2_CTRL_MD_DEVAD 0xa9f4UL //ACCESS:RW DataWidth:0x5 Description: Reserved for future XGXS cores which require an md_devad input. Drives output misc_serdes0_md_devad. Global register.
#define MISC_REG_WC2_CTRL_MD_DEVAD_SIZE 1
#define MISC_REG_WC2_CTRL_MD_ST 0xa9f8UL //ACCESS:RW DataWidth:0x1 Description: MDIO State. This bit defines the LSB of the MDIO state machine in the WarpCore. A logic-1 enables clause 22 and a logic-0 enables clause 45. Drives output misc_serdes0_md_st. Global register.
#define MISC_REG_WC2_CTRL_MD_ST_SIZE 1
#define MISC_REG_WC2_CTRL_PHY_ADDR 0xa9fcUL //ACCESS:RW DataWidth:0x5 Description: MDIO PHY Address. The WC uses this address to determine whether or not it is the recipient of the message on the MDIO interface. The value is compared to the value on ctrl_md_devad. Drives output misc_serdes0_phy_addr. Global register.
#define MISC_REG_WC2_CTRL_PHY_ADDR_SIZE 1
#define MISC_REG_WC2_CTRL_PLL_BYPASS 0xaa00UL //ACCESS:RW DataWidth:0x1 Description: Phase-locked-loop Bypass. Drives output misc_serdes0_pll_bypass. Global register.
#define MISC_REG_WC2_CTRL_PLL_BYPASS_SIZE 1
#define MISC_REG_WC2_CTRL_REMOTEMDIOEN 0xaa04UL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO enable. Drives output misc_serdes0_remotemdioen. Global register.
#define MISC_REG_WC2_CTRL_REMOTEMDIOEN_SIZE 1
#define MISC_REG_WC0_MODE_STRAP 0xaa08UL //ACCESS:RW DataWidth:0x4 Description: 4 - os8: Independent channel mode w/ vco set to 10.3125G ; 5 - os5: Independent channel mode w/ vco set to 6.25G; 12 - combo Single port mode. In Independent Channel modes the core supports multiple ports. This can be four single lane ports; two dual lane ports; or 1 dual lane port with two singles. Lanes 0 and 2 can be configured as either a single lane or dual lane port; lanes 1 and 3 can only be programmed as a single lane port. When lane 0 or 2 is programmed into a dual lane mode then lanes 1 and 3 are configured as the second lane of the dual lane port and therefore are not avaiable to be configured as an individual port. In os8 mode each of the lanes within the core are capable of supporting rates 10M; 100M (FX; SGMII); 1G (Fiber; SGMII); 2.5G; 10G; and 20G (DXGXS). In 0s5 each of these modes are supported except for 10G/20G. In combo mode the core operates as a single port capable of supporting rates from 10M to 40G. Global register. Hard reset.
#define MISC_REG_WC0_MODE_STRAP_SIZE 1
#define MISC_REG_WC1_MODE_STRAP 0xaa0cUL //ACCESS:RW DataWidth:0x4 Description: 4 - os8: Independent channel mode w/ vco set to 10.3125G ; 5 - os5: Independent channel mode w/ vco set to 6.25G; 12 - combo Single port mode. In Independent Channel modes the core supports multiple ports. This can be four single lane ports; two dual lane ports; or 1 dual lane port with two singles. Lanes 0 and 2 can be configured as either a single lane or dual lane port; lanes 1 and 3 can only be programmed as a single lane port. When lane 0 or 2 is programmed into a dual lane mode then lanes 1 and 3 are configured as the second lane of the dual lane port and therefore are not avaiable to be configured as an individual port. In os8 mode each of the lanes within the core are capable of supporting rates 10M; 100M (FX; SGMII); 1G (Fiber; SGMII); 2.5G; 10G; and 20G (DXGXS). In 0s5 each of these modes are supported except for 10G/20G. In combo mode the core operates as a single port capable of supporting rates from 10M to 40G. Global register. Hard reset.
#define MISC_REG_WC1_MODE_STRAP_SIZE 1
#define MISC_REG_WC2_MODE_STRAP 0xaa10UL //ACCESS:RW DataWidth:0x4 Description: 4 - os8: Independent channel mode w/ vco set to 10.3125G ; 5 - os5: Independent channel mode w/ vco set to 6.25G; 12 - combo Single port mode. In Independent Channel modes the core supports multiple ports. This can be four single lane ports; two dual lane ports; or 1 dual lane port with two singles. Lanes 0 and 2 can be configured as either a single lane or dual lane port; lanes 1 and 3 can only be programmed as a single lane port. When lane 0 or 2 is programmed into a dual lane mode then lanes 1 and 3 are configured as the second lane of the dual lane port and therefore are not avaiable to be configured as an individual port. In os8 mode each of the lanes within the core are capable of supporting rates 10M; 100M (FX; SGMII); 1G (Fiber; SGMII); 2.5G; 10G; and 20G (DXGXS). In 0s5 each of these modes are supported except for 10G/20G. In combo mode the core operates as a single port capable of supporting rates from 10M to 40G. Global register. Hard reset.
#define MISC_REG_WC2_MODE_STRAP_SIZE 1
#define MISC_REG_XGXS_SERDES_MODE_SEL_OVWR 0xaa14UL //ACCESS:RW DataWidth:0x2 Description: WC0/WC1 to WC2 Mode select. [0] - Override Control. When 1 the logic based on port4mode_en and swap_mode is overrode by bit 1 value. When 0 the output is driven by logic based on port4mode_en and swap_mode. [1] - Override Value. Indicates the value of Mode select when bit 0 is asserted.This control is used to select between the WarpCore0/1 and the WarpCore2 for transmitting and receiving data. When Mode select is 0 the WarpCore2 is selected to override the WarpCore0/1. This is only valid in specified special mode 0. Global register. Reset on hard reset.
#define MISC_REG_XGXS_SERDES_MODE_SEL_OVWR_SIZE 1
#define MISC_REG_XMAC_LPI_TX_DETECT_P0 0xaa18UL //ACCESS:R DataWidth:0x2 Description: XMAC transmit LPI (Low Power Indication) state. This per port signal is set to 1; whenever the transmit interface is in LPI state and LPI_IDLES are being sent out on the TX Warpcore interface. Only bit 0 is applicable.
#define MISC_REG_XMAC_LPI_TX_DETECT_P0_SIZE 1
#define MISC_REG_XMAC_LPI_TX_DETECT_P1 0xaa1cUL //ACCESS:R DataWidth:0x2 Description: XMAC transmit LPI state. This per port signal is set to 1; whenever the transmit interface is in LPI state and LPI_IDLES are being sent out on the TX Warpcore interface. Only bit 0 is applicable.
#define MISC_REG_XMAC_LPI_TX_DETECT_P1_SIZE 1
#define MISC_REG_PLL_MAIN_E40_CH1_MDIV 0xaa2cUL //ACCESS:RW DataWidth:0x8 Description: Post-divider ratio for channel-1 (divider ratio = code value). 00000000: 256; 00000001: 1; 00000010: 2; 00000011: 3; : :; 11111101: 253; 11111110: 254; 11111111: 255. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_CH1_MDIV_SIZE 1
#define MISC_REG_PLL_MAIN_E40_CH_LOAD_EN 0xaa30UL //ACCESS:RW DataWidth:0x6 Description: Allows glitch free load capability. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_CH_LOAD_EN_SIZE 1
#define MISC_REG_PLL_MAIN_E40_CH_ENABLEB 0xaa34UL //ACCESS:RW DataWidth:0x6 Description: Channel enable (only enables channel 0). Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E40_CH_ENABLEB_SIZE 1
#define MISC_REG_PLL_STORM_E40_CH1_MDIV 0xaa38UL //ACCESS:RW DataWidth:0x8 Description: Post-divider ratio for channel-1 (divider ratio = code value). 00000000: 256; 00000001: 1; 00000010: 2; 00000011: 3; : :; 11111101: 253; 11111110: 254; 11111111: 255. Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_E40_CH1_MDIV_SIZE 1
#define MISC_REG_PLL_STORM_E40_CH_ENABLEB 0xaa3cUL //ACCESS:RW DataWidth:0x6 Description: Channel enable (only enables channel 0). Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_E40_CH_ENABLEB_SIZE 1
#define MISC_REG_PLL_STORM_E40_CH_LOAD_EN 0xaa40UL //ACCESS:RW DataWidth:0x6 Description: Allows glitch free load capability. Global register. Reset on POR reset.
#define MISC_REG_PLL_STORM_E40_CH_LOAD_EN_SIZE 1
#define MISC_REG_LCPLL_E40_BYPASS 0xaa44UL //ACCESS:RW DataWidth:0x1 Description: LCPLL Bypass. Drives the 156.25mhz applied to the balls of the LCPLL directly to warpcore. This will allow to continue testing of E3. By doing this we can use the same CML traces from LCPLL to Warpcore. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_BYPASS_SIZE 1
#define MISC_REG_LCPLL_E40_CH0_MDIV 0xaa48UL //ACCESS:RW DataWidth:0x8 Description: LCPLL Post-divider ratio for channel-0 (divider ratio = code value). 00000000= 256; 00000001= 1; 00000010= 2; 00000011= 3;-;11111101= 253; 11111110= 254;11111111= 255. Divide by 20 to get 156.25MHz. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_CH0_MDIV_SIZE 1
#define MISC_REG_LCPLL_E40_CH4_MDIV 0xaa4cUL //ACCESS:RW DataWidth:0x8 Description: LCPLL Post-divider ratio for channel-4 (divider ratio = code value). 00000000= 256; 00000001= 1; 00000010= 2; 00000011= 3;-;11111101= 253; 11111110= 254;11111111= 255. Divide by 50 to get 62.5MHz. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_CH4_MDIV_SIZE 1
#define MISC_REG_LCPLL_E40_CH5_MDIV 0xaa50UL //ACCESS:RW DataWidth:0x8 Description: LCPLL Post-divider ratio for channel-5 (divider ratio = code value). 00000000= 256; 00000001= 1; 00000010= 2; 00000011= 3;-;11111101= 253; 11111110= 254;11111111= 255. Divide by 25 to get 125Mhz. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_CH5_MDIV_SIZE 1
#define MISC_REG_LCPLL_E40_CH_ENABLEB 0xaa54UL //ACCESS:RW DataWidth:0x6 Description: LCPLL Enable (ACTIVE LOW) for post-divider channels 0-5. 0= channel ENABLED; 1= channel DISABLED (powered OFF); Bit<0>= post-divider channel-0; Bit<1>= post-divider channel-1; Bit<2>= post-divider channel-2; Bit<3>= post-divider channel-3; Bit<4>= post-divider channel-4; Bit<5>= post-divider channel-5. Enable channels 0;5;6. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_CH_ENABLEB_SIZE 1
#define MISC_REG_LCPLL_E40_CH_LOAD_EN 0xaa58UL //ACCESS:RW DataWidth:0x6 Description: LCPLL LOAD ENABLE for post-divider channel 0-5. Allows on-the-fly divider re-programming (glitch free). 0= HOLD present divider setting; 1= LOAD in new divider setting; Bit<0>= LOAD ENABLE for post-divider channel-0; Bit<1>= LOAD ENABLE for post-divider channel-1; Bit<2>= LOAD ENABLE for post-divider channel-2; Bit<3>= LOAD ENABLE for post-divider channel-3; Bit<4>= LOAD ENABLE for post-divider channel-4; Bit<5>= LOAD ENABLE for post-divider channel-5. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_CH_LOAD_EN_SIZE 1
#define MISC_REG_LCPLL_E40_CTRL_1 0xaa5cUL //ACCESS:RW DataWidth:0x1e Description: LCPLL configuration control register. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_CTRL_1_SIZE 1
#define MISC_REG_LCPLL_E40_CTRL_2 0xaa60UL //ACCESS:RW DataWidth:0xa Description: [2:0]: Loop gain in frequency acquisition mode. [5:3]: Gain of P/I loop filter integrator path during fine phase acquisition mode. [9:6]: Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_CTRL_2_SIZE 1
#define MISC_REG_LCPLL_E40_FREF_SEL 0xaa64UL //ACCESS:RW DataWidth:0x1 Description: LCPLL 25MHz select. If 1 - selects the 25Mhz clock from the balls or the pins of the LCPLL; if 0 - select 25Mhz from OSC. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_FREF_SEL_SIZE 1
#define MISC_REG_LCPLL_E40_NDIV_FRAC 0xaa68UL //ACCESS:RW DataWidth:0x14 Description: LCPLL Fractional feedback divider control.Resolution= 1/(2^20). Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_NDIV_FRAC_SIZE 1
#define MISC_REG_LCPLL_E40_NDIV_INT 0xaa6cUL //ACCESS:RW DataWidth:0x8 Description: LCPLL Feedback divider control (Code = divider ratio). 00000000= divide-by-256; 00000001= XXX; 00000010= XXX;...; 00000111= XXX; 00001000= divide-by-8; 00001001= divide-by-9; 00001010= divide-by-10;...; 11111110= divide-by-254; 11111111= divide-by-255. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_NDIV_INT_SIZE 1
#define MISC_REG_LCPLL_E40_PDIV 0xaa70UL //ACCESS:RW DataWidth:0x3 Description: LCPLL input reference clock pre-divider control (code = divider ratio). 000= divide-by-8; 001= divide-by-1; 010= divide-by-2; 011= divide-by-3; 100= divide-by-4; 101= divide-by-5; 110= divide-by-6; 111= divide-by-7. Global register. Reset on POR reset.
#define MISC_REG_LCPLL_E40_PDIV_SIZE 1
#define MISC_REG_LCPLL_E40_PWRDWN 0xaa74UL //ACCESS:RW DataWidth:0x1 Description: LCPLL power down. Global register. Active High. Reset on POR reset.
#define MISC_REG_LCPLL_E40_PWRDWN_SIZE 1
#define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78UL //ACCESS:RW DataWidth:0x1 Description: LCPLL VCO reset. Global register. Active Low Reset on POR reset.
#define MISC_REG_LCPLL_E40_RESETB_ANA_SIZE 1
#define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7cUL //ACCESS:RW DataWidth:0x1 Description: LCPLL post-divider reset. Global register. Active Low Reset on POR reset.
#define MISC_REG_LCPLL_E40_RESETB_DIG_SIZE 1
#define MISC_REG_LCPLL_E40_STATUS 0xaa80UL //ACCESS:R DataWidth:0xc Description: LCPLL state RO register. Global register.
#define MISC_REG_LCPLL_E40_STATUS_SIZE 1
#define MISC_REG_E1HMF_MODE_P0 0xaa84UL //ACCESS:RW DataWidth:0x1 Description: Multifunction for WOL port0. Reset on hard reset.
#define MISC_REG_E1HMF_MODE_P0_SIZE 1
#define MISC_REG_E1HMF_MODE_P1 0xaa88UL //ACCESS:RW DataWidth:0x1 Description: Multifunction for WOL port1. Reset on hard reset.
#define MISC_REG_E1HMF_MODE_P1_SIZE 1
#define MISC_REG_WC0_PRTAD_BCST 0xaa8cUL //ACCESS:RW DataWidth:0x5 Description: Broadcast port address. MDIO port address that the core respond to in addition to prtad. Allow multiple cores to be written to during a single MDIO frame (broadcast). Only works for MDIO writes. Drives output misc_xgxs0_prtad_bcst. Global register.
#define MISC_REG_WC0_PRTAD_BCST_SIZE 1
#define MISC_REG_WC1_PRTAD_BCST 0xaa90UL //ACCESS:RW DataWidth:0x5 Description: Broadcast port address. MDIO port address that the core respond to in addition to prtad. Allow multiple cores to be written to during a single MDIO frame (broadcast). Only works for MDIO writes. Drives output misc_xgxs1_prtad_bcst. Global register.
#define MISC_REG_WC1_PRTAD_BCST_SIZE 1
#define MISC_REG_WC2_PRTAD_BCST 0xaa94UL //ACCESS:RW DataWidth:0x5 Description: Broadcast port address. MDIO port address that the core respond to in addition to prtad. Allow multiple cores to be written to during a single MDIO frame (broadcast). Only works for MDIO writes. Drives output misc_serdes0_prtad_bcst. Global register.
#define MISC_REG_WC2_PRTAD_BCST_SIZE 1
#define MISC_REG_WC0_RESET 0xac30UL //ACCESS:RW DataWidth:0xa Description: reset reg#3;write/read one = the specific block is out of reset; write/read zero = the specific block is in reset; addr 0-wr- the write value will be written to the register; addr 1-set - one will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change) ; addr 2-clear - zero will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change); addr 3-ignore; read ignore from all addr except addr 00. [0]: rstb_hw: Active low reset which when asserted drives entire WC into the reset state. All flops which within WC are driven into an initial state; as well as the analog core. Output clocks txck_out; rxck0_10g; and clk_25 will be driven to 0 upon its assertion. [1]: iddq. Enables iddq testing where the supply current (Idd) is measured in the quiescent state. [2]: pwrdwn: Active high control which forces the analog core of the WC into power-down mode; and forces digital logic of the WC into reset. Output clock (refclk) remains active. [3]: pwrdwn_sd: Power down signal detect. [4]: txd10g_fifo_rstb: Transmit 10Gbps FIFO reset; active low. Used to reset the transmit FIFO used in xlgmii operation. [8:5]: txd1g_fifo_rstb: Transmit 1Gbps FIFO reset; active low. Used to reset the per-lane transmit FIFOs used in the mii/gmii operation. [9]: txd10g_fifo_rstb_dxgxs1: Transmit 10Gbps DXGXS FIFO reset; active low. Used to reset the transmit FIFO used in the DXGXS logic in xlgmii operation. Global register.
#define MISC_REG_WC0_RESET_SIZE 3
#define MISC_REG_WC1_RESET 0xac40UL //ACCESS:RW DataWidth:0xa Description: reset reg#3;write/read one = the specific block is out of reset; write/read zero = the specific block is in reset; addr 0-wr- the write value will be written to the register; addr 1-set - one will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change) ; addr 2-clear - zero will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change); addr 3-ignore; read ignore from all addr except addr 00. [0]: rstb_hw: Active low reset which when asserted drives entire WC into the reset state. All flops which within WC are driven into an initial state; as well as the analog core. Output clocks txck_out; rxck0_10g; and clk_25 will be driven to 0 upon its assertion. [1]: iddq. Enables iddq testing where the supply current (Idd) is measured in the quiescent state. [2]: pwrdwn: Active high control which forces the analog core of the WC into power-down mode; and forces digital logic of the WC into reset. Output clock (refclk) remains active. [3]: pwrdwn_sd: Power down signal detect. [4]: txd10g_fifo_rstb: Transmit 10Gbps FIFO reset; active low. Used to reset the transmit FIFO used in xlgmii operation. [8:5]: txd1g_fifo_rstb: Transmit 1Gbps FIFO reset; active low. Used to reset the per-lane transmit FIFOs used in the mii/gmii operation. [9]: txd10g_fifo_rstb_dxgxs1: Transmit 10Gbps DXGXS FIFO reset; active low. Used to reset the transmit FIFO used in the DXGXS logic in xlgmii operation. Global register.
#define MISC_REG_WC1_RESET_SIZE 3
#define MISC_REG_WC2_RESET 0xac50UL //ACCESS:RW DataWidth:0xa Description: reset reg#3;write/read one = the specific block is out of reset; write/read zero = the specific block is in reset; addr 0-wr- the write value will be written to the register; addr 1-set - one will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change) ; addr 2-clear - zero will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change); addr 3-ignore; read ignore from all addr except addr 00. [0]: rstb_hw: Active low reset which when asserted drives entire WC into the reset state. All flops which within WC are driven into an initial state; as well as the analog core. Output clocks txck_out; rxck0_10g; and clk_25 will be driven to 0 upon its assertion. [1]: iddq. Enables iddq testing where the supply current (Idd) is measured in the quiescent state. [2]: pwrdwn: Active high control which forces the analog core of the WC into power-down mode; and forces digital logic of the WC into reset. Output clock (refclk) remains active. [3]: pwrdwn_sd: Power down signal detect. [4]: txd10g_fifo_rstb: Transmit 10Gbps FIFO reset; active low. Used to reset the transmit FIFO used in xlgmii operation. [8:5]: txd1g_fifo_rstb: Transmit 1Gbps FIFO reset; active low. Used to reset the per-lane transmit FIFOs used in the mii/gmii operation. [9]: txd10g_fifo_rstb_dxgxs1: Transmit 10Gbps DXGXS FIFO reset; active low. Used to reset the transmit FIFO used in the DXGXS logic in xlgmii operation. Global register.
#define MISC_REG_WC2_RESET_SIZE 3
#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8UL //ACCESS:R DataWidth:0xc Description: [7:0] 8 MSB of LCPLL second register. Inside order of bits: [0-4] capSelectM[4:0] (reset value 0) bits to vco cap value; 00000 for most cap and lowest frequency. [5] capForceSlowdown_en (reset value 0) bit to enable capForceSlowdown into capSeq. [6] capForceSlowdown (reset value 0) bit to force slowdown. [7] Slowdn_xor (reset value 0) bit to invert slowdn (added for test chip); [8] LCPLL RESET (reset value 0) RESET pin of the LCPLL: Reset for VCO tuning sequencer. (active high; longer than 30 usec); [9] LCPLL BYPASS_CML (reset value 0) BYPASS_CMD pin of the LCPLL: Bypass mode enable (active high): 0= Normal mode; 1= Bypass mode (CMOS bypass clock fed thru BYPASS MUX to CML output buffers); [10] LCPLL BYPEN_CMOS (reset value 0) Bypass mode clock selection: 0= CMOS clock derived from REFP/N fed to bypass MUX; 1= CMOS clock from Byp_CLK156 is fed to bypass MUX; [11] LCPLL PWRDN (reset value 1) PLL power down (active high): 0 = Normal mode; 1 = Power down. Global register.
#define MISC_REG_LCPLL_CTRL_REG_2_SIZE 1
#define MISC_REG_LCPLL_STATE 0xa4a0UL //ACCESS:R DataWidth:0x10 Description: LCPLL state RO register. Mapped as follows: [0] freqDone_SM bit indicating freq det is done. [1] freqPass_SM bit indicating frequency lock. [2] pllSeqDone bit indicating pll sequencer is done. [3] pllSeqPass bit indicating pll sequencer finised successfully. [6:4] pllState pll sequence state variable. [9:7] capState cap sequencer state variable; for test purposes. [14:10] capSelect cap selection to VCO; 00000 for most cap and lowest vco frequency. [15] Slowdn indicator (PLL_LOW) VCO comparator output. Global register.
#define MISC_REG_LCPLL_STATE_SIZE 1
#define MISC_REG_OSCCNTRL 0xa4acUL //ACCESS:R DataWidth:0xc Description: OSCFUNDS control word. Inside order map: [11:10] Iamp_adj adjust the current of the gain amplifier.(00: 150 uA; 01: 200 uA; 10: 250 uA; 11: 300 uA (reset value 10). [9:8] Icbuf_adj adjust the current to the CMOS to CML buffer (00: 225 uA; 01: 300 uA; 10: 375 uA; 11: 450 uA (reset value 10). [7:6] xtal_adjCM adjust the common-mode of the oscillator first stage (01: 1.45 V; 00: 1.54 V; 10: 1.62 V; 11: 1.66 V (reset value 00). [5] Frequency-monitor output enable (0 - off ; 1 - on) (reset value 0). [4] XCcml_6P; XCcml_6N Removed on latest revision of the IP. (0-on; 1-off) (reset value 1). [3] XCcml_5P; XCcml_5N Removed on latest revision of the IP. (0-on; 1-off) (reset value 1). [2] XCcml_4P; XCcml_4N (0-on; 1-off) (reset value 1). [1] XCcml_3P; XCcml_3N (0-on; 1-off) (reset value 0). [0] XCcml_2P; XCcml_2N (0-on; 1-off) (reset value 0)
#define MISC_REG_OSCCNTRL_SIZE 1
#define MISC_REG_RESET_REG_3 0xa5a0UL //ACCESS:R DataWidth:0x20 Description: reset reg#3;write/read one = the specific block is out of reset; write/read zero = the specific block is in reset; addr 0-wr- the write value will be written to the register; addr 1-set - one will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change) ; addr 2-clear - zero will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change); addr 3-ignore; read ignore from all addr except addr 00; inside order of the bits is: [0] misc_nig_mux_serdes0_rstb_hw (NIG - Reset Controls to SERDES0); [1] misc_nig_mux_serdes0_iddq (NIG - Reset Controls to SERDES0); [2] misc_nig_mux_serdes0_pwrdwn (NIG - Reset Controls to SERDES0); [3] misc_nig_mux_serdes0_pwrdwn_sd (NIG - Reset Controls to SERDES0); [4] misc_nig_mux_xgxs0_rstb_hw (NIG - Reset Controls to XGXS 0) (2-port mode: per-path; 4-port-mode: global); [5] misc_nig_mux_xgxs0_iddq (NIG - Reset Controls to XGXS 0) (2-port mode: per-path; 4-port-mode: global); [6] misc_nig_mux_xgxs0_pwrdwn (NIG - Reset Controls to XGXS 0) (2-port mode: per-path; 4-port-mode: global); [7] misc_nig_mux_xgxs0_pwrdwn_sd (NIG - Reset Controls to XGXS 0) (2-port mode: per-path; 4-port-mode: global); [8] misc_nig_mux_xgxs0_txd_fifo_rstb (NIG - Reset Controls to XGXS 0) (2-port mode: per-path; 4-port-mode: global); [9-15] Reserved; [16] misc_nig_mux_serdes1_rstb_hw (NIG - Reset Controls to SERDES1); [17] misc_nig_mux_serdes1_iddq (NIG - Reset Controls to SERDES1); [18] misc_nig_mux_serdes1_pwrdwn (NIG - Reset Controls to SERDES1); [19] misc_nig_mux_serdes1_pwrdwn_sd (NIG - Reset Controls to SERDES1); [20] misc_nig_mux_xgxs1_rstb_hw (NIG - Reset Controls to XGXS 1); [21] misc_nig_mux_xgxs1_iddq (NIG - Reset Controls to XGXS 1); [22] misc_nig_mux_xgxs1_pwrdwn (NIG - Reset Controls to XGXS 1); [23] misc_nig_mux_xgxs1_pwrdwn_sd (NIG - Reset Controls to XGXS 1); [24] misc_nig_mux_xgxs1_txd_fifo_rstb (NIG - Reset Controls to XGXS 1); [25-31] Reserved;
#define MISC_REG_RESET_REG_3_SIZE 3
#define MISC_REG_E1HMF_MODE 0xa5f8UL //ACCESS:R DataWidth:0x1 Description: multifunction for WOL. If clr WOL signal of the PXP will be send on bit 0 only. Global register. Reset on hard reset.
#define MISC_REG_E1HMF_MODE_SIZE 1
#define MISC_REG_PLL_STORM_E65_TEST_EN 0xa638UL //ACCESS:R DataWidth:0x1 Description: Test mode output enable (active HIGH): ;0= testout in High-Z state; 1= testout active. Global register.
#define MISC_REG_PLL_STORM_E65_TEST_EN_SIZE 1
#define MISC_REG_PLL_STORM_E65_P1_DIV 0xa63cUL //ACCESS:R DataWidth:0x4 Description: Input reference clock pre-divider control: 0000= divide-by-16; 0001= divide-by-1; 0010= divide-by-2 ; 0011= divide-by-3; 0100= divide-by-4; 0101= divide-by-5; 0110= divide-by-6; 0111= divide-by-7; 1000= divide-by-8; 1001= divide-by-9; 1010= divide-by-10; 1011= divide-by-11; 1100= divide-by-12 ;1101= divide-by-13; 1110= divide-by-14; 1111= divide-by-15. Global register.
#define MISC_REG_PLL_STORM_E65_P1_DIV_SIZE 1
#define MISC_REG_PLL_STORM_E65_P2_DIV 0xa640UL //ACCESS:R DataWidth:0x4 Description: Feedback pre-divider control: 0000= divide-by-16; 0001= divide-by-1; 0010= divide-by-2 ; 0011= divide-by-3; 0100= divide-by-4; 0101= divide-by-5; 0110= divide-by-6; 0111= divide-by-7; 1000= divide-by-8; 1001= divide-by-9; 1010= divide-by-10; 1011= divide-by-11; 1100= divide-by-12 ;1101= divide-by-13; 1110= divide-by-14; 1111= divide-by-15. Global register.
#define MISC_REG_PLL_STORM_E65_P2_DIV_SIZE 1
#define MISC_REG_PLL_STORM_E65_NDIV_MODE 0xa644UL //ACCESS:R DataWidth:0x3 Description: Feedback Divider Mode Control: (Note: If the fractional part is n/8; it is basically still interger-N mode; the modulator is not working. So the loop filter setting should still follow integer-N modes setting); 000= Integer-N Mode (DEFAULT); 001= MASH ??? ; odulator Unit Mode; 010= MFB ??? Modulator Unit Mode (default for frac); th011= MASH ??? Modulator 1/8 Mode; th100= MFB ??? Modulator 1/8 Mode; 101= unused; 110= unused; 111= unused. Global register.
#define MISC_REG_PLL_STORM_E65_NDIV_MODE_SIZE 1
#define MISC_REG_PLL_STORM_E65_NDIV_FRAC 0xa648UL //ACCESS:R DataWidth:0x18 Description: Fractional control for feedback divider: i_ndiv_frac[23:0]; 24 Divide fraction= i_ndiv_frac [23:0] / 2. Global register.
#define MISC_REG_PLL_STORM_E65_NDIV_FRAC_SIZE 1
#define MISC_REG_PLL_STORM_E65_M1_DIV 0xa64cUL //ACCESS:R DataWidth:0x8 Description: Clock channel-1 post divider control: (divide ratio= code value); 00000000= divide-by-256; 00000001= divide-by-1; 00000010= divide-by-2; 00000011= divide-by-3; 00000100= divide-by-4; 00000101= divide-by-5; 00000110= divide-by-6 ... 11111011= divide-by-251; 11111100= divide-by-252; 11111101= divide-by-253; 11111110= divide-by-254; 11111111= divide-by-255. Global register.
#define MISC_REG_PLL_STORM_E65_M1_DIV_SIZE 1
#define MISC_REG_PLL_STORM_E65_VCO_RNG 0xa650UL //ACCESS:R DataWidth:0x2 Description: VCO range control register: (bit [1] unused at present); x0: [ 800MHz ; 1600 MHz ]; x1: (1600MHz; 3200 MHz]. Global register.
#define MISC_REG_PLL_STORM_E65_VCO_RNG_SIZE 1
#define MISC_REG_PLL_STORM_E65_PLL_TEST_SE 0xa654UL //ACCESS:R DataWidth:0x3 Description: Test mode clock select: 0000= VCO Vcontrol (see section 6; i_pll_ctrl[31:30]); 0001= VCO/8 clock; 0010= frefi; 0011= fdbki; 0100= watchdog timer reset output; 0101= clkout1; 0110= clkout2; 0111= clkout3; 1000=clkout4**; 1001=clkout5**; 1010=clkout6** Global register.
#define MISC_REG_PLL_STORM_E65_PLL_TEST_SE_SIZE 1
#define MISC_REG_PLL_STORM_E65_CTRL_1 0xa658UL //ACCESS:R DataWidth:0x20 Description: Configuration control register block. Bits ; Name ; Default Setting ; Description. [3:0] - Icp_off[3:0] ; reset value - 0 ; Description (Offset down current: Icp_off= Icp_off[4:0] /31 x 0.5LSB of Icp ). [4] - freq_det_dis ; reset value - 0 ; Description (Watchdog disable. freq_det_dis=0 watchdog works. freq_det_dis=1 disable watchdog to prevent frequency comparison).[9:5] - Icpx[4:0] ; reset value - 1110 ; Description (Up/Down current (Icp): Icp= (1 + Icpx[4:0]) x IUNIT; I= (1.6 x (Vc-V) /14 kohm )/10; ( for Fvco<1600MHz)). [12:10] - Rz[2:0] ; reset value - 1 ; Description (Rz= (1 + Rz[2:0]) x 7 kohm)). [14:13] - Cz[1:0] ; reset value - 0 ; Description (Cz= (1 + Cz[1:0]) x 36.48 pF)). [16:15] - Cp[1:0] ; reset value - 0 ; Description (Cp= 2Cp[1:0] x 0.57 pF). [18:17] - Rn[1:0] ; reset value - 0 ; Description (3 pole resistor: Rn= (4 + Rn[1:0]) x 7 kohm). [20:19] - Cn[1:0] ; reset value - 0 ; Description (3 pole cap: Cn=2Cn[1:0]x 0.57 pF). [21] - LF_order ; reset value - 0 ; Description (Loop Filter Order: 0= 2nd order ; Rz is programmable; Cz=36.48 pF / Cp=0.57 pF; Rn;Cn are unused; recommended for integer division mode; 1= 3rd order ; Rz;Rn;Cz;Cp;Cn are all programmable; recommended for fractional division mode). [23:22] - lpf_bw[1:0] ; reset value - 0 ; Description (Bandwidth of low-bandwidth amp: =1 / (2RaCa); Ca= 18.24 pF ; Ra= (4 - lpf_bw[1:0]) x 112 k). [26:24] - kvco_xf[2:0] ; reset value - 0 ; Description (Current driven by vcf: Icf= Icu x (2 + 2xf[0]+ 6xf[1]+ 10xf[2])). [29:27] - kvco_xs[2:0] ; reset value - 100 - (Fvco< 1.6GHz) 111 -(Fvco> 1.6GHz) ; Description (Current driven by vcs: Ics= Icu x (2xs[0]+ 6xs[1]+ 10xs[2]); Icf + Ics= Ic; Kvco is reduced by (Icf / Ic)). [31:30] - testa_sel ; reset value - 0 ; Description (Analog select signals to test port: 00= vcf; 01= vcs; 10= vci; 11= vco_vreg). Global register.
#define MISC_REG_PLL_STORM_E65_CTRL_1_SIZE 1
#define MISC_REG_PLL_STORM_E65_CTRL_2 0xa65cUL //ACCESS:R DataWidth:0x6 Description: Configuration control register block. 0] - ; biasin_en ; reset value - 0 ; Description (CML bias reference enable: 0= disable; 1= enable). [1] - ; Lowcur_en ; reset value - 0 ; Description (CML output buffer drive: 0= 400-? output impedance (1.2 mA); 1= 800-? output impedance (0.6 mA)). [3:2] - ; ctap_adj[1:0] ; reset value - 1 ; Description (CTAT current I variation: ;00=-6.25%; 01/10=0%; 11=6.25%). [5:4] - ; ptap_adj[1:0] ; reset value - 1 ; Description (PTAT current I variation: 00=-6.25%; 01/10=0%; 11=6.25%). Global register.
#define MISC_REG_PLL_STORM_E65_CTRL_2_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_TEST_EN 0xa660UL //ACCESS:R DataWidth:0x1 Description: Test mode output enable (active HIGH): ;0= testout in High-Z state; 1= testout active. Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_TEST_EN_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_P1_DIV 0xa664UL //ACCESS:R DataWidth:0x4 Description: Input reference clock pre-divider control: 0000= divide-by-16; 0001= divide-by-1; 0010= divide-by-2 ; 0011= divide-by-3; 0100= divide-by-4; 0101= divide-by-5; 0110= divide-by-6; 0111= divide-by-7; 1000= divide-by-8; 1001= divide-by-9; 1010= divide-by-10; 1011= divide-by-11; 1100= divide-by-12 ;1101= divide-by-13; 1110= divide-by-14; 1111= divide-by-15. Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_P1_DIV_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_P2_DIV 0xa668UL //ACCESS:R DataWidth:0x4 Description: Feedback pre-divider control: 0000= divide-by-16; 0001= divide-by-1; 0010= divide-by-2 ; 0011= divide-by-3; 0100= divide-by-4; 0101= divide-by-5; 0110= divide-by-6; 0111= divide-by-7; 1000= divide-by-8; 1001= divide-by-9; 1010= divide-by-10; 1011= divide-by-11; 1100= divide-by-12 ;1101= divide-by-13; 1110= divide-by-14; 1111= divide-by-15. Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_P2_DIV_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_NDIV_MODE 0xa66cUL //ACCESS:R DataWidth:0x3 Description: Feedback Divider Mode Control: (Note: If the fractional part is n/8; it is basically still interger-N mode; the modulator is not working. So the loop filter setting should still follow integer-N modes setting); 000= Integer-N Mode (DEFAULT); 001= MASH ??? ; odulator Unit Mode; 010= MFB ??? Modulator Unit Mode (default for frac); th011= MASH ??? Modulator 1/8 Mode; th100= MFB ??? Modulator 1/8 Mode; 101= unused; 110= unused; 111= unused. Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_NDIV_MODE_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_NDIV_FRAC 0xa670UL //ACCESS:R DataWidth:0x18 Description: Fractional control for feedback divider: i_ndiv_frac[23:0]; 24 Divide fraction= i_ndiv_frac [23:0] / 2. Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_NDIV_FRAC_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_M1_DIV 0xa674UL //ACCESS:R DataWidth:0x8 Description: Clock channel-1 post divider control: (divide ratio= code value); 00000000= divide-by-256; 00000001= divide-by-1; 00000010= divide-by-2; 00000011= divide-by-3; 00000100= divide-by-4; 00000101= divide-by-5; 00000110= divide-by-6 ... 11111011= divide-by-251; 11111100= divide-by-252; 11111101= divide-by-253; 11111110= divide-by-254; 11111111= divide-by-255. Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_M1_DIV_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_VCO_RNG 0xa678UL //ACCESS:R DataWidth:0x2 Description: VCO range control register: (bit [1] unused at present); x0: [ 800MHz ; 1600 MHz ]; x1: (1600MHz; 3200 MHz]. Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_VCO_RNG_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_PLL_TEST_SE 0xa67cUL //ACCESS:R DataWidth:0x3 Description: Test mode clock select: 0000= VCO Vcontrol (see section 6; i_pll_ctrl[31:30]); 0001= VCO/8 clock; 0010= frefi; 0011= fdbki; 0100= watchdog timer reset output; 0101= clkout1; 0110= clkout2; 0111= clkout3; 1000=clkout4**; 1001=clkout5**; 1010=clkout6**. Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_PLL_TEST_SE_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_CTRL_1 0xa680UL //ACCESS:R DataWidth:0x20 Description: Configuration control register block. Bits ; Name ; Default Setting ; Description. [3:0] - Icp_off[3:0] ; reset value - 0 ; Description (Offset down current: Icp_off= Icp_off[4:0] /31 x 0.5LSB of Icp ). [4] - freq_det_dis ; reset value - 0 ; Description (Watchdog disable. freq_det_dis=0 watchdog works. freq_det_dis=1 disable watchdog to prevent frequency comparison).[9:5] - Icpx[4:0] ; reset value - 1110 ; Description (Up/Down current (Icp): Icp= (1 + Icpx[4:0]) x IUNIT; I= (1.6 x (Vc-V) /14 kohm )/10; ( for Fvco<1600MHz)). [12:10] - Rz[2:0] ; reset value - 1 ; Description (Rz= (1 + Rz[2:0]) x 7 kohm)). [14:13] - Cz[1:0] ; reset value - 0 ; Description (Cz= (1 + Cz[1:0]) x 36.48 pF)). [16:15] - Cp[1:0] ; reset value - 0 ; Description (Cp= 2Cp[1:0] x 0.57 pF). [18:17] - Rn[1:0] ; reset value - 0 ; Description (3 pole resistor: Rn= (4 + Rn[1:0]) x 7 kohm). [20:19] - Cn[1:0] ; reset value - 0 ; Description (3 pole cap: Cn=2Cn[1:0]x 0.57 pF). [21] - LF_order ; reset value - 0 ; Description (Loop Filter Order: 0= 2nd order ; Rz is programmable; Cz=36.48 pF / Cp=0.57 pF; Rn;Cn are unused; recommended for integer division mode; 1= 3rd order ; Rz;Rn;Cz;Cp;Cn are all programmable; recommended for fractional division mode). [23:22] - lpf_bw[1:0] ; reset value - 0 ; Description (Bandwidth of low-bandwidth amp: =1 / (2RaCa); Ca= 18.24 pF ; Ra= (4 - lpf_bw[1:0]) x 112 k). [26:24] - kvco_xf[2:0] ; reset value - 0 ; Description (Current driven by vcf: Icf= Icu x (2 + 2xf[0]+ 6xf[1]+ 10xf[2])). [29:27] - kvco_xs[2:0] ; reset value - 100 - (Fvco< 1.6GHz) 111 -(Fvco> 1.6GHz) ; Description (Current driven by vcs: Ics= Icu x (2xs[0]+ 6xs[1]+ 10xs[2]); Icf + Ics= Ic; Kvco is reduced by (Icf / Ic)). [31:30] - testa_sel ; reset value - 0 ; Description (Analog select signals to test port: 00= vcf; 01= vcs; 10= vci; 11= vco_vreg). Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_CTRL_1_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_CTRL_2 0xa684UL //ACCESS:R DataWidth:0x6 Description: Configuration control register block. 0] - ; biasin_en ; reset value - 0 ; Description (CML bias reference enable: 0= disable; 1= enable). [1] - ; Lowcur_en ; reset value - 0 ; Description (CML output buffer drive: 0= 400-? output impedance (1.2 mA); 1= 800-? output impedance (0.6 mA)). [3:2] - ; ctap_adj[1:0] ; reset value - 1 ; Description (CTAT current I variation: ;00=-6.25%; 01/10=0%; 11=6.25%). [5:4] - ; ptap_adj[1:0] ; reset value - 1 ; Description (PTAT current I variation: 00=-6.25%; 01/10=0%; 11=6.25%). Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_CTRL_2_SIZE 1
#define MISC_REG_XGXS0_CTRL_MD_ST 0xa730UL //ACCESS:R DataWidth:0x1 Description: 4-port mode control to XGXS; Hardwired ST bits LSB: 0 - clause 45; 1 - clause 22. Drives output misc_xgxs0_mux_md_st. Global register.
#define MISC_REG_XGXS0_CTRL_MD_ST_SIZE 1
#define MISC_REG_TEMPMON_CTRL 0xa73cUL //ACCESS:R DataWidth:0x8 Description: Temperature Monitor control. [7:1] - Analog bias adjustments; [0] - ADC test mode enable (when 0 - SAR ADC test mode; when 1 - Temp monitor normal mode).Global register.
#define MISC_REG_TEMPMON_CTRL_SIZE 1
#define MISC_REG_TEMPMON_PWR 0xa740UL //ACCESS:R DataWidth:0x2 Description: Temperature Monitor power control. [0] - Temperature monitor reset (0 - asserted; 1 - de-asserted); [1] - Temperature monitor power down (0 - power down; 1 - power up).Global register.
#define MISC_REG_TEMPMON_PWR_SIZE 1
#define MISC_REG_TEMPMON_HOLD 0xa744UL //ACCESS:R DataWidth:0x1 Description: Temperature Monitor hold. 0 - update every 400us; 1 - hold on to the value forever.Global register.
#define MISC_REG_TEMPMON_HOLD_SIZE 1
#define MISC_REG_TEMPMON_DATA 0xa748UL //ACCESS:R DataWidth:0x9 Description: Temperature Monitor output.Global register.
#define MISC_REG_TEMPMON_DATA_SIZE 1
#define MISC_REG_XGXS0_CTRL_MD_DEVAD 0xa760UL //ACCESS:R DataWidth:0x5 Description: 4-port mode control to XGXS; Hardwired Device Address bits CL45 DEVAD. Drives output misc_xgxs0_mux_md_devad. Global register.
#define MISC_REG_XGXS0_CTRL_MD_DEVAD_SIZE 1
#define MISC_REG_XGXS0_CTRL_PHY_ADDR 0xa764UL //ACCESS:R DataWidth:0x5 Description: 4-port mode control to XGXS; Hardwired port address - CL22 PHY_ADD and CL45 PRTAD. Drives output misc_xgxs0_mux_phy_addr. Global register.
#define MISC_REG_XGXS0_CTRL_PHY_ADDR_SIZE 1
#define MISC_REG_XGXS0_CTRL_REMOTEMDIOEN 0xa768UL //ACCESS:R DataWidth:0x1 Description: 4-port mode control to XGXS; remote PHY in-band MDIO. Drives output misc_xgxs0_mux_remotemdioen. Global register.
#define MISC_REG_XGXS0_CTRL_REMOTEMDIOEN_SIZE 1
#define MISC_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0xa76cUL //ACCESS:R DataWidth:0x1 Description: 4-port mode control to XGXS; remote PHY in-band MDIO. When set causes the remote MDIO arbitration to be performed via pins instead of mdio register bits. Drives output misc_xgxs0_mux_extremotemdiost. Global register.
#define MISC_REG_XGXS0_CTRL_EXTREMOTEMDIOST_SIZE 1
#define MISC_REG_XGXS0_CTRL_PLL_BYPASS 0xa770UL //ACCESS:R DataWidth:0x1 Description: control to xgxs - PLL bypass
#define MISC_REG_XGXS0_CTRL_PLL_BYPASS_SIZE 1
#define MISC_REG_VOLTMON_CTRL 0xa790UL //ACCESS:R DataWidth:0x1c Description: Volatge Monitor control. [5:0] - 6 bit trim for the PTAT Resistor (Nominal +/- 7 0n 64 steps) - denoted as i_bg_ptat[5:0] internally. 2s complement logic. 000000 - Nominal (Default); 000001 - Nominal + 0.22% (i.e. +7%/32); 111111 - Nominal - 0.22% (i.e. -7%/32; [7:6] - Enable measurement of different voltages. Denoted as i_bg_out_tempco[1:0] internally. 00 - Reference voltage measurement (sum of PTAT and CTAT) (Default); 01 - PTAT voltage measurement; 10 - CTAT voltage measurement; 11 - same as 00 setting; [13:8] - 6 bit trim for the CTAT Resistor (Nominal +/- 10 0n 64 steps) - denoted as i_bg_ctat[5:0] internally. 2s complement logic. 000000 - Nominal (Default) ; 000001 - Nominal + 0.3% (i.e. +10%/32); 111111 - Nominal - 0.3% (i.e. -10%/32); [19:14] - 6 bit trim for the vtemp Resistor (Nominal +/- 4 0n 64 steps) - denoted as i_vtemp_trim[5:0] internally. 2s complement logic. 000000 - Nominal (Default); 000001 - Nominal + 0.12% (i.e. + 4%/32); 111111 - Nominal - 0.12% (i.e. - 4%/32); [21:20] - Enable vtemp output and select between PTAT/CTAT mode .Denoted as i_vtemp_ptatctat[1:0] internally. 00 - no output; 01 - PTAT voltage measurement (Default); 10 - CTAT voltage measurement; [22] - Select the type of high supply voltage being monitored. (3.3V/2.5V). Denoted as i_3p3_2p5_sel internally. When 0 - monitored voltage range = 3.3V +/- 0.6V; When 1- monitored voltage range = 2.5V +/- 0.4V; [23] - Select between temperature monitor and voltage monitor. When 0 - voltage monitor; When 1 -temperature monitor; [24] - Enable bandgap test signal output. [25] - Select the test signal. When 0 - o_test = vref; When 1- o_test = vtemp; [26] - Enable ADC test mode. [27] - Reserved bit. Global register.
#define MISC_REG_VOLTMON_CTRL_SIZE 1
#define MISC_REG_VOLTMON_DATA 0xa794UL //ACCESS:R DataWidth:0x9 Description: Voltage Monitor output.Global register.
#define MISC_REG_VOLTMON_DATA_SIZE 1
#define MISC_REG_VOLTMON_HOLD 0xa798UL //ACCESS:R DataWidth:0x1 Description: Voltage Monitor hold. 0 - update; 1 - hold on to the value forever.Global register.
#define MISC_REG_VOLTMON_HOLD_SIZE 1
#define MISC_REG_VOLTMON_PWR 0xa79cUL //ACCESS:R DataWidth:0x2 Description: Voltage Monitor power control. [0] - Voltage monitor reset (0 - asserted; 1 - de-asserted); [1] - Voltage monitor power down (0 - power down; 1 - power up).Global register.
#define MISC_REG_VOLTMON_PWR_SIZE 1
#define MISC_REG_VOLTMON_SEL 0xa7a0UL //ACCESS:R DataWidth:0x1 Description: Voltage Monitor select. 1 = choose 3.3V; 0 = choose 1.2V.Global register.
#define MISC_REG_VOLTMON_SEL_SIZE 1
#define MISC_REG_PWRWDOG_PWRDN 0xa7a4UL //ACCESS:R DataWidth:0x1 Description: Power watchdog power down. 1 - power down; 0 - power up.Global register.
#define MISC_REG_PWRWDOG_PWRDN_SIZE 1
#define MISC_REG_PWRWDOG_CGFG 0xa7a8UL //ACCESS:R DataWidth:0x8 Description: Power watchdog configuration. Adjustment of integer delay cgfg[7:4] and fractional delay cgfg[3:0]; valid range [0:191]. Global register.
#define MISC_REG_PWRWDOG_CGFG_SIZE 1
#define MISC_REG_PWRWDOG_RSEL 0xa7acUL //ACCESS:R DataWidth:0x3 Description: Power watchdog selection of delay setting of ring delay element; recommended setting is 3b100 for longest ring delay; 3b010 will shorten the ring by one inverter+inverting mux; 3b001 will shorten the ring by two inverter+inverting mux cells;Global register.
#define MISC_REG_PWRWDOG_RSEL_SIZE 1
#define MISC_REG_PWRWDOG_CLEARCFG 0xa7b0UL //ACCESS:R DataWidth:0x3 Description: Power watchdog selection of delay chain for the reset pulse; recommended setting is 3b100 for longest pulse; 3b010 will shorten the reset pulse by one inverter+inverting mux delay; 3b001 will shorten the reset pulse by two inverter+inverting mux delays; set clearcfg more or equal than rsel to ensure the ring gets flushed from the previous cycle; reducing the reset pulse length is needed to reach the highest possible operating frequencies.Global register.
#define MISC_REG_PWRWDOG_CLEARCFG_SIZE 1
#define MISC_REG_PWRWDOG_START 0xa7b4UL //ACCESS:R DataWidth:0x6 Description: Power watchdog. Sets the number of trips through the ring delay element to start+1; range for start is [-1:31].Global register.
#define MISC_REG_PWRWDOG_START_SIZE 1
#define MISC_REG_PWRWDOG_ACCU_RUN 0xa7b8UL //ACCESS:R DataWidth:0x1 Description: Power watchdog. When 0 all registers and states are of power watchdog accu sub-module are reset. Global register.
#define MISC_REG_PWRWDOG_ACCU_RUN_SIZE 1
#define MISC_REG_PWRWDOG_ACCU_SKIP 0xa7bcUL //ACCESS:R DataWidth:0x2 Description: Power watchdog. Allows to decimate the good signal to measure for beats. Global register.
#define MISC_REG_PWRWDOG_ACCU_SKIP_SIZE 1
#define MISC_REG_PWRWDOG_ACCU_SKIP_START 0xa7c0UL //ACCESS:R DataWidth:0x2 Description: Power watchdog. Start value of skip counter. Global register.
#define MISC_REG_PWRWDOG_ACCU_SKIP_START_SIZE 1
#define MISC_REG_PWRWDOG_DATA 0xa7c4UL //ACCESS:R DataWidth:0xa Description: Power watchdog data.Global register.
#define MISC_REG_PWRWDOG_DATA_SIZE 1
#define MISC_REG_PWRWDOG_DONE 0xa7c8UL //ACCESS:R DataWidth:0x1 Description: Power watchdog done. Global register.
#define MISC_REG_PWRWDOG_DONE_SIZE 1
#define MISC_REG_PLL_MAIN_E65_CTRL_1 0xa800UL //ACCESS:R DataWidth:0x20 Description: Configuration control register block. Bits ; Name ; Default Setting ; Description. [3:0] - Icp_off[3:0] ; reset value - 0 ; Description (Offset down current: Icp_off= Icp_off[4:0] /31 x 0.5LSB of Icp ). [4] - freq_det_dis ; reset value - 0 ; Description (Watchdog disable. freq_det_dis=0 watchdog works. freq_det_dis=1 disable watchdog to prevent frequency comparison).[9:5] - Icpx[4:0] ; reset value - 1110 ; Description (Up/Down current (Icp): Icp= (1 + Icpx[4:0]) x IUNIT; I= (1.6 x (Vc-V) /14 kohm )/10; ( for Fvco<1600MHz)). [12:10] - Rz[2:0] ; reset value - 1 ; Description (Rz= (1 + Rz[2:0]) x 7 kohm)). [14:13] - Cz[1:0] ; reset value - 0 ; Description (Cz= (1 + Cz[1:0]) x 36.48 pF)). [16:15] - Cp[1:0] ; reset value - 0 ; Description (Cp= 2Cp[1:0] x 0.57 pF). [18:17] - Rn[1:0] ; reset value - 0 ; Description (3 pole resistor: Rn= (4 + Rn[1:0]) x 7 kohm). [20:19] - Cn[1:0] ; reset value - 0 ; Description (3 pole cap: Cn=2Cn[1:0]x 0.57 pF). [21] - LF_order ; reset value - 0 ; Description (Loop Filter Order: 0= 2nd order ; Rz is programmable; Cz=36.48 pF / Cp=0.57 pF; Rn;Cn are unused; recommended for integer division mode; 1= 3rd order ; Rz;Rn;Cz;Cp;Cn are all programmable; recommended for fractional division mode). [23:22] - lpf_bw[1:0] ; reset value - 0 ; Description (Bandwidth of low-bandwidth amp: =1 / (2RaCa); Ca= 18.24 pF ; Ra= (4 - lpf_bw[1:0]) x 112 k). [26:24] - kvco_xf[2:0] ; reset value - 0 ; Description (Current driven by vcf: Icf= Icu x (2 + 2xf[0]+ 6xf[1]+ 10xf[2])). [29:27] - kvco_xs[2:0] ; reset value - 100 - (Fvco< 1.6GHz) 111 -(Fvco> 1.6GHz) ; Description (Current driven by vcs: Ics= Icu x (2xs[0]+ 6xs[1]+ 10xs[2]); Icf + Ics= Ic; Kvco is reduced by (Icf / Ic)). [31:30] - testa_sel ; reset value - 0 ; Description (Analog select signals to test port: 00= vcf; 01= vcs; 10= vci; 11= vco_vreg). Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_CTRL_1_SIZE 1
#define MISC_REG_PLL_MAIN_E65_CTRL_2 0xa804UL //ACCESS:R DataWidth:0x6 Description: Configuration control register block. 0] - ; biasin_en ; reset value - 0 ; Description (CML bias reference enable: 0= disable; 1= enable). [1] - ; Lowcur_en ; reset value - 0 ; Description (CML output buffer drive: 0= 400-? output impedance (1.2 mA); 1= 800-? output impedance (0.6 mA)). [3:2] - ; ctap_adj[1:0] ; reset value - 1 ; Description (CTAT current I variation: ;00=-6.25%; 01/10=0%; 11=6.25%). [5:4] - ; ptap_adj[1:0] ; reset value - 1 ; Description (PTAT current I variation: 00=-6.25%; 01/10=0%; 11=6.25%). Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_CTRL_2_SIZE 1
#define MISC_REG_PLL_MAIN_E65_M1_DIV 0xa808UL //ACCESS:R DataWidth:0x8 Description: Clock channel-1 post divider control: (divide ratio= code value); 00000000= divide-by-256; 00000001= divide-by-1; 00000010= divide-by-2; 00000011= divide-by-3; 00000100= divide-by-4; 00000101= divide-by-5; 00000110= divide-by-6 ... 11111011= divide-by-251; 11111100= divide-by-252; 11111101= divide-by-253; 11111110= divide-by-254; 11111111= divide-by-255. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_M1_DIV_SIZE 1
#define MISC_REG_PLL_MAIN_E65_NDIV_FRAC 0xa80cUL //ACCESS:R DataWidth:0x18 Description: Fractional control for feedback divider: i_ndiv_frac[23:0]; 24 Divide fraction= i_ndiv_frac [23:0] / 2. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_NDIV_FRAC_SIZE 1
#define MISC_REG_PLL_MAIN_E65_NDIV_MODE 0xa810UL //ACCESS:R DataWidth:0x3 Description: Feedback Divider Mode Control: (Note: If the fractional part is n/8; it is basically still interger-N mode; the modulator is not working. So the loop filter setting should still follow integer-N modes setting); 000= Integer-N Mode (DEFAULT); 001= MASH ??? ; odulator Unit Mode; 010= MFB ??? Modulator Unit Mode (default for frac); th011= MASH ??? Modulator 1/8 Mode; th100= MFB ??? Modulator 1/8 Mode; 101= unused; 110= unused; 111= unused. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_NDIV_MODE_SIZE 1
#define MISC_REG_PLL_MAIN_E65_P1_DIV 0xa814UL //ACCESS:R DataWidth:0x4 Description: Input reference clock pre-divider control: 0000= divide-by-16; 0001= divide-by-1; 0010= divide-by-2 ; 0011= divide-by-3; 0100= divide-by-4; 0101= divide-by-5; 0110= divide-by-6; 0111= divide-by-7; 1000= divide-by-8; 1001= divide-by-9; 1010= divide-by-10; 1011= divide-by-11; 1100= divide-by-12 ;1101= divide-by-13; 1110= divide-by-14; 1111= divide-by-15. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_P1_DIV_SIZE 1
#define MISC_REG_PLL_MAIN_E65_P2_DIV 0xa818UL //ACCESS:R DataWidth:0x4 Description: Feedback pre-divider control: 0000= divide-by-16; 0001= divide-by-1; 0010= divide-by-2 ; 0011= divide-by-3; 0100= divide-by-4; 0101= divide-by-5; 0110= divide-by-6; 0111= divide-by-7; 1000= divide-by-8; 1001= divide-by-9; 1010= divide-by-10; 1011= divide-by-11; 1100= divide-by-12 ;1101= divide-by-13; 1110= divide-by-14; 1111= divide-by-15. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_P2_DIV_SIZE 1
#define MISC_REG_PLL_MAIN_E65_PLL_TEST_SE 0xa81cUL //ACCESS:R DataWidth:0x3 Description: Test mode clock select: 0000= VCO Vcontrol (see section 6; i_pll_ctrl[31:30]); 0001= VCO/8 clock; 0010= frefi; 0011= fdbki; 0100= watchdog timer reset output; 0101= clkout1; 0110= clkout2; 0111= clkout3; 1000=clkout4**; 1001=clkout5**; 1010=clkout6**. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_PLL_TEST_SE_SIZE 1
#define MISC_REG_PLL_MAIN_E65_TEST_EN 0xa820UL //ACCESS:R DataWidth:0x1 Description: Test mode output enable (active HIGH): ;0= testout in High-Z state; 1= testout active. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_TEST_EN_SIZE 1
#define MISC_REG_PLL_MAIN_E65_VCO_RNG 0xa824UL //ACCESS:R DataWidth:0x2 Description: VCO range control register: (bit [1] unused at present); x0: [ 800MHz ; 1600 MHz ]; x1: (1600MHz; 3200 MHz]. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_VCO_RNG_SIZE 1
#define MISC_REG_PLL_MAIN_E65_NDIV_INT 0xa828UL //ACCESS:R DataWidth:0x9 Description: Clock channel-1 post divider control:(divide ratio= code value);00000000= divide-by-256; 00000001= divide-by-1; 00000010= divide-by-2; 00000011= divide-by-3; 00000100= divide-by-4; 00000101= divide-by-5; 00000110= divide-by-6...11111011= divide-by-251; 11111100= divide-by-252; 11111101= divide-by-253; 11111110= divide-by-254; 11111111= divide-by-255. Global register. Reset on POR reset.
#define MISC_REG_PLL_MAIN_E65_NDIV_INT_SIZE 1
#define MISC_REG_MISC_OSC65_CONTROL 0xa82cUL //ACCESS:R DataWidth:0x10 Description: osccntrl[15:14] Iamp_adj [1:0] adjust the current of the gain amplifier; osccntrl[13:12] Icbuf_adj [1:0] adjust the current to the CMOS to CML buffer; osccntrl[11] IbFD_adj adjust the current to the Frequency Doubler Block; osccntrl[10] Activate the amplitude limiter function. Constrains the amplitude on XP and XN to =1.5 Vpp single-ended regardless of crystal type or load capacitors. This limiter is automatically disabled in bypass mode. osccntrl[9:8] xtal_adjCM [1:0] adjust the common-mode of the oscillator first stage osccntrl[7] bypass frequency ; osccntrl[6] cml_6p cml_6n 0: output is active; osccntrl[5] cml_5p cml_5n 0: output is active ;osccntrl[4] cml_4p cml_4n 0: output is active; osccntrl[3] cml_3p cml_3n 0: output is active; osccntrl[2] cml_2p cml_2n 0: output is active; osccntrl[1] Frequency-monitor output enable; osccntrl[0] Frequency Doubler power down. Global register. Reset on POR reset.
#define MISC_REG_MISC_OSC65_CONTROL_SIZE 1
#define MISC_REG_PLL_STORM_E65_NDIV_INT 0xa830UL //ACCESS:R DataWidth:0x9 Description: Clock channel-1 post divider control:(divide ratio= code value);00000000= divide-by-256; 00000001= divide-by-1; 00000010= divide-by-2; 00000011= divide-by-3; 00000100= divide-by-4; 00000101= divide-by-5; 00000110= divide-by-6...11111011= divide-by-251; 11111100= divide-by-252; 11111101= divide-by-253; 11111110= divide-by-254; 11111111= divide-by-255. Global register.
#define MISC_REG_PLL_STORM_E65_NDIV_INT_SIZE 1
#define MISC_REG_PLL_MAIN_E65_OTP_NDIV_INT 0xa834UL //ACCESS:R DataWidth:0x9 Description: Clock channel-1 post divider control:(divide ratio= code value);00000000= divide-by-256; 00000001= divide-by-1; 00000010= divide-by-2; 00000011= divide-by-3; 00000100= divide-by-4; 00000101= divide-by-5; 00000110= divide-by-6...11111011= divide-by-251; 11111100= divide-by-252; 11111101= divide-by-253; 11111110= divide-by-254; 11111111= divide-by-255. Global register.
#define MISC_REG_PLL_MAIN_E65_OTP_NDIV_INT_SIZE 1
#define MISC_REG_LCPLL_E65_CTRL_0 0xa838UL //ACCESS:R DataWidth:0x20 Description: Bit [0] reserved ;Bits [4:1] OC [3:0] ;Bits [8:5] Icp_ctrl [3:0] ;Bits[10:9] FD_ctrl[1:0] Bits [14:11] Bias_ctrl[3:0] ;Bits [20:15] Pll_observe[5:0] ;Bits [26:21] LF_ctrl[5:0] ;Bit [31:27] PLL_ctrl[5:0]. Global register.
#define MISC_REG_LCPLL_E65_CTRL_0_SIZE 1
#define MISC_REG_LCPLL_E65_CTRL_1 0xa83cUL //ACCESS:R DataWidth:0x20 Description: Bit [43:32] pll_val[11:0] ;Bit [45:44] ref_val[1:0] ;Bit [46] TAL_enable_b ;Bit [47] cal_enable_b ;Bit [50:48] refresh_cap_cnt[2:0] ;Bit [51] refresh_cal ;Bit [54:52] numCapChange[2:0] ;Bit [63:55] force_caps_val[8:0]. Global register.
#define MISC_REG_LCPLL_E65_CTRL_1_SIZE 1
#define MISC_REG_LCPLL_E65_CTRL_2 0xa840UL //ACCESS:R DataWidth:0x20 Description: Bit [71:64] delayBeforeOpenLoop[7:0] ;Bit [79:72] delayAfterRefresh[7:0] Bit [87:80] delayAfterOpenLoop[7:0] ;Bit [95:88] delayAfterCloseLoop[7:0]. Global register.
#define MISC_REG_LCPLL_E65_CTRL_2_SIZE 1
#define MISC_REG_LCPLL_E65_CTRL_3 0xa844UL //ACCESS:R DataWidth:0x20 Description: Bit [107:96] calSetCount[11:0] ;Bits [108] force_caps ;Bit [109] clk_gate_ovr ;Bit [110] cal_mode ;Bit [111] calSetCountOvr ;Bit [119:112] cal_ref_timeout[7:0] ;Bit[124:120] enableTimeOut ;Bit[127:125] reserved. Global register.
#define MISC_REG_LCPLL_E65_CTRL_3_SIZE 1
#define MISC_REG_MISC_UNUSED_EMPTY_0 0xa54cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_0_SIZE 1
#define MISC_REG_MISC_UNUSED_EMPTY_1 0xa554UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_1_SIZE 1
#define MISC_REG_MISC_UNUSED_EMPTY_2 0xa55cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_2_SIZE 1
#define MISC_REG_MISC_UNUSED_EMPTY_3 0xa564UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_3_SIZE 1
#define MISC_REG_MISC_UNUSED_EMPTY_4 0xa56cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_4_SIZE 1
#define MISC_REG_MISC_UNUSED_EMPTY_5 0xa578UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_5_SIZE 2
#define MISC_REG_MISC_UNUSED_EMPTY_6 0xa5b0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_6_SIZE 4
#define MISC_REG_MISC_UNUSED_EMPTY_7 0xa7dcUL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_7_SIZE 1
#define MISC_REG_MISC_UNUSED_EMPTY_8 0xa7f8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_8_SIZE 2
#define MISC_REG_MISC_UNUSED_EMPTY_9 0xa970UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_9_SIZE 1
#define MISC_REG_MISC_UNUSED_EMPTY_10 0xaa98UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_10_SIZE 102
#define MISC_REG_MISC_UNUSED_EMPTY_11 0xac64UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MISC_REG_MISC_UNUSED_EMPTY_11_SIZE 1255
#define MSTAT_REG_MSTAT_INT_STS 0x7f0UL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
#define MSTAT_MSTAT_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define MSTAT_MSTAT_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define MSTAT_REG_MSTAT_INT_STS_CLR 0x7f4UL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
#define MSTAT_MSTAT_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define MSTAT_MSTAT_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define MSTAT_REG_MSTAT_INT_STS_WR 0x7f8UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
#define MSTAT_MSTAT_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define MSTAT_MSTAT_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define MSTAT_REG_MSTAT_INT_MASK 0x7fcUL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
#define MSTAT_MSTAT_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define MSTAT_MSTAT_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define MSTAT_REG_TX_STAT_GTXPOK_LO 0UL //ACCESS:RW DataWidth:0x20 Description: 1 [00] Tx Good Packet Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTXPOK_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTXPOK_HI 0x4UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GTXPOK statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GTXPOK_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTXPF_LO 0x8UL //ACCESS:RW DataWidth:0x20 Description: 1 [01] Tx Pause Packet Counter Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTXPF_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTXPF_HI 0xcUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GTXPF statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GTXPF_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTXPP_LO 0x10UL //ACCESS:RW DataWidth:0x20 Description: 1 [02] Tx PFC Packet Counter Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTXPP_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTXPP_HI 0x14UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GTXPP statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GTXPP_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTFCS_LO 0x18UL //ACCESS:RW DataWidth:0x20 Description: 1 [03] Tx FCS Error Packet Counter Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTFCS_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTFCS_HI 0x1cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GTFCS statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GTFCS_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTUCA_LO 0x20UL //ACCESS:RW DataWidth:0x20 Description: 1 [04] Tx Unicast Packet Counter Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTUCA_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTUCA_HI 0x24UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GTUCA statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GTUCA_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTMCA_LO 0x28UL //ACCESS:RW DataWidth:0x20 Description: 1 [05] Tx Multicast Packet Counter Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTMCA_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTMCA_HI 0x2cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GTMCA statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GTMCA_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTBCA_LO 0x30UL //ACCESS:RW DataWidth:0x20 Description: 1 [06] Tx Broadcast Packet Counter Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTBCA_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTBCA_HI 0x34UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GTBCA statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GTBCA_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTPKT_LO 0x38UL //ACCESS:RW DataWidth:0x20 Description: 1 [07] Tx Total Packet Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTPKT_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTPKT_HI 0x3cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GTPKT statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GTPKT_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GT64_LO 0x40UL //ACCESS:RW DataWidth:0x20 Description: 1 [08] Packet Size = 64 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GT64_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GT64_HI 0x44UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GT64 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GT64_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GT127_LO 0x48UL //ACCESS:RW DataWidth:0x20 Description: 1 [09] Packet Size = 65-127 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GT127_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GT127_HI 0x4cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GT127 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GT127_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GT255_LO 0x50UL //ACCESS:RW DataWidth:0x20 Description: 1 [10] Packet Size = 128-255 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GT255_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GT255_HI 0x54UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GT255 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GT255_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GT511_LO 0x58UL //ACCESS:RW DataWidth:0x20 Description: 1 [11] Packet Size = 256-511 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GT511_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GT511_HI 0x5cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GT511 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GT511_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GT1023_LO 0x60UL //ACCESS:RW DataWidth:0x20 Description: 1 [12] Packet Size = 512-1023 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GT1023_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GT1023_HI 0x64UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GT1023 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GT1023_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GT1518_LO 0x68UL //ACCESS:RW DataWidth:0x20 Description: 1 [13] Packet Size = 1024-1522 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GT1518_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GT1518_HI 0x6cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GT1518 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GT1518_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GT2047_LO 0x70UL //ACCESS:RW DataWidth:0x20 Description: 1 [14] Packet Size = 1523-2047 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GT2047_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GT2047_HI 0x74UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GT2047 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GT2047_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GT4095_LO 0x78UL //ACCESS:RW DataWidth:0x20 Description: 1 [15] Packet Size = 2048-4095 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GT4095_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GT4095_HI 0x7cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GT4095 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GT4095_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GT9216_LO 0x80UL //ACCESS:RW DataWidth:0x20 Description: 1 [16] Packet Size = 4096-9216 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GT9216_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GT9216_HI 0x84UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GT9216 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GT9216_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GT16383_LO 0x88UL //ACCESS:RW DataWidth:0x20 Description: 1 [17] Packet Size = 9217-16383 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GT16383_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GT16383_HI 0x8cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GT16383 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GT16383_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTUFL_LO 0x90UL //ACCESS:RW DataWidth:0x20 Description: 1 [18] Tx FIFO Underflow Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTUFL_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTUFL_HI 0x94UL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the TX_STAT_GTUFL statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
#define MSTAT_REG_TX_STAT_GTUFL_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTERR_LO 0x98UL //ACCESS:RW DataWidth:0x20 Description: 1 [19] Tx Errored Packet Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTERR_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTERR_HI 0x9cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the TX_STAT_GTERR statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_TX_STAT_GTERR_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTBYT_LO 0xa0UL //ACCESS:RW DataWidth:0x20 Description: 16 [36:21] Tx Byte Count ([20] = Enable) Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_TX_STAT_GTBYT_LO_SIZE 1
#define MSTAT_REG_TX_STAT_GTBYT_HI 0xa4UL //ACCESS:RW DataWidth:0xd Description: This is the upper half of the TX_STAT_GTBYT statistic. Write to this register write bits 12:0. Reads from this register will clear bits 12:0.
#define MSTAT_REG_TX_STAT_GTBYT_HI_SIZE 1
#define MSTAT_REG_ETHERSTATSCOLLISIONS_LO 0xa8UL //ACCESS:RW DataWidth:0x20 Description: 4 [41:38] Total number of collisions detected ([37] = Enable) Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_ETHERSTATSCOLLISIONS_LO_SIZE 1
#define MSTAT_REG_ETHERSTATSCOLLISIONS_HI 0xacUL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the ETHERSTATSCOLLISIONS statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
#define MSTAT_REG_ETHERSTATSCOLLISIONS_HI_SIZE 1
#define MSTAT_REG_DOT3STATSSINGLECOLLISIONFRAMES_LO 0xb0UL //ACCESS:RW DataWidth:0x20 Description: 1 [42] Number of packets sent after one collision Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_DOT3STATSSINGLECOLLISIONFRAMES_LO_SIZE 1
#define MSTAT_REG_DOT3STATSSINGLECOLLISIONFRAMES_HI 0xb4UL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the DOT3STATSSINGLECOLLISIONFRAMES statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
#define MSTAT_REG_DOT3STATSSINGLECOLLISIONFRAMES_HI_SIZE 1
#define MSTAT_REG_DOT3STATSMULTIPLECOLLISIONFRAMES_LO 0xb8UL //ACCESS:RW DataWidth:0x20 Description: 1 [43] Number of packets sent after more than one collision Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_DOT3STATSMULTIPLECOLLISIONFRAMES_LO_SIZE 1
#define MSTAT_REG_DOT3STATSMULTIPLECOLLISIONFRAMES_HI 0xbcUL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the DOT3STATSMULTIPLECOLLISIONFRAMES statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
#define MSTAT_REG_DOT3STATSMULTIPLECOLLISIONFRAMES_HI_SIZE 1
#define MSTAT_REG_DOT3STATSDEFERREDTRANSMISSIONS_LO 0xc0UL //ACCESS:RW DataWidth:0x20 Description: 1 [44] Number of transmissions delayed due to an Rx packet on the wire Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_DOT3STATSDEFERREDTRANSMISSIONS_LO_SIZE 1
#define MSTAT_REG_DOT3STATSDEFERREDTRANSMISSIONS_HI 0xc4UL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the DOT3STATSDEFERREDTRANSMISSIONS statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
#define MSTAT_REG_DOT3STATSDEFERREDTRANSMISSIONS_HI_SIZE 1
#define MSTAT_REG_DOT3STATSEXCESSIVECOLLISIONS_LO 0xc8UL //ACCESS:RW DataWidth:0x20 Description: 1 [45] Number of packets dropped due to 16 collisions Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_DOT3STATSEXCESSIVECOLLISIONS_LO_SIZE 1
#define MSTAT_REG_DOT3STATSEXCESSIVECOLLISIONS_HI 0xccUL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the DOT3STATSEXCESSIVECOLLISIONS statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
#define MSTAT_REG_DOT3STATSEXCESSIVECOLLISIONS_HI_SIZE 1
#define MSTAT_REG_DOT3STATSLATECOLLISIONS_LO 0xd0UL //ACCESS:RW DataWidth:0x20 Description: 1 [46] Number of packets dropped due to late collisions Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_DOT3STATSLATECOLLISIONS_LO_SIZE 1
#define MSTAT_REG_DOT3STATSLATECOLLISIONS_HI 0xd4UL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the DOT3STATSLATECOLLISIONS statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
#define MSTAT_REG_DOT3STATSLATECOLLISIONS_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GR64_LO 0x200UL //ACCESS:RW DataWidth:0x20 Description: 1 [47] Packet Size = 64 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GR64_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GR64_HI 0x204UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GR64 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GR64_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GR127_LO 0x208UL //ACCESS:RW DataWidth:0x20 Description: 1 [48] Packet Size = 65-127 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GR127_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GR127_HI 0x20cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GR127 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GR127_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GR255_LO 0x210UL //ACCESS:RW DataWidth:0x20 Description: 1 [49] Packet Size = 128-255 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GR255_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GR255_HI 0x214UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GR255 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GR255_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GR511_LO 0x218UL //ACCESS:RW DataWidth:0x20 Description: 1 [50] Packet Size = 256-511 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GR511_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GR511_HI 0x21cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GR511 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GR511_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GR1023_LO 0x220UL //ACCESS:RW DataWidth:0x20 Description: 1 [51] Packet Size = 512-1023 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GR1023_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GR1023_HI 0x224UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GR1023 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GR1023_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GR1518_LO 0x228UL //ACCESS:RW DataWidth:0x20 Description: 1 [52] Packet Size = 1024-1522 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GR1518_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GR1518_HI 0x22cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GR1518 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GR1518_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GR2047_LO 0x230UL //ACCESS:RW DataWidth:0x20 Description: 1 [53] Packet Size = 1523-2047 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GR2047_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GR2047_HI 0x234UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GR2047 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GR2047_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GR4095_LO 0x238UL //ACCESS:RW DataWidth:0x20 Description: 1 [54] Packet Size = 2048-4095 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GR4095_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GR4095_HI 0x23cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GR4095 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GR4095_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GR9216_LO 0x240UL //ACCESS:RW DataWidth:0x20 Description: 1 [55] Packet Size = 4096-9216 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GR9216_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GR9216_HI 0x244UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GR9216 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GR9216_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GR16383_LO 0x248UL //ACCESS:RW DataWidth:0x20 Description: 1 [56] Packet Size = 9217-16383 Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GR16383_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GR16383_HI 0x24cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GR16383 statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GR16383_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRPKT_LO 0x250UL //ACCESS:RW DataWidth:0x20 Description: 1 [57] Valid Rx Packet Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRPKT_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRPKT_HI 0x254UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRPKT statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRPKT_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRFCS_LO 0x258UL //ACCESS:RW DataWidth:0x20 Description: 1 [58] FCS Error Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRFCS_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRFCS_HI 0x25cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRFCS statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRFCS_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRUCA_LO 0x260UL //ACCESS:RW DataWidth:0x20 Description: 1 [59] Unicast Packet Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRUCA_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRUCA_HI 0x264UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRUCA statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRUCA_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRMCA_LO 0x268UL //ACCESS:RW DataWidth:0x20 Description: 1 [60] Mulitcast Packet Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRMCA_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRMCA_HI 0x26cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRMCA statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRMCA_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRBCA_LO 0x270UL //ACCESS:RW DataWidth:0x20 Description: 1 [61] Broadcast Packet Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRBCA_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRBCA_HI 0x274UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRBCA statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRBCA_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRXPF_LO 0x278UL //ACCESS:RW DataWidth:0x20 Description: 1 [62] Pause Frame Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRXPF_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRXPF_HI 0x27cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRXPF statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRXPF_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRXPP_LO 0x280UL //ACCESS:RW DataWidth:0x20 Description: 1 [63] PFC Frame Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRXPP_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRXPP_HI 0x284UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRXPP statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRXPP_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRXUO_LO 0x288UL //ACCESS:RW DataWidth:0x20 Description: 1 [64] Control Frame w/ Unknown Opcode Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRXUO_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRXUO_HI 0x28cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRXUO statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRXUO_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GROVR_LO 0x290UL //ACCESS:RW DataWidth:0x20 Description: 1 [65] Oversized Packet Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GROVR_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GROVR_HI 0x294UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GROVR statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GROVR_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRXCF_LO 0x298UL //ACCESS:RW DataWidth:0x20 Description: 1 [66] Control Frame Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRXCF_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRXCF_HI 0x29cUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRXCF statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRXCF_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRFLR_LO 0x2a0UL //ACCESS:RW DataWidth:0x20 Description: 1 [67] Frame Length Error. Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRFLR_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRFLR_HI 0x2a4UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRFLR statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRFLR_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRPOK_LO 0x2a8UL //ACCESS:RW DataWidth:0x20 Description: 1 [68] Ok Packet Count (UC or MC or BC) Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRPOK_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRPOK_HI 0x2acUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRPOK statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRPOK_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRBYT_LO 0x2b0UL //ACCESS:RW DataWidth:0x20 Description: 16 [85:70] Total Rx Byte Count ([69] = Enable) Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRBYT_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRBYT_HI 0x2b4UL //ACCESS:RW DataWidth:0xd Description: This is the upper half of the RX_STAT_GRBYT statistic. Write to this register write bits 12:0. Reads from this register will clear bits 12:0.
#define MSTAT_REG_RX_STAT_GRBYT_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRUND_LO 0x2b8UL //ACCESS:RW DataWidth:0x20 Description: 1 [86] Undersized Packet Count. < 64; Good FCS Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRUND_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRUND_HI 0x2bcUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRUND statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRUND_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRFRG_LO 0x2c0UL //ACCESS:RW DataWidth:0x20 Description: 1 [87] Fragment Count. < 64; Bad FCS Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRFRG_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRFRG_HI 0x2c4UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRFRG statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRFRG_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRERB_LO 0x2c8UL //ACCESS:RW DataWidth:0x20 Description: 16 [104:89] Error Packet Byte Count ([88] = Enable) Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRERB_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRERB_HI 0x2ccUL //ACCESS:RW DataWidth:0xd Description: This is the upper half of the RX_STAT_GRERB statistic. Write to this register write bits 12:0. Reads from this register will clear bits 12:0.
#define MSTAT_REG_RX_STAT_GRERB_HI_SIZE 1
#define MSTAT_REG_RX_STAT_GRFRE_LO 0x2d0UL //ACCESS:RW DataWidth:0x20 Description: 1 [105] Frame Error Packet Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RX_STAT_GRFRE_LO_SIZE 1
#define MSTAT_REG_RX_STAT_GRFRE_HI 0x2d4UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RX_STAT_GRFRE statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RX_STAT_GRFRE_HI_SIZE 1
#define MSTAT_REG_DOT3STATSALIGNMENTERRORS_LO 0x2d8UL //ACCESS:RW DataWidth:0x20 Description: 1 [106] Number of packets with invalid size (extra nibble) Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_DOT3STATSALIGNMENTERRORS_LO_SIZE 1
#define MSTAT_REG_DOT3STATSALIGNMENTERRORS_HI 0x2dcUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the DOT3STATSALIGNMENTERRORS statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_DOT3STATSALIGNMENTERRORS_HI_SIZE 1
#define MSTAT_REG_FALSECARRIERERRORS_LO 0x2e0UL //ACCESS:RW DataWidth:0x20 Description: 1 [107] Number of False Carrier Events detected. Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_FALSECARRIERERRORS_LO_SIZE 1
#define MSTAT_REG_FALSECARRIERERRORS_HI 0x2e4UL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the FALSECARRIERERRORS statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_FALSECARRIERERRORS_HI_SIZE 1
#define MSTAT_REG_RXLLFCMSGCNT_LO 0x2e8UL //ACCESS:RW DataWidth:0x20 Description: 1 [108] Rx LLFC Packet Count Write to this register write bits 31:0. Reads from this register will clear bits 31:0.
#define MSTAT_REG_RXLLFCMSGCNT_LO_SIZE 1
#define MSTAT_REG_RXLLFCMSGCNT_HI 0x2ecUL //ACCESS:RW DataWidth:0x7 Description: This is the upper half of the RxLLFCMSGCNT statistic. Write to this register write bits 6:0. Reads from this register will clear bits 6:0.
#define MSTAT_REG_RXLLFCMSGCNT_HI_SIZE 1
#define MSTAT_REG_TX_STAT_GTXPOK_WB 0x400UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTXPOK statitic.
#define MSTAT_REG_TX_STAT_GTXPOK_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GTXPF_WB 0x408UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTXPF statitic.
#define MSTAT_REG_TX_STAT_GTXPF_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GTXPP_WB 0x410UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTXPP statitic.
#define MSTAT_REG_TX_STAT_GTXPP_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GTFCS_WB 0x418UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTFCS statitic.
#define MSTAT_REG_TX_STAT_GTFCS_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GTUCA_WB 0x420UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTUCA statitic.
#define MSTAT_REG_TX_STAT_GTUCA_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GTMCA_WB 0x428UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTMCA statitic.
#define MSTAT_REG_TX_STAT_GTMCA_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GTBCA_WB 0x430UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTBCA statitic.
#define MSTAT_REG_TX_STAT_GTBCA_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GTPKT_WB 0x438UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTPKT statitic.
#define MSTAT_REG_TX_STAT_GTPKT_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GT64_WB 0x440UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GT64 statitic.
#define MSTAT_REG_TX_STAT_GT64_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GT127_WB 0x448UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GT127 statitic.
#define MSTAT_REG_TX_STAT_GT127_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GT255_WB 0x450UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GT255 statitic.
#define MSTAT_REG_TX_STAT_GT255_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GT511_WB 0x458UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GT511 statitic.
#define MSTAT_REG_TX_STAT_GT511_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GT1023_WB 0x460UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GT1023 statitic.
#define MSTAT_REG_TX_STAT_GT1023_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GT1518_WB 0x468UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GT1518 statitic.
#define MSTAT_REG_TX_STAT_GT1518_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GT2047_WB 0x470UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GT2047 statitic.
#define MSTAT_REG_TX_STAT_GT2047_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GT4095_WB 0x478UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GT4095 statitic.
#define MSTAT_REG_TX_STAT_GT4095_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GT9216_WB 0x480UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GT9216 statitic.
#define MSTAT_REG_TX_STAT_GT9216_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GT16383_WB 0x488UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GT16383 statitic.
#define MSTAT_REG_TX_STAT_GT16383_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GTUFL_WB 0x490UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTUFL statitic.
#define MSTAT_REG_TX_STAT_GTUFL_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GTERR_WB 0x498UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTERR statitic.
#define MSTAT_REG_TX_STAT_GTERR_WB_SIZE 2
#define MSTAT_REG_TX_STAT_GTBYT_WB 0x4a0UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the TX_STAT_GTBYT statitic.
#define MSTAT_REG_TX_STAT_GTBYT_WB_SIZE 2
#define MSTAT_REG_ETHERSTATSCOLLISIONS_WB 0x4a8UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the ETHERSTATSCOLLISIONS statitic.
#define MSTAT_REG_ETHERSTATSCOLLISIONS_WB_SIZE 2
#define MSTAT_REG_DOT3STATSSINGLECOLLISIONFRAMES_WB 0x4b0UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the DOT3STATSSINGLECOLLISIONFRAMES statitic.
#define MSTAT_REG_DOT3STATSSINGLECOLLISIONFRAMES_WB_SIZE 2
#define MSTAT_REG_DOT3STATSMULTIPLECOLLISIONFRAMES_WB 0x4b8UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the DOT3STATSMULTIPLECOLLISIONFRAMES statitic.
#define MSTAT_REG_DOT3STATSMULTIPLECOLLISIONFRAMES_WB_SIZE 2
#define MSTAT_REG_DOT3STATSDEFERREDTRANSMISSIONS_WB 0x4c0UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the DOT3STATSDEFERREDTRANSMISSIONS statitic.
#define MSTAT_REG_DOT3STATSDEFERREDTRANSMISSIONS_WB_SIZE 2
#define MSTAT_REG_DOT3STATSEXCESSIVECOLLISIONS_WB 0x4c8UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the DOT3STATSEXCESSIVECOLLISIONS statitic.
#define MSTAT_REG_DOT3STATSEXCESSIVECOLLISIONS_WB_SIZE 2
#define MSTAT_REG_DOT3STATSLATECOLLISIONS_WB 0x4d0UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the DOT3STATSLATECOLLISIONS statitic.
#define MSTAT_REG_DOT3STATSLATECOLLISIONS_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GR64_WB 0x600UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GR64 statitic.
#define MSTAT_REG_RX_STAT_GR64_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GR127_WB 0x608UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GR127 statitic.
#define MSTAT_REG_RX_STAT_GR127_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GR255_WB 0x610UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GR255 statitic.
#define MSTAT_REG_RX_STAT_GR255_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GR511_WB 0x618UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GR511 statitic.
#define MSTAT_REG_RX_STAT_GR511_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GR1023_WB 0x620UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GR1023 statitic.
#define MSTAT_REG_RX_STAT_GR1023_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GR1518_WB 0x628UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GR1518 statitic.
#define MSTAT_REG_RX_STAT_GR1518_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GR2047_WB 0x630UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GR2047 statitic.
#define MSTAT_REG_RX_STAT_GR2047_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GR4095_WB 0x638UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GR4095 statitic.
#define MSTAT_REG_RX_STAT_GR4095_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GR9216_WB 0x640UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GR9216 statitic.
#define MSTAT_REG_RX_STAT_GR9216_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GR16383_WB 0x648UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GR16383 statitic.
#define MSTAT_REG_RX_STAT_GR16383_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRPKT_WB 0x650UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRPKT statitic.
#define MSTAT_REG_RX_STAT_GRPKT_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRFCS_WB 0x658UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRFCS statitic.
#define MSTAT_REG_RX_STAT_GRFCS_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRUCA_WB 0x660UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRUCA statitic.
#define MSTAT_REG_RX_STAT_GRUCA_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRMCA_WB 0x668UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRMCA statitic.
#define MSTAT_REG_RX_STAT_GRMCA_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRBCA_WB 0x670UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRBCA statitic.
#define MSTAT_REG_RX_STAT_GRBCA_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRXPF_WB 0x678UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRXPF statitic.
#define MSTAT_REG_RX_STAT_GRXPF_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRXPP_WB 0x680UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRXPP statitic.
#define MSTAT_REG_RX_STAT_GRXPP_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRXUO_WB 0x688UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRXUO statitic.
#define MSTAT_REG_RX_STAT_GRXUO_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GROVR_WB 0x690UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GROVR statitic.
#define MSTAT_REG_RX_STAT_GROVR_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRXCF_WB 0x698UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRXCF statitic.
#define MSTAT_REG_RX_STAT_GRXCF_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRFLR_WB 0x6a0UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRFLR statitic.
#define MSTAT_REG_RX_STAT_GRFLR_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRPOK_WB 0x6a8UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRPOK statitic.
#define MSTAT_REG_RX_STAT_GRPOK_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRBYT_WB 0x6b0UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRBYT statitic.
#define MSTAT_REG_RX_STAT_GRBYT_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRUND_WB 0x6b8UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRUND statitic.
#define MSTAT_REG_RX_STAT_GRUND_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRFRG_WB 0x6c0UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRFRG statitic.
#define MSTAT_REG_RX_STAT_GRFRG_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRERB_WB 0x6c8UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRERB statitic.
#define MSTAT_REG_RX_STAT_GRERB_WB_SIZE 2
#define MSTAT_REG_RX_STAT_GRFRE_WB 0x6d0UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RX_STAT_GRFRE statitic.
#define MSTAT_REG_RX_STAT_GRFRE_WB_SIZE 2
#define MSTAT_REG_DOT3STATSALIGNMENTERRORS_WB 0x6d8UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the DOT3STATSALIGNMENTERRORS statitic.
#define MSTAT_REG_DOT3STATSALIGNMENTERRORS_WB_SIZE 2
#define MSTAT_REG_FALSECARRIERERRORS_WB 0x6e0UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the FALSECARRIERERRORS statitic.
#define MSTAT_REG_FALSECARRIERERRORS_WB_SIZE 2
#define MSTAT_REG_RXLLFCMSGCNT_WB 0x6e8UL //ACCESS:WB_R DataWidth:0x40 Description: This register provides WB-RO access of the RxLLFCMSGCNT statitic.
#define MSTAT_REG_RXLLFCMSGCNT_WB_SIZE 2
#define MSTAT_REG_MSTAT_UNUSED_EMPTY_0 0xd8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MSTAT_REG_MSTAT_UNUSED_EMPTY_0_SIZE 74
#define MSTAT_REG_MSTAT_UNUSED_EMPTY_1 0x2f0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MSTAT_REG_MSTAT_UNUSED_EMPTY_1_SIZE 68
#define MSTAT_REG_MSTAT_UNUSED_EMPTY_2 0x4d8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MSTAT_REG_MSTAT_UNUSED_EMPTY_2_SIZE 74
#define MSTAT_REG_MSTAT_UNUSED_EMPTY_3 0x6f0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define MSTAT_REG_MSTAT_UNUSED_EMPTY_3_SIZE 64
#define NIG_REG_NIG_INGRESS_PORT_RMP_FIFO_0_TM 0x10000UL //ACCESS:RW DataWidth:0x5 Description: TM for management fifo
#define NIG_REG_NIG_INGRESS_PORT_RMP_FIFO_1_TM 0x10004UL //ACCESS:RW DataWidth:0x5 Description: TM for management fifo
#define NIG_REG_NIG_INGRESS_EOP_FIFO_0_TM 0x10008UL //ACCESS:RW DataWidth:0x5 Description: TM for eop fifo of port0
#define NIG_REG_NIG_INGRESS_EOP_FIFO_1_TM 0x1000cUL //ACCESS:RW DataWidth:0x5 Description: TM for eop fifo of port1
#define NIG_REG_NIG_INGRESS_EOP_FIFO_2_TM 0x10010UL //ACCESS:RW DataWidth:0x5 Description: TM for eop fifo of LB
#define NIG_REG_NIG_EGRESS_RMP_FIFO_0_TM 0x10014UL //ACCESS:RW DataWidth:0x5 Description: TM for rmp fifo in TX
#define NIG_REG_NIG_EGRESS_RMP_FIFO_1_TM 0x10018UL //ACCESS:RW DataWidth:0x5 Description: TM for rmp fifo in TX
#define NIG_REG_EGRESS_DEBUG_ALM_FULL 0x1001cUL //ACCESS:RW DataWidth:0x4 Description: Almoust full for debug FIFO in NIG_TX_DBG
#define NIG_REG_EGRESS_DELAY_ALM_FULL 0x10020UL //ACCESS:RW DataWidth:0x4 Description: Almoust full for delay PBF FIFO in NIG_TX_PORT0 and NIG_TX_PORT1
#define NIG_REG_INGRESS_PBF_LB_BUFFER_ALM_FULL 0x10028UL //ACCESS:RW DataWidth:0x4 Description: Almoust full for Delay FIFO from PBF in NIG_RX_lb
#define NIG_REG_TIMER0_MAX 0x1002cUL //ACCESS:RW DataWidth:0x20 Description: Maximum value for timer ~nig_registers_timer0_counter.timer0_counter in NIG_TX_PORT0
#define NIG_REG_TIMER1_MAX 0x10030UL //ACCESS:RW DataWidth:0x20 Description: Maximum value for timer ~nig_registers_timer1_counter.timer1_counter in NIG_TX_PORT1
#define NIG_REG_TIMER0_WRAP 0x10034UL //ACCESS:RW DataWidth:0x1 Description: If 1- ~nig_registers_timer0_counter.timer0_counter counts from 0 after it gets maximum value = ~nig_registers_timer0_max.timer0_max. In this case interrupt to RBC may be sent some times: each time when counter gets maximum. Other way if 0 - it stops to count for port0
#define NIG_REG_TIMER1_WRAP 0x10038UL //ACCESS:RW DataWidth:0x1 Description: If 1- ~nig_registers_timer1_counter.timer1_counter counts from 0 after it gets maximum value ~nig_registers_timer1_max.timer1_max. In this case interrupt to RBC may be sent some times: each time when counter gets maximum. Other way if 0 - it stops to count for port1
#define NIG_REG_EGRESS_DEBUG_PORT 0x10054UL //ACCESS:RW DataWidth:0x1 Description: Port configuration for packet from debug IF. 1 - debug packet for port 1; other way for port 0
#define NIG_REG_EGRESS_EMAC0_PORT 0x10058UL //ACCESS:RW DataWidth:0x1 Description: MAC configuration for packets of port0. If 1 - all packet outputs to emac for port0; other way to bmac for port0
#define NIG_REG_EGRESS_EMAC1_PORT 0x1005cUL //ACCESS:RW DataWidth:0x1 Description: MAC configuration for packets of port1. If 1 - all packet outputs to emac for port1; other way to bmac for port1. This bit is not used in E2 since port 1 only has EMAC.
#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060UL //ACCESS:RW DataWidth:0x1 Description: If 1 - egress drain mode for port0 is active. In this mode all packets from PBFare not forwarded to the MAC and just deleted from FIFO. First packet may be deleted from the middle. And last packet will be always deleted till the end.
#define NIG_REG_EGRESS_DRAIN1_MODE 0x10064UL //ACCESS:RW DataWidth:0x1 Description: If 1 - egress drain mode for port1 is active. In this mode all packets from PBFare not forwarded to the MAC and just deleted from FIFO. First packet may be deleted from the middle. And last packet will be always deleted till the end.
#define NIG_REG_EGRESS_PARITY_ERR_MASK 0x10068UL //ACCESS:RW DataWidth:0x1 Description: if 1 - egress drain mode is enabled when parity error input Is active ti NIG. Otherway always masks parity error.
#define NIG_REG_INGRESS_MNG0_PKT_END 0x1006cUL //ACCESS:RW DataWidth:0x1 Description: When UMP and RBC end to work with RX management packet of port0; RBC has to write to this register. It will cause to increment consumer pointer in RX management FIFO and NIG will pass to work with a next packet.
#define NIG_REG_INGRESS_MNG1_PKT_END 0x10070UL //ACCESS:RW DataWidth:0x1 Description: When UMP and RBC end to work with RX management packet of port1; RBC has to write to this register. It will cause to increment consumer pointer in RX management FIFO and NIG will pass to work with a next packet.
#define NIG_REG_LLH0_T_BIT 0x10074UL //ACCESS:RW DataWidth:0x1 Description: t bit for llh0
#define NIG_REG_LLH1_T_BIT 0x10078UL //ACCESS:RW DataWidth:0x1 Description: t bit for llh1
#define NIG_REG_LLH0_CM_HEADER 0x1007cUL //ACCESS:RW DataWidth:0x20 Description: cm header for llh0
#define NIG_REG_LLH1_CM_HEADER 0x10080UL //ACCESS:RW DataWidth:0x20 Description: cm header for llh1
#define NIG_REG_LLH0_EVENT_ID 0x10084UL //ACCESS:RW DataWidth:0x8 Description: event id for llh0
#define NIG_REG_LLH1_EVENT_ID 0x10088UL //ACCESS:RW DataWidth:0x8 Description: event id for llh1
#define NIG_REG_LLH0_ERROR_MASK 0x1008cUL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_VERSION_NOT_4 (0x1<<0)
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_VERSION_NOT_4_SIZE 0
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_VERSION_NOT_6 (0x1<<1)
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_VERSION_NOT_6_SIZE 1
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_HEADER_LESS_5 (0x1<<2)
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_HEADER_LESS_5_SIZE 2
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_HEADER_BIG_5 (0x1<<3)
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_HEADER_BIG_5_SIZE 3
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_UDP_LEN (0x1<<4)
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_UDP_LEN_SIZE 4
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_MAC_ERR (0x1<<5)
#define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_MAC_ERR_SIZE 5
#define NIG_REG_LLH1_ERROR_MASK 0x10090UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_VERSION_NOT_4 (0x1<<0)
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_VERSION_NOT_4_SIZE 0
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_VERSION_NOT_6 (0x1<<1)
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_VERSION_NOT_6_SIZE 1
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_HEADER_LESS_5 (0x1<<2)
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_HEADER_LESS_5_SIZE 2
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_HEADER_BIG_5 (0x1<<3)
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_HEADER_BIG_5_SIZE 3
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_UDP_LEN (0x1<<4)
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_UDP_LEN_SIZE 4
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_MAC_ERR (0x1<<5)
#define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_MAC_ERR_SIZE 5
#define NIG_REG_STAT0_MR_P 0x10094UL //ACCESS:ST DataWidth:0x8 Description: RX statistics for port 0 of xgxs or serdes: number of mr_page
#define NIG_REG_STAT1_MR_P 0x10098UL //ACCESS:ST DataWidth:0x8 Description: RX statistics for port1 of xgxs or serdes: number of mr_page
#define NIG_REG_STAT0_CL73_MR_P 0x1009cUL //ACCESS:ST DataWidth:0x8 Description: RX statistics for port 0 of xgxs or serdes: number of cl73 mr_page
#define NIG_REG_STAT1_CL73_MR_P 0x100a0UL //ACCESS:ST DataWidth:0x8 Description: RX statistics for port1 of xgxs or serdes: number of cl73 mr_page
#define NIG_REG_PBF_LB_IN_EN 0x100b4UL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX PBF LP IF
#define NIG_REG_PRS_REQ_IN_EN 0x100b8UL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX parser request IF
#define NIG_REG_INGRESS_UMP0_IN_EN 0x100bcUL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX UMP port 0 request IF
#define NIG_REG_INGRESS_UMP1_IN_EN 0x100c0UL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX UMP port 1 request IF
#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4UL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX BRB1 pause port 0 IF
#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8UL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX BRB1 pause port 1 IF
#define NIG_REG_EGRESS_PBF0_IN_EN 0x100ccUL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX PBF user packet from IF0
#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0UL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX PBF user packet from IF1
#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4UL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX UMP management packet port0 IF
#define NIG_REG_EGRESS_UMP1_IN_EN 0x100d8UL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX UMP management packet port1 IF
#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dcUL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX Debug packet
#define NIG_REG_XCM0_OUT_EN 0x100f0UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX_XCM0 IF
#define NIG_REG_XCM1_OUT_EN 0x100f4UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX_XCM1 IF
#define NIG_REG_BRB0_OUT_EN 0x100f8UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX BRB1 port0 IF
#define NIG_REG_BRB1_OUT_EN 0x100fcUL //ACCESS:RW DataWidth:0x1 Description: output enable for RX BRB1 port1 IF
#define NIG_REG_BRB_LB_OUT_EN 0x10100UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX BRB1 LP IF
#define NIG_REG_PRS_EOP_OUT_EN 0x10104UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX parser descriptor IF
#define NIG_REG_INGRESS_UMP0_OUT_EN 0x10108UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX UMP port 0 response IF
#define NIG_REG_INGRESS_UMP1_OUT_EN 0x1010cUL //ACCESS:RW DataWidth:0x1 Description: output enable for RX UMP port 1 response IF
#define NIG_REG_LLH0_ACPI_UPON_MGMT 0x10128UL //ACCESS:RW DataWidth:0x1 Description: for llh0 : 1 = if match on both WoL & mangement - set power_on; 0 - if match on both WoL & mangement - do not set power_on
#define NIG_REG_LLH1_ACPI_UPON_MGMT 0x1012cUL //ACCESS:RW DataWidth:0x1 Description: for llh1 : 1 = if match on both WoL & mangement - set power_on; 0 - if match on both WoL & mangement - do not set power_on
#define NIG_REG_LLH0_XCM_MASK 0x10130UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN_SIZE 0
#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_MAC_FRAME (0x1<<1)
#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_MAC_FRAME_SIZE 1
#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_LLFC (0x1<<2)
#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_LLFC_SIZE 2
#define NIG_REG_LLH1_XCM_MASK 0x10134UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN_SIZE 0
#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_MAC_FRAME (0x1<<1)
#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_MAC_FRAME_SIZE 1
#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_LLFC (0x1<<2)
#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_LLFC_SIZE 2
#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_mac_0: 1 out of 2 Description: destination MAC address 1; The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_MAC_0_1 0x101c4UL //ACCESS:RW DataWidth:0x10 Register llh0_dest_mac_0: 2 out of 2 Description: destination MAC address 1; The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_MAC_1_0 0x101c8UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_mac_1: 1 out of 2 Description: destination MAC address 2;The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_MAC_1_1 0x101ccUL //ACCESS:RW DataWidth:0x10 Register llh0_dest_mac_1: 2 out of 2 Description: destination MAC address 2;The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_MAC_2_0 0x101d0UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_mac_2: 1 out of 2 Description: destination MAC address 3;The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_MAC_2_1 0x101d4UL //ACCESS:RW DataWidth:0x10 Register llh0_dest_mac_2: 2 out of 2 Description: destination MAC address 3;The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_IP_0_0 0x101d8UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_0: 1 out of 4 Description: destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_0_1 0x101dcUL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_0: 2 out of 4 Description: destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_0_2 0x101e0UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_0: 3 out of 4 Description: destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_0_3 0x101e4UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_0: 4 out of 4 Description: destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_1_0 0x101e8UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_1: 1 out of 4 Description: destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_1_1 0x101ecUL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_1: 2 out of 4 Description: destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_1_2 0x101f0UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_1: 3 out of 4 Description: destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_1_3 0x101f4UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_1: 4 out of 4 Description: destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_2_0 0x101f8UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_2: 1 out of 4 Description: destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_2_1 0x101fcUL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_2: 2 out of 4 Description: destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_2_2 0x10200UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_2: 3 out of 4 Description: destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_DEST_IP_2_3 0x10204UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_ip_2: 4 out of 4 Description: destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208UL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4
#define NIG_REG_LLH0_IPV4_IPV6_1 0x1020cUL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_1.llh0_dest_ip_1. 0 - IPv6; 1-IPv4
#define NIG_REG_LLH0_IPV4_IPV6_2 0x10210UL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_2.llh0_dest_ip_2. 0 - IPv6; 1-IPv4
#define NIG_REG_LLH0_DEST_UDP_0 0x10214UL //ACCESS:RW DataWidth:0x10 Description: destination UDP address 1 The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_UDP_1 0x10218UL //ACCESS:RW DataWidth:0x10 Description: destination UDP address 2 The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_UDP_2 0x1021cUL //ACCESS:RW DataWidth:0x10 Description: destination UDP address 3 The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_TCP_0 0x10220UL //ACCESS:RW DataWidth:0x10 Description: destination TCP address 1. The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_TCP_1 0x10224UL //ACCESS:RW DataWidth:0x10 Description: destination TCP address 2. The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_TCP_2 0x10228UL //ACCESS:RW DataWidth:0x10 Description: destination TCP address 3. The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_VLAN_ID_0 0x1022cUL //ACCESS:RW DataWidth:0xc Description: VLAN ID 1. In case of VLAN packet the LLH will look for this ID.
#define NIG_REG_LLH0_VLAN_ID_1 0x10230UL //ACCESS:RW DataWidth:0xc Description: VLAN ID 2. In case of VLAN packet the LLH will look for this ID.
#define NIG_REG_LLH0_VLAN_ID_2 0x10234UL //ACCESS:RW DataWidth:0xc Description: VLAN ID 3. In case of VLAN packet the LLH will look for this ID.
#define NIG_REG_LLH0_BCN_TYPE 0x10238UL //ACCESS:RW DataWidth:0x10 Description: BCN EtherType. The LLH will look for this Ethertype as a BCN identifier.
#define NIG_REG_LLH0_MCP_MASK 0x1023cUL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_BRCST (0x1<<0)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_BRCST_SIZE 0
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MLCST (0x1<<1)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MLCST_SIZE 1
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UNCST (0x1<<2)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UNCST_SIZE 2
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MAC0 (0x1<<3)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MAC0_SIZE 3
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MAC1 (0x1<<4)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MAC1_SIZE 4
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MAC2 (0x1<<5)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MAC2_SIZE 5
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_ARP (0x1<<6)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_ARP_SIZE 6
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_IP0 (0x1<<7)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_IP0_SIZE 7
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_IP1 (0x1<<8)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_IP1_SIZE 8
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_IP2 (0x1<<9)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_IP2_SIZE 9
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_U_SRC (0x1<<10)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_U_SRC_SIZE 10
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_T_SRC (0x1<<11)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_T_SRC_SIZE 11
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_RMCP (0x1<<12)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_RMCP_SIZE 12
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_DHCP (0x1<<13)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_DHCP_SIZE 13
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_U_DST (0x1<<14)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_U_DST_SIZE 14
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UDP0 (0x1<<15)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UDP0_SIZE 15
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UDP1 (0x1<<16)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UDP1_SIZE 16
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UDP2 (0x1<<17)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UDP2_SIZE 17
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_T_DST (0x1<<18)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_T_DST_SIZE 18
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_TCP0 (0x1<<19)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_TCP0_SIZE 19
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_TCP1 (0x1<<20)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_TCP1_SIZE 20
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_TCP2 (0x1<<21)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_TCP2_SIZE 21
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN_ID0 (0x1<<22)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN_ID0_SIZE 22
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN_ID1 (0x1<<23)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN_ID1_SIZE 23
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN_ID2 (0x1<<24)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN_ID2_SIZE 24
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN (0x1<<25)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN_SIZE 25
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NO_VLAN (0x1<<26)
#define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NO_VLAN_SIZE 26
#define NIG_REG_LLH1_MCP_MASK 0x10240UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_BRCST (0x1<<0)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_BRCST_SIZE 0
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MLCST (0x1<<1)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MLCST_SIZE 1
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UNCST (0x1<<2)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UNCST_SIZE 2
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MAC0 (0x1<<3)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MAC0_SIZE 3
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MAC1 (0x1<<4)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MAC1_SIZE 4
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MAC2 (0x1<<5)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MAC2_SIZE 5
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_ARP (0x1<<6)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_ARP_SIZE 6
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_IP0 (0x1<<7)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_IP0_SIZE 7
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_IP1 (0x1<<8)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_IP1_SIZE 8
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_IP2 (0x1<<9)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_IP2_SIZE 9
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_U_SRC (0x1<<10)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_U_SRC_SIZE 10
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_T_SRC (0x1<<11)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_T_SRC_SIZE 11
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_RMCP (0x1<<12)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_RMCP_SIZE 12
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_DHCP (0x1<<13)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_DHCP_SIZE 13
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_U_DST (0x1<<14)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_U_DST_SIZE 14
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UDP0 (0x1<<15)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UDP0_SIZE 15
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UDP1 (0x1<<16)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UDP1_SIZE 16
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UDP2 (0x1<<17)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UDP2_SIZE 17
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_T_DST (0x1<<18)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_T_DST_SIZE 18
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_TCP0 (0x1<<19)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_TCP0_SIZE 19
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_TCP1 (0x1<<20)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_TCP1_SIZE 20
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_TCP2 (0x1<<21)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_TCP2_SIZE 21
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN_ID0 (0x1<<22)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN_ID0_SIZE 22
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN_ID1 (0x1<<23)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN_ID1_SIZE 23
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN_ID2 (0x1<<24)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN_ID2_SIZE 24
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN (0x1<<25)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN_SIZE 25
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NO_VLAN (0x1<<26)
#define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NO_VLAN_SIZE 26
#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST_SIZE 0
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST_SIZE 1
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST_SIZE 2
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN_SIZE 3
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN_SIZE 4
#define NIG_LLH0_BRB1_DRV_MASK_REG_P0_LLH_BRB1_DRV_MASK_ALLMLCST (0x1<<5)
#define NIG_LLH0_BRB1_DRV_MASK_REG_P0_LLH_BRB1_DRV_MASK_ALLMLCST_SIZE 5
#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_BRCST (0x1<<0)
#define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_BRCST_SIZE 0
#define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_MLCST (0x1<<1)
#define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_MLCST_SIZE 1
#define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_UNCST (0x1<<2)
#define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_UNCST_SIZE 2
#define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_VLAN (0x1<<3)
#define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_VLAN_SIZE 3
#define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
#define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_NO_VLAN_SIZE 4
#define NIG_LLH1_BRB1_DRV_MASK_REG_P1_LLH_BRB1_DRV_MASK_ALLMLCST (0x1<<5)
#define NIG_LLH1_BRB1_DRV_MASK_REG_P1_LLH_BRB1_DRV_MASK_ALLMLCST_SIZE 5
#define NIG_REG_LLH0_BRB1_MCP_MASK 0x1024cUL //ACCESS:RW DataWidth:0x16 Multi Field Register
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_MAC0 (0x1<<0)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_MAC0_SIZE 0
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_MAC1 (0x1<<1)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_MAC1_SIZE 1
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_MAC2 (0x1<<2)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_MAC2_SIZE 2
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_ARP (0x1<<3)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_ARP_SIZE 3
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_IP0 (0x1<<4)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_IP0_SIZE 4
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_IP1 (0x1<<5)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_IP1_SIZE 5
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_IP2 (0x1<<6)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_IP2_SIZE 6
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_UDP_SRC_SIZE 7
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_TCP_SRC_SIZE 8
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_RMCP (0x1<<9)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_RMCP_SIZE 9
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_DHCP (0x1<<10)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_DHCP_SIZE 10
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_UDP_DST_SIZE 11
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_UDP0 (0x1<<12)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_UDP0_SIZE 12
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_UDP1 (0x1<<13)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_UDP1_SIZE 13
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_UDP2 (0x1<<14)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_UDP2_SIZE 14
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_TCP_DST_SIZE 15
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_TCP0 (0x1<<16)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_TCP0_SIZE 16
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_TCP1 (0x1<<17)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_TCP1_SIZE 17
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_TCP2 (0x1<<18)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_TCP2_SIZE 18
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_VLAN_ID0 (0x1<<19)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_VLAN_ID0_SIZE 19
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_VLAN_ID1 (0x1<<20)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_VLAN_ID1_SIZE 20
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_VLAN_ID2 (0x1<<21)
#define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_VLAN_ID2_SIZE 21
#define NIG_REG_LLH1_BRB1_MCP_MASK 0x10250UL //ACCESS:RW DataWidth:0x16 Multi Field Register
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_MAC0 (0x1<<0)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_MAC0_SIZE 0
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_MAC1 (0x1<<1)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_MAC1_SIZE 1
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_MAC2 (0x1<<2)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_MAC2_SIZE 2
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_ARP (0x1<<3)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_ARP_SIZE 3
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_IP0 (0x1<<4)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_IP0_SIZE 4
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_IP1 (0x1<<5)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_IP1_SIZE 5
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_IP2 (0x1<<6)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_IP2_SIZE 6
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_UDP_SRC_SIZE 7
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_TCP_SRC_SIZE 8
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_RMCP (0x1<<9)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_RMCP_SIZE 9
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_DHCP (0x1<<10)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_DHCP_SIZE 10
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_UDP_DST_SIZE 11
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_UDP0 (0x1<<12)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_UDP0_SIZE 12
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_UDP1 (0x1<<13)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_UDP1_SIZE 13
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_UDP2 (0x1<<14)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_UDP2_SIZE 14
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_TCP_DST_SIZE 15
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_TCP0 (0x1<<16)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_TCP0_SIZE 16
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_TCP1 (0x1<<17)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_TCP1_SIZE 17
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_TCP2 (0x1<<18)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_TCP2_SIZE 18
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_VLAN_ID0 (0x1<<19)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_VLAN_ID0_SIZE 19
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_VLAN_ID1 (0x1<<20)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_VLAN_ID1_SIZE 20
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_VLAN_ID2 (0x1<<21)
#define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_VLAN_ID2_SIZE 21
#define NIG_REG_LLH0_ACPI_VLAN_STRIP 0x10254UL //ACCESS:RW DataWidth:0x1 Description: Remove VLAN before calculating ACPI pattern. This bit is replaced by llh_acpi_tag_rm in E2.
#define NIG_REG_LLH1_ACPI_VLAN_STRIP 0x10258UL //ACCESS:RW DataWidth:0x1 Description: remove VLAN before calculating ACPI pattern.
#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025cUL //ACCESS:RW DataWidth:0x1 Description: send to BRB1 if no match on any of RMP rules.
#define NIG_REG_LLH1_DEST_MAC_0_0 0x10260UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_mac_0: 1 out of 2 Description: destination MAC address 1; The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_MAC_0_1 0x10264UL //ACCESS:RW DataWidth:0x10 Register llh1_dest_mac_0: 2 out of 2 Description: destination MAC address 1; The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_MAC_1_0 0x10268UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_mac_1: 1 out of 2 Description: destination MAC address 2; The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_MAC_1_1 0x1026cUL //ACCESS:RW DataWidth:0x10 Register llh1_dest_mac_1: 2 out of 2 Description: destination MAC address 2; The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_MAC_2_0 0x10270UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_mac_2: 1 out of 2 Description: destination MAC address 3; The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_MAC_2_1 0x10274UL //ACCESS:RW DataWidth:0x10 Register llh1_dest_mac_2: 2 out of 2 Description: destination MAC address 3; The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_IP_0_0 0x10278UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_0: 1 out of 4 Description: destination IP address 1; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_0_1 0x1027cUL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_0: 2 out of 4 Description: destination IP address 1; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_0_2 0x10280UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_0: 3 out of 4 Description: destination IP address 1; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_0_3 0x10284UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_0: 4 out of 4 Description: destination IP address 1; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_1_0 0x10288UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_1: 1 out of 4 Description: destination IP address 2; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_1_1 0x1028cUL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_1: 2 out of 4 Description: destination IP address 2; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_1_2 0x10290UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_1: 3 out of 4 Description: destination IP address 2; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_1_3 0x10294UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_1: 4 out of 4 Description: destination IP address 2; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_2_0 0x10298UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_2: 1 out of 4 Description: destination IP address 3; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_2_1 0x1029cUL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_2: 2 out of 4 Description: destination IP address 3; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_2_2 0x102a0UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_2: 3 out of 4 Description: destination IP address 3; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_DEST_IP_2_3 0x102a4UL //ACCESS:RW DataWidth:0x20 Register llh1_dest_ip_2: 4 out of 4 Description: destination IP address 3; The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
#define NIG_REG_LLH1_IPV4_IPV6_0 0x102a8UL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4
#define NIG_REG_LLH1_IPV4_IPV6_1 0x102acUL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_1.llh0_dest_ip_1. 0 - IPv6; 1-IPv4
#define NIG_REG_LLH1_IPV4_IPV6_2 0x102b0UL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_2.llh0_dest_ip_2. 0 - IPv6; 1-IPv4
#define NIG_REG_LLH1_DEST_UDP_0 0x102b4UL //ACCESS:RW DataWidth:0x10 Description: destination UDP address 1;The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_UDP_1 0x102b8UL //ACCESS:RW DataWidth:0x10 Description: destination UDP address 2 ;The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_UDP_2 0x102bcUL //ACCESS:RW DataWidth:0x10 Description: destination UDP address 3 ;The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_TCP_0 0x102c0UL //ACCESS:RW DataWidth:0x10 Description: destination TCP address 1. The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_TCP_1 0x102c4UL //ACCESS:RW DataWidth:0x10 Description: destination TCP address 2. The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_TCP_2 0x102c8UL //ACCESS:RW DataWidth:0x10 Description: destination TCP address 3. The LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_VLAN_ID_0 0x102ccUL //ACCESS:RW DataWidth:0xc Description: VLAN ID 1. In case of VLAN packet; the LLH will look for this ID.
#define NIG_REG_LLH1_VLAN_ID_1 0x102d0UL //ACCESS:RW DataWidth:0xc Description: VLAN ID 2. In case of VLAN packet; the LLH will look for this ID.
#define NIG_REG_LLH1_VLAN_ID_2 0x102d4UL //ACCESS:RW DataWidth:0xc Description: VLAN ID 3. In case of VLAN packet; the LLH will look for this ID.
#define NIG_REG_LLH1_BCN_TYPE 0x102d8UL //ACCESS:RW DataWidth:0x10 Description: BCN EtherType. The LLH will look for this Ethertype as a BCN identifier.
#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dcUL //ACCESS:RW DataWidth:0x1 Description: send to BRB1 if no match on any of RMP rules.
#define NIG_REG_LED_MODE_P0 0x102f0UL //ACCESS:RW DataWidth:0x4 Description: led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 9-11PHY7; 12 MAC4; 13-15 PHY10;
#define NIG_REG_LED_MODE_P1 0x102f4UL //ACCESS:RW DataWidth:0x4 Description: led mode for port1: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 9-11PHY7; 12 MAC4; 13-15 PHY10;
#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8UL //ACCESS:RW DataWidth:0x1 Description: Port0: If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit ~nig_registers_ led_control_traffic_p0.led_control_traffic_p0 and bit ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0
#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P1 0x102fcUL //ACCESS:RW DataWidth:0x1 Description: Port1: If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit ~nig_registers_led_control_traffic_p1.led_control_traffic_p1 and bit ~nig_registers_led_control_blink_traffic_p1.led_control_blink_traffic_p1.
#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300UL //ACCESS:RW DataWidth:0x1 Description: Port0: If set along with the led_control_override_trafic_p0 bit; turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also set; the LED will blink with blink rate specified in ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 fields.
#define NIG_REG_LED_CONTROL_TRAFFIC_P1 0x10304UL //ACCESS:RW DataWidth:0x1 Description: Port1: If set along with the ~nig_registers_led_control_override_trafic_p0.led_control_override_trafic_p0 bit; turns on the Traffic LED. If the ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 bit is also set; the LED will blink with blink rate specified in ~nig_registers_led_control_blink_rate_p1.led_control_blink_rate_p1 and ~nig_registers_led_control_blink_rate_ena_p1.led_control_blink_rate_ena_p1 fields.
#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308UL //ACCESS:RW DataWidth:0x1 Description: Port0: If set along with the ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED bit; the Traffic LED will blink with the blink rate specified in ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 fields.
#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P1 0x1030cUL //ACCESS:RW DataWidth:0x1 Description: Port1: If set along with the ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED bit; the Traffic LED will blink with the blink rate specified in ~nig_registers_led_control_blink_rate_p1.led_control_blink_rate_p1 and ~nig_registers_led_control_blink_rate_ena_p1. led_control_blink_rate_ena_p1 fields.
#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310UL //ACCESS:RW DataWidth:0xc Description: Port0: Specifies the period of each blink cycle (on + off) for Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field is reset to 0x080; giving a default blink period of approximately 8Hz.
#define NIG_REG_LED_CONTROL_BLINK_RATE_P1 0x10314UL //ACCESS:RW DataWidth:0xc Description: Port1: Specifies the period of each blink cycle (on + off) for Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field is reset to 0x080; giving a default blink period of approximately 8Hz.
#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318UL //ACCESS:RW DataWidth:0x1 Description: Port0: This bit is set to enable the use of the ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field defined below. If this bit is cleared; then the blink rate will be about 8Hz.
#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P1 0x1031cUL //ACCESS:RW DataWidth:0x1 Description: Port1: This bit is set to enable the use of the ~nig_registers_led_control_blink_rate_p1.led_control_blink_rate_p1 field defined below. If this bit is cleared; then the blink rate will be about 8Hz.
#define NIG_REG_LED_10G_P0 0x10320UL //ACCESS:RW DataWidth:0x1 Description: led 10g for port 0
#define NIG_REG_LED_10G_P1 0x10324UL //ACCESS:RW DataWidth:0x1 Description: led 10g for port 1
#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT_SIZE 0
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_COMPLETE (0x1<<1)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_COMPLETE_SIZE 1
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_CFG_CHANGE (0x1<<2)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_CFG_CHANGE_SIZE 2
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_STATUS (0x1<<3)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_STATUS_SIZE 3
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_CHANGE (0x1<<4)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_CHANGE_SIZE 4
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_ATTN (0x1<<5)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_ATTN_SIZE 5
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MAC_CRS (0x1<<6)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MAC_CRS_SIZE 6
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_AUTONEG_COMPLETE (0x1<<7)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_AUTONEG_COMPLETE_SIZE 7
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_FIBER_RXACT (0x1<<8)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_FIBER_RXACT_SIZE 8
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS_SIZE 9
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MR_PAGE_RX (0x1<<10)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MR_PAGE_RX_SIZE 10
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_AN_COMPLETE (0x1<<11)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_AN_COMPLETE_SIZE 11
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_MR_PAGE_RX (0x1<<12)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_MR_PAGE_RX_SIZE 12
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_RX_SIGDET (0x1<<13)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_RX_SIGDET_SIZE 13
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_REMOTEMDIOREQ (0x1<<14)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_REMOTEMDIOREQ_SIZE 14
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G_SIZE 15
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_AUTONEG_COMPLETE (0x1<<16)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_AUTONEG_COMPLETE_SIZE 16
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_FIBER_RXACT (0x1<<17)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_FIBER_RXACT_SIZE 17
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MR_PAGE_RX (0x1<<22)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MR_PAGE_RX_SIZE 22
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_AN_COMPLETE (0x1<<23)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_AN_COMPLETE_SIZE 23
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_MR_PAGE_RX (0x1<<24)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_MR_PAGE_RX_SIZE 24
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_RX_SIGDET (0x1<<25)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_RX_SIGDET_SIZE 25
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MAC_CRS (0x1<<26)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MAC_CRS_SIZE 26
#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032cUL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_INT (0x1<<0)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_INT_SIZE 0
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_COMPLETE (0x1<<1)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_COMPLETE_SIZE 1
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_CFG_CHANGE (0x1<<2)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_CFG_CHANGE_SIZE 2
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_STATUS (0x1<<3)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_STATUS_SIZE 3
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_CHANGE (0x1<<4)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_CHANGE_SIZE 4
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_ATTN (0x1<<5)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_ATTN_SIZE 5
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MAC_CRS (0x1<<6)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MAC_CRS_SIZE 6
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_AUTONEG_COMPLETE (0x1<<7)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_AUTONEG_COMPLETE_SIZE 7
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_FIBER_RXACT (0x1<<8)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_FIBER_RXACT_SIZE 8
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_LINK_STATUS (0x1<<9)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_LINK_STATUS_SIZE 9
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MR_PAGE_RX (0x1<<10)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MR_PAGE_RX_SIZE 10
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_AN_COMPLETE (0x1<<11)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_AN_COMPLETE_SIZE 11
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_MR_PAGE_RX (0x1<<12)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_MR_PAGE_RX_SIZE 12
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_RX_SIGDET (0x1<<13)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_RX_SIGDET_SIZE 13
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_REMOTEMDIOREQ (0x1<<14)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_REMOTEMDIOREQ_SIZE 14
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK10G (0x1<<15)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK10G_SIZE 15
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_AUTONEG_COMPLETE (0x1<<16)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_AUTONEG_COMPLETE_SIZE 16
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_FIBER_RXACT (0x1<<17)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_FIBER_RXACT_SIZE 17
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK_STATUS (0xf<<18)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK_STATUS_SIZE 18
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MR_PAGE_RX (0x1<<22)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MR_PAGE_RX_SIZE 22
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_AN_COMPLETE (0x1<<23)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_AN_COMPLETE_SIZE 23
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_MR_PAGE_RX (0x1<<24)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_MR_PAGE_RX_SIZE 24
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_RX_SIGDET (0x1<<25)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_RX_SIGDET_SIZE 25
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MAC_CRS (0x1<<26)
#define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MAC_CRS_SIZE 26
#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT_SIZE 0
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_COMPLETE (0x1<<1)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_COMPLETE_SIZE 1
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_CFG_CHANGE (0x1<<2)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_CFG_CHANGE_SIZE 2
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_LINK_STATUS (0x1<<3)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_LINK_STATUS_SIZE 3
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_LINK_CHANGE (0x1<<4)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_LINK_CHANGE_SIZE 4
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_ATTN (0x1<<5)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_ATTN_SIZE 5
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_MAC_CRS (0x1<<6)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_MAC_CRS_SIZE 6
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_AUTONEG_COMPLETE (0x1<<7)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_AUTONEG_COMPLETE_SIZE 7
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_FIBER_RXACT (0x1<<8)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_FIBER_RXACT_SIZE 8
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS_SIZE 9
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_MR_PAGE_RX (0x1<<10)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_MR_PAGE_RX_SIZE 10
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_CL73_AN_COMPLETE (0x1<<11)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_CL73_AN_COMPLETE_SIZE 11
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_CL73_MR_PAGE_RX (0x1<<12)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_CL73_MR_PAGE_RX_SIZE 12
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_RX_SIGDET (0x1<<13)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_RX_SIGDET_SIZE 13
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_REMOTEMDIOREQ (0x1<<14)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_REMOTEMDIOREQ_SIZE 14
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G_SIZE 15
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_AUTONEG_COMPLETE (0x1<<16)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_AUTONEG_COMPLETE_SIZE 16
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_FIBER_RXACT (0x1<<17)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_FIBER_RXACT_SIZE 17
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS_SIZE 18
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_MR_PAGE_RX (0x1<<22)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_MR_PAGE_RX_SIZE 22
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_CL73_AN_COMPLETE (0x1<<23)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_CL73_AN_COMPLETE_SIZE 23
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_CL73_MR_PAGE_RX (0x1<<24)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_CL73_MR_PAGE_RX_SIZE 24
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_RX_SIGDET (0x1<<25)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_RX_SIGDET_SIZE 25
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_MAC_CRS (0x1<<26)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_MAC_CRS_SIZE 26
#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_MI_INT (0x1<<0)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_MI_INT_SIZE 0
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_MI_COMPLETE (0x1<<1)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_MI_COMPLETE_SIZE 1
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_CFG_CHANGE (0x1<<2)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_CFG_CHANGE_SIZE 2
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_LINK_STATUS (0x1<<3)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_LINK_STATUS_SIZE 3
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_LINK_CHANGE (0x1<<4)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_LINK_CHANGE_SIZE 4
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_ATTN (0x1<<5)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_ATTN_SIZE 5
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_MAC_CRS (0x1<<6)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_MAC_CRS_SIZE 6
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_AUTONEG_COMPLETE (0x1<<7)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_AUTONEG_COMPLETE_SIZE 7
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_FIBER_RXACT (0x1<<8)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_FIBER_RXACT_SIZE 8
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_LINK_STATUS (0x1<<9)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_LINK_STATUS_SIZE 9
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_MR_PAGE_RX (0x1<<10)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_MR_PAGE_RX_SIZE 10
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_CL73_AN_COMPLETE (0x1<<11)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_CL73_AN_COMPLETE_SIZE 11
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_CL73_MR_PAGE_RX (0x1<<12)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_CL73_MR_PAGE_RX_SIZE 12
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_RX_SIGDET (0x1<<13)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_RX_SIGDET_SIZE 13
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_REMOTEMDIOREQ (0x1<<14)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_REMOTEMDIOREQ_SIZE 14
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_LINK10G (0x1<<15)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_LINK10G_SIZE 15
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_AUTONEG_COMPLETE (0x1<<16)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_AUTONEG_COMPLETE_SIZE 16
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_FIBER_RXACT (0x1<<17)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_FIBER_RXACT_SIZE 17
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_LINK_STATUS (0xf<<18)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_LINK_STATUS_SIZE 18
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_MR_PAGE_RX (0x1<<22)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_MR_PAGE_RX_SIZE 22
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_CL73_AN_COMPLETE (0x1<<23)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_CL73_AN_COMPLETE_SIZE 23
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_CL73_MR_PAGE_RX (0x1<<24)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_CL73_MR_PAGE_RX_SIZE 24
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_RX_SIGDET (0x1<<25)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_RX_SIGDET_SIZE 25
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_MAC_CRS (0x1<<26)
#define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_MAC_CRS_SIZE 26
#define NIG_REG_DBG_SELECT 0x10388UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from NIG to the DBG block) - for selecting a line to output to the DBG block
#define NIG_REG_DBG_BYTE_ENABLE 0x1038cUL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from NIG to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define NIG_REG_DBG_SHIFT 0x10390UL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from NIG to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define NIG_REG_PORT_SWAP 0x10394UL //ACCESS:RW DataWidth:0x1 Description: Value of this register will be transmitted to port swap when ~nig_registers_strap_override.strap_override =1
#define NIG_REG_STRAP_OVERRIDE 0x10398UL //ACCESS:RW DataWidth:0x1 Description: port swap mux selection. If this register equal to 0 then port swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then ort swap is equal to ~nig_registers_port_swap.port_swap
#define NIG_REG_SEL_DBG_IFMUX_TEST 0x1039cUL //ACCESS:RW DataWidth:0x1 Description: selection to mux from dbg block for output to ifmux.
#define NIG_REG_SEL_MUX_DBG_VECTOR 0x103a0UL //ACCESS:RW DataWidth:0x2 Description: selection of vector: 0 - from emac0; 1-from emac1; 2 - from msp; 3 - NA
#define NIG_REG_SEL_MUX_DBG_VECTOR_NUM 0x103a4UL //ACCESS:RW DataWidth:0x1 Description: If 0 - selection of vector: from port 0; 1 - from port 1
#define NIG_REG_DEBUG_SEL_1 0x103a8UL //ACCESS:RW DataWidth:0x4 Description: Debug only. This control is outputted to EMAC0 EMAC1 and MCP. It is used as a select for the debug mux sel_1 logic which exists in these blocks; it controls which signals are to be outputted on the Debug 1 interface.
#define NIG_REG_DEBUG_SEL_2 0x103acUL //ACCESS:RW DataWidth:0x4 Description: Debug only. This control is outputted to EMAC0 EMAC1 and MCP. It is used as a select for the debug mux sel_2 logic which exists in these blocks; it controls which signals are to be outputted on the Debug 2 interface.
#define NIG_REG_NIG_INT_STS_0 0x103b0UL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define NIG_NIG_INT_STS_0_REG_INGRESS_EOP_PORT0_ERROR (0x1<<1)
#define NIG_NIG_INT_STS_0_REG_INGRESS_EOP_PORT0_ERROR_SIZE 1
#define NIG_NIG_INT_STS_0_REG_INGRESS_EOP_PORT1_ERROR (0x1<<2)
#define NIG_NIG_INT_STS_0_REG_INGRESS_EOP_PORT1_ERROR_SIZE 2
#define NIG_NIG_INT_STS_0_REG_INGRESS_EOP_LB_ERROR (0x1<<3)
#define NIG_NIG_INT_STS_0_REG_INGRESS_EOP_LB_ERROR_SIZE 3
#define NIG_NIG_INT_STS_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR (0x1<<4)
#define NIG_NIG_INT_STS_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR_SIZE 4
#define NIG_NIG_INT_STS_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR (0x1<<5)
#define NIG_NIG_INT_STS_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR_SIZE 5
#define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC0_ERROR (0x1<<6)
#define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC0_ERROR_SIZE 6
#define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC1_ERROR (0x1<<7)
#define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC1_ERROR_SIZE 7
#define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC0_REGS_ERROR (0x1<<8)
#define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC0_REGS_ERROR_SIZE 8
#define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC1_REGS_ERROR (0x1<<9)
#define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC1_REGS_ERROR_SIZE 9
#define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC0_POP_ERROR (0x1<<10)
#define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC0_POP_ERROR_SIZE 10
#define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC1_POP_ERROR (0x1<<11)
#define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC1_POP_ERROR_SIZE 11
#define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC0_PUSH_ERROR (0x1<<12)
#define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC0_PUSH_ERROR_SIZE 12
#define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC1_PUSH_ERROR (0x1<<13)
#define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC1_PUSH_ERROR_SIZE 13
#define NIG_NIG_INT_STS_0_REG_INGRESS_LB_PBF_DELAY_ERROR (0x1<<14)
#define NIG_NIG_INT_STS_0_REG_INGRESS_LB_PBF_DELAY_ERROR_SIZE 14
#define NIG_NIG_INT_STS_0_REG_EGRESS_MNG0_FIFO_ERROR (0x1<<15)
#define NIG_NIG_INT_STS_0_REG_EGRESS_MNG0_FIFO_ERROR_SIZE 15
#define NIG_NIG_INT_STS_0_REG_EGRESS_MNG1_FIFO_ERROR (0x1<<16)
#define NIG_NIG_INT_STS_0_REG_EGRESS_MNG1_FIFO_ERROR_SIZE 16
#define NIG_NIG_INT_STS_0_REG_EGRESS_DEBUG_FIFO_ERROR (0x1<<17)
#define NIG_NIG_INT_STS_0_REG_EGRESS_DEBUG_FIFO_ERROR_SIZE 17
#define NIG_NIG_INT_STS_0_REG_EGRESS_DELAY0_ERROR (0x1<<18)
#define NIG_NIG_INT_STS_0_REG_EGRESS_DELAY0_ERROR_SIZE 18
#define NIG_NIG_INT_STS_0_REG_EGRESS_DELAY1_ERROR (0x1<<19)
#define NIG_NIG_INT_STS_0_REG_EGRESS_DELAY1_ERROR_SIZE 19
#define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC0_PUSH_ERROR (0x1<<20)
#define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC0_PUSH_ERROR_SIZE 20
#define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC1_PUSH_ERROR (0x1<<21)
#define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC1_PUSH_ERROR_SIZE 21
#define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC0_POP_ERROR (0x1<<22)
#define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC0_POP_ERROR_SIZE 22
#define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC1_POP_ERROR (0x1<<23)
#define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC1_POP_ERROR_SIZE 23
#define NIG_NIG_INT_STS_0_REG_EGRESS_BMAC0_ERROR (0x1<<24)
#define NIG_NIG_INT_STS_0_REG_EGRESS_BMAC0_ERROR_SIZE 24
#define NIG_NIG_INT_STS_0_REG_EGRESS_BMAC1_ERROR (0x1<<25)
#define NIG_NIG_INT_STS_0_REG_EGRESS_BMAC1_ERROR_SIZE 25
#define NIG_NIG_INT_STS_0_REG_TIMER0_MAX_INT (0x1<<26)
#define NIG_NIG_INT_STS_0_REG_TIMER0_MAX_INT_SIZE 26
#define NIG_NIG_INT_STS_0_REG_TIMER1_MAX_INT (0x1<<27)
#define NIG_NIG_INT_STS_0_REG_TIMER1_MAX_INT_SIZE 27
#define NIG_NIG_INT_STS_0_REG_LLH0_FIFO_ERROR (0x1<<28)
#define NIG_NIG_INT_STS_0_REG_LLH0_FIFO_ERROR_SIZE 28
#define NIG_NIG_INT_STS_0_REG_LLH1_FIFO_ERROR (0x1<<29)
#define NIG_NIG_INT_STS_0_REG_LLH1_FIFO_ERROR_SIZE 29
#define NIG_NIG_INT_STS_0_REG_LLFC0_POP_ERROR (0x1<<30)
#define NIG_NIG_INT_STS_0_REG_LLFC0_POP_ERROR_SIZE 30
#define NIG_NIG_INT_STS_0_REG_LLFC1_POP_ERROR (0x1<<31)
#define NIG_NIG_INT_STS_0_REG_LLFC1_POP_ERROR_SIZE 31
#define NIG_REG_NIG_INT_STS_CLR_0 0x103b4UL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EOP_PORT0_ERROR (0x1<<1)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EOP_PORT0_ERROR_SIZE 1
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EOP_PORT1_ERROR (0x1<<2)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EOP_PORT1_ERROR_SIZE 2
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EOP_LB_ERROR (0x1<<3)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EOP_LB_ERROR_SIZE 3
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR (0x1<<4)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR_SIZE 4
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR (0x1<<5)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR_SIZE 5
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC0_ERROR (0x1<<6)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC0_ERROR_SIZE 6
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC1_ERROR (0x1<<7)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC1_ERROR_SIZE 7
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC0_REGS_ERROR (0x1<<8)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC0_REGS_ERROR_SIZE 8
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC1_REGS_ERROR (0x1<<9)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC1_REGS_ERROR_SIZE 9
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC0_POP_ERROR (0x1<<10)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC0_POP_ERROR_SIZE 10
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC1_POP_ERROR (0x1<<11)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC1_POP_ERROR_SIZE 11
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC0_PUSH_ERROR (0x1<<12)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC0_PUSH_ERROR_SIZE 12
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC1_PUSH_ERROR (0x1<<13)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC1_PUSH_ERROR_SIZE 13
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_LB_PBF_DELAY_ERROR (0x1<<14)
#define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_LB_PBF_DELAY_ERROR_SIZE 14
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_MNG0_FIFO_ERROR (0x1<<15)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_MNG0_FIFO_ERROR_SIZE 15
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_MNG1_FIFO_ERROR (0x1<<16)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_MNG1_FIFO_ERROR_SIZE 16
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_DEBUG_FIFO_ERROR (0x1<<17)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_DEBUG_FIFO_ERROR_SIZE 17
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_DELAY0_ERROR (0x1<<18)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_DELAY0_ERROR_SIZE 18
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_DELAY1_ERROR (0x1<<19)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_DELAY1_ERROR_SIZE 19
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC0_PUSH_ERROR (0x1<<20)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC0_PUSH_ERROR_SIZE 20
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC1_PUSH_ERROR (0x1<<21)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC1_PUSH_ERROR_SIZE 21
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC0_POP_ERROR (0x1<<22)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC0_POP_ERROR_SIZE 22
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC1_POP_ERROR (0x1<<23)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC1_POP_ERROR_SIZE 23
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_BMAC0_ERROR (0x1<<24)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_BMAC0_ERROR_SIZE 24
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_BMAC1_ERROR (0x1<<25)
#define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_BMAC1_ERROR_SIZE 25
#define NIG_NIG_INT_STS_CLR_0_REG_TIMER0_MAX_INT (0x1<<26)
#define NIG_NIG_INT_STS_CLR_0_REG_TIMER0_MAX_INT_SIZE 26
#define NIG_NIG_INT_STS_CLR_0_REG_TIMER1_MAX_INT (0x1<<27)
#define NIG_NIG_INT_STS_CLR_0_REG_TIMER1_MAX_INT_SIZE 27
#define NIG_NIG_INT_STS_CLR_0_REG_LLH0_FIFO_ERROR (0x1<<28)
#define NIG_NIG_INT_STS_CLR_0_REG_LLH0_FIFO_ERROR_SIZE 28
#define NIG_NIG_INT_STS_CLR_0_REG_LLH1_FIFO_ERROR (0x1<<29)
#define NIG_NIG_INT_STS_CLR_0_REG_LLH1_FIFO_ERROR_SIZE 29
#define NIG_NIG_INT_STS_CLR_0_REG_LLFC0_POP_ERROR (0x1<<30)
#define NIG_NIG_INT_STS_CLR_0_REG_LLFC0_POP_ERROR_SIZE 30
#define NIG_NIG_INT_STS_CLR_0_REG_LLFC1_POP_ERROR (0x1<<31)
#define NIG_NIG_INT_STS_CLR_0_REG_LLFC1_POP_ERROR_SIZE 31
#define NIG_REG_NIG_INT_STS_WR_0 0x103b8UL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EOP_PORT0_ERROR (0x1<<1)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EOP_PORT0_ERROR_SIZE 1
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EOP_PORT1_ERROR (0x1<<2)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EOP_PORT1_ERROR_SIZE 2
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EOP_LB_ERROR (0x1<<3)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EOP_LB_ERROR_SIZE 3
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR (0x1<<4)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR_SIZE 4
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR (0x1<<5)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR_SIZE 5
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC0_ERROR (0x1<<6)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC0_ERROR_SIZE 6
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC1_ERROR (0x1<<7)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC1_ERROR_SIZE 7
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC0_REGS_ERROR (0x1<<8)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC0_REGS_ERROR_SIZE 8
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC1_REGS_ERROR (0x1<<9)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC1_REGS_ERROR_SIZE 9
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC0_POP_ERROR (0x1<<10)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC0_POP_ERROR_SIZE 10
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC1_POP_ERROR (0x1<<11)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC1_POP_ERROR_SIZE 11
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC0_PUSH_ERROR (0x1<<12)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC0_PUSH_ERROR_SIZE 12
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC1_PUSH_ERROR (0x1<<13)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC1_PUSH_ERROR_SIZE 13
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_LB_PBF_DELAY_ERROR (0x1<<14)
#define NIG_NIG_INT_STS_WR_0_REG_INGRESS_LB_PBF_DELAY_ERROR_SIZE 14
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_MNG0_FIFO_ERROR (0x1<<15)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_MNG0_FIFO_ERROR_SIZE 15
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_MNG1_FIFO_ERROR (0x1<<16)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_MNG1_FIFO_ERROR_SIZE 16
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_DEBUG_FIFO_ERROR (0x1<<17)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_DEBUG_FIFO_ERROR_SIZE 17
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_DELAY0_ERROR (0x1<<18)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_DELAY0_ERROR_SIZE 18
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_DELAY1_ERROR (0x1<<19)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_DELAY1_ERROR_SIZE 19
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC0_PUSH_ERROR (0x1<<20)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC0_PUSH_ERROR_SIZE 20
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC1_PUSH_ERROR (0x1<<21)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC1_PUSH_ERROR_SIZE 21
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC0_POP_ERROR (0x1<<22)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC0_POP_ERROR_SIZE 22
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC1_POP_ERROR (0x1<<23)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC1_POP_ERROR_SIZE 23
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_BMAC0_ERROR (0x1<<24)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_BMAC0_ERROR_SIZE 24
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_BMAC1_ERROR (0x1<<25)
#define NIG_NIG_INT_STS_WR_0_REG_EGRESS_BMAC1_ERROR_SIZE 25
#define NIG_NIG_INT_STS_WR_0_REG_TIMER0_MAX_INT (0x1<<26)
#define NIG_NIG_INT_STS_WR_0_REG_TIMER0_MAX_INT_SIZE 26
#define NIG_NIG_INT_STS_WR_0_REG_TIMER1_MAX_INT (0x1<<27)
#define NIG_NIG_INT_STS_WR_0_REG_TIMER1_MAX_INT_SIZE 27
#define NIG_NIG_INT_STS_WR_0_REG_LLH0_FIFO_ERROR (0x1<<28)
#define NIG_NIG_INT_STS_WR_0_REG_LLH0_FIFO_ERROR_SIZE 28
#define NIG_NIG_INT_STS_WR_0_REG_LLH1_FIFO_ERROR (0x1<<29)
#define NIG_NIG_INT_STS_WR_0_REG_LLH1_FIFO_ERROR_SIZE 29
#define NIG_NIG_INT_STS_WR_0_REG_LLFC0_POP_ERROR (0x1<<30)
#define NIG_NIG_INT_STS_WR_0_REG_LLFC0_POP_ERROR_SIZE 30
#define NIG_NIG_INT_STS_WR_0_REG_LLFC1_POP_ERROR (0x1<<31)
#define NIG_NIG_INT_STS_WR_0_REG_LLFC1_POP_ERROR_SIZE 31
#define NIG_REG_NIG_INT_MASK_0 0x103bcUL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EOP_PORT0_ERROR (0x1<<1)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EOP_PORT0_ERROR_SIZE 1
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EOP_PORT1_ERROR (0x1<<2)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EOP_PORT1_ERROR_SIZE 2
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EOP_LB_ERROR (0x1<<3)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EOP_LB_ERROR_SIZE 3
#define NIG_NIG_INT_MASK_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR (0x1<<4)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR_SIZE 4
#define NIG_NIG_INT_MASK_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR (0x1<<5)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR_SIZE 5
#define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC0_ERROR (0x1<<6)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC0_ERROR_SIZE 6
#define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC1_ERROR (0x1<<7)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC1_ERROR_SIZE 7
#define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC0_REGS_ERROR (0x1<<8)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC0_REGS_ERROR_SIZE 8
#define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC1_REGS_ERROR (0x1<<9)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC1_REGS_ERROR_SIZE 9
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC0_POP_ERROR (0x1<<10)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC0_POP_ERROR_SIZE 10
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC1_POP_ERROR (0x1<<11)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC1_POP_ERROR_SIZE 11
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC0_PUSH_ERROR (0x1<<12)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC0_PUSH_ERROR_SIZE 12
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC1_PUSH_ERROR (0x1<<13)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC1_PUSH_ERROR_SIZE 13
#define NIG_NIG_INT_MASK_0_REG_INGRESS_LB_PBF_DELAY_ERROR (0x1<<14)
#define NIG_NIG_INT_MASK_0_REG_INGRESS_LB_PBF_DELAY_ERROR_SIZE 14
#define NIG_NIG_INT_MASK_0_REG_EGRESS_MNG0_FIFO_ERROR (0x1<<15)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_MNG0_FIFO_ERROR_SIZE 15
#define NIG_NIG_INT_MASK_0_REG_EGRESS_MNG1_FIFO_ERROR (0x1<<16)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_MNG1_FIFO_ERROR_SIZE 16
#define NIG_NIG_INT_MASK_0_REG_EGRESS_DEBUG_FIFO_ERROR (0x1<<17)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_DEBUG_FIFO_ERROR_SIZE 17
#define NIG_NIG_INT_MASK_0_REG_EGRESS_DELAY0_ERROR (0x1<<18)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_DELAY0_ERROR_SIZE 18
#define NIG_NIG_INT_MASK_0_REG_EGRESS_DELAY1_ERROR (0x1<<19)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_DELAY1_ERROR_SIZE 19
#define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC0_PUSH_ERROR (0x1<<20)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC0_PUSH_ERROR_SIZE 20
#define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC1_PUSH_ERROR (0x1<<21)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC1_PUSH_ERROR_SIZE 21
#define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC0_POP_ERROR (0x1<<22)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC0_POP_ERROR_SIZE 22
#define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC1_POP_ERROR (0x1<<23)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC1_POP_ERROR_SIZE 23
#define NIG_NIG_INT_MASK_0_REG_EGRESS_BMAC0_ERROR (0x1<<24)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_BMAC0_ERROR_SIZE 24
#define NIG_NIG_INT_MASK_0_REG_EGRESS_BMAC1_ERROR (0x1<<25)
#define NIG_NIG_INT_MASK_0_REG_EGRESS_BMAC1_ERROR_SIZE 25
#define NIG_NIG_INT_MASK_0_REG_TIMER0_MAX_INT (0x1<<26)
#define NIG_NIG_INT_MASK_0_REG_TIMER0_MAX_INT_SIZE 26
#define NIG_NIG_INT_MASK_0_REG_TIMER1_MAX_INT (0x1<<27)
#define NIG_NIG_INT_MASK_0_REG_TIMER1_MAX_INT_SIZE 27
#define NIG_NIG_INT_MASK_0_REG_LLH0_FIFO_ERROR (0x1<<28)
#define NIG_NIG_INT_MASK_0_REG_LLH0_FIFO_ERROR_SIZE 28
#define NIG_NIG_INT_MASK_0_REG_LLH1_FIFO_ERROR (0x1<<29)
#define NIG_NIG_INT_MASK_0_REG_LLH1_FIFO_ERROR_SIZE 29
#define NIG_NIG_INT_MASK_0_REG_LLFC0_POP_ERROR (0x1<<30)
#define NIG_NIG_INT_MASK_0_REG_LLFC0_POP_ERROR_SIZE 30
#define NIG_NIG_INT_MASK_0_REG_LLFC1_POP_ERROR (0x1<<31)
#define NIG_NIG_INT_MASK_0_REG_LLFC1_POP_ERROR_SIZE 31
#define NIG_REG_NIG_INT_STS_1 0x103c0UL //ACCESS:R DataWidth:0x1b Description: Interrupt register #1 read
#define NIG_NIG_INT_STS_1_REG_LLFC0_PUSH_ERROR (0x1<<0)
#define NIG_NIG_INT_STS_1_REG_LLFC0_PUSH_ERROR_SIZE 0
#define NIG_NIG_INT_STS_1_REG_LLFC1_PUSH_ERROR (0x1<<1)
#define NIG_NIG_INT_STS_1_REG_LLFC1_PUSH_ERROR_SIZE 1
#define NIG_NIG_INT_STS_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN (0x1<<2)
#define NIG_NIG_INT_STS_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN_SIZE 2
#define NIG_NIG_INT_STS_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN (0x1<<3)
#define NIG_NIG_INT_STS_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN_SIZE 3
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS0_TIMER_MAX_INT (0x1<<4)
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS0_TIMER_MAX_INT_SIZE 4
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS1_TIMER_MAX_INT (0x1<<5)
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS1_TIMER_MAX_INT_SIZE 5
#define NIG_NIG_INT_STS_1_REG_P1_RX_COS0_TIMER_MAX_INT (0x1<<6)
#define NIG_NIG_INT_STS_1_REG_P1_RX_COS0_TIMER_MAX_INT_SIZE 6
#define NIG_NIG_INT_STS_1_REG_P1_RX_COS1_TIMER_MAX_INT (0x1<<7)
#define NIG_NIG_INT_STS_1_REG_P1_RX_COS1_TIMER_MAX_INT_SIZE 7
#define NIG_NIG_INT_STS_1_REG_P0_TX_MNG_HOST_FIFO_ERROR (0x1<<8)
#define NIG_NIG_INT_STS_1_REG_P0_TX_MNG_HOST_FIFO_ERROR_SIZE 8
#define NIG_NIG_INT_STS_1_REG_P1_TX_MNG_HOST_FIFO_ERROR (0x1<<9)
#define NIG_NIG_INT_STS_1_REG_P1_TX_MNG_HOST_FIFO_ERROR_SIZE 9
#define NIG_NIG_INT_STS_1_REG_P0_HBUF_DSCR_FIFO_ERROR (0x1<<10)
#define NIG_NIG_INT_STS_1_REG_P0_HBUF_DSCR_FIFO_ERROR_SIZE 10
#define NIG_NIG_INT_STS_1_REG_P1_HBUF_DSCR_FIFO_ERROR (0x1<<11)
#define NIG_NIG_INT_STS_1_REG_P1_HBUF_DSCR_FIFO_ERROR_SIZE 11
#define NIG_NIG_INT_STS_1_REG_P0_TLLH_FIFO_ERROR (0x1<<12)
#define NIG_NIG_INT_STS_1_REG_P0_TLLH_FIFO_ERROR_SIZE 12
#define NIG_NIG_INT_STS_1_REG_P1_TLLH_FIFO_ERROR (0x1<<13)
#define NIG_NIG_INT_STS_1_REG_P1_TLLH_FIFO_ERROR_SIZE 13
#define NIG_NIG_INT_STS_1_REG_P0_RX_MACFIFO_ERROR (0x1<<14)
#define NIG_NIG_INT_STS_1_REG_P0_RX_MACFIFO_ERROR_SIZE 14
#define NIG_NIG_INT_STS_1_REG_P1_RX_MACFIFO_ERROR (0x1<<15)
#define NIG_NIG_INT_STS_1_REG_P1_RX_MACFIFO_ERROR_SIZE 15
#define NIG_NIG_INT_STS_1_REG_P0_TX_MACFIFO_ERROR (0x1<<16)
#define NIG_NIG_INT_STS_1_REG_P0_TX_MACFIFO_ERROR_SIZE 16
#define NIG_NIG_INT_STS_1_REG_P1_TX_MACFIFO_ERROR (0x1<<17)
#define NIG_NIG_INT_STS_1_REG_P1_TX_MACFIFO_ERROR_SIZE 17
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS2_TIMER_MAX_INT (0x1<<18)
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS2_TIMER_MAX_INT_SIZE 18
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS3_TIMER_MAX_INT (0x1<<19)
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS3_TIMER_MAX_INT_SIZE 19
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS4_TIMER_MAX_INT (0x1<<20)
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS4_TIMER_MAX_INT_SIZE 20
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS5_TIMER_MAX_INT (0x1<<21)
#define NIG_NIG_INT_STS_1_REG_P0_RX_COS5_TIMER_MAX_INT_SIZE 21
#define NIG_NIG_INT_STS_1_REG_P1_RX_COS2_TIMER_MAX_INT (0x1<<22)
#define NIG_NIG_INT_STS_1_REG_P1_RX_COS2_TIMER_MAX_INT_SIZE 22
#define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY2_ERROR (0x1<<23)
#define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY2_ERROR_SIZE 23
#define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY3_ERROR (0x1<<24)
#define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY3_ERROR_SIZE 24
#define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY4_ERROR (0x1<<25)
#define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY4_ERROR_SIZE 25
#define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY5_ERROR (0x1<<26)
#define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY5_ERROR_SIZE 26
#define NIG_REG_NIG_INT_STS_CLR_1 0x103c4UL //ACCESS:RC DataWidth:0x1b Description: Interrupt register #1 read clear
#define NIG_NIG_INT_STS_CLR_1_REG_LLFC0_PUSH_ERROR (0x1<<0)
#define NIG_NIG_INT_STS_CLR_1_REG_LLFC0_PUSH_ERROR_SIZE 0
#define NIG_NIG_INT_STS_CLR_1_REG_LLFC1_PUSH_ERROR (0x1<<1)
#define NIG_NIG_INT_STS_CLR_1_REG_LLFC1_PUSH_ERROR_SIZE 1
#define NIG_NIG_INT_STS_CLR_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN (0x1<<2)
#define NIG_NIG_INT_STS_CLR_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN_SIZE 2
#define NIG_NIG_INT_STS_CLR_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN (0x1<<3)
#define NIG_NIG_INT_STS_CLR_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN_SIZE 3
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS0_TIMER_MAX_INT (0x1<<4)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS0_TIMER_MAX_INT_SIZE 4
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS1_TIMER_MAX_INT (0x1<<5)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS1_TIMER_MAX_INT_SIZE 5
#define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_COS0_TIMER_MAX_INT (0x1<<6)
#define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_COS0_TIMER_MAX_INT_SIZE 6
#define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_COS1_TIMER_MAX_INT (0x1<<7)
#define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_COS1_TIMER_MAX_INT_SIZE 7
#define NIG_NIG_INT_STS_CLR_1_REG_P0_TX_MNG_HOST_FIFO_ERROR (0x1<<8)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_TX_MNG_HOST_FIFO_ERROR_SIZE 8
#define NIG_NIG_INT_STS_CLR_1_REG_P1_TX_MNG_HOST_FIFO_ERROR (0x1<<9)
#define NIG_NIG_INT_STS_CLR_1_REG_P1_TX_MNG_HOST_FIFO_ERROR_SIZE 9
#define NIG_NIG_INT_STS_CLR_1_REG_P0_HBUF_DSCR_FIFO_ERROR (0x1<<10)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_HBUF_DSCR_FIFO_ERROR_SIZE 10
#define NIG_NIG_INT_STS_CLR_1_REG_P1_HBUF_DSCR_FIFO_ERROR (0x1<<11)
#define NIG_NIG_INT_STS_CLR_1_REG_P1_HBUF_DSCR_FIFO_ERROR_SIZE 11
#define NIG_NIG_INT_STS_CLR_1_REG_P0_TLLH_FIFO_ERROR (0x1<<12)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_TLLH_FIFO_ERROR_SIZE 12
#define NIG_NIG_INT_STS_CLR_1_REG_P1_TLLH_FIFO_ERROR (0x1<<13)
#define NIG_NIG_INT_STS_CLR_1_REG_P1_TLLH_FIFO_ERROR_SIZE 13
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_MACFIFO_ERROR (0x1<<14)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_MACFIFO_ERROR_SIZE 14
#define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_MACFIFO_ERROR (0x1<<15)
#define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_MACFIFO_ERROR_SIZE 15
#define NIG_NIG_INT_STS_CLR_1_REG_P0_TX_MACFIFO_ERROR (0x1<<16)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_TX_MACFIFO_ERROR_SIZE 16
#define NIG_NIG_INT_STS_CLR_1_REG_P1_TX_MACFIFO_ERROR (0x1<<17)
#define NIG_NIG_INT_STS_CLR_1_REG_P1_TX_MACFIFO_ERROR_SIZE 17
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS2_TIMER_MAX_INT (0x1<<18)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS2_TIMER_MAX_INT_SIZE 18
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS3_TIMER_MAX_INT (0x1<<19)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS3_TIMER_MAX_INT_SIZE 19
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS4_TIMER_MAX_INT (0x1<<20)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS4_TIMER_MAX_INT_SIZE 20
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS5_TIMER_MAX_INT (0x1<<21)
#define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS5_TIMER_MAX_INT_SIZE 21
#define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_COS2_TIMER_MAX_INT (0x1<<22)
#define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_COS2_TIMER_MAX_INT_SIZE 22
#define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY2_ERROR (0x1<<23)
#define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY2_ERROR_SIZE 23
#define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY3_ERROR (0x1<<24)
#define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY3_ERROR_SIZE 24
#define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY4_ERROR (0x1<<25)
#define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY4_ERROR_SIZE 25
#define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY5_ERROR (0x1<<26)
#define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY5_ERROR_SIZE 26
#define NIG_REG_NIG_INT_STS_WR_1 0x103c8UL //ACCESS:WR DataWidth:0x1b Description: Interrupt register #1 bit set or clear
#define NIG_NIG_INT_STS_WR_1_REG_LLFC0_PUSH_ERROR (0x1<<0)
#define NIG_NIG_INT_STS_WR_1_REG_LLFC0_PUSH_ERROR_SIZE 0
#define NIG_NIG_INT_STS_WR_1_REG_LLFC1_PUSH_ERROR (0x1<<1)
#define NIG_NIG_INT_STS_WR_1_REG_LLFC1_PUSH_ERROR_SIZE 1
#define NIG_NIG_INT_STS_WR_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN (0x1<<2)
#define NIG_NIG_INT_STS_WR_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN_SIZE 2
#define NIG_NIG_INT_STS_WR_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN (0x1<<3)
#define NIG_NIG_INT_STS_WR_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN_SIZE 3
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS0_TIMER_MAX_INT (0x1<<4)
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS0_TIMER_MAX_INT_SIZE 4
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS1_TIMER_MAX_INT (0x1<<5)
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS1_TIMER_MAX_INT_SIZE 5
#define NIG_NIG_INT_STS_WR_1_REG_P1_RX_COS0_TIMER_MAX_INT (0x1<<6)
#define NIG_NIG_INT_STS_WR_1_REG_P1_RX_COS0_TIMER_MAX_INT_SIZE 6
#define NIG_NIG_INT_STS_WR_1_REG_P1_RX_COS1_TIMER_MAX_INT (0x1<<7)
#define NIG_NIG_INT_STS_WR_1_REG_P1_RX_COS1_TIMER_MAX_INT_SIZE 7
#define NIG_NIG_INT_STS_WR_1_REG_P0_TX_MNG_HOST_FIFO_ERROR (0x1<<8)
#define NIG_NIG_INT_STS_WR_1_REG_P0_TX_MNG_HOST_FIFO_ERROR_SIZE 8
#define NIG_NIG_INT_STS_WR_1_REG_P1_TX_MNG_HOST_FIFO_ERROR (0x1<<9)
#define NIG_NIG_INT_STS_WR_1_REG_P1_TX_MNG_HOST_FIFO_ERROR_SIZE 9
#define NIG_NIG_INT_STS_WR_1_REG_P0_HBUF_DSCR_FIFO_ERROR (0x1<<10)
#define NIG_NIG_INT_STS_WR_1_REG_P0_HBUF_DSCR_FIFO_ERROR_SIZE 10
#define NIG_NIG_INT_STS_WR_1_REG_P1_HBUF_DSCR_FIFO_ERROR (0x1<<11)
#define NIG_NIG_INT_STS_WR_1_REG_P1_HBUF_DSCR_FIFO_ERROR_SIZE 11
#define NIG_NIG_INT_STS_WR_1_REG_P0_TLLH_FIFO_ERROR (0x1<<12)
#define NIG_NIG_INT_STS_WR_1_REG_P0_TLLH_FIFO_ERROR_SIZE 12
#define NIG_NIG_INT_STS_WR_1_REG_P1_TLLH_FIFO_ERROR (0x1<<13)
#define NIG_NIG_INT_STS_WR_1_REG_P1_TLLH_FIFO_ERROR_SIZE 13
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_MACFIFO_ERROR (0x1<<14)
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_MACFIFO_ERROR_SIZE 14
#define NIG_NIG_INT_STS_WR_1_REG_P1_RX_MACFIFO_ERROR (0x1<<15)
#define NIG_NIG_INT_STS_WR_1_REG_P1_RX_MACFIFO_ERROR_SIZE 15
#define NIG_NIG_INT_STS_WR_1_REG_P0_TX_MACFIFO_ERROR (0x1<<16)
#define NIG_NIG_INT_STS_WR_1_REG_P0_TX_MACFIFO_ERROR_SIZE 16
#define NIG_NIG_INT_STS_WR_1_REG_P1_TX_MACFIFO_ERROR (0x1<<17)
#define NIG_NIG_INT_STS_WR_1_REG_P1_TX_MACFIFO_ERROR_SIZE 17
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS2_TIMER_MAX_INT (0x1<<18)
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS2_TIMER_MAX_INT_SIZE 18
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS3_TIMER_MAX_INT (0x1<<19)
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS3_TIMER_MAX_INT_SIZE 19
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS4_TIMER_MAX_INT (0x1<<20)
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS4_TIMER_MAX_INT_SIZE 20
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS5_TIMER_MAX_INT (0x1<<21)
#define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS5_TIMER_MAX_INT_SIZE 21
#define NIG_NIG_INT_STS_WR_1_REG_P1_RX_COS2_TIMER_MAX_INT (0x1<<22)
#define NIG_NIG_INT_STS_WR_1_REG_P1_RX_COS2_TIMER_MAX_INT_SIZE 22
#define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY2_ERROR (0x1<<23)
#define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY2_ERROR_SIZE 23
#define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY3_ERROR (0x1<<24)
#define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY3_ERROR_SIZE 24
#define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY4_ERROR (0x1<<25)
#define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY4_ERROR_SIZE 25
#define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY5_ERROR (0x1<<26)
#define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY5_ERROR_SIZE 26
#define NIG_REG_NIG_INT_MASK_1 0x103ccUL //ACCESS:RW DataWidth:0x1b Description: Interrupt mask register #1 read/write
#define NIG_NIG_INT_MASK_1_REG_LLFC0_PUSH_ERROR (0x1<<0)
#define NIG_NIG_INT_MASK_1_REG_LLFC0_PUSH_ERROR_SIZE 0
#define NIG_NIG_INT_MASK_1_REG_LLFC1_PUSH_ERROR (0x1<<1)
#define NIG_NIG_INT_MASK_1_REG_LLFC1_PUSH_ERROR_SIZE 1
#define NIG_NIG_INT_MASK_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN (0x1<<2)
#define NIG_NIG_INT_MASK_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN_SIZE 2
#define NIG_NIG_INT_MASK_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN (0x1<<3)
#define NIG_NIG_INT_MASK_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN_SIZE 3
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS0_TIMER_MAX_INT (0x1<<4)
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS0_TIMER_MAX_INT_SIZE 4
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS1_TIMER_MAX_INT (0x1<<5)
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS1_TIMER_MAX_INT_SIZE 5
#define NIG_NIG_INT_MASK_1_REG_P1_RX_COS0_TIMER_MAX_INT (0x1<<6)
#define NIG_NIG_INT_MASK_1_REG_P1_RX_COS0_TIMER_MAX_INT_SIZE 6
#define NIG_NIG_INT_MASK_1_REG_P1_RX_COS1_TIMER_MAX_INT (0x1<<7)
#define NIG_NIG_INT_MASK_1_REG_P1_RX_COS1_TIMER_MAX_INT_SIZE 7
#define NIG_NIG_INT_MASK_1_REG_P0_TX_MNG_HOST_FIFO_ERROR (0x1<<8)
#define NIG_NIG_INT_MASK_1_REG_P0_TX_MNG_HOST_FIFO_ERROR_SIZE 8
#define NIG_NIG_INT_MASK_1_REG_P1_TX_MNG_HOST_FIFO_ERROR (0x1<<9)
#define NIG_NIG_INT_MASK_1_REG_P1_TX_MNG_HOST_FIFO_ERROR_SIZE 9
#define NIG_NIG_INT_MASK_1_REG_P0_HBUF_DSCR_FIFO_ERROR (0x1<<10)
#define NIG_NIG_INT_MASK_1_REG_P0_HBUF_DSCR_FIFO_ERROR_SIZE 10
#define NIG_NIG_INT_MASK_1_REG_P1_HBUF_DSCR_FIFO_ERROR (0x1<<11)
#define NIG_NIG_INT_MASK_1_REG_P1_HBUF_DSCR_FIFO_ERROR_SIZE 11
#define NIG_NIG_INT_MASK_1_REG_P0_TLLH_FIFO_ERROR (0x1<<12)
#define NIG_NIG_INT_MASK_1_REG_P0_TLLH_FIFO_ERROR_SIZE 12
#define NIG_NIG_INT_MASK_1_REG_P1_TLLH_FIFO_ERROR (0x1<<13)
#define NIG_NIG_INT_MASK_1_REG_P1_TLLH_FIFO_ERROR_SIZE 13
#define NIG_NIG_INT_MASK_1_REG_P0_RX_MACFIFO_ERROR (0x1<<14)
#define NIG_NIG_INT_MASK_1_REG_P0_RX_MACFIFO_ERROR_SIZE 14
#define NIG_NIG_INT_MASK_1_REG_P1_RX_MACFIFO_ERROR (0x1<<15)
#define NIG_NIG_INT_MASK_1_REG_P1_RX_MACFIFO_ERROR_SIZE 15
#define NIG_NIG_INT_MASK_1_REG_P0_TX_MACFIFO_ERROR (0x1<<16)
#define NIG_NIG_INT_MASK_1_REG_P0_TX_MACFIFO_ERROR_SIZE 16
#define NIG_NIG_INT_MASK_1_REG_P1_TX_MACFIFO_ERROR (0x1<<17)
#define NIG_NIG_INT_MASK_1_REG_P1_TX_MACFIFO_ERROR_SIZE 17
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS2_TIMER_MAX_INT (0x1<<18)
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS2_TIMER_MAX_INT_SIZE 18
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS3_TIMER_MAX_INT (0x1<<19)
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS3_TIMER_MAX_INT_SIZE 19
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS4_TIMER_MAX_INT (0x1<<20)
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS4_TIMER_MAX_INT_SIZE 20
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS5_TIMER_MAX_INT (0x1<<21)
#define NIG_NIG_INT_MASK_1_REG_P0_RX_COS5_TIMER_MAX_INT_SIZE 21
#define NIG_NIG_INT_MASK_1_REG_P1_RX_COS2_TIMER_MAX_INT (0x1<<22)
#define NIG_NIG_INT_MASK_1_REG_P1_RX_COS2_TIMER_MAX_INT_SIZE 22
#define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY2_ERROR (0x1<<23)
#define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY2_ERROR_SIZE 23
#define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY3_ERROR (0x1<<24)
#define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY3_ERROR_SIZE 24
#define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY4_ERROR (0x1<<25)
#define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY4_ERROR_SIZE 25
#define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY5_ERROR (0x1<<26)
#define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY5_ERROR_SIZE 26
#define NIG_REG_LLH0_DEST_MAC_3_0 0x16004UL //ACCESS:RW DataWidth:0x20 Register llh0_dest_mac_3: 1 out of 2 Description: Destination MAC address 3. LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_DEST_MAC_3_1 0x16008UL //ACCESS:RW DataWidth:0x10 Register llh0_dest_mac_3: 2 out of 2 Description: Destination MAC address 3. LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_MAC_3_0 0x1600cUL //ACCESS:RW DataWidth:0x20 Register llh1_dest_mac_3: 1 out of 2 Description: Destination MAC address 3. LLH will look for this address in all incoming packets.
#define NIG_REG_LLH1_DEST_MAC_3_1 0x16010UL //ACCESS:RW DataWidth:0x10 Register llh1_dest_mac_3: 2 out of 2 Description: Destination MAC address 3. LLH will look for this address in all incoming packets.
#define NIG_REG_LLH0_OUTER_VLAN_ID 0x16014UL //ACCESS:RW DataWidth:0xc Description: VLAN ID of the outer VLAN on port 0.
#define NIG_REG_LLH1_OUTER_VLAN_ID 0x16018UL //ACCESS:RW DataWidth:0xc Description: VLAN ID of the outer VLAN on port 1.
#define NIG_REG_LLH0_MCP_MASK_MF 0x1601cUL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_OUTER_VLAN (0x1<<0)
#define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_OUTER_VLAN_SIZE 0
#define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_NO_OUTER_VLAN (0x1<<1)
#define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_NO_OUTER_VLAN_SIZE 1
#define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_OUTER_VLAN_ID (0x1<<2)
#define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_OUTER_VLAN_ID_SIZE 2
#define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_MAC3 (0x1<<3)
#define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_MAC3_SIZE 3
#define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_IPV6_MLCST (0x1<<4)
#define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_IPV6_MLCST_SIZE 4
#define NIG_LLH0_MCP_MASK_MF_REG_P0_LLH_MCP_MASK_PF_OUTER_VLAN (0x1<<5)
#define NIG_LLH0_MCP_MASK_MF_REG_P0_LLH_MCP_MASK_PF_OUTER_VLAN_SIZE 5
#define NIG_REG_LLH1_MCP_MASK_MF 0x16020UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_OUTER_VLAN (0x1<<0)
#define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_OUTER_VLAN_SIZE 0
#define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_NO_OUTER_VLAN (0x1<<1)
#define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_NO_OUTER_VLAN_SIZE 1
#define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_OUTER_VLAN_ID (0x1<<2)
#define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_OUTER_VLAN_ID_SIZE 2
#define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_MAC3 (0x1<<3)
#define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_MAC3_SIZE 3
#define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_IPV6_MLCST (0x1<<4)
#define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_IPV6_MLCST_SIZE 4
#define NIG_LLH1_MCP_MASK_MF_REG_P1_LLH_MCP_MASK_PF_OUTER_VLAN (0x1<<5)
#define NIG_LLH1_MCP_MASK_MF_REG_P1_LLH_MCP_MASK_PF_OUTER_VLAN_SIZE 5
#define NIG_REG_LLH_MF_MODE 0x16024UL //ACCESS:RW DataWidth:0x1 Description: When this bit is set; the LLH will classify the packet before sending it to the BRB or calculating WoL on it. This bit is applicable to both ports 0 and 1 for E2. This bit only controls port 0 in E3.
#define NIG_REG_LLH_E1HOV_TYPE_1 0x16028UL //ACCESS:RW DataWidth:0x10 Description: Outer VLAN type identifier for multi-function mode. In non multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
#define NIG_REG_LLH_E1HOV_TYPE_2 0x1602cUL //ACCESS:RW DataWidth:0x10 Description: Outer VLAN type identifier for multi-function mode. In non multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
#define NIG_REG_LLH_E1HOV_TYPE_3 0x16030UL //ACCESS:RW DataWidth:0x10 Description: Outer VLAN type identifier for multi-function mode. In non multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
#define NIG_REG_LLH_E1HOV_TYPE_4 0x16034UL //ACCESS:RW DataWidth:0x10 Description: Outer VLAN type identifier for multi-function mode. In non multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
#define NIG_REG_LLH_E1HOV_TYPE_5 0x16038UL //ACCESS:RW DataWidth:0x10 Description: Outer VLAN type identifier for multi-function mode. In non multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
#define NIG_REG_LLH_E1HOV_TYPE_6 0x1603cUL //ACCESS:RW DataWidth:0x10 Description: Outer VLAN type identifier for multi-function mode. In non multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
#define NIG_REG_LLH_E1HOV_TYPE_7 0x16040UL //ACCESS:RW DataWidth:0x10 Description: Outer VLAN type identifier for multi-function mode. In non multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
#define NIG_REG_LLH_E1HOV_TYPE_8 0x16044UL //ACCESS:RW DataWidth:0x10 Description: Outer VLAN type identifier for multi-function mode. In non multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define NIG_LLH0_BRB1_DRV_MASK_MF_REG_LLH0_BRB1_DRV_MASK_OUTER_VLAN (0x1<<0)
#define NIG_LLH0_BRB1_DRV_MASK_MF_REG_LLH0_BRB1_DRV_MASK_OUTER_VLAN_SIZE 0
#define NIG_LLH0_BRB1_DRV_MASK_MF_REG_LLH0_BRB1_DRV_MASK_NO_OUTER_VLAN (0x1<<1)
#define NIG_LLH0_BRB1_DRV_MASK_MF_REG_LLH0_BRB1_DRV_MASK_NO_OUTER_VLAN_SIZE 1
#define NIG_LLH0_BRB1_DRV_MASK_MF_REG_P0_LLH_BRB1_DRV_MASK_PF_OUTER_VLAN (0x1<<2)
#define NIG_LLH0_BRB1_DRV_MASK_MF_REG_P0_LLH_BRB1_DRV_MASK_PF_OUTER_VLAN_SIZE 2
#define NIG_REG_LLH1_BRB1_DRV_MASK_MF 0x1604cUL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define NIG_LLH1_BRB1_DRV_MASK_MF_REG_LLH1_BRB1_DRV_MASK_OUTER_VLAN (0x1<<0)
#define NIG_LLH1_BRB1_DRV_MASK_MF_REG_LLH1_BRB1_DRV_MASK_OUTER_VLAN_SIZE 0
#define NIG_LLH1_BRB1_DRV_MASK_MF_REG_LLH1_BRB1_DRV_MASK_NO_OUTER_VLAN (0x1<<1)
#define NIG_LLH1_BRB1_DRV_MASK_MF_REG_LLH1_BRB1_DRV_MASK_NO_OUTER_VLAN_SIZE 1
#define NIG_LLH1_BRB1_DRV_MASK_MF_REG_P1_LLH_BRB1_DRV_MASK_PF_OUTER_VLAN (0x1<<2)
#define NIG_LLH1_BRB1_DRV_MASK_MF_REG_P1_LLH_BRB1_DRV_MASK_PF_OUTER_VLAN_SIZE 2
#define NIG_REG_LLH0_BRB1_MCP_MASK_MF 0x16050UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define NIG_LLH0_BRB1_MCP_MASK_MF_REG_LLH0_BRB1_MCP_MASK_MAC3 (0x1<<0)
#define NIG_LLH0_BRB1_MCP_MASK_MF_REG_LLH0_BRB1_MCP_MASK_MAC3_SIZE 0
#define NIG_LLH0_BRB1_MCP_MASK_MF_REG_LLH0_BRB1_MCP_MASK_OUTER_VLAN_ID (0x1<<1)
#define NIG_LLH0_BRB1_MCP_MASK_MF_REG_LLH0_BRB1_MCP_MASK_OUTER_VLAN_ID_SIZE 1
#define NIG_LLH0_BRB1_MCP_MASK_MF_REG_LLH0_BRB1_MCP_MASK_IPV6_MLCST (0x1<<2)
#define NIG_LLH0_BRB1_MCP_MASK_MF_REG_LLH0_BRB1_MCP_MASK_IPV6_MLCST_SIZE 2
#define NIG_REG_LLH1_BRB1_MCP_MASK_MF 0x16054UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define NIG_LLH1_BRB1_MCP_MASK_MF_REG_LLH1_BRB1_MCP_MASK_MAC3 (0x1<<0)
#define NIG_LLH1_BRB1_MCP_MASK_MF_REG_LLH1_BRB1_MCP_MASK_MAC3_SIZE 0
#define NIG_LLH1_BRB1_MCP_MASK_MF_REG_LLH1_BRB1_MCP_MASK_OUTER_VLAN_ID (0x1<<1)
#define NIG_LLH1_BRB1_MCP_MASK_MF_REG_LLH1_BRB1_MCP_MASK_OUTER_VLAN_ID_SIZE 1
#define NIG_LLH1_BRB1_MCP_MASK_MF_REG_LLH1_BRB1_MCP_MASK_IPV6_MLCST (0x1<<2)
#define NIG_LLH1_BRB1_MCP_MASK_MF_REG_LLH1_BRB1_MCP_MASK_IPV6_MLCST_SIZE 2
#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058UL //ACCESS:RW DataWidth:0x10 Description: classes are high-priority for port0
#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605cUL //ACCESS:RW DataWidth:0x10 Description: classes are high-priority for port1
#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060UL //ACCESS:RW DataWidth:0x10 Description: classes are low-priority for port0
#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064UL //ACCESS:RW DataWidth:0x10 Description: classes are low-priority for port1
#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070UL //ACCESS:RW DataWidth:0x3 Description: for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- tsdm enable; b2- usdm enable
#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074UL //ACCESS:RW DataWidth:0x3 Description: for port1 enable for llfc ppp and pause. b0 - brb1 enable; b1- tsdm enable; b2- usdm enable
#define NIG_REG_LLFC_EGRESS_CYCLE_NUM_0 0x16078UL //ACCESS:RW DataWidth:0x9 Description: number of cycles between 2 LLFC request to BMAC; The minimum value of this register must be 16. The value of this register must be bigger then ~BIGMAC_REGISTERS_TX_LLFC_CTRLl.llfc_img register *BMAC_clk/sys_clk for port0
#define NIG_REG_LLFC_EGRESS_CYCLE_NUM_1 0x1607cUL //ACCESS:RW DataWidth:0x9 Description: number of cycles between 2 LLFC request to BMAC; The minimum value of this register must be 16. The value of this register must be bigger then ~BIGMAC_REGISTERS_TX_LLFC_CTRLl.llfc_img register *BMAC_clk/sys_clk for port1
#define NIG_REG_LLH0_CLS_TYPE 0x16080UL //ACCESS:RW DataWidth:0x2 Description: Determine the classification participants. 0: no classification.1: classification upon VLAN id. 2: classification upon MAC address. 3: classification upon both VLAN id & MAC addr.
#define NIG_REG_LLH1_CLS_TYPE 0x16084UL //ACCESS:RW DataWidth:0x2 Description: Determine the classification participants. 0: no classification.1: classification upon VLAN id. 2: classification upon MAC address. 3: classification upon both VLAN id & MAC addr.
#define NIG_REG_LLH0_MNG_OUTER_VLAN_STRIP 0x16088UL //ACCESS:RW DataWidth:0x1 Description: Remove outer VLAN before sending the packet to the RMP. This configuration is ORed with llh_mng_tag_rm - the new E2 tag removal configuration.
#define NIG_REG_LLH1_MNG_OUTER_VLAN_STRIP 0x1608cUL //ACCESS:RW DataWidth:0x1 Description: remove outer VLAN before sending the packet to the RMP.
#define NIG_REG_PPP_STORM_ID 0x160a0UL //ACCESS:RW DataWidth:0x4 Description: STORM ID for header in PP message to PXP internal write IF
#define NIG_REG_PPP_ADDRESS 0x160a4UL //ACCESS:RW DataWidth:0x10 Description: ADDRESS for header in PP message to PXP internal write IF
#define NIG_REG_PPP_TRIG 0x160a8UL //ACCESS:RW DataWidth:0x4 Description: Trigger for header in PP message to PXP internal write IF
#define NIG_REG_PPP_T124PARAM 0x160acUL //ACCESS:RW DataWidth:0x8 Description: T124param for header in PP message to PXP internal write IF
#define NIG_REG_PPP_ENABLE_0 0x160b0UL //ACCESS:RW DataWidth:0x1 Description: PPP enable for port0. This register may get 1 only when ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the same port
#define NIG_REG_PPP_ENABLE_1 0x160b4UL //ACCESS:RW DataWidth:0x1 Description: PPP enable for port1. This register may get 1 only when ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the same port
#define NIG_REG_PAUSE_ENABLE_0 0x160c0UL //ACCESS:RW DataWidth:0x1 Description: Pause enable for port0. This register may get 1 only when ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same port
#define NIG_REG_PAUSE_ENABLE_1 0x160c4UL //ACCESS:RW DataWidth:0x1 Description: Pause enable for port1. This register may get 1 only when ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same port
#define NIG_REG_LLFC_OUT_EN_0 0x160c8UL //ACCESS:RW DataWidth:0x1 Description: Output enable of message to LLFC BMAC IF for port0
#define NIG_REG_LLFC_OUT_EN_1 0x160ccUL //ACCESS:RW DataWidth:0x1 Description: Output enable of message to LLFC BMAC IF for port1
#define NIG_REG_LLH0_MAC_CF_TYPE 0x160d0UL //ACCESS:RW DataWidth:0x10 Description: MAC control frame EtherType. The LLH will look for this Ethertype as a MAC CF identifier. Default is IEEE 0x8808.
#define NIG_REG_LLH1_MAC_CF_TYPE 0x160d4UL //ACCESS:RW DataWidth:0x10 Description: MAC control frame EtherType. The LLH will look for this Ethertype as a MAC CF identifier. Default is IEEE 0x8808.
#define NIG_REG_LLH_E1HOV_MODE 0x160d8UL //ACCESS:RW DataWidth:0x1 Description: When this bit is set; the LLH will expect all packets to be with outer VLAN. This is not applicable to E2.
#define NIG_REG_PPP_OUT_EN 0x16204UL //ACCESS:RW DataWidth:0x1 Description: Output enable of message to PXP IF
#define NIG_REG_LLFC_ENABLE_0 0x16208UL //ACCESS:RW DataWidth:0x1 Description: SAFC enable for port0. This register may get 1 only when ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same port
#define NIG_REG_LLFC_ENABLE_1 0x1620cUL //ACCESS:RW DataWidth:0x1 Description: SAFC enable for port1. This register may get 1 only when ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same port
#define NIG_REG_LATCH_BC_0 0x16210UL //ACCESS:RW DataWidth:0x1b Description: 0 - must be active for Everest A0; 1- for Everest B0 when latch logic for interrupts must be used. Enable per bit of interrupt of ~latch_status.latch_status
#define NIG_REG_LATCH_BC_1 0x16214UL //ACCESS:RW DataWidth:0x1b Description: 0 - must be active for Everest A0; 1- for Everest B0 when latch logic for interrupts must be used. Enable per bit of interrupt of ~latch_status.latch_status
#define NIG_REG_LLH0_SYNC_LLFC_TM 0x18010UL //ACCESS:RW DataWidth:0x2 Description: TM for LLH_SYNC_FIFO for port0
#define NIG_REG_LLH1_SYNC_LLFC_TM 0x18014UL //ACCESS:RW DataWidth:0x2 Description: TM for LLH_SYNC_FIFO for port1
#define NIG_REG_ECO_RESERVED 0x18018UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO
#define NIG_REG_FIFOS_TM 0x1801cUL //ACCESS:RW DataWidth:0x4 Description: TM for fifos: LLH0 fifo [1:0]; LLH1 fifo[3:2]
#define NIG_REG_P0_TAG_ETHERTYPE_0 0x18020UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 0. This tag is used for VNTAG classification and filtering in E3 B0 - when enabled.
#define NIG_REG_P0_TAG_ETHERTYPE_1 0x18024UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 1
#define NIG_REG_P0_TAG_ETHERTYPE_2 0x18028UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 2
#define NIG_REG_P0_TAG_LEN_0 0x1802cUL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 0 - in bytes. The length is between 2B and 14B; in 2B granularity. This length does not include the Ethertype field.
#define NIG_REG_P0_TAG_LEN_1 0x18030UL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 1 - in bytes. The length is between 2B and 14B; in 2B granularity. This length does not include the Ethertype field.
#define NIG_REG_P0_TAG_LEN_2 0x18034UL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 2 - in bytes. The length is between 2B and 14B; in 2B granularity. This length does not include the Ethertype field.
#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.
#define NIG_REG_P0_HDRS_AFTER_OUTER_VLAN 0x1803cUL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the outer VLAN header.
#define NIG_REG_P0_HDRS_AFTER_INNER_VLAN 0x18040UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the inner VLAN header.
#define NIG_REG_P0_HDRS_AFTER_LLC 0x18044UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the LLC header.
#define NIG_REG_P0_HDRS_AFTER_TAG_0 0x18048UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 0
#define NIG_REG_P0_HDRS_AFTER_TAG_1 0x1804cUL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 1
#define NIG_REG_P0_HDRS_AFTER_TAG_2 0x18050UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 2
#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054UL //ACCESS:RW DataWidth:0x20 Description: Eight 4-bit configurations for specifying which COS (0-15 for future expansion) each priorty is to be mapped to. Bits 3:0 specify the COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit priority field is extracted from the outer-most VLAN in receive packet. Only COS 0 and COS 1 are supported in E2.
#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058UL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to COS 0. A priority is mapped to COS 0 when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS.
#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805cUL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to COS 1. A priority is mapped to COS 1 when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS.
#define NIG_REG_P0_RX_COS0_TIMER_WRAP 0x18060UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 0 timer to start over when it reaches the configured maximum time.
#define NIG_REG_P0_RX_COS1_TIMER_WRAP 0x18064UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 1 timer to start over when it reaches the configured maximum time.
#define NIG_REG_P0_RX_COS0_TIMER_MAX 0x18068UL //ACCESS:RW DataWidth:0x20 Description: This register specifies the period of time (in term of the number of core clocks) RX COS0 is paused before asserting rx_cos0_timer_max_int interrupt.
#define NIG_REG_P0_RX_COS1_TIMER_MAX 0x1806cUL //ACCESS:RW DataWidth:0x20 Description: This register specifies the period of time (in term of the number of core clocks) RX COS1 is paused before asserting rx_cos1_timer_max_int interrupt.
#define NIG_REG_P0_LLFC_XOFF_TIMER_MAX 0x18070UL //ACCESS:RW DataWidth:0x14 Description: Timeout value for LLFC XOFF timer in the TX direction for sending refresh LLFC messages to the BMAC. The value is in term of the number of core clocks. The timer starts whenever an LLFC request is sent to the BMAC with at least one priority in the XOFF state. An update LLFC request is sent when the timer expires. The value should be less than LLFC XOFF TIME * 8 clk per incr * core clk freq / MAC RX clk freq. The default value is set with XOFF time of 0x8000; RX clock frequency at 156.25 Mhz; and core clock frequency at 250 Mhz.
#define NIG_REG_P0_HWLLFC_RX_ENABLE 0x18074UL //ACCESS:RW DataWidth:0x1 Description: HW LLFC receive enable bit. Set this bit to enable the HW LLFC/SAFC functionality in the NIG in the RX path. The NIG block determines the XOFF/XON state of each class according to the BigMAC output SAFC signals and the mapping configuration. If a class is in XOFF state then stop the corresponding PBF queue. Other HW flow control modes such as PAUSE and PFC should be disabled when this bit is set.
#define NIG_REG_P0_HWPFC_ENABLE 0x18078UL //ACCESS:RW DataWidth:0x1 Description: HW PFC enable bit. Set this bit to enable the PFC functionality in the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be disabled when this bit is set.
#define NIG_REG_P0_ETHERTYPE0_FOR_XCM 0x1807cUL //ACCESS:RW DataWidth:0x10 Description: Ethertype for filtering packets to XCM for future flow control and congestion management protocols (QFC/QCN).
#define NIG_REG_P0_ETHERTYPE1_FOR_XCM 0x18080UL //ACCESS:RW DataWidth:0x10 Description: Ethertype for filtering packets to XCM for future flow control and congestion management protocols (QFC/QCN).
#define NIG_REG_P0_ETHERTYPE0_FOR_XCM_MASK 0x18084UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching ethertype0_for_xcm to be forwarded to XCM.
#define NIG_REG_P0_ETHERTYPE1_FOR_XCM_MASK 0x18088UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching ethertype1_for_xcm to be forwarded to XCM.
#define NIG_REG_P0_LLH_DEST_MAC_4_0 0x1808cUL //ACCESS:RW DataWidth:0x20 Register p0_llh_dest_mac_4: 1 out of 2 Description: Destination MAC address 4. LLH will look for this address in all incoming packets.
#define NIG_REG_P0_LLH_DEST_MAC_4_1 0x18090UL //ACCESS:RW DataWidth:0x10 Register p0_llh_dest_mac_4: 2 out of 2 Description: Destination MAC address 4. LLH will look for this address in all incoming packets.
#define NIG_REG_P0_LLH_DEST_MAC_5_0 0x18094UL //ACCESS:RW DataWidth:0x20 Register p0_llh_dest_mac_5: 1 out of 2 Description: Destination MAC address 5. LLH will look for this address in all incoming packets.
#define NIG_REG_P0_LLH_DEST_MAC_5_1 0x18098UL //ACCESS:RW DataWidth:0x10 Register p0_llh_dest_mac_5: 2 out of 2 Description: Destination MAC address 5. LLH will look for this address in all incoming packets.
#define NIG_REG_P0_LLH_ETHERTYPE0 0x180a4UL //ACCESS:RW DataWidth:0x10 Description: Ethertype for filtering packets.
#define NIG_REG_P0_LLH_ETHERTYPE1 0x180a8UL //ACCESS:RW DataWidth:0x10 Description: Ethertype for filtering packets.
#define NIG_REG_P0_FRAME_CRACKER_SOFT_RST 0x180c0UL //ACCESS:RW DataWidth:0x1 Description: Soft reset bit for frame cracker - not expected to be used.
#define NIG_REG_P0_FCOE_TYPE 0x180c4UL //ACCESS:RW DataWidth:0x10 Description: FCOE Ethertype - default is 0x8906.
#define NIG_REG_P0_LLH_MNG_TAG_RM 0x180ccUL //ACCESS:RW DataWidth:0x6 Description: L2 tag removal configuration for RX management traffic. Bit mapped as follow: bit 0 - outer VLAN; bit 1 - inner VLAN; bit 2 - LLC/SNAP; bit 3 - tag 0; bit 4 - tag 1; bit 5 - tag 2. Set these bits to 1's to enable the removal of the corresponding L2 tags when they are present in the receive packet. Clear the bit to keep the tag in the receive packet. This configuration is ORed with {5'd0;llh0_mng_outer_vlan_strip} for backward compatibility.
#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8UL //ACCESS:RW DataWidth:0x9 Description: Specify whether the client competes directly in the strict priority arbiter. The bits are mapped according to client ID (client IDs are defined in tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is set to enable strict priorities for all clients.
#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ecUL //ACCESS:RW DataWidth:0x9 Description: Specify whether the client is subject to WFQ credit blocking. The bits are mapped according to client ID (client IDs are defined in tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is 0 for not using WFQ credit blocking.
#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4UL //ACCESS:RW DataWidth:0xc Description: Specify the number of strict priority arbitration slots between two round-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the strict priority with anti-starvation arbiter becomes a round-robin arbiter.
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 0 when it is time to increment.
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fcUL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 1 when it is time to increment.
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 2 when it is time to increment.
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 3 when it is time to increment.
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 4 when it is time to increment.
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810cUL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 0 is allowed to reach.
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 1 is allowed to reach.
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 2 is allowed to reach.
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 3 is allowed to reach.
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811cUL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 4 is allowed to reach.
#define NIG_REG_P0_COS_DRAIN_EN 0x18120UL //ACCESS:RW DataWidth:0x6 Description: Set these bits to enable the drain mode for COS0 and COS5. Bit 0 is for COS0 flow. Bit 5 is for COS5 flow. When enabled -- draining of the corrresponding PBF COS FIFO starts immediately - packet data are dropped and not forwarded to the MAC. When disabled--draining stops at the next packet boundary.
#define NIG_REG_P0_RX_MCPCOS_PRIORITY_MASK 0x18124UL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to MCP COS. A priority is mapped to MCP COS when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS. MCP COS is used to flow control TX management traffic from MCP.
#define NIG_REG_P0_LLH_ARP_TYPE 0x18128UL //ACCESS:RW DataWidth:0x10 Description: Ethertype for ARP (filtering rules B). Defaut is 0x0806.
#define NIG_REG_P0_LLH_ICMPV4_NXTHDR 0x1812cUL //ACCESS:RW DataWidth:0x8 Description: IPv4 protocol field for ICMPv4 - defaults to 0x01.
#define NIG_REG_P0_LLH_ICMPV6_NXTHDR 0x18130UL //ACCESS:RW DataWidth:0x8 Description: IPv6 next header field for ICMPv6 - defaults to 0x3A.
#define NIG_REG_P0_LLH_LLDP_TYPE 0x18134UL //ACCESS:RW DataWidth:0x10 Description: Ethertype for LLDP (filtering rules C).
#define NIG_REG_P0_LLH_MCP_MASK_A 0x18138UL //ACCESS:RW DataWidth:0x5 Multi Field Register
#define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_MAC4 (0x1<<0)
#define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_MAC4_SIZE 0
#define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_MAC5 (0x1<<1)
#define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_MAC5_SIZE 1
#define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_ETHERTYPE0 (0x1<<2)
#define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_ETHERTYPE0_SIZE 2
#define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_ETHERTYPE1 (0x1<<3)
#define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_ETHERTYPE1_SIZE 3
#define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_ALLMLCST (0x1<<4)
#define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_ALLMLCST_SIZE 4
#define NIG_REG_P0_LLH_MCP_MASK_B 0x1813cUL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define NIG_P0_LLH_MCP_MASK_B_REG_P0_LLH_MCP_MASK_B_ARP (0x1<<0)
#define NIG_P0_LLH_MCP_MASK_B_REG_P0_LLH_MCP_MASK_B_ARP_SIZE 0
#define NIG_P0_LLH_MCP_MASK_B_REG_P0_LLH_MCP_MASK_B_ICMPV4 (0x1<<1)
#define NIG_P0_LLH_MCP_MASK_B_REG_P0_LLH_MCP_MASK_B_ICMPV4_SIZE 1
#define NIG_P0_LLH_MCP_MASK_B_REG_P0_LLH_MCP_MASK_B_ICMPV6 (0x1<<2)
#define NIG_P0_LLH_MCP_MASK_B_REG_P0_LLH_MCP_MASK_B_ICMPV6_SIZE 2
#define NIG_REG_P0_LLH_MCP_MASK_C_LLDP 0x18140UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching llh_lldp_type to be forwarded to MCP.
#define NIG_REG_P0_LLH_BRB1_MCP_MASK_A 0x18144UL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_MAC4 (0x1<<0)
#define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_MAC4_SIZE 0
#define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_MAC5 (0x1<<1)
#define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_MAC5_SIZE 1
#define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_ETHERTYPE0 (0x1<<2)
#define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_ETHERTYPE0_SIZE 2
#define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_ETHERTYPE1 (0x1<<3)
#define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_ETHERTYPE1_SIZE 3
#define NIG_REG_P0_LLH_MCP_OVMASK_B 0x18148UL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_OUTER_VLAN (0x1<<0)
#define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_OUTER_VLAN_SIZE 0
#define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_NO_OUTER_VLAN (0x1<<1)
#define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_NO_OUTER_VLAN_SIZE 1
#define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_OUTER_VLAN_ID (0x1<<2)
#define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_OUTER_VLAN_ID_SIZE 2
#define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_PF_OUTER_VLAN (0x1<<3)
#define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_PF_OUTER_VLAN_SIZE 3
#define NIG_REG_P0_LLH_MCP_OVMASK_C 0x1814cUL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_OUTER_VLAN (0x1<<0)
#define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_OUTER_VLAN_SIZE 0
#define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_NO_OUTER_VLAN (0x1<<1)
#define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_NO_OUTER_VLAN_SIZE 1
#define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_OUTER_VLAN_ID (0x1<<2)
#define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_OUTER_VLAN_ID_SIZE 2
#define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_PF_OUTER_VLAN (0x1<<3)
#define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_PF_OUTER_VLAN_SIZE 3
#define NIG_REG_P0_XCM_TYPE_VALID 0x18150UL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_MCF (0x1<<0)
#define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_MCF_SIZE 0
#define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_BCN (0x1<<1)
#define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_BCN_SIZE 1
#define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_ETHERTYPE0 (0x1<<2)
#define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_ETHERTYPE0_SIZE 2
#define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_ETHERTYPE1 (0x1<<3)
#define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_ETHERTYPE1_SIZE 3
#define NIG_REG_P0_TX_ARB_DBG_CLIENT_DISABLE 0x1816cUL //ACCESS:RW DataWidth:0x2 Description: Set these bits to disable debug traffic at the inputs to the ETS arbiter. Bit 0 is for debug traffic from the current path. Bit 1 is for debug traffic from the other path.
#define NIG_REG_EGRESS_DEBUG_PATH 0x18170UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to select the path for sending debug traffic. 0 selects the current path. 1 selects the other path.
#define NIG_REG_P1_TAG_ETHERTYPE_0 0x18174UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 0. This tag is used for VNTAG classification and filtering in E3 B0 - when enabled.
#define NIG_REG_P1_TAG_ETHERTYPE_1 0x18178UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 1
#define NIG_REG_P1_TAG_ETHERTYPE_2 0x1817cUL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 2
#define NIG_REG_P1_TAG_LEN_0 0x18180UL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 0 - in bytes. The length is between 2B and 14B; in 2B granularity. This length does not include the Ethertype field.
#define NIG_REG_P1_TAG_LEN_1 0x18184UL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 1 - in bytes. The length is between 2B and 14B; in 2B granularity. This length does not include the Ethertype field.
#define NIG_REG_P1_TAG_LEN_2 0x18188UL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 2 - in bytes. The length is between 2B and 14B; in 2B granularity. This length does not include the Ethertype field.
#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818cUL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.
#define NIG_REG_P1_HDRS_AFTER_OUTER_VLAN 0x18190UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the outer VLAN header.
#define NIG_REG_P1_HDRS_AFTER_INNER_VLAN 0x18194UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the inner VLAN header.
#define NIG_REG_P1_HDRS_AFTER_LLC 0x18198UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the LLC header.
#define NIG_REG_P1_HDRS_AFTER_TAG_0 0x1819cUL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 0
#define NIG_REG_P1_HDRS_AFTER_TAG_1 0x181a0UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 1
#define NIG_REG_P1_HDRS_AFTER_TAG_2 0x181a4UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 2
#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8UL //ACCESS:RW DataWidth:0x20 Description: Eight 4-bit configurations for specifying which COS (0-15 for future expansion) each priorty is to be mapped to. Bits 3:0 specify the COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit priority field is extracted from the outer-most VLAN in receive packet. Only COS 0 and COS 1 are supported in E2.
#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181acUL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to COS 0. A priority is mapped to COS 0 when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS.
#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0UL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to COS 1. A priority is mapped to COS 1 when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS.
#define NIG_REG_P1_RX_MCPCOS_PRIORITY_MASK 0x181b4UL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to MCP COS. A priority is mapped to MCP COS when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS. MCP COS is used to flow control TX management traffic from MCP.
#define NIG_REG_P1_RX_COS0_TIMER_WRAP 0x181b8UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 0 timer to start over when it reaches the configured maximum time.
#define NIG_REG_P1_RX_COS1_TIMER_WRAP 0x181bcUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 1 timer to start over when it reaches the configured maximum time.
#define NIG_REG_P1_RX_COS0_TIMER_MAX 0x181c0UL //ACCESS:RW DataWidth:0x20 Description: This register specifies the period of time (in term of the number of core clocks) RX COS0 is paused before asserting rx_cos0_timer_max_int interrupt.
#define NIG_REG_P1_RX_COS1_TIMER_MAX 0x181c4UL //ACCESS:RW DataWidth:0x20 Description: This register specifies the period of time (in term of the number of core clocks) RX COS1 is paused before asserting rx_cos1_timer_max_int interrupt.
#define NIG_REG_P1_LLFC_XOFF_TIMER_MAX 0x181c8UL //ACCESS:RW DataWidth:0x14 Description: Timeout value for LLFC XOFF timer in the TX direction for sending refresh LLFC messages to the BMAC. The value is in term of the number of core clocks. The timer starts whenever an LLFC request is sent to the BMAC with at least one priority in the XOFF state. An update LLFC request is sent when the timer expires. The value should be less than LLFC XOFF TIME * 8 clk per incr * core clk freq / MAC RX clk freq. The default value is set with XOFF time of 0x8000; RX clock frequency at 156.25 Mhz; and core clock frequency at 250 Mhz.
#define NIG_REG_P1_HWLLFC_RX_ENABLE 0x181ccUL //ACCESS:RW DataWidth:0x1 Description: HW LLFC receive enable bit. Set this bit to enable the HW LLFC/SAFC functionality in the NIG in the RX path. The NIG block determines the XOFF/XON state of each class according to the BigMAC output SAFC signals and the mapping configuration. If a class is in XOFF state then stop the corresponding PBF queue. Other HW flow control modes such as PAUSE and PFC should be disabled when this bit is set.
#define NIG_REG_P1_HWPFC_ENABLE 0x181d0UL //ACCESS:RW DataWidth:0x1 Description: HW PFC enable bit. Set this bit to enable the PFC functionality in the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be disabled when this bit is set.
#define NIG_REG_P1_ETHERTYPE0_FOR_XCM 0x181d4UL //ACCESS:RW DataWidth:0x10 Description: Ethertype for filtering packets to XCM for future flow control and congestion management protocols (QFC/QCN).
#define NIG_REG_P1_ETHERTYPE1_FOR_XCM 0x181d8UL //ACCESS:RW DataWidth:0x10 Description: Ethertype for filtering packets to XCM for future flow control and congestion management protocols (QFC/QCN).
#define NIG_REG_P1_ETHERTYPE0_FOR_XCM_MASK 0x181dcUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching ethertype0_for_xcm to be forwarded to XCM.
#define NIG_REG_P1_ETHERTYPE1_FOR_XCM_MASK 0x181e0UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching ethertype1_for_xcm to be forwarded to XCM.
#define NIG_REG_P1_LLH_DEST_MAC_4_0 0x181e4UL //ACCESS:RW DataWidth:0x20 Register p1_llh_dest_mac_4: 1 out of 2 Description: Destination MAC address 4. LLH will look for this address in all incoming packets.
#define NIG_REG_P1_LLH_DEST_MAC_4_1 0x181e8UL //ACCESS:RW DataWidth:0x10 Register p1_llh_dest_mac_4: 2 out of 2 Description: Destination MAC address 4. LLH will look for this address in all incoming packets.
#define NIG_REG_P1_LLH_DEST_MAC_5_0 0x181ecUL //ACCESS:RW DataWidth:0x20 Register p1_llh_dest_mac_5: 1 out of 2 Description: Destination MAC address 5. LLH will look for this address in all incoming packets.
#define NIG_REG_P1_LLH_DEST_MAC_5_1 0x181f0UL //ACCESS:RW DataWidth:0x10 Register p1_llh_dest_mac_5: 2 out of 2 Description: Destination MAC address 5. LLH will look for this address in all incoming packets.
#define NIG_REG_P1_LLH_ETHERTYPE0 0x181f4UL //ACCESS:RW DataWidth:0x10 Description: Ethertype for filtering packets.
#define NIG_REG_P1_LLH_ETHERTYPE1 0x181f8UL //ACCESS:RW DataWidth:0x10 Description: Ethertype for filtering packets.
#define NIG_REG_P1_LLH_ARP_TYPE 0x181fcUL //ACCESS:RW DataWidth:0x10 Description: Ethertype for ARP (filtering rules B). Defaut is 0x0806.
#define NIG_REG_P1_LLH_ICMPV4_NXTHDR 0x18200UL //ACCESS:RW DataWidth:0x8 Description: IPv4 protocol field for ICMPv4 - defaults to 0x01.
#define NIG_REG_P1_LLH_ICMPV6_NXTHDR 0x18204UL //ACCESS:RW DataWidth:0x8 Description: IPv6 next header field for ICMPv6 - defaults to 0x3A.
#define NIG_REG_P1_LLH_LLDP_TYPE 0x18208UL //ACCESS:RW DataWidth:0x10 Description: Ethertype for LLDP (filtering rules C).
#define NIG_REG_P1_LLH_MCP_MASK_A 0x1820cUL //ACCESS:RW DataWidth:0x5 Multi Field Register
#define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_MAC4 (0x1<<0)
#define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_MAC4_SIZE 0
#define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_MAC5 (0x1<<1)
#define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_MAC5_SIZE 1
#define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_ETHERTYPE0 (0x1<<2)
#define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_ETHERTYPE0_SIZE 2
#define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_ETHERTYPE1 (0x1<<3)
#define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_ETHERTYPE1_SIZE 3
#define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_ALLMLCST (0x1<<4)
#define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_ALLMLCST_SIZE 4
#define NIG_REG_P1_LLH_MCP_MASK_B 0x18210UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define NIG_P1_LLH_MCP_MASK_B_REG_P1_LLH_MCP_MASK_B_ARP (0x1<<0)
#define NIG_P1_LLH_MCP_MASK_B_REG_P1_LLH_MCP_MASK_B_ARP_SIZE 0
#define NIG_P1_LLH_MCP_MASK_B_REG_P1_LLH_MCP_MASK_B_ICMPV4 (0x1<<1)
#define NIG_P1_LLH_MCP_MASK_B_REG_P1_LLH_MCP_MASK_B_ICMPV4_SIZE 1
#define NIG_P1_LLH_MCP_MASK_B_REG_P1_LLH_MCP_MASK_B_ICMPV6 (0x1<<2)
#define NIG_P1_LLH_MCP_MASK_B_REG_P1_LLH_MCP_MASK_B_ICMPV6_SIZE 2
#define NIG_REG_P1_LLH_MCP_MASK_C_LLDP 0x18214UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching llh_lldp_type to be forwarded to MCP.
#define NIG_REG_P1_LLH_BRB1_MCP_MASK_A 0x18218UL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_MAC4 (0x1<<0)
#define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_MAC4_SIZE 0
#define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_MAC5 (0x1<<1)
#define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_MAC5_SIZE 1
#define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_ETHERTYPE0 (0x1<<2)
#define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_ETHERTYPE0_SIZE 2
#define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_ETHERTYPE1 (0x1<<3)
#define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_ETHERTYPE1_SIZE 3
#define NIG_REG_P1_LLH_MCP_OVMASK_B 0x1821cUL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_OUTER_VLAN (0x1<<0)
#define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_OUTER_VLAN_SIZE 0
#define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_NO_OUTER_VLAN (0x1<<1)
#define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_NO_OUTER_VLAN_SIZE 1
#define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_OUTER_VLAN_ID (0x1<<2)
#define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_OUTER_VLAN_ID_SIZE 2
#define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_PF_OUTER_VLAN (0x1<<3)
#define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_PF_OUTER_VLAN_SIZE 3
#define NIG_REG_P1_LLH_MCP_OVMASK_C 0x18220UL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_OUTER_VLAN (0x1<<0)
#define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_OUTER_VLAN_SIZE 0
#define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_NO_OUTER_VLAN (0x1<<1)
#define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_NO_OUTER_VLAN_SIZE 1
#define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_OUTER_VLAN_ID (0x1<<2)
#define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_OUTER_VLAN_ID_SIZE 2
#define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_PF_OUTER_VLAN (0x1<<3)
#define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_PF_OUTER_VLAN_SIZE 3
#define NIG_REG_P1_FRAME_CRACKER_SOFT_RST 0x18224UL //ACCESS:RW DataWidth:0x1 Description: Soft reset bit for frame cracker - not expected to be used.
#define NIG_REG_P1_FCOE_TYPE 0x18228UL //ACCESS:RW DataWidth:0x10 Description: FCOE Ethertype - default is 0x8906.
#define NIG_REG_P1_LLH_MNG_TAG_RM 0x1822cUL //ACCESS:RW DataWidth:0x6 Description: L2 tag removal configuration for RX management traffic. Bit mapped as follow: bit 0 - outer VLAN; bit 1 - inner VLAN; bit 2 - LLC/SNAP; bit 3 - tag 0; bit 4 - tag 1; bit 5 - tag 2. Set these bits to 1's to enable the removal of the corresponding L2 tags when they are present in the receive packet. Clear the bit to keep the tag in the receive packet. This configuration is ORed with {5'd0;llh0_mng_outer_vlan_strip} for backward compatibility.
#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234UL //ACCESS:RW DataWidth:0x9 Description: Specify whether the client competes directly in the strict priority arbiter. The bits are mapped according to client ID (client IDs are defined in tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is set to enable strict priorities for all clients.
#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238UL //ACCESS:RW DataWidth:0x9 Description: Specify whether the client is subject to WFQ credit blocking. The bits are mapped according to client ID (client IDs are defined in tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is 0 for not using WFQ credit blocking.
#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240UL //ACCESS:RW DataWidth:0xc Description: Specify the number of strict priority arbitration slots between two round-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the strict priority with anti-starvation arbiter becomes a round-robin arbiter.
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 0 when it is time to increment.
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 1 when it is time to increment.
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824cUL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 2 when it is time to increment.
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 3 when it is time to increment.
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 4 when it is time to increment.
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 0 is allowed to reach.
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825cUL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 1 is allowed to reach.
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 2 is allowed to reach.
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 3 is allowed to reach.
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 4 is allowed to reach.
#define NIG_REG_P1_XCM_TYPE_VALID 0x1826cUL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_MCF (0x1<<0)
#define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_MCF_SIZE 0
#define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_BCN (0x1<<1)
#define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_BCN_SIZE 1
#define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_ETHERTYPE0 (0x1<<2)
#define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_ETHERTYPE0_SIZE 2
#define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_ETHERTYPE1 (0x1<<3)
#define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_ETHERTYPE1_SIZE 3
#define NIG_REG_P1_TX_ARB_DBG_CLIENT_DISABLE 0x18270UL //ACCESS:RW DataWidth:0x2 Description: Set these bits to disable debug traffic at the inputs to the ETS arbiter. Bit 0 is for debug traffic from the current path. Bit 1 is for debug traffic from the other path.
#define NIG_REG_P0_LLH_GLOBAL_ERROR_MASK 0x18288UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define NIG_P0_LLH_GLOBAL_ERROR_MASK_REG_P0_LLH_XCM_ERROR_MASK (0x1<<0)
#define NIG_P0_LLH_GLOBAL_ERROR_MASK_REG_P0_LLH_XCM_ERROR_MASK_SIZE 0
#define NIG_P0_LLH_GLOBAL_ERROR_MASK_REG_P0_LLH_MCP_ERROR_MASK (0x1<<1)
#define NIG_P0_LLH_GLOBAL_ERROR_MASK_REG_P0_LLH_MCP_ERROR_MASK_SIZE 1
#define NIG_P0_LLH_GLOBAL_ERROR_MASK_REG_P0_LLH_BRB1_ERROR_MASK (0x1<<2)
#define NIG_P0_LLH_GLOBAL_ERROR_MASK_REG_P0_LLH_BRB1_ERROR_MASK_SIZE 2
#define NIG_REG_P1_COS_DRAIN_EN 0x1828cUL //ACCESS:RW DataWidth:0x6 Description: Set these bits to enable the drain mode for COS0 and COS1. Bit 0 is for COS0 flow. Bit 1 is for COS1 flow. When enabled -- draining of the corrresponding PBF COS FIFO starts immediately - packet data are dropped and not forwarded to the MAC. When disabled--draining stops at the next packet boundary.
#define NIG_REG_P1_LLH_GLOBAL_ERROR_MASK 0x18290UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define NIG_P1_LLH_GLOBAL_ERROR_MASK_REG_P1_LLH_XCM_ERROR_MASK (0x1<<0)
#define NIG_P1_LLH_GLOBAL_ERROR_MASK_REG_P1_LLH_XCM_ERROR_MASK_SIZE 0
#define NIG_P1_LLH_GLOBAL_ERROR_MASK_REG_P1_LLH_MCP_ERROR_MASK (0x1<<1)
#define NIG_P1_LLH_GLOBAL_ERROR_MASK_REG_P1_LLH_MCP_ERROR_MASK_SIZE 1
#define NIG_P1_LLH_GLOBAL_ERROR_MASK_REG_P1_LLH_BRB1_ERROR_MASK (0x1<<2)
#define NIG_P1_LLH_GLOBAL_ERROR_MASK_REG_P1_LLH_BRB1_ERROR_MASK_SIZE 2
#define NIG_REG_P0_TX_MNG_DESTINATION 0x182c4UL //ACCESS:RW DataWidth:0x2 Description: Destination of the packet that will be loaded through the UMP-to-NIG interface. Value of 1 indicates to send to the network. Value of 2 indicates to send to the host. Value of 3 indicates to send to both the network and host. Value of 0 is invalid and causes the packet to be not loaded into the Management TX buffers.
#define NIG_REG_P0_TX_MNG_HOST_CTRL 0x182c8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define NIG_P0_TX_MNG_HOST_CTRL_REG_P0_TX_MNG_HOST_SIDEBAND_INFO (0xffff<<0)
#define NIG_P0_TX_MNG_HOST_CTRL_REG_P0_TX_MNG_HOST_SIDEBAND_INFO_SIZE 0
#define NIG_P0_TX_MNG_HOST_CTRL_REG_P0_TX_MNG_HOST_PORT_ID_TAG (0x1<<16)
#define NIG_P0_TX_MNG_HOST_CTRL_REG_P0_TX_MNG_HOST_PORT_ID_TAG_SIZE 16
#define NIG_P0_TX_MNG_HOST_CTRL_REG_P0_TX_MNG_HOST_VNIC_NUM (0x3<<17)
#define NIG_P0_TX_MNG_HOST_CTRL_REG_P0_TX_MNG_HOST_VNIC_NUM_SIZE 17
#define NIG_P0_TX_MNG_HOST_CTRL_REG_P0_TX_MNG_HOST_OUTER_VLAN_HEADER_INSERT (0x1<<19)
#define NIG_P0_TX_MNG_HOST_CTRL_REG_P0_TX_MNG_HOST_OUTER_VLAN_HEADER_INSERT_SIZE 19
#define NIG_REG_P0_TX_MNG_HOST_OUTER_VLAN_MSB 0x182ccUL //ACCESS:RW DataWidth:0x14 Description: The 20 most significant bits of the outer VLAN header to be inserted into MCP packets that are forwarded to the host. These bits compose of 16-bit Ethertype; 3-bit priority; and 1-bit canonical format indicator. The 12 LSB bits of the inserted VLAN header is selected from the per-PF VLAN IDs based on the configured VNIC number.
#define NIG_REG_P0_TX_MNG_HOST_FIFO_TM 0x182d0UL //ACCESS:RW DataWidth:0x5 Description: TM for MCP TX FIFO used for fowarding packets to the host.
#define NIG_REG_P1_TX_MNG_DESTINATION 0x182d4UL //ACCESS:RW DataWidth:0x2 Description: Destination of the packet that will be loaded through the UMP-to-NIG interface. Value of 1 indicates to send to the network. Value of 2 indicates to send to the host. Value of 3 indicates to send to both the network and host. Value of 0 is invalid and causes the packet to be not loaded into the Management TX buffers.
#define NIG_REG_P1_TX_MNG_HOST_CTRL 0x182d8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define NIG_P1_TX_MNG_HOST_CTRL_REG_P1_TX_MNG_HOST_SIDEBAND_INFO (0xffff<<0)
#define NIG_P1_TX_MNG_HOST_CTRL_REG_P1_TX_MNG_HOST_SIDEBAND_INFO_SIZE 0
#define NIG_P1_TX_MNG_HOST_CTRL_REG_P1_TX_MNG_HOST_PORT_ID_TAG (0x1<<16)
#define NIG_P1_TX_MNG_HOST_CTRL_REG_P1_TX_MNG_HOST_PORT_ID_TAG_SIZE 16
#define NIG_P1_TX_MNG_HOST_CTRL_REG_P1_TX_MNG_HOST_VNIC_NUM (0x3<<17)
#define NIG_P1_TX_MNG_HOST_CTRL_REG_P1_TX_MNG_HOST_VNIC_NUM_SIZE 17
#define NIG_P1_TX_MNG_HOST_CTRL_REG_P1_TX_MNG_HOST_OUTER_VLAN_HEADER_INSERT (0x1<<19)
#define NIG_P1_TX_MNG_HOST_CTRL_REG_P1_TX_MNG_HOST_OUTER_VLAN_HEADER_INSERT_SIZE 19
#define NIG_REG_P1_TX_MNG_HOST_OUTER_VLAN_MSB 0x182dcUL //ACCESS:RW DataWidth:0x14 Description: The 20 most significant bits of the outer VLAN header to be inserted into MCP packets that are forwarded to the host. These bits compose of 16-bit Ethertype; 3-bit priority; and 1-bit canonical format indicator. The 12 LSB bits of the inserted VLAN header is selected from the per-PF VLAN IDs based on the configured VNIC number.
#define NIG_REG_P1_TX_MNG_HOST_FIFO_TM 0x182e0UL //ACCESS:RW DataWidth:0x5 Description: TM for MCP TX FIFO used for fowarding packets to the host.
#define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4UL //ACCESS:RW DataWidth:0x1 Description: MCP-to-host path enable. Set this bit to enable the routing of MCP packets to BRB LB interface to forward the packet to the host. All packets from MCP are forwarded to the network when this bit is cleared - regardless of the configured destination in tx_mng_destination register. When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter for BRB LB interface is bypassed and PBF LB traffic is always selected to send to BRB LB.
#define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8UL //ACCESS:RW DataWidth:0x1 Description: MCP-to-host path enable. Set this bit to enable the routing of MCP packets to BRB LB interface to forward the packet to the host. All packets from MCP are forwarded to the network when this bit is cleared - regardless of the configured destination in tx_mng_destination register.
#define NIG_REG_P0_TX_HOST_MNG_ENABLE 0x1835cUL //ACCESS:RW DataWidth:0x1 Description: Host-to-MCP path enable. Set this bit to enable the routing of management packets from PBF interface toward MCP when the criteria for the MCP filters are met. All packets from PBF are forwarded to the network when this bit is cleared.
#define NIG_REG_P0_TLLH_MCP_MASK 0x18360UL //ACCESS:RW DataWidth:0x1d Multi Field Register
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_BRCST (0x1<<0)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_BRCST_SIZE 0
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MLCST (0x1<<1)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MLCST_SIZE 1
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UNCST (0x1<<2)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UNCST_SIZE 2
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC0 (0x1<<3)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC0_SIZE 3
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC1 (0x1<<4)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC1_SIZE 4
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC2 (0x1<<5)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC2_SIZE 5
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_ARP (0x1<<6)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_ARP_SIZE 6
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IP0 (0x1<<7)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IP0_SIZE 7
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IP1 (0x1<<8)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IP1_SIZE 8
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IP2 (0x1<<9)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IP2_SIZE 9
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_U_SRC (0x1<<10)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_U_SRC_SIZE 10
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_T_SRC (0x1<<11)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_T_SRC_SIZE 11
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_RMCP (0x1<<12)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_RMCP_SIZE 12
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_DHCP (0x1<<13)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_DHCP_SIZE 13
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_U_DST (0x1<<14)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_U_DST_SIZE 14
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UDP0 (0x1<<15)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UDP0_SIZE 15
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UDP1 (0x1<<16)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UDP1_SIZE 16
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UDP2 (0x1<<17)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UDP2_SIZE 17
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_T_DST (0x1<<18)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_T_DST_SIZE 18
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_TCP0 (0x1<<19)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_TCP0_SIZE 19
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_TCP1 (0x1<<20)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_TCP1_SIZE 20
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_TCP2 (0x1<<21)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_TCP2_SIZE 21
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN_ID0 (0x1<<22)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN_ID0_SIZE 22
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN_ID1 (0x1<<23)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN_ID1_SIZE 23
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN_ID2 (0x1<<24)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN_ID2_SIZE 24
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN (0x1<<25)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN_SIZE 25
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NO_VLAN (0x1<<26)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NO_VLAN_SIZE 26
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC3 (0x1<<27)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC3_SIZE 27
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IPV6_MLCST (0x1<<28)
#define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IPV6_MLCST_SIZE 28
#define NIG_REG_P0_TLLH_MCP_MASK_EXT 0x18364UL //ACCESS:RW DataWidth:0x5 Multi Field Register
#define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_MAC4 (0x1<<0)
#define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_MAC4_SIZE 0
#define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_MAC5 (0x1<<1)
#define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_MAC5_SIZE 1
#define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_ETHERTYPE0 (0x1<<2)
#define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_ETHERTYPE0_SIZE 2
#define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_ETHERTYPE1 (0x1<<3)
#define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_ETHERTYPE1_SIZE 3
#define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_ALLMLCST (0x1<<4)
#define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_ALLMLCST_SIZE 4
#define NIG_REG_P0_TLLH_NTWK_DRV_MASK 0x18368UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_BRCST (0x1<<0)
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_BRCST_SIZE 0
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_MLCST (0x1<<1)
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_MLCST_SIZE 1
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_UNCST (0x1<<2)
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_UNCST_SIZE 2
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_VLAN (0x1<<3)
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_VLAN_SIZE 3
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_NO_VLAN (0x1<<4)
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_NO_VLAN_SIZE 4
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_ALLMLCST (0x1<<5)
#define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_ALLMLCST_SIZE 5
#define NIG_REG_P0_TLLH_NTWK_MCP_MASK 0x1836cUL //ACCESS:RW DataWidth:0x1c Multi Field Register
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC0 (0x1<<0)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC0_SIZE 0
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC1 (0x1<<1)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC1_SIZE 1
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC2 (0x1<<2)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC2_SIZE 2
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_ARP (0x1<<3)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_ARP_SIZE 3
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IP0 (0x1<<4)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IP0_SIZE 4
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IP1 (0x1<<5)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IP1_SIZE 5
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IP2 (0x1<<6)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IP2_SIZE 6
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_SRC_SIZE 7
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_SRC_SIZE 8
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_RMCP (0x1<<9)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_RMCP_SIZE 9
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_DHCP (0x1<<10)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_DHCP_SIZE 10
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_DST_SIZE 11
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_UDP0 (0x1<<12)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_UDP0_SIZE 12
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_UDP1 (0x1<<13)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_UDP1_SIZE 13
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_UDP2 (0x1<<14)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_UDP2_SIZE 14
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_DST_SIZE 15
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_TCP0 (0x1<<16)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_TCP0_SIZE 16
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_TCP1 (0x1<<17)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_TCP1_SIZE 17
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_TCP2 (0x1<<18)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_TCP2_SIZE 18
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_VLAN_ID0 (0x1<<19)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_VLAN_ID0_SIZE 19
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_VLAN_ID1 (0x1<<20)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_VLAN_ID1_SIZE 20
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_VLAN_ID2 (0x1<<21)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_VLAN_ID2_SIZE 21
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC3 (0x1<<22)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC3_SIZE 22
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IPV6_MLCST (0x1<<23)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IPV6_MLCST_SIZE 23
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC4 (0x1<<24)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC4_SIZE 24
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC5 (0x1<<25)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC5_SIZE 25
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_ETHERTYPE0 (0x1<<26)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_ETHERTYPE0_SIZE 26
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_ETHERTYPE1 (0x1<<27)
#define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_ETHERTYPE1_SIZE 27
#define NIG_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK 0x18370UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_BRCST (0x1<<0)
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_BRCST_SIZE 0
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_MLCST (0x1<<1)
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_MLCST_SIZE 1
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_UNCST (0x1<<2)
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_UNCST_SIZE 2
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_VLAN (0x1<<3)
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_VLAN_SIZE 3
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_NO_VLAN (0x1<<4)
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_NO_VLAN_SIZE 4
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_ALLMLCST (0x1<<5)
#define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_ALLMLCST_SIZE 5
#define NIG_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK 0x18374UL //ACCESS:RW DataWidth:0x1c Multi Field Register
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC0 (0x1<<0)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC0_SIZE 0
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC1 (0x1<<1)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC1_SIZE 1
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC2 (0x1<<2)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC2_SIZE 2
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_ARP (0x1<<3)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_ARP_SIZE 3
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IP0 (0x1<<4)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IP0_SIZE 4
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IP1 (0x1<<5)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IP1_SIZE 5
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IP2 (0x1<<6)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IP2_SIZE 6
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_SRC_SIZE 7
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_SRC_SIZE 8
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_RMCP (0x1<<9)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_RMCP_SIZE 9
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_DHCP (0x1<<10)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_DHCP_SIZE 10
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_DST_SIZE 11
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP0 (0x1<<12)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP0_SIZE 12
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP1 (0x1<<13)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP1_SIZE 13
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP2 (0x1<<14)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP2_SIZE 14
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_DST_SIZE 15
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP0 (0x1<<16)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP0_SIZE 16
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP1 (0x1<<17)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP1_SIZE 17
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP2 (0x1<<18)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP2_SIZE 18
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID0 (0x1<<19)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID0_SIZE 19
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID1 (0x1<<20)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID1_SIZE 20
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID2 (0x1<<21)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID2_SIZE 21
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC3 (0x1<<22)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC3_SIZE 22
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IPV6_MLCST (0x1<<23)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IPV6_MLCST_SIZE 23
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC4 (0x1<<24)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC4_SIZE 24
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC5 (0x1<<25)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC5_SIZE 25
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE0 (0x1<<26)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE0_SIZE 26
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE1 (0x1<<27)
#define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE1_SIZE 27
#define NIG_REG_P0_TLLH_GLOBAL_ERROR_MASK 0x18378UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define NIG_P0_TLLH_GLOBAL_ERROR_MASK_REG_P0_TLLH_MCP_ERROR_MASK (0x1<<0)
#define NIG_P0_TLLH_GLOBAL_ERROR_MASK_REG_P0_TLLH_MCP_ERROR_MASK_SIZE 0
#define NIG_P0_TLLH_GLOBAL_ERROR_MASK_REG_P0_TLLH_NTWK_ERROR_MASK (0x1<<1)
#define NIG_P0_TLLH_GLOBAL_ERROR_MASK_REG_P0_TLLH_NTWK_ERROR_MASK_SIZE 1
#define NIG_REG_P0_HBUF_MEM_RBC_ACCESS 0x1837cUL //ACCESS:RW DataWidth:0x1 Description: Debug only. This bit is for selecting the RX management memory for register read/write access through ingress_mng*_fifo register space. Set to 1 to select the Host-to-BMC buffer (HBUF). Set to 0 to select the MCP RX buffer:w.
#define NIG_REG_P0_TLLH_FIFO_TM 0x18380UL //ACCESS:RW DataWidth:0x2 Description: TM for TLLH FIFO
#define NIG_REG_P0_HBUF_TM 0x18384UL //ACCESS:RW DataWidth:0x5 Description: TM for Host-to-BMC buffer.
#define NIG_REG_P0_TLLH_FRAME_CRACKER_SOFT_RST 0x18388UL //ACCESS:RW DataWidth:0x1 Description: Soft reset bit for frame cracker - not expected to be used.
#define NIG_REG_P1_TX_HOST_MNG_ENABLE 0x1838cUL //ACCESS:RW DataWidth:0x1 Description: Host-to-MCP path enable. Set this bit to enable the routing of management packets from PBF interface toward MCP when the criteria for the MCP filters are met. All packets from PBF are forwarded to the network when this bit is cleared.
#define NIG_REG_P1_TLLH_MCP_MASK 0x18390UL //ACCESS:RW DataWidth:0x1d Multi Field Register
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_BRCST (0x1<<0)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_BRCST_SIZE 0
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MLCST (0x1<<1)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MLCST_SIZE 1
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UNCST (0x1<<2)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UNCST_SIZE 2
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC0 (0x1<<3)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC0_SIZE 3
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC1 (0x1<<4)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC1_SIZE 4
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC2 (0x1<<5)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC2_SIZE 5
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_ARP (0x1<<6)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_ARP_SIZE 6
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IP0 (0x1<<7)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IP0_SIZE 7
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IP1 (0x1<<8)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IP1_SIZE 8
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IP2 (0x1<<9)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IP2_SIZE 9
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_U_SRC (0x1<<10)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_U_SRC_SIZE 10
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_T_SRC (0x1<<11)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_T_SRC_SIZE 11
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_RMCP (0x1<<12)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_RMCP_SIZE 12
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_DHCP (0x1<<13)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_DHCP_SIZE 13
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_U_DST (0x1<<14)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_U_DST_SIZE 14
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UDP0 (0x1<<15)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UDP0_SIZE 15
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UDP1 (0x1<<16)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UDP1_SIZE 16
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UDP2 (0x1<<17)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UDP2_SIZE 17
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_T_DST (0x1<<18)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_T_DST_SIZE 18
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_TCP0 (0x1<<19)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_TCP0_SIZE 19
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_TCP1 (0x1<<20)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_TCP1_SIZE 20
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_TCP2 (0x1<<21)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_TCP2_SIZE 21
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN_ID0 (0x1<<22)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN_ID0_SIZE 22
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN_ID1 (0x1<<23)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN_ID1_SIZE 23
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN_ID2 (0x1<<24)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN_ID2_SIZE 24
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN (0x1<<25)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN_SIZE 25
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NO_VLAN (0x1<<26)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NO_VLAN_SIZE 26
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC3 (0x1<<27)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC3_SIZE 27
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IPV6_MLCST (0x1<<28)
#define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IPV6_MLCST_SIZE 28
#define NIG_REG_P1_TLLH_MCP_MASK_EXT 0x18394UL //ACCESS:RW DataWidth:0x5 Multi Field Register
#define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_MAC4 (0x1<<0)
#define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_MAC4_SIZE 0
#define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_MAC5 (0x1<<1)
#define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_MAC5_SIZE 1
#define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_ETHERTYPE0 (0x1<<2)
#define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_ETHERTYPE0_SIZE 2
#define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_ETHERTYPE1 (0x1<<3)
#define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_ETHERTYPE1_SIZE 3
#define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_ALLMLCST (0x1<<4)
#define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_ALLMLCST_SIZE 4
#define NIG_REG_P1_TLLH_NTWK_DRV_MASK 0x18398UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_BRCST (0x1<<0)
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_BRCST_SIZE 0
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_MLCST (0x1<<1)
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_MLCST_SIZE 1
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_UNCST (0x1<<2)
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_UNCST_SIZE 2
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_VLAN (0x1<<3)
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_VLAN_SIZE 3
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_NO_VLAN (0x1<<4)
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_NO_VLAN_SIZE 4
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_ALLMLCST (0x1<<5)
#define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_ALLMLCST_SIZE 5
#define NIG_REG_P1_TLLH_NTWK_MCP_MASK 0x1839cUL //ACCESS:RW DataWidth:0x1c Multi Field Register
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC0 (0x1<<0)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC0_SIZE 0
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC1 (0x1<<1)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC1_SIZE 1
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC2 (0x1<<2)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC2_SIZE 2
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_ARP (0x1<<3)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_ARP_SIZE 3
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IP0 (0x1<<4)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IP0_SIZE 4
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IP1 (0x1<<5)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IP1_SIZE 5
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IP2 (0x1<<6)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IP2_SIZE 6
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_SRC_SIZE 7
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_SRC_SIZE 8
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_RMCP (0x1<<9)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_RMCP_SIZE 9
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_DHCP (0x1<<10)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_DHCP_SIZE 10
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_DST_SIZE 11
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_UDP0 (0x1<<12)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_UDP0_SIZE 12
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_UDP1 (0x1<<13)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_UDP1_SIZE 13
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_UDP2 (0x1<<14)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_UDP2_SIZE 14
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_DST_SIZE 15
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_TCP0 (0x1<<16)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_TCP0_SIZE 16
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_TCP1 (0x1<<17)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_TCP1_SIZE 17
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_TCP2 (0x1<<18)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_TCP2_SIZE 18
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_VLAN_ID0 (0x1<<19)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_VLAN_ID0_SIZE 19
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_VLAN_ID1 (0x1<<20)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_VLAN_ID1_SIZE 20
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_VLAN_ID2 (0x1<<21)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_VLAN_ID2_SIZE 21
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC3 (0x1<<22)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC3_SIZE 22
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IPV6_MLCST (0x1<<23)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IPV6_MLCST_SIZE 23
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC4 (0x1<<24)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC4_SIZE 24
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC5 (0x1<<25)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC5_SIZE 25
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_ETHERTYPE0 (0x1<<26)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_ETHERTYPE0_SIZE 26
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_ETHERTYPE1 (0x1<<27)
#define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_ETHERTYPE1_SIZE 27
#define NIG_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK 0x183a0UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_BRCST (0x1<<0)
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_BRCST_SIZE 0
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_MLCST (0x1<<1)
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_MLCST_SIZE 1
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_UNCST (0x1<<2)
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_UNCST_SIZE 2
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_VLAN (0x1<<3)
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_VLAN_SIZE 3
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_NO_VLAN (0x1<<4)
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_NO_VLAN_SIZE 4
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_ALLMLCST (0x1<<5)
#define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_ALLMLCST_SIZE 5
#define NIG_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK 0x183a4UL //ACCESS:RW DataWidth:0x1c Multi Field Register
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC0 (0x1<<0)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC0_SIZE 0
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC1 (0x1<<1)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC1_SIZE 1
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC2 (0x1<<2)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC2_SIZE 2
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_ARP (0x1<<3)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_ARP_SIZE 3
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IP0 (0x1<<4)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IP0_SIZE 4
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IP1 (0x1<<5)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IP1_SIZE 5
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IP2 (0x1<<6)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IP2_SIZE 6
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_SRC_SIZE 7
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_SRC_SIZE 8
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_RMCP (0x1<<9)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_RMCP_SIZE 9
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_DHCP (0x1<<10)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_DHCP_SIZE 10
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_DST_SIZE 11
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP0 (0x1<<12)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP0_SIZE 12
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP1 (0x1<<13)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP1_SIZE 13
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP2 (0x1<<14)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP2_SIZE 14
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_DST_SIZE 15
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP0 (0x1<<16)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP0_SIZE 16
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP1 (0x1<<17)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP1_SIZE 17
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP2 (0x1<<18)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP2_SIZE 18
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID0 (0x1<<19)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID0_SIZE 19
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID1 (0x1<<20)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID1_SIZE 20
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID2 (0x1<<21)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID2_SIZE 21
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC3 (0x1<<22)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC3_SIZE 22
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IPV6_MLCST (0x1<<23)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IPV6_MLCST_SIZE 23
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC4 (0x1<<24)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC4_SIZE 24
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC5 (0x1<<25)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC5_SIZE 25
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE0 (0x1<<26)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE0_SIZE 26
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE1 (0x1<<27)
#define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE1_SIZE 27
#define NIG_REG_P1_TLLH_GLOBAL_ERROR_MASK 0x183a8UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define NIG_P1_TLLH_GLOBAL_ERROR_MASK_REG_P1_TLLH_MCP_ERROR_MASK (0x1<<0)
#define NIG_P1_TLLH_GLOBAL_ERROR_MASK_REG_P1_TLLH_MCP_ERROR_MASK_SIZE 0
#define NIG_P1_TLLH_GLOBAL_ERROR_MASK_REG_P1_TLLH_NTWK_ERROR_MASK (0x1<<1)
#define NIG_P1_TLLH_GLOBAL_ERROR_MASK_REG_P1_TLLH_NTWK_ERROR_MASK_SIZE 1
#define NIG_REG_P1_HBUF_MEM_RBC_ACCESS 0x183acUL //ACCESS:RW DataWidth:0x1 Description: Debug only. This bit is for selecting the RX management memory for register read/write access through ingress_mng*_fifo register space. Set to 1 to select the Host-to-BMC buffer (HBUF). Set to 0 to select the MCP RX buffer:w.
#define NIG_REG_P1_TLLH_FIFO_TM 0x183b0UL //ACCESS:RW DataWidth:0x2 Description: TM for TLLH FIFO
#define NIG_REG_P1_HBUF_TM 0x183b4UL //ACCESS:RW DataWidth:0x5 Description: TM for Host-to-BMC buffer.
#define NIG_REG_P1_TLLH_FRAME_CRACKER_SOFT_RST 0x183b8UL //ACCESS:RW DataWidth:0x1 Description: Soft reset bit for frame cracker - not expected to be used.
#define NIG_REG_NIG_PRTY_STS_0 0x183bcUL //ACCESS:R DataWidth:0x20 Description: Parity register #0 read
#define NIG_NIG_PRTY_STS_0_REG_PARITY (0x1<<0)
#define NIG_NIG_PRTY_STS_0_REG_PARITY_SIZE 0
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_EOP0_PARITY (0x1<<1)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_EOP0_PARITY_SIZE 1
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_EOP1_PARITY (0x1<<2)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_EOP1_PARITY_SIZE 2
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_EOP_LB_PARITY (0x1<<3)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_EOP_LB_PARITY_SIZE 3
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG0_PARITY0 (0x1<<4)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG0_PARITY0_SIZE 4
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG1_PARITY0 (0x1<<5)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG1_PARITY0_SIZE 5
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG0_PARITY1 (0x1<<6)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG0_PARITY1_SIZE 6
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG1_PARITY1 (0x1<<7)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG1_PARITY1_SIZE 7
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_BMAC0_PARITY (0x1<<8)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_BMAC0_PARITY_SIZE 8
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_BMAC1_PARITY (0x1<<9)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_BMAC1_PARITY_SIZE 9
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_EMAC0_RDDATA_PARITY (0x1<<10)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_EMAC0_RDDATA_PARITY_SIZE 10
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_EMAC1_RDDATA_PARITY (0x1<<11)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_EMAC1_RDDATA_PARITY_SIZE 11
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_LB_PBF_DELAY_PARITY (0x1<<12)
#define NIG_NIG_PRTY_STS_0_REG_INGRESS_LB_PBF_DELAY_PARITY_SIZE 12
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_MNG0_FIFO_PARITY (0x1<<13)
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_MNG0_FIFO_PARITY_SIZE 13
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_MNG1_FIFO_PARITY (0x1<<14)
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_MNG1_FIFO_PARITY_SIZE 14
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_DEBUG_FIFO_PARITY (0x1<<15)
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_DEBUG_FIFO_PARITY_SIZE 15
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_DELAY0_PARITY (0x1<<16)
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_DELAY0_PARITY_SIZE 16
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_DELAY1_PARITY (0x1<<17)
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_DELAY1_PARITY_SIZE 17
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_BMAC0_PARITY (0x1<<18)
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_BMAC0_PARITY_SIZE 18
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_BMAC1_PARITY (0x1<<19)
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_BMAC1_PARITY_SIZE 19
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_EMAC0_RDDATA_PARITY (0x1<<20)
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_EMAC0_RDDATA_PARITY_SIZE 20
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_EMAC1_RDDATA_PARITY (0x1<<21)
#define NIG_NIG_PRTY_STS_0_REG_EGRESS_EMAC1_RDDATA_PARITY_SIZE 21
#define NIG_NIG_PRTY_STS_0_REG_LLH0_FIFO_PARITY (0x1<<22)
#define NIG_NIG_PRTY_STS_0_REG_LLH0_FIFO_PARITY_SIZE 22
#define NIG_NIG_PRTY_STS_0_REG_LLH1_FIFO_PARITY (0x1<<23)
#define NIG_NIG_PRTY_STS_0_REG_LLH1_FIFO_PARITY_SIZE 23
#define NIG_NIG_PRTY_STS_0_REG_LLH0_ACPI_PARITY (0x1<<24)
#define NIG_NIG_PRTY_STS_0_REG_LLH0_ACPI_PARITY_SIZE 24
#define NIG_NIG_PRTY_STS_0_REG_LLH1_ACPI_PARITY (0x1<<25)
#define NIG_NIG_PRTY_STS_0_REG_LLH1_ACPI_PARITY_SIZE 25
#define NIG_NIG_PRTY_STS_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR (0x1<<26)
#define NIG_NIG_PRTY_STS_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR_SIZE 26
#define NIG_NIG_PRTY_STS_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR (0x1<<27)
#define NIG_NIG_PRTY_STS_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR_SIZE 27
#define NIG_NIG_PRTY_STS_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR (0x1<<28)
#define NIG_NIG_PRTY_STS_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR_SIZE 28
#define NIG_NIG_PRTY_STS_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR (0x1<<29)
#define NIG_NIG_PRTY_STS_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR_SIZE 29
#define NIG_NIG_PRTY_STS_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR (0x1<<30)
#define NIG_NIG_PRTY_STS_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR_SIZE 30
#define NIG_NIG_PRTY_STS_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR (0x1<<31)
#define NIG_NIG_PRTY_STS_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR_SIZE 31
#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0UL //ACCESS:RC DataWidth:0x20 Description: Parity register #0 read clear
#define NIG_NIG_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
#define NIG_NIG_PRTY_STS_CLR_0_REG_PARITY_SIZE 0
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EOP0_PARITY (0x1<<1)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EOP0_PARITY_SIZE 1
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EOP1_PARITY (0x1<<2)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EOP1_PARITY_SIZE 2
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EOP_LB_PARITY (0x1<<3)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EOP_LB_PARITY_SIZE 3
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG0_PARITY0 (0x1<<4)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG0_PARITY0_SIZE 4
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG1_PARITY0 (0x1<<5)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG1_PARITY0_SIZE 5
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG0_PARITY1 (0x1<<6)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG0_PARITY1_SIZE 6
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG1_PARITY1 (0x1<<7)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG1_PARITY1_SIZE 7
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_BMAC0_PARITY (0x1<<8)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_BMAC0_PARITY_SIZE 8
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_BMAC1_PARITY (0x1<<9)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_BMAC1_PARITY_SIZE 9
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EMAC0_RDDATA_PARITY (0x1<<10)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EMAC0_RDDATA_PARITY_SIZE 10
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EMAC1_RDDATA_PARITY (0x1<<11)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EMAC1_RDDATA_PARITY_SIZE 11
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_LB_PBF_DELAY_PARITY (0x1<<12)
#define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_LB_PBF_DELAY_PARITY_SIZE 12
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_MNG0_FIFO_PARITY (0x1<<13)
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_MNG0_FIFO_PARITY_SIZE 13
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_MNG1_FIFO_PARITY (0x1<<14)
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_MNG1_FIFO_PARITY_SIZE 14
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_DEBUG_FIFO_PARITY (0x1<<15)
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_DEBUG_FIFO_PARITY_SIZE 15
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_DELAY0_PARITY (0x1<<16)
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_DELAY0_PARITY_SIZE 16
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_DELAY1_PARITY (0x1<<17)
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_DELAY1_PARITY_SIZE 17
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_BMAC0_PARITY (0x1<<18)
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_BMAC0_PARITY_SIZE 18
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_BMAC1_PARITY (0x1<<19)
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_BMAC1_PARITY_SIZE 19
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_EMAC0_RDDATA_PARITY (0x1<<20)
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_EMAC0_RDDATA_PARITY_SIZE 20
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_EMAC1_RDDATA_PARITY (0x1<<21)
#define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_EMAC1_RDDATA_PARITY_SIZE 21
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FIFO_PARITY (0x1<<22)
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FIFO_PARITY_SIZE 22
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FIFO_PARITY (0x1<<23)
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FIFO_PARITY_SIZE 23
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_ACPI_PARITY (0x1<<24)
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_ACPI_PARITY_SIZE 24
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_ACPI_PARITY (0x1<<25)
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_ACPI_PARITY_SIZE 25
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR (0x1<<26)
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR_SIZE 26
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR (0x1<<27)
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR_SIZE 27
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR (0x1<<28)
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR_SIZE 28
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR (0x1<<29)
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR_SIZE 29
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR (0x1<<30)
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR_SIZE 30
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR (0x1<<31)
#define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR_SIZE 31
#define NIG_REG_NIG_PRTY_STS_WR_0 0x183c4UL //ACCESS:WR DataWidth:0x20 Description: Parity register #0 bit set or clear
#define NIG_NIG_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
#define NIG_NIG_PRTY_STS_WR_0_REG_PARITY_SIZE 0
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EOP0_PARITY (0x1<<1)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EOP0_PARITY_SIZE 1
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EOP1_PARITY (0x1<<2)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EOP1_PARITY_SIZE 2
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EOP_LB_PARITY (0x1<<3)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EOP_LB_PARITY_SIZE 3
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG0_PARITY0 (0x1<<4)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG0_PARITY0_SIZE 4
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG1_PARITY0 (0x1<<5)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG1_PARITY0_SIZE 5
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG0_PARITY1 (0x1<<6)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG0_PARITY1_SIZE 6
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG1_PARITY1 (0x1<<7)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG1_PARITY1_SIZE 7
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_BMAC0_PARITY (0x1<<8)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_BMAC0_PARITY_SIZE 8
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_BMAC1_PARITY (0x1<<9)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_BMAC1_PARITY_SIZE 9
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EMAC0_RDDATA_PARITY (0x1<<10)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EMAC0_RDDATA_PARITY_SIZE 10
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EMAC1_RDDATA_PARITY (0x1<<11)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EMAC1_RDDATA_PARITY_SIZE 11
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_LB_PBF_DELAY_PARITY (0x1<<12)
#define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_LB_PBF_DELAY_PARITY_SIZE 12
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_MNG0_FIFO_PARITY (0x1<<13)
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_MNG0_FIFO_PARITY_SIZE 13
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_MNG1_FIFO_PARITY (0x1<<14)
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_MNG1_FIFO_PARITY_SIZE 14
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_DEBUG_FIFO_PARITY (0x1<<15)
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_DEBUG_FIFO_PARITY_SIZE 15
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_DELAY0_PARITY (0x1<<16)
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_DELAY0_PARITY_SIZE 16
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_DELAY1_PARITY (0x1<<17)
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_DELAY1_PARITY_SIZE 17
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_BMAC0_PARITY (0x1<<18)
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_BMAC0_PARITY_SIZE 18
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_BMAC1_PARITY (0x1<<19)
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_BMAC1_PARITY_SIZE 19
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_EMAC0_RDDATA_PARITY (0x1<<20)
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_EMAC0_RDDATA_PARITY_SIZE 20
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_EMAC1_RDDATA_PARITY (0x1<<21)
#define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_EMAC1_RDDATA_PARITY_SIZE 21
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FIFO_PARITY (0x1<<22)
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FIFO_PARITY_SIZE 22
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FIFO_PARITY (0x1<<23)
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FIFO_PARITY_SIZE 23
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_ACPI_PARITY (0x1<<24)
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_ACPI_PARITY_SIZE 24
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_ACPI_PARITY (0x1<<25)
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_ACPI_PARITY_SIZE 25
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR (0x1<<26)
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR_SIZE 26
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR (0x1<<27)
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR_SIZE 27
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR (0x1<<28)
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR_SIZE 28
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR (0x1<<29)
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR_SIZE 29
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR (0x1<<30)
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR_SIZE 30
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR (0x1<<31)
#define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR_SIZE 31
#define NIG_REG_NIG_PRTY_MASK_0 0x183c8UL //ACCESS:RW DataWidth:0x20 Description: Parity mask register #0 read/write
#define NIG_NIG_PRTY_MASK_0_REG_PARITY (0x1<<0)
#define NIG_NIG_PRTY_MASK_0_REG_PARITY_SIZE 0
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EOP0_PARITY (0x1<<1)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EOP0_PARITY_SIZE 1
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EOP1_PARITY (0x1<<2)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EOP1_PARITY_SIZE 2
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EOP_LB_PARITY (0x1<<3)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EOP_LB_PARITY_SIZE 3
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG0_PARITY0 (0x1<<4)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG0_PARITY0_SIZE 4
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG1_PARITY0 (0x1<<5)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG1_PARITY0_SIZE 5
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG0_PARITY1 (0x1<<6)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG0_PARITY1_SIZE 6
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG1_PARITY1 (0x1<<7)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG1_PARITY1_SIZE 7
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_BMAC0_PARITY (0x1<<8)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_BMAC0_PARITY_SIZE 8
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_BMAC1_PARITY (0x1<<9)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_BMAC1_PARITY_SIZE 9
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EMAC0_RDDATA_PARITY (0x1<<10)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EMAC0_RDDATA_PARITY_SIZE 10
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EMAC1_RDDATA_PARITY (0x1<<11)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EMAC1_RDDATA_PARITY_SIZE 11
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_LB_PBF_DELAY_PARITY (0x1<<12)
#define NIG_NIG_PRTY_MASK_0_REG_INGRESS_LB_PBF_DELAY_PARITY_SIZE 12
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_MNG0_FIFO_PARITY (0x1<<13)
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_MNG0_FIFO_PARITY_SIZE 13
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_MNG1_FIFO_PARITY (0x1<<14)
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_MNG1_FIFO_PARITY_SIZE 14
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_DEBUG_FIFO_PARITY (0x1<<15)
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_DEBUG_FIFO_PARITY_SIZE 15
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_DELAY0_PARITY (0x1<<16)
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_DELAY0_PARITY_SIZE 16
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_DELAY1_PARITY (0x1<<17)
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_DELAY1_PARITY_SIZE 17
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_BMAC0_PARITY (0x1<<18)
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_BMAC0_PARITY_SIZE 18
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_BMAC1_PARITY (0x1<<19)
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_BMAC1_PARITY_SIZE 19
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_EMAC0_RDDATA_PARITY (0x1<<20)
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_EMAC0_RDDATA_PARITY_SIZE 20
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_EMAC1_RDDATA_PARITY (0x1<<21)
#define NIG_NIG_PRTY_MASK_0_REG_EGRESS_EMAC1_RDDATA_PARITY_SIZE 21
#define NIG_NIG_PRTY_MASK_0_REG_LLH0_FIFO_PARITY (0x1<<22)
#define NIG_NIG_PRTY_MASK_0_REG_LLH0_FIFO_PARITY_SIZE 22
#define NIG_NIG_PRTY_MASK_0_REG_LLH1_FIFO_PARITY (0x1<<23)
#define NIG_NIG_PRTY_MASK_0_REG_LLH1_FIFO_PARITY_SIZE 23
#define NIG_NIG_PRTY_MASK_0_REG_LLH0_ACPI_PARITY (0x1<<24)
#define NIG_NIG_PRTY_MASK_0_REG_LLH0_ACPI_PARITY_SIZE 24
#define NIG_NIG_PRTY_MASK_0_REG_LLH1_ACPI_PARITY (0x1<<25)
#define NIG_NIG_PRTY_MASK_0_REG_LLH1_ACPI_PARITY_SIZE 25
#define NIG_NIG_PRTY_MASK_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR (0x1<<26)
#define NIG_NIG_PRTY_MASK_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR_SIZE 26
#define NIG_NIG_PRTY_MASK_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR (0x1<<27)
#define NIG_NIG_PRTY_MASK_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR_SIZE 27
#define NIG_NIG_PRTY_MASK_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR (0x1<<28)
#define NIG_NIG_PRTY_MASK_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR_SIZE 28
#define NIG_NIG_PRTY_MASK_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR (0x1<<29)
#define NIG_NIG_PRTY_MASK_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR_SIZE 29
#define NIG_NIG_PRTY_MASK_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR (0x1<<30)
#define NIG_NIG_PRTY_MASK_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR_SIZE 30
#define NIG_NIG_PRTY_MASK_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR (0x1<<31)
#define NIG_NIG_PRTY_MASK_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR_SIZE 31
#define NIG_REG_NIG_PRTY_STS_1 0x183ccUL //ACCESS:R DataWidth:0x10 Description: Parity register #1 read
#define NIG_NIG_PRTY_STS_1_REG_P0_TX_MNG_HOST_FIFO_PARITY (0x1<<0)
#define NIG_NIG_PRTY_STS_1_REG_P0_TX_MNG_HOST_FIFO_PARITY_SIZE 0
#define NIG_NIG_PRTY_STS_1_REG_P1_TX_MNG_HOST_FIFO_PARITY (0x1<<1)
#define NIG_NIG_PRTY_STS_1_REG_P1_TX_MNG_HOST_FIFO_PARITY_SIZE 1
#define NIG_NIG_PRTY_STS_1_REG_P0_HBUF_PARITY0 (0x1<<2)
#define NIG_NIG_PRTY_STS_1_REG_P0_HBUF_PARITY0_SIZE 2
#define NIG_NIG_PRTY_STS_1_REG_P0_HBUF_PARITY1 (0x1<<3)
#define NIG_NIG_PRTY_STS_1_REG_P0_HBUF_PARITY1_SIZE 3
#define NIG_NIG_PRTY_STS_1_REG_P1_HBUF_PARITY0 (0x1<<4)
#define NIG_NIG_PRTY_STS_1_REG_P1_HBUF_PARITY0_SIZE 4
#define NIG_NIG_PRTY_STS_1_REG_P1_HBUF_PARITY1 (0x1<<5)
#define NIG_NIG_PRTY_STS_1_REG_P1_HBUF_PARITY1_SIZE 5
#define NIG_NIG_PRTY_STS_1_REG_P0_TLLH_FIFO_PARITY (0x1<<6)
#define NIG_NIG_PRTY_STS_1_REG_P0_TLLH_FIFO_PARITY_SIZE 6
#define NIG_NIG_PRTY_STS_1_REG_P1_TLLH_FIFO_PARITY (0x1<<7)
#define NIG_NIG_PRTY_STS_1_REG_P1_TLLH_FIFO_PARITY_SIZE 7
#define NIG_NIG_PRTY_STS_1_REG_P0_RX_MACFIFO_PARITY (0x1<<8)
#define NIG_NIG_PRTY_STS_1_REG_P0_RX_MACFIFO_PARITY_SIZE 8
#define NIG_NIG_PRTY_STS_1_REG_P1_RX_MACFIFO_PARITY (0x1<<9)
#define NIG_NIG_PRTY_STS_1_REG_P1_RX_MACFIFO_PARITY_SIZE 9
#define NIG_NIG_PRTY_STS_1_REG_P0_TX_MACFIFO_PARITY (0x1<<10)
#define NIG_NIG_PRTY_STS_1_REG_P0_TX_MACFIFO_PARITY_SIZE 10
#define NIG_NIG_PRTY_STS_1_REG_P1_TX_MACFIFO_PARITY (0x1<<11)
#define NIG_NIG_PRTY_STS_1_REG_P1_TX_MACFIFO_PARITY_SIZE 11
#define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY2_PARITY (0x1<<12)
#define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY2_PARITY_SIZE 12
#define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY3_PARITY (0x1<<13)
#define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY3_PARITY_SIZE 13
#define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY4_PARITY (0x1<<14)
#define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY4_PARITY_SIZE 14
#define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY5_PARITY (0x1<<15)
#define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY5_PARITY_SIZE 15
#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0UL //ACCESS:RC DataWidth:0x10 Description: Parity register #1 read clear
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_TX_MNG_HOST_FIFO_PARITY (0x1<<0)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_TX_MNG_HOST_FIFO_PARITY_SIZE 0
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_TX_MNG_HOST_FIFO_PARITY (0x1<<1)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_TX_MNG_HOST_FIFO_PARITY_SIZE 1
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_HBUF_PARITY0 (0x1<<2)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_HBUF_PARITY0_SIZE 2
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_HBUF_PARITY1 (0x1<<3)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_HBUF_PARITY1_SIZE 3
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_HBUF_PARITY0 (0x1<<4)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_HBUF_PARITY0_SIZE 4
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_HBUF_PARITY1 (0x1<<5)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_HBUF_PARITY1_SIZE 5
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_TLLH_FIFO_PARITY (0x1<<6)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_TLLH_FIFO_PARITY_SIZE 6
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_TLLH_FIFO_PARITY (0x1<<7)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_TLLH_FIFO_PARITY_SIZE 7
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_RX_MACFIFO_PARITY (0x1<<8)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_RX_MACFIFO_PARITY_SIZE 8
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_RX_MACFIFO_PARITY (0x1<<9)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_RX_MACFIFO_PARITY_SIZE 9
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_TX_MACFIFO_PARITY (0x1<<10)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P0_TX_MACFIFO_PARITY_SIZE 10
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_TX_MACFIFO_PARITY (0x1<<11)
#define NIG_NIG_PRTY_STS_CLR_1_REG_P1_TX_MACFIFO_PARITY_SIZE 11
#define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY2_PARITY (0x1<<12)
#define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY2_PARITY_SIZE 12
#define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY3_PARITY (0x1<<13)
#define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY3_PARITY_SIZE 13
#define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY4_PARITY (0x1<<14)
#define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY4_PARITY_SIZE 14
#define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY5_PARITY (0x1<<15)
#define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY5_PARITY_SIZE 15
#define NIG_REG_NIG_PRTY_STS_WR_1 0x183d4UL //ACCESS:WR DataWidth:0x10 Description: Parity register #1 bit set or clear
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_TX_MNG_HOST_FIFO_PARITY (0x1<<0)
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_TX_MNG_HOST_FIFO_PARITY_SIZE 0
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_TX_MNG_HOST_FIFO_PARITY (0x1<<1)
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_TX_MNG_HOST_FIFO_PARITY_SIZE 1
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_HBUF_PARITY0 (0x1<<2)
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_HBUF_PARITY0_SIZE 2
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_HBUF_PARITY1 (0x1<<3)
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_HBUF_PARITY1_SIZE 3
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_HBUF_PARITY0 (0x1<<4)
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_HBUF_PARITY0_SIZE 4
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_HBUF_PARITY1 (0x1<<5)
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_HBUF_PARITY1_SIZE 5
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_TLLH_FIFO_PARITY (0x1<<6)
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_TLLH_FIFO_PARITY_SIZE 6
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_TLLH_FIFO_PARITY (0x1<<7)
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_TLLH_FIFO_PARITY_SIZE 7
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_RX_MACFIFO_PARITY (0x1<<8)
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_RX_MACFIFO_PARITY_SIZE 8
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_RX_MACFIFO_PARITY (0x1<<9)
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_RX_MACFIFO_PARITY_SIZE 9
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_TX_MACFIFO_PARITY (0x1<<10)
#define NIG_NIG_PRTY_STS_WR_1_REG_P0_TX_MACFIFO_PARITY_SIZE 10
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_TX_MACFIFO_PARITY (0x1<<11)
#define NIG_NIG_PRTY_STS_WR_1_REG_P1_TX_MACFIFO_PARITY_SIZE 11
#define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY2_PARITY (0x1<<12)
#define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY2_PARITY_SIZE 12
#define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY3_PARITY (0x1<<13)
#define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY3_PARITY_SIZE 13
#define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY4_PARITY (0x1<<14)
#define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY4_PARITY_SIZE 14
#define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY5_PARITY (0x1<<15)
#define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY5_PARITY_SIZE 15
#define NIG_REG_NIG_PRTY_MASK_1 0x183d8UL //ACCESS:RW DataWidth:0x10 Description: Parity mask register #1 read/write
#define NIG_NIG_PRTY_MASK_1_REG_P0_TX_MNG_HOST_FIFO_PARITY (0x1<<0)
#define NIG_NIG_PRTY_MASK_1_REG_P0_TX_MNG_HOST_FIFO_PARITY_SIZE 0
#define NIG_NIG_PRTY_MASK_1_REG_P1_TX_MNG_HOST_FIFO_PARITY (0x1<<1)
#define NIG_NIG_PRTY_MASK_1_REG_P1_TX_MNG_HOST_FIFO_PARITY_SIZE 1
#define NIG_NIG_PRTY_MASK_1_REG_P0_HBUF_PARITY0 (0x1<<2)
#define NIG_NIG_PRTY_MASK_1_REG_P0_HBUF_PARITY0_SIZE 2
#define NIG_NIG_PRTY_MASK_1_REG_P0_HBUF_PARITY1 (0x1<<3)
#define NIG_NIG_PRTY_MASK_1_REG_P0_HBUF_PARITY1_SIZE 3
#define NIG_NIG_PRTY_MASK_1_REG_P1_HBUF_PARITY0 (0x1<<4)
#define NIG_NIG_PRTY_MASK_1_REG_P1_HBUF_PARITY0_SIZE 4
#define NIG_NIG_PRTY_MASK_1_REG_P1_HBUF_PARITY1 (0x1<<5)
#define NIG_NIG_PRTY_MASK_1_REG_P1_HBUF_PARITY1_SIZE 5
#define NIG_NIG_PRTY_MASK_1_REG_P0_TLLH_FIFO_PARITY (0x1<<6)
#define NIG_NIG_PRTY_MASK_1_REG_P0_TLLH_FIFO_PARITY_SIZE 6
#define NIG_NIG_PRTY_MASK_1_REG_P1_TLLH_FIFO_PARITY (0x1<<7)
#define NIG_NIG_PRTY_MASK_1_REG_P1_TLLH_FIFO_PARITY_SIZE 7
#define NIG_NIG_PRTY_MASK_1_REG_P0_RX_MACFIFO_PARITY (0x1<<8)
#define NIG_NIG_PRTY_MASK_1_REG_P0_RX_MACFIFO_PARITY_SIZE 8
#define NIG_NIG_PRTY_MASK_1_REG_P1_RX_MACFIFO_PARITY (0x1<<9)
#define NIG_NIG_PRTY_MASK_1_REG_P1_RX_MACFIFO_PARITY_SIZE 9
#define NIG_NIG_PRTY_MASK_1_REG_P0_TX_MACFIFO_PARITY (0x1<<10)
#define NIG_NIG_PRTY_MASK_1_REG_P0_TX_MACFIFO_PARITY_SIZE 10
#define NIG_NIG_PRTY_MASK_1_REG_P1_TX_MACFIFO_PARITY (0x1<<11)
#define NIG_NIG_PRTY_MASK_1_REG_P1_TX_MACFIFO_PARITY_SIZE 11
#define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY2_PARITY (0x1<<12)
#define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY2_PARITY_SIZE 12
#define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY3_PARITY (0x1<<13)
#define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY3_PARITY_SIZE 13
#define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY4_PARITY (0x1<<14)
#define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY4_PARITY_SIZE 14
#define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY5_PARITY (0x1<<15)
#define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY5_PARITY_SIZE 15
#define NIG_REG_P0_ACPI_MF_GLOBAL_EN 0x18500UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable ACPI pattern matching in multi-function mode even when the per-function outer VLAN matching fails.
#define NIG_REG_P0_LLH_CLS_TYPE_IVLAN 0x18504UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable VNIC classification based on Inner VLAN instead of the default Outer VLAN.
#define NIG_REG_P0_LLH_CLS_TYPE_PERFUNC_EN 0x18508UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the use of separate classification type configuration for each function. Set to 0 to use registers p*_llh_cls_type_ivlan and llh*_cls_type as the global classification type registers. Set to 1 to use the p*_llh_cls_type_func* registers as the classification type registers - one register for each function.
#define NIG_REG_P0_LLH_CLS_TYPE_FUNC0 0x1850cUL //ACCESS:RW DataWidth:0x4 Description: This register selects the classification type for function 0. Bits 1:0 specify the classication type - similar to llh*_cls_type. Bit 2 specifies whether the classification is based on Inner VLAN or Outer VLAN - similar to p*_llh_cls_type_ivlan. Bit 3 specifies whether the classification is based on VNTAG - similar to p*_llh_cls_type_vntag register. This register is used only when p*_llh_cls_type_perfunc_en is set.
#define NIG_REG_P0_LLH_CLS_TYPE_FUNC1 0x18510UL //ACCESS:RW DataWidth:0x4 Description: This register selects the classification type for function 1. Bits 1:0 specify the classication type - similar to llh*_cls_type. Bit 2 specifies whether the classification is based on Inner VLAN or Outer VLAN - similar to p*_llh_cls_type_ivlan. Bit 3 specifies whether the classification is based on VNTAG - similar to p*_llh_cls_type_vntag register. This register is used only when p*_llh_cls_type_perfunc_en is set.
#define NIG_REG_P0_LLH_CLS_TYPE_FUNC2 0x18514UL //ACCESS:RW DataWidth:0x4 Description: This register selects the classification type for function 2. Bits 1:0 specify the classication type - similar to llh*_cls_type. Bit 2 specifies whether the classification is based on Inner VLAN or Outer VLAN - similar to p*_llh_cls_type_ivlan. Bit 3 specifies whether the classification is based on VNTAG - similar to p*_llh_cls_type_vntag register. This register is used only when p*_llh_cls_type_perfunc_en is set.
#define NIG_REG_P0_LLH_CLS_TYPE_FUNC3 0x18518UL //ACCESS:RW DataWidth:0x4 Description: This register selects the classification type for function 3. Bits 1:0 specify the classication type - similar to llh*_cls_type. Bit 2 specifies whether the classification is based on Inner VLAN or Outer VLAN - similar to p*_llh_cls_type_ivlan. Bit 3 specifies whether the classification is based on VNTAG - similar to p*_llh_cls_type_vntag register. This register is used only when p*_llh_cls_type_perfunc_en is set.
#define NIG_REG_P1_ACPI_MF_GLOBAL_EN 0x1851cUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable ACPI pattern matching in multi-function mode even when the per-function outer VLAN matching fails.
#define NIG_REG_P1_LLH_CLS_TYPE_IVLAN 0x18520UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable VNIC classification based on Inner VLAN instead of the default Outer VLAN.
#define NIG_REG_P1_LLH_CLS_TYPE_PERFUNC_EN 0x18524UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the use separate classification type configuration for each function. Set to 0 to use registers p*_llh_cls_type_ivlan and llh*_cls_type as the global classification type registers. Set to 1 to use the p*_llh_cls_type_func* registers as the classification type registers - one register for each function.
#define NIG_REG_P1_LLH_CLS_TYPE_FUNC0 0x18528UL //ACCESS:RW DataWidth:0x4 Description: This register selects the classification type for function 0. Bits 1:0 specify the classication type - similar to llh*_cls_type. Bit 2 specifies whether the classification is based on Inner VLAN or Outer VLAN - similar to p*_llh_cls_type_ivlan. Bit 3 specifies whether the classification is based on VNTAG - similar to p*_llh_cls_type_vntag register. This register is used only when p*_llh_cls_type_perfunc_en is set.
#define NIG_REG_P1_LLH_CLS_TYPE_FUNC1 0x1852cUL //ACCESS:RW DataWidth:0x4 Description: This register selects the classification type for function 1. Bits 1:0 specify the classication type - similar to llh*_cls_type. Bit 2 specifies whether the classification is based on Inner VLAN or Outer VLAN - similar to p*_llh_cls_type_ivlan. Bit 3 specifies whether the classification is based on VNTAG - similar to p*_llh_cls_type_vntag register. This register is used only when p*_llh_cls_type_perfunc_en is set.
#define NIG_REG_P1_LLH_CLS_TYPE_FUNC2 0x18530UL //ACCESS:RW DataWidth:0x4 Description: This register selects the classification type for function 2. Bits 1:0 specify the classication type - similar to llh*_cls_type. Bit 2 specifies whether the classification is based on Inner VLAN or Outer VLAN - similar to p*_llh_cls_type_ivlan. Bit 3 specifies whether the classification is based on VNTAG - similar to p*_llh_cls_type_vntag register. This register is used only when p*_llh_cls_type_perfunc_en is set.
#define NIG_REG_P1_LLH_CLS_TYPE_FUNC3 0x18534UL //ACCESS:RW DataWidth:0x4 Description: This register selects the classification type for function 3. Bits 1:0 specify the classication type - similar to llh*_cls_type. Bit 2 specifies whether the classification is based on Inner VLAN or Outer VLAN - similar to p*_llh_cls_type_ivlan. Bit 3 specifies whether the classification is based on VNTAG - similar to p*_llh_cls_type_vntag register. This register is used only when p*_llh_cls_type_perfunc_en is set.
#define NIG_REG_BRB_LB_CLS_FAIL_SEL 0x18538UL //ACCESS:RW DataWidth:0x1 Description: This bit selects the value for the BRB LB 'classification failed' signal. Clear this bit to select the hard-wired zero value. Set this bit to take the value from bit 11 of the sideband_info[15:0] signal.
#define NIG_REG_P0_LED_20G 0x185a8UL //ACCESS:RW DataWidth:0x1 Description: This bit controls the 20G LED output to CNIG.
#define NIG_REG_P0_MAC_IN_EN 0x185acUL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX MAC interface.
#define NIG_REG_P0_MAC_OUT_EN 0x185b0UL //ACCESS:RW DataWidth:0x1 Description: Output enable for TX MAC interface
#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4UL //ACCESS:RW DataWidth:0x1 Description: Output enable for TX PAUSE signal to the MAC.
#define NIG_REG_P0_MAC_RSV_ERR_MASK 0x185b8UL //ACCESS:RW DataWidth:0x14 Description: This register directly controls the MAC input mask to enable/disable error conditions from triggering RX error output.
#define NIG_REG_P0_TX_MACFIFO_ALM_FULL_THR 0x185bcUL //ACCESS:RW DataWidth:0x4 Description: Almost full threshold for TX MAC FIFO.
#define NIG_REG_P1_MAC_IN_EN 0x185c0UL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX MAC interface.
#define NIG_REG_P1_MAC_OUT_EN 0x185c4UL //ACCESS:RW DataWidth:0x1 Description: Output enable for TX MAC interface
#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8UL //ACCESS:RW DataWidth:0x1 Description: Output enable for TX PAUSE signal to the MAC.
#define NIG_REG_P1_MAC_RSV_ERR_MASK 0x185ccUL //ACCESS:RW DataWidth:0x14 Description: This register directly controls the MAC input mask to enable/disable error conditions from triggering RX error output.
#define NIG_REG_P1_TX_MACFIFO_ALM_FULL_THR 0x185d0UL //ACCESS:RW DataWidth:0x4 Description: Almost full threshold for TX MAC FIFO.
#define NIG_REG_P0_HIGIG_HDR_SIZE 0x185fcUL //ACCESS:RW DataWidth:0x4 Description: Specify the size of the HiGig header. 0 - HiGig mode is disabled. 3 - HiGig header of 12 bytes is present. 4 - HiGig header of 16 bytes is present. All other values are invalid.
#define NIG_REG_P0_TXUMP_W_HIGIG 0x18600UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to 1 when HiGig mode is enabled (p*_higig_hdr_size > 0). Clear this bit to 0 when HiGig mode is disabled (p*_higig_hdr_size == 0).
#define NIG_REG_P1_HIGIG_HDR_SIZE 0x18604UL //ACCESS:RW DataWidth:0x4 Description: Specify the size of the HiGig header. 0 - HiGig mode is disabled. 3 - HiGig header of 12 bytes is present. 4 - HiGig header of 16 bytes is present. All other values are invalid.
#define NIG_REG_P1_TXUMP_W_HIGIG 0x18608UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to 1 when HiGig mode is enabled (p*_higig_hdr_size > 0). Clear this bit to 0 when HiGig mode is disabled (p*_higig_hdr_size == 0).
#define NIG_REG_LLH1_MF_MODE 0x18614UL //ACCESS:RW DataWidth:0x1 Description: When this bit is set; the LLH will classify the packet before sending it to the BRB or calculating WoL on it. This bit controls port 1 only. The legacy llh_multi_function_mode bit controls port 0.
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680UL //ACCESS:RW DataWidth:0x20 Description: Specify the client number to be assigned to each priority of the strict priority arbiter. This register specifies bits 31:0 of the 36-bit value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 client; bits [35-32] are for priority 8 client. The clients are assigned the following IDs: 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is set to 0x345678021. This is a new register (with 2_) added in E3 B0 to accommodate the 9 input clients to ETS arbiter.
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684UL //ACCESS:RW DataWidth:0x4 Description: Specify the client number to be assigned to each priority of the strict priority arbiter. This register specifies bits 35:32 of the 36-bit value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 client; bits [35-32] are for priority 8 client. The clients are assigned the following IDs: 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is set to 0x345678021. This is a new register (with 2_) added in E3 B0 to accommodate the 9 input clients to ETS arbiter.
#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688UL //ACCESS:RW DataWidth:0x20 Description: Specify which of the credit registers the client is to be mapped to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are for client 0; bits [35:32] are for client 8. For clients that are not subject to WFQ credit blocking - their specifications here are not used. This is a new register (with 2_) added in E3 B0 to accommodate the 9 input clients to ETS arbiter. The reset default is set for management and debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to use credit registers 0-5 respectively (0x543210876). Note that credit registers can not be shared between clients.
#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868cUL //ACCESS:RW DataWidth:0x4 Description: Specify which of the credit registers the client is to be mapped to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are for client 0; bits [35:32] are for client 8. For clients that are not subject to WFQ credit blocking - their specifications here are not used. This is a new register (with 2_) added in E3 B0 to accommodate the 9 input clients to ETS arbiter. The reset default is set for management and debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to use credit registers 0-5 respectively (0x543210876). Note that credit registers can not be shared between clients.
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 5 when it is time to increment.
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 6 when it is time to increment.
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 7 when it is time to increment.
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869cUL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 8 when it is time to increment.
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 5 is allowed to reach.
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 6 is allowed to reach.
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 7 is allowed to reach.
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186acUL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 8 is allowed to reach.
#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0UL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to COS 2. A priority is mapped to COS 2 when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS.
#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4UL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to COS 3. A priority is mapped to COS 3 when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS.
#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8UL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to COS 4. A priority is mapped to COS 4 when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS.
#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bcUL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to COS 5. A priority is mapped to COS 5 when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS.
#define NIG_REG_P0_RX_COS2_TIMER_WRAP 0x186c0UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 2 timer to start over when it reaches the configured maximum time.
#define NIG_REG_P0_RX_COS3_TIMER_WRAP 0x186c4UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 3 timer to start over when it reaches the configured maximum time.
#define NIG_REG_P0_RX_COS4_TIMER_WRAP 0x186c8UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 4 timer to start over when it reaches the configured maximum time.
#define NIG_REG_P0_RX_COS5_TIMER_WRAP 0x186ccUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 5 timer to start over when it reaches the configured maximum time.
#define NIG_REG_P0_RX_COS2_TIMER_MAX 0x186d0UL //ACCESS:RW DataWidth:0x20 Description: This register specifies the period of time (in term of the number of core clocks) RX COS2 is paused before asserting rx_cos2_timer_max_int interrupt.
#define NIG_REG_P0_RX_COS3_TIMER_MAX 0x186d4UL //ACCESS:RW DataWidth:0x20 Description: This register specifies the period of time (in term of the number of core clocks) RX COS3 is paused before asserting rx_cos3_timer_max_int interrupt.
#define NIG_REG_P0_RX_COS4_TIMER_MAX 0x186d8UL //ACCESS:RW DataWidth:0x20 Description: This register specifies the period of time (in term of the number of core clocks) RX COS4 is paused before asserting rx_cos4_timer_max_int interrupt.
#define NIG_REG_P0_RX_COS5_TIMER_MAX 0x186dcUL //ACCESS:RW DataWidth:0x20 Description: This register specifies the period of time (in term of the number of core clocks) RX COS5 is paused before asserting rx_cos5_timer_max_int interrupt.
#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0UL //ACCESS:RW DataWidth:0x20 Description: Specify the client number to be assigned to each priority of the strict priority arbiter. This register specifies bits 31:0 of the 36-bit value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 client; bits [35-32] are for priority 8 client. The clients are assigned the following IDs: 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is set to 0x345678021. This is a new register (with 2_) added in E3 B0 to accommodate the 9 input clients to ETS arbiter. Note that this register is the same as the one for port 0, except that port 1 only has COS 0-2 traffic. There is no traffic for COS 3-5 of port 1.
#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4UL //ACCESS:RW DataWidth:0x4 Description: Specify the client number to be assigned to each priority of the strict priority arbiter. This register specifies bits 35:32 of the 36-bit value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 client; bits [35-32] are for priority 8 client. The clients are assigned the following IDs: 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is set to 0x345678021. This is a new register (with 2_) added in E3 B0 to accommodate the 9 input clients to ETS arbiter. Note that this register is the same as the one for port 0, except that port 1 only has COS 0-2 traffic. There is no traffic for COS 3-5 of port 1.
#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8UL //ACCESS:RW DataWidth:0x20 Description: Specify which of the credit registers the client is to be mapped to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are for client 0; bits [35:32] are for client 8. For clients that are not subject to WFQ credit blocking - their specifications here are not used. This is a new register (with 2_) added in E3 B0 to accommodate the 9 input clients to ETS arbiter. The reset default is set for management and debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to use credit registers 0-5 respectively (0x543210876). Note that credit registers can not be shared between clients. Note also that there are only COS0-2 in port 1- there is a total of 6 clients in port 1. Only credit registers 0-5 are valid. This register should be configured appropriately before enabling WFQ.
#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ecUL //ACCESS:RW DataWidth:0x4 Description: Specify which of the credit registers the client is to be mapped to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are for client 0; bits [35:32] are for client 8. For clients that are not subject to WFQ credit blocking - their specifications here are not used. This is a new register (with 2_) added in E3 B0 to accommodate the 9 input clients to ETS arbiter. The reset default is set for management and debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to use credit registers 0-5 respectively (0x543210876). Note that credit registers can not be shared between clients. Note also that there are only COS0-2 in port 1- there is a total of 6 clients in port 1. Only credit registers 0-5 are valid. This register should be configured appropriately before enabling WFQ.
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0UL //ACCESS:RW DataWidth:0x20 Description: Specify the weight (in bytes) to be added to credit register 5 when it is time to increment.
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4UL //ACCESS:RW DataWidth:0x20 Description: Specify the upper bound that credit register 5 is allowed to reach.
#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8UL //ACCESS:RW DataWidth:0x10 Description: Bit-map indicating which SAFC/PFC priorities to map to COS 2. A priority is mapped to COS 2 when the corresponding mask bit is 1. More than one bit may be set; allowing multiple priorities to be mapped to one COS.
#define NIG_REG_P1_RX_COS2_TIMER_WRAP 0x186fcUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 2 timer to start over when it reaches the configured maximum time.
#define NIG_REG_P1_RX_COS2_TIMER_MAX 0x18700UL //ACCESS:RW DataWidth:0x20 Description: This register specifies the period of time (in term of the number of core clocks) RX COS2 is paused before asserting rx_cos2_timer_max_int interrupt.
#define NIG_REG_EGRESS_PBF2TO5_IN_EN 0x18704UL //ACCESS:RW DataWidth:0x4 Description: Input enable for TX PBF interfaces 2 to 5. Bit 0 is for interface 2. Bit 3 is for interface 5.
#define NIG_REG_P0_LLH_CLS_TYPE_VNTAG 0x18708UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable VNIC classification based on VNTAG. Note that classifications based on VLAN and MAC addresses are disabled when VNTAG classification is enabled.
#define NIG_REG_P1_LLH_CLS_TYPE_VNTAG 0x1870cUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable VNIC classification based on VNTAG. Note that classifications based on VLAN and MAC addresses are disabled when VNTAG classification is enabled.
#define NIG_REG_P0_LLH_DST_VIF0 0x18710UL //ACCESS:RW DataWidth:0xe Description: Destination VIF to be compared with the value in VNTAG header (for MCP filter rule C).
#define NIG_REG_P0_LLH_DST_VIF1 0x18714UL //ACCESS:RW DataWidth:0xe Description: Destination VIF to be compared with the value in VNTAG header (for MCP filter rule C).
#define NIG_REG_P0_LLH_MCP_MASK_C_DST_VIF0 0x18718UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with VNTAG matching p*_llh_dst_vif0 to be forwarded to MCP.
#define NIG_REG_P0_LLH_MCP_MASK_C_DST_VIF1 0x1871cUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with VNTAG matching p*_llh_dst_vif1 to be forwarded to MCP.
#define NIG_REG_P1_LLH_DST_VIF0 0x18720UL //ACCESS:RW DataWidth:0xe Description: Destination VIF to be compared with the value in VNTAG header (for MCP filter rule C).
#define NIG_REG_P1_LLH_DST_VIF1 0x18724UL //ACCESS:RW DataWidth:0xe Description: Destination VIF to be compared with the value in VNTAG header (for MCP filter rule C).
#define NIG_REG_P1_LLH_MCP_MASK_C_DST_VIF0 0x18728UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with VNTAG matching p*_llh_dst_vif0 to be forwarded to MCP.
#define NIG_REG_P1_LLH_MCP_MASK_C_DST_VIF1 0x1872cUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with VNTAG matching p*_llh_dst_vif1 to be forwarded to MCP.
#define NIG_REG_P0_PTP_EN 0x18788UL //ACCESS:RW DataWidth:0x6 Description: Enable for TimeSync feature. Bits [2:0] are for RX side. Bits [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables V1 frame format in timesync event detection on RX side. Bit 2 enables V2 frame format in timesync event detection on RX side. Bit 3 enables TimeSync on TX side. Bit 4 enables V1 frame format in timesync event detection on TX side. Bit 5 enables V2 frame format in timesync event detection on TX side. Note that for HW to detect PTP packet and extract data from the packet, at least one of the version bits of that traffic direction has to be enabled.
#define NIG_REG_P0_LLH_PTP_ETHERTYPE_1 0x1879cUL //ACCESS:RW DataWidth:0x10 Description: MAC Ethertype 1 for PTP packet detection. Ethertype 0 is fixed at 0x88F7. This register defaults to 0x88f7.
#define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a0UL //ACCESS:RW DataWidth:0xb Description: Mask register for the various parameters used in determining PTP packet presence. Set each bit to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable MAC DA 2. The reset default is set to mask out all parameters.
#define NIG_REG_P0_LLH_PTP_RULE_MASK 0x187a4UL //ACCESS:RW DataWidth:0xe Description: Mask regiser for the rules used in detecting PTP packets. Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset default is to mask out all of the rules. Note that rules 0-3 are for IPv4 packets only and require that the packet is IPv4 for the rules to match. Note that rules 4-7 are for IPv6 packets only and require that the packet is IPv6 for the rules to match.
#define NIG_REG_P0_LLH_PTP_TO_MCP 0x187a8UL //ACCESS:RW DataWidth:0x1 Description: Set to 1 to enable PTP packets to be forwarded to MCP.
#define NIG_REG_P0_LLH_PTP_TO_HOST 0x187acUL //ACCESS:RW DataWidth:0x1 Description: Set to 1 to enable PTP packets to be forwarded to the host.
#define NIG_REG_P1_PTP_EN 0x187b0UL //ACCESS:RW DataWidth:0x6 Description: Enable for TimeSync feature. Bits [2:0] are for RX side. Bits [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables V1 frame format in timesync event detection on RX side. Bit 2 enables V2 frame format in timesync event detection on RX side. Bit 3 enables TimeSync on TX side. Bit 4 enables V1 frame format in timesync event detection on TX side. Bit 5 enables V2 frame format in timesync event detection on TX side. Note that for HW to detect PTP packet and extract data from the packet, at least one of the version bits of that traffic direction has to be enabled.
#define NIG_REG_P1_LLH_PTP_ETHERTYPE_1 0x187c4UL //ACCESS:RW DataWidth:0x10 Description: MAC Ethertype 1 for PTP packet detection. Ethertype 0 is fixed at 0x88F7. This register defaults to 0x88f7.
#define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c8UL //ACCESS:RW DataWidth:0xb Description: Mask register for the various parameters used in determining PTP packet presence. Set each bit to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable MAC DA 2. The reset default is set to mask out all parameters.
#define NIG_REG_P1_LLH_PTP_RULE_MASK 0x187ccUL //ACCESS:RW DataWidth:0xe Description: Mask regiser for the rules used in detecting PTP packets. Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset default is to mask out all of the rules. Note that rules 0-3 are for IPv4 packets only and require that the packet is IPv4 for the rules to match. Note that rules 4-7 are for IPv6 packets only and require that the packet is IPv6 for the rules to match.
#define NIG_REG_P1_LLH_PTP_TO_MCP 0x187d0UL //ACCESS:RW DataWidth:0x1 Description: Set to 1 to enable PTP packets to be forwarded to MCP.
#define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d4UL //ACCESS:RW DataWidth:0x1 Description: Set to 1 to enable PTP packets to be forwarded to the host.
#define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f0UL //ACCESS:RW DataWidth:0xb Description: Mask register for the various parameters used in determining PTP packet presence. Set each bit to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable MAC DA 2. The reset default is set to mask out all parameters.
#define NIG_REG_P0_TLLH_PTP_RULE_MASK 0x187f4UL //ACCESS:RW DataWidth:0xe Description: Mask regiser for the rules used in detecting PTP packets. Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset default is to mask out all of the rules.
#define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f8UL //ACCESS:RW DataWidth:0xb Description: Mask register for the various parameters used in determining PTP packet presence. Set each bit to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable MAC DA 2. The reset default is set to mask out all parameters.
#define NIG_REG_P1_TLLH_PTP_RULE_MASK 0x187fcUL //ACCESS:RW DataWidth:0xe Description: Mask regiser for the rules used in detecting PTP packets. Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset default is to mask out all of the rules.
#define NIG_REG_P0_TX_TAG_INSERT_MODE 0x18a18UL //ACCESS:RW DataWidth:0x2 Description: Set this field to select the tag insertion mode for TX management traffic to be sent to the network. A value of 1 selects the 4-byte insertion mode. A value of 2 selects the 6-byte insertion mode. A value of 3 selects the 10-byte insertion mode. Set this register to 0 to disable tag insertion.
#define NIG_REG_P0_TX_4BYTE_TAG 0x18a1cUL //ACCESS:RW DataWidth:0x20 Description: 4-byte tag for used in TX tag insertion for management traffic from the UMP interface.
#define NIG_REG_P0_TX_6BYTE_TAG_4LSB 0x18a20UL //ACCESS:RW DataWidth:0x20 Description: 6-byte tag for used in TX tag insertion for management traffic from the UMP interface. This register holds the lower 4 bytes of the 6-byte tag.
#define NIG_REG_P0_TX_6BYTE_TAG_2MSB 0x18a24UL //ACCESS:RW DataWidth:0x10 Description: 6-byte tag for used in TX tag insertion for management traffic from the UMP interface. This register holds the upper 2 bytes of the 6-byte tag.
#define NIG_REG_P1_TX_TAG_INSERT_MODE 0x18a28UL //ACCESS:RW DataWidth:0x2 Description: Set this field to select the tag insertion mode for TX management traffic to be sent to the network. A value of 1 selects the 4-byte insertion mode. A value of 2 selects the 6-byte insertion mode. A value of 3 selects the 10-byte insertion mode. Set this register to 0 to disable tag insertion.
#define NIG_REG_P1_TX_4BYTE_TAG 0x18a2cUL //ACCESS:RW DataWidth:0x20 Description: 4-byte tag for used in TX tag insertion for management traffic from the UMP interface.
#define NIG_REG_P1_TX_6BYTE_TAG_4LSB 0x18a30UL //ACCESS:RW DataWidth:0x20 Description: 6-byte tag for used in TX tag insertion for management traffic from the UMP interface. This register holds the lower 4 bytes of the 6-byte tag.
#define NIG_REG_P1_TX_6BYTE_TAG_2MSB 0x18a34UL //ACCESS:RW DataWidth:0x10 Description: 6-byte tag for used in TX tag insertion for management traffic from the UMP interface. This register holds the upper 2 bytes of the 6-byte tag.
#define NIG_REG_P0_LLH_PTP_MAC_DA_2_LSB 0x18a38UL //ACCESS:RW DataWidth:0x20 Description: MAC destination address 2 for PTP packet detection. This register holds the lower 4 bytes of the address. MAC destination address 0 is fixed at 0x011B_1900_0000. MAC destination address 1 is fixed at 0x0180_C200_000E. This register defaults to 0x011B_1900_0000.
#define NIG_REG_P0_LLH_PTP_MAC_DA_2_MSB 0x18a3cUL //ACCESS:RW DataWidth:0x10 Description: MAC destination address 2 for PTP packet detection. This register holds the lower 4 bytes of the address. MAC destination address 0 is fixed at 0x011B_1900_0000. MAC destination address 1 is fixed at 0x0180_C200_000E. This register defaults to 0x011B_1900_0000.
#define NIG_REG_P1_LLH_PTP_MAC_DA_2_LSB 0x18a40UL //ACCESS:RW DataWidth:0x20 Description: MAC destination address 2 for PTP packet detection. This register holds the lower 4 bytes of the address. MAC destination address 0 is fixed at 0x011B_1900_0000. MAC destination address 1 is fixed at 0x0180_C200_000E. This register defaults to 0x011B_1900_0000.
#define NIG_REG_P1_LLH_PTP_MAC_DA_2_MSB 0x18a44UL //ACCESS:RW DataWidth:0x10 Description: MAC destination address 2 for PTP packet detection. This register holds the lower 4 bytes of the address. MAC destination address 0 is fixed at 0x011B_1900_0000. MAC destination address 1 is fixed at 0x0180_C200_000E. This register defaults to 0x011B_1900_0000.
#define NIG_REG_P0_PTP_SW_TXTSEN 0x18a48UL //ACCESS:RW DataWidth:0x1 Description: Enable for SW-specified packet timestamp mode. NIG will capture the timestamp value of the packet that SW indicated through PBF interface for host traffic or through the p*_tx_mng_timestamp_pkt bit for TX management packet. Note that the p*_ptp_en[3] bit has to be set to enable TimeSync on TX side for this mode to work. NIG will extract and capture the sequence ID if one of the version bits is enabled.
#define NIG_REG_P0_TX_MNG_TIMESTAMP_PKT 0x18a4cUL //ACCESS:RW DataWidth:0x1 Description: Indicate to timestamp the packet from MCP to network when *_ptp_sw_txtsen is set.
#define NIG_REG_P1_PTP_SW_TXTSEN 0x18a50UL //ACCESS:RW DataWidth:0x1 Description: Enable for SW-specified packet timestamp mode. NIG will capture the timestamp value of the packet that SW indicated through PBF interface for host traffic or through the p*_tx_mng_timestamp_pkt bit for TX management packet. Note that the p*_ptp_en[3] bit has to be set to enable TimeSync on TX side for this mode to work. NIG will extract and capture the sequence ID if one of the version bits is enabled.
#define NIG_REG_P1_TX_MNG_TIMESTAMP_PKT 0x18a54UL //ACCESS:RW DataWidth:0x1 Description: Indicate to timestamp the packet from MCP to network when *_ptp_sw_txtsen is set.
#define NIG_REG_P0_RX_FC_STATUS_CLEAR 0x18a58UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to clear the current flow control (PFC and LLFC) latched status.
#define NIG_REG_P1_RX_FC_STATUS_CLEAR 0x18a5cUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to clear the current flow control (PFC and LLFC) latched status.
#define NIG_REG_LLH0_ACPI_ENABLE 0x10138UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: When this bit is set ACPI packet recognition will be enabled. This bit must not be enabled until after after all other acpi registers were configured.
#define NIG_REG_LLH0_ACPI_ENABLE_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_0_LEN 0x1013cUL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 0
#define NIG_REG_LLH0_ACPI_PAT_0_LEN_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_1_LEN 0x10140UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 1
#define NIG_REG_LLH0_ACPI_PAT_1_LEN_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_2_LEN 0x10144UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 2
#define NIG_REG_LLH0_ACPI_PAT_2_LEN_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_3_LEN 0x10148UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 3
#define NIG_REG_LLH0_ACPI_PAT_3_LEN_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_4_LEN 0x1014cUL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 4
#define NIG_REG_LLH0_ACPI_PAT_4_LEN_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_5_LEN 0x10150UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 5
#define NIG_REG_LLH0_ACPI_PAT_5_LEN_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 6
#define NIG_REG_LLH0_ACPI_PAT_6_LEN_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_7_LEN 0x10158UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 7
#define NIG_REG_LLH0_ACPI_PAT_7_LEN_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015cUL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 0
#define NIG_REG_LLH0_ACPI_PAT_0_CRC_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_1_CRC 0x10160UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 1
#define NIG_REG_LLH0_ACPI_PAT_1_CRC_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_2_CRC 0x10164UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 2
#define NIG_REG_LLH0_ACPI_PAT_2_CRC_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_3_CRC 0x10168UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 3
#define NIG_REG_LLH0_ACPI_PAT_3_CRC_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_4_CRC 0x1016cUL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 4
#define NIG_REG_LLH0_ACPI_PAT_4_CRC_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_5_CRC 0x10170UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 5
#define NIG_REG_LLH0_ACPI_PAT_5_CRC_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_6_CRC 0x10174UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 6
#define NIG_REG_LLH0_ACPI_PAT_6_CRC_SIZE 1
#define NIG_REG_LLH0_ACPI_PAT_7_CRC 0x10178UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 7
#define NIG_REG_LLH0_ACPI_PAT_7_CRC_SIZE 1
#define NIG_REG_LLH1_ACPI_ENABLE 0x1017cUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: When this bit is set ACPI packet recognition will be enabled. This bit must not be enabled until after after all other acpi registers were configured.
#define NIG_REG_LLH1_ACPI_ENABLE_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_0_LEN 0x10180UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 0
#define NIG_REG_LLH1_ACPI_PAT_0_LEN_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_1_LEN 0x10184UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 1
#define NIG_REG_LLH1_ACPI_PAT_1_LEN_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_2_LEN 0x10188UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 2
#define NIG_REG_LLH1_ACPI_PAT_2_LEN_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_3_LEN 0x1018cUL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 3
#define NIG_REG_LLH1_ACPI_PAT_3_LEN_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_4_LEN 0x10190UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 4
#define NIG_REG_LLH1_ACPI_PAT_4_LEN_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_5_LEN 0x10194UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 5
#define NIG_REG_LLH1_ACPI_PAT_5_LEN_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_6_LEN 0x10198UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 6
#define NIG_REG_LLH1_ACPI_PAT_6_LEN_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_7_LEN 0x1019cUL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: Length in bytes of ACPI pattern 7
#define NIG_REG_LLH1_ACPI_PAT_7_LEN_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_0_CRC 0x101a0UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 0
#define NIG_REG_LLH1_ACPI_PAT_0_CRC_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_1_CRC 0x101a4UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 1
#define NIG_REG_LLH1_ACPI_PAT_1_CRC_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_2_CRC 0x101a8UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 2
#define NIG_REG_LLH1_ACPI_PAT_2_CRC_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_3_CRC 0x101acUL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 3
#define NIG_REG_LLH1_ACPI_PAT_3_CRC_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_4_CRC 0x101b0UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 4
#define NIG_REG_LLH1_ACPI_PAT_4_CRC_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_5_CRC 0x101b4UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 5
#define NIG_REG_LLH1_ACPI_PAT_5_CRC_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_6_CRC 0x101b8UL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 6
#define NIG_REG_LLH1_ACPI_PAT_6_CRC_SIZE 1
#define NIG_REG_LLH1_ACPI_PAT_7_CRC 0x101bcUL //ACCESS:RW DataWidth:0x20 SPLIT:4 Description: CRC32C for pattern 7
#define NIG_REG_LLH1_ACPI_PAT_7_CRC_SIZE 1
#define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY 0x10418UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in DEBUG_FIFO in NIG_TX_DBG
#define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY_SIZE 1
#define NIG_REG_EGRESS_DEBUG_FIFO_FULL 0x1041cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in DEBUG_FIFO in NIG_TX_DBG
#define NIG_REG_EGRESS_DEBUG_FIFO_FULL_SIZE 1
#define NIG_REG_EGRESS_DELAY0_EMPTY 0x10420UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT0
#define NIG_REG_EGRESS_DELAY0_EMPTY_SIZE 1
#define NIG_REG_EGRESS_DELAY0_FULL 0x10424UL //ACCESS:R DataWidth:0x1 Description: FIFO full in DELAY_PBF_FIFO in NIG_RX_PORT0
#define NIG_REG_EGRESS_DELAY0_FULL_SIZE 1
#define NIG_REG_EGRESS_DELAY1_EMPTY 0x10428UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT1
#define NIG_REG_EGRESS_DELAY1_EMPTY_SIZE 1
#define NIG_REG_EGRESS_DELAY1_FULL 0x1042cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in DELAY_PBF_FIFO in NIG_RX_PORT1
#define NIG_REG_EGRESS_DELAY1_FULL_SIZE 1
#define NIG_REG_EGRESS_MNG0_BYTE_VALID 0x10458UL //ACCESS:W DataWidth:0x3 Description: Byte valid for egress management packet from MCP. Write only for the last cycle of the management packet; Value = 0 means all 64 bits are valid; Value = 1 means bits[63:56] are vali;Value = 7 means bits[63:8] are valid.;
#define NIG_REG_EGRESS_MNG0_BYTE_VALID_SIZE 1
#define NIG_REG_EGRESS_MNG0_FIFO 0x1045cUL //ACCESS:RW DataWidth:0x20 Description: TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order.
#define NIG_REG_EGRESS_MNG0_FIFO_SIZE 1
#define NIG_REG_EGRESS_MNG0_FIFO_EMPTY 0x10460UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in MNG_FIFO in NIG_TX_PORT0
#define NIG_REG_EGRESS_MNG0_FIFO_EMPTY_SIZE 1
#define NIG_REG_EGRESS_MNG0_FIFO_FULL 0x10464UL //ACCESS:R DataWidth:0x1 Description: FIFO full in MNG_FIFO in NIG_TX_PORT0
#define NIG_REG_EGRESS_MNG0_FIFO_FULL_SIZE 1
#define NIG_REG_EGRESS_MNG0_FIFO_MSB 0x10468UL //ACCESS:R DataWidth:0x2 Description: Debug only.MSB of egress_MNG_FIFO in NIG_egress_PORT0. Empty[1]; parity[0];
#define NIG_REG_EGRESS_MNG0_FIFO_MSB_SIZE 1
#define NIG_REG_EGRESS_MNG1_BYTE_VALID 0x1046cUL //ACCESS:W DataWidth:0x3 Description: Byte valid for egress management packet from MCP. Write only for the last cycle of the management packet; Value = 0 means all 64 bits are valid; Value = 1 means bits[63:56] are vali;Value = 7 means bits[63:8] are valid.;
#define NIG_REG_EGRESS_MNG1_BYTE_VALID_SIZE 1
#define NIG_REG_EGRESS_MNG1_FIFO 0x10470UL //ACCESS:RW DataWidth:0x20 Description: TX_MNG_FIFO in NIG_TX_PORT1; data[31:0] written in FIFO order.
#define NIG_REG_EGRESS_MNG1_FIFO_SIZE 1
#define NIG_REG_EGRESS_MNG1_FIFO_EMPTY 0x10474UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in MNG_FIFO in NIG_TX_PORT1
#define NIG_REG_EGRESS_MNG1_FIFO_EMPTY_SIZE 1
#define NIG_REG_EGRESS_MNG1_FIFO_FULL 0x10478UL //ACCESS:R DataWidth:0x1 Description: FIFO full in MNG_FIFO in NIG_TX_PORT1
#define NIG_REG_EGRESS_MNG1_FIFO_FULL_SIZE 1
#define NIG_REG_EGRESS_MNG1_FIFO_MSB 0x1047cUL //ACCESS:R DataWidth:0x2 Description: Debug only. MSB of egress_MNG_FIFO in NIG_egress_PORT0. Empty[1]; parity[0];
#define NIG_REG_EGRESS_MNG1_FIFO_MSB_SIZE 1
#define NIG_REG_EMAC0_STATUS_MISC_ATTN 0x10480UL //ACCESS:R DataWidth:0x1 Description: status from emac0. A value of 1 indicates that 1 of the attentions occurred. (enabled inside the ~emac_reg_emac_attention_ena.emac_attention_ena fields).
#define NIG_REG_EMAC0_STATUS_MISC_ATTN_SIZE 1
#define NIG_REG_EMAC0_STATUS_MISC_CFG_CHANGE 0x10484UL //ACCESS:R DataWidth:0x1 Description: status from emac0. This register is not applicable.
#define NIG_REG_EMAC0_STATUS_MISC_CFG_CHANGE_SIZE 1
#define NIG_REG_EMAC0_STATUS_MISC_LINK_CHANGE 0x10488UL //ACCESS:R DataWidth:0x1 Description: status from emac0. This bit is set on each change of the link.
#define NIG_REG_EMAC0_STATUS_MISC_LINK_CHANGE_SIZE 1
#define NIG_REG_EMAC0_STATUS_MISC_LINK_STATUS 0x1048cUL //ACCESS:R DataWidth:0x1 Description: status from emac0. A value of 1 indicates that the physical interface is linked (when all is configured correctly).
#define NIG_REG_EMAC0_STATUS_MISC_LINK_STATUS_SIZE 1
#define NIG_REG_EMAC0_STATUS_MISC_MI_COMPLETE 0x10490UL //ACCESS:R DataWidth:0x1 Description: status from emac0 This bit is set each time the Management Interface transaction has completed.
#define NIG_REG_EMAC0_STATUS_MISC_MI_COMPLETE_SIZE 1
#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494UL //ACCESS:R DataWidth:0x1 Description: status from emac0. This bit is set when MDINT from either the EXT_MDINT pin or from the Copper PHY is driven low. This condition must be cleared in the attached PHY device that is driving the MINT pin.
#define NIG_REG_EMAC0_STATUS_MISC_MI_INT_SIZE 1
#define NIG_REG_EMAC1_STATUS_MISC_ATTN 0x10498UL //ACCESS:R DataWidth:0x1 Description: status from emac0. A value of 1 indicates that 1 of the attentions occurred. (enabled inside the ~emac_reg_emac_attention_ena.emac_attention_ena fields).
#define NIG_REG_EMAC1_STATUS_MISC_ATTN_SIZE 1
#define NIG_REG_EMAC1_STATUS_MISC_CFG_CHANGE 0x1049cUL //ACCESS:R DataWidth:0x1 Description: status from emac0. This register is not applicable.
#define NIG_REG_EMAC1_STATUS_MISC_CFG_CHANGE_SIZE 1
#define NIG_REG_EMAC1_STATUS_MISC_LINK_CHANGE 0x104a0UL //ACCESS:R DataWidth:0x1 Description: status from emac0. This bit is set on each change of the link.
#define NIG_REG_EMAC1_STATUS_MISC_LINK_CHANGE_SIZE 1
#define NIG_REG_EMAC1_STATUS_MISC_LINK_STATUS 0x104a4UL //ACCESS:R DataWidth:0x1 Description: status from emac0. A value of 1 indicates that the physical interface is linked (when all is configured correctly).
#define NIG_REG_EMAC1_STATUS_MISC_LINK_STATUS_SIZE 1
#define NIG_REG_EMAC1_STATUS_MISC_MI_COMPLETE 0x104a8UL //ACCESS:R DataWidth:0x1 Description: status from emac0 This bit is set each time the Management Interface transaction has completed.
#define NIG_REG_EMAC1_STATUS_MISC_MI_COMPLETE_SIZE 1
#define NIG_REG_EMAC1_STATUS_MISC_MI_INT 0x104acUL //ACCESS:R DataWidth:0x1 Description: status from emac0. This bit is set when MDINT from either the EXT_MDINT pin or from the Copper PHY is driven low. This condition must be cleared in the attached PHY device that is driving the MINT pin.
#define NIG_REG_EMAC1_STATUS_MISC_MI_INT_SIZE 1
#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP
#define NIG_REG_INGRESS_EOP_LB_EMPTY_SIZE 1
#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4UL //ACCESS:RW DataWidth:0x11 Description: Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16]
#define NIG_REG_INGRESS_EOP_LB_FIFO_SIZE 1
#define NIG_REG_INGRESS_EOP_LB_FULL 0x104e8UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EOP descriptor FIFO of LP in NIG_RX_EOP
#define NIG_REG_INGRESS_EOP_LB_FULL_SIZE 1
#define NIG_REG_INGRESS_EOP_PORT0_EMPTY 0x104ecUL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EOP descriptor FIFO of port 0 in NIG_RX_EOP
#define NIG_REG_INGRESS_EOP_PORT0_EMPTY_SIZE 1
#define NIG_REG_INGRESS_EOP_PORT0_FIFO 0x104f0UL //ACCESS:RW DataWidth:0x11 Description: Debug only. RX_EOP_DSCR_PORT0_FIFO in NIG_RX_EOP. Data packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16]
#define NIG_REG_INGRESS_EOP_PORT0_FIFO_SIZE 1
#define NIG_REG_INGRESS_EOP_PORT0_FULL 0x104f4UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EOP descriptor FIFO of port 0 in NIG_RX_EOP
#define NIG_REG_INGRESS_EOP_PORT0_FULL_SIZE 1
#define NIG_REG_INGRESS_EOP_PORT1_EMPTY 0x104f8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EOP descriptor FIFO of port 1 in NIG_RX_EOP
#define NIG_REG_INGRESS_EOP_PORT1_EMPTY_SIZE 1
#define NIG_REG_INGRESS_EOP_PORT1_FIFO 0x104fcUL //ACCESS:RW DataWidth:0x11 Description: Debug only. RX_EOP_DSCR_port1_FIFO in NIG_RX_EOP. Data packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16]
#define NIG_REG_INGRESS_EOP_PORT1_FIFO_SIZE 1
#define NIG_REG_INGRESS_EOP_PORT1_FULL 0x10500UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EOP descriptor FIFO of port 1 in NIG_RX_EOP
#define NIG_REG_INGRESS_EOP_PORT1_FULL_SIZE 1
#define NIG_REG_INGRESS_LB_PBF_DELAY_ALM_FULL 0x10504UL //ACCESS:R DataWidth:0x1 Description: FIFO almost full in PBF_DELAY_lb_FIFO in NIG_RX_lb
#define NIG_REG_INGRESS_LB_PBF_DELAY_ALM_FULL_SIZE 1
#define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY 0x10508UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in PBF_DELAY_lb_FIFO in NIG_RX_lb
#define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY_SIZE 1
#define NIG_REG_INGRESS_LB_PBF_DELAY_FULL 0x1050cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in PBF_DELAY_lb_FIFO in NIG_RX_lb
#define NIG_REG_INGRESS_LB_PBF_DELAY_FULL_SIZE 1
#define NIG_REG_INGRESS_MNG0_CONTEXT0 0x10510UL //ACCESS:R DataWidth:0xc Description: Context of management packet in rmp0 block for packet started at addr 0 {error[11]; eop_nyte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_INGRESS_MNG0_CONTEXT0_SIZE 1
#define NIG_REG_INGRESS_MNG0_CONTEXT1 0x10514UL //ACCESS:R DataWidth:0xc Description: Context of management packet in rmp0 block for packet started at addr 192 {error[11]; eop_nyte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_INGRESS_MNG0_CONTEXT1_SIZE 1
#define NIG_REG_INGRESS_MNG0_CONTEXT2 0x10518UL //ACCESS:R DataWidth:0xc Description: Context of management packet in rmp0 block for packet started at addr 384 {error[11]; eop_nyte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_INGRESS_MNG0_CONTEXT2_SIZE 1
#define NIG_REG_INGRESS_MNG0_CONTEXT3 0x1051cUL //ACCESS:R DataWidth:0xc Description: Context of management packet in rmp0 block for packet started at addr 576 {error[11]; eop_nyte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_INGRESS_MNG0_CONTEXT3_SIZE 1
#define NIG_REG_INGRESS_MNG1_CONTEXT0 0x10520UL //ACCESS:R DataWidth:0xc Description: Context of management packet in rmp1 block for packet started at addr 0 {error[11]; eop_nyte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_INGRESS_MNG1_CONTEXT0_SIZE 1
#define NIG_REG_INGRESS_MNG1_CONTEXT1 0x10524UL //ACCESS:R DataWidth:0xc Description: Context of management packet in rmp1 block for packet started at addr 192 {error[11]; eop_nyte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_INGRESS_MNG1_CONTEXT1_SIZE 1
#define NIG_REG_INGRESS_MNG1_CONTEXT2 0x10528UL //ACCESS:R DataWidth:0xc Description: Context of management packet in rmp1 block for packet started at addr 384 {error[11]; eop_nyte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_INGRESS_MNG1_CONTEXT2_SIZE 1
#define NIG_REG_INGRESS_MNG1_CONTEXT3 0x1052cUL //ACCESS:R DataWidth:0xc Description: Context of management packet in rmp1 block for packet started at addr 576 {error[11]; eop_nyte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_INGRESS_MNG1_CONTEXT3_SIZE 1
#define NIG_REG_INGRESS_RMP0_DSCR_EMPTY 0x10530UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in dscr_fifo in NIG_RX_RMP block
#define NIG_REG_INGRESS_RMP0_DSCR_EMPTY_SIZE 1
#define NIG_REG_INGRESS_RMP0_DSCR_FULL 0x10534UL //ACCESS:R DataWidth:0x1 Description: FIFO full in dscr_fifo in NIG_RX_RMP block
#define NIG_REG_INGRESS_RMP0_DSCR_FULL_SIZE 1
#define NIG_REG_INGRESS_RMP1_DSCR_EMPTY 0x10538UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in dscr_fifo in NIG_RX_RMP block
#define NIG_REG_INGRESS_RMP1_DSCR_EMPTY_SIZE 1
#define NIG_REG_INGRESS_RMP1_DSCR_FULL 0x1053cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in dscr_fifo in NIG_RX_RMP block
#define NIG_REG_INGRESS_RMP1_DSCR_FULL_SIZE 1
#define NIG_REG_LED_STATUS_ACTIVE_P0 0x10540UL //ACCESS:R DataWidth:0x1 Description: status of led active for port0
#define NIG_REG_LED_STATUS_ACTIVE_P0_SIZE 1
#define NIG_REG_LED_STATUS_ACTIVE_P1 0x10544UL //ACCESS:R DataWidth:0x1 Description: status of led active for port1
#define NIG_REG_LED_STATUS_ACTIVE_P1_SIZE 1
#define NIG_REG_LLH0_FIFO_EMPTY 0x10548UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in LLH port0
#define NIG_REG_LLH0_FIFO_EMPTY_SIZE 1
#define NIG_REG_LLH0_FIFO_FULL 0x1054cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in LLH port0
#define NIG_REG_LLH0_FIFO_FULL_SIZE 1
#define NIG_REG_LLH0_PAT_IND 0x10550UL //ACCESS:R DataWidth:0x8 Description: pattern index for debugging ofLLH0
#define NIG_REG_LLH0_PAT_IND_SIZE 1
#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554UL //ACCESS:RW DataWidth:0x8 Description: init credit counter for port0 in LLH
#define NIG_REG_LLH0_XCM_INIT_CREDIT_SIZE 1
#define NIG_REG_LLH1_FIFO_EMPTY 0x10558UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in LLH port1
#define NIG_REG_LLH1_FIFO_EMPTY_SIZE 1
#define NIG_REG_LLH1_FIFO_FULL 0x1055cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in LLH port1
#define NIG_REG_LLH1_FIFO_FULL_SIZE 1
#define NIG_REG_LLH1_PAT_IND 0x10560UL //ACCESS:R DataWidth:0x8 Description: pattern index for debugging ofLLH0
#define NIG_REG_LLH1_PAT_IND_SIZE 1
#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564UL //ACCESS:RW DataWidth:0x8 Description: init credit counter for port1 in LLH
#define NIG_REG_LLH1_XCM_INIT_CREDIT_SIZE 1
#define NIG_REG_SERDES0_STATUS_AUTONEG_COMPLETE 0x10568UL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of CL37 AN complete.
#define NIG_REG_SERDES0_STATUS_AUTONEG_COMPLETE_SIZE 1
#define NIG_REG_SERDES0_STATUS_CL73_AN_COMPLETE 0x1056cUL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of CL73 AN complete
#define NIG_REG_SERDES0_STATUS_CL73_AN_COMPLETE_SIZE 1
#define NIG_REG_SERDES0_STATUS_CL73_MR_PAGE_RX 0x10570UL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of received CL73 AN page.
#define NIG_REG_SERDES0_STATUS_CL73_MR_PAGE_RX_SIZE 1
#define NIG_REG_SERDES0_STATUS_FIBER_RXACT 0x10574UL //ACCESS:R DataWidth:0x1 Description: Detection of Fiber RX activity.
#define NIG_REG_SERDES0_STATUS_FIBER_RXACT_SIZE 1
#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578UL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of link status
#define NIG_REG_SERDES0_STATUS_LINK_STATUS_SIZE 1
#define NIG_REG_SERDES0_STATUS_MAC_COL 0x1057cUL //ACCESS:R DataWidth:0x1 Description: Indication of MAC collision. Valid upon half duplex link.
#define NIG_REG_SERDES0_STATUS_MAC_COL_SIZE 1
#define NIG_REG_SERDES0_STATUS_MAC_CRS 0x10580UL //ACCESS:R DataWidth:0x1 Description: Indication of MAC carrier sense event.
#define NIG_REG_SERDES0_STATUS_MAC_CRS_SIZE 1
#define NIG_REG_SERDES0_STATUS_MR_PAGE_RX 0x10584UL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of received CL37 AN page.
#define NIG_REG_SERDES0_STATUS_MR_PAGE_RX_SIZE 1
#define NIG_REG_SERDES0_STATUS_RX_SIGDET 0x10588UL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of Rx signal detected on its pins.
#define NIG_REG_SERDES0_STATUS_RX_SIGDET_SIZE 1
#define NIG_REG_SERDES0_STATUS_SPEED_10 0x1058cUL //ACCESS:R DataWidth:0x1 Description: When set SERDES0 link speed is 10M
#define NIG_REG_SERDES0_STATUS_SPEED_10_SIZE 1
#define NIG_REG_SERDES0_STATUS_SPEED_100 0x10590UL //ACCESS:R DataWidth:0x1 Description: When set SERDES0 link speed is 100M
#define NIG_REG_SERDES0_STATUS_SPEED_100_SIZE 1
#define NIG_REG_SERDES0_STATUS_SPEED_1000 0x10594UL //ACCESS:R DataWidth:0x1 Description: When set SERDES0 link speed is 1G
#define NIG_REG_SERDES0_STATUS_SPEED_1000_SIZE 1
#define NIG_REG_SERDES0_STATUS_SPEED_1000_KX 0x10598UL //ACCESS:R DataWidth:0x1 Description: When set SERDES0 link speed is 1G-KX
#define NIG_REG_SERDES0_STATUS_SPEED_1000_KX_SIZE 1
#define NIG_REG_SERDES0_STATUS_SPEED_2500 0x1059cUL //ACCESS:R DataWidth:0x1 Description: When set SERDES0 link speed is 2.5G
#define NIG_REG_SERDES0_STATUS_SPEED_2500_SIZE 1
#define NIG_REG_SERDES0_STATUS_TXPLL_LOCK 0x105a0UL //ACCESS:R DataWidth:0x1 Description: when set SERDES0 TX PLL is locked.
#define NIG_REG_SERDES0_STATUS_TXPLL_LOCK_SIZE 1
#define NIG_REG_SERDES1_STATUS_AUTONEG_COMPLETE 0x105a4UL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of CL37 AN complete.
#define NIG_REG_SERDES1_STATUS_AUTONEG_COMPLETE_SIZE 1
#define NIG_REG_SERDES1_STATUS_CL73_AN_COMPLETE 0x105a8UL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of CL73 AN complete.
#define NIG_REG_SERDES1_STATUS_CL73_AN_COMPLETE_SIZE 1
#define NIG_REG_SERDES1_STATUS_CL73_MR_PAGE_RX 0x105acUL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of received CL73 AN page.
#define NIG_REG_SERDES1_STATUS_CL73_MR_PAGE_RX_SIZE 1
#define NIG_REG_SERDES1_STATUS_FIBER_RXACT 0x105b0UL //ACCESS:R DataWidth:0x1 Description: Detection of Fiber RX activity.
#define NIG_REG_SERDES1_STATUS_FIBER_RXACT_SIZE 1
#define NIG_REG_SERDES1_STATUS_LINK_STATUS 0x105b4UL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of link status
#define NIG_REG_SERDES1_STATUS_LINK_STATUS_SIZE 1
#define NIG_REG_SERDES1_STATUS_MAC_COL 0x105b8UL //ACCESS:R DataWidth:0x1 Description: Indication of MAC collision. Valid upon half duplex link.
#define NIG_REG_SERDES1_STATUS_MAC_COL_SIZE 1
#define NIG_REG_SERDES1_STATUS_MAC_CRS 0x105bcUL //ACCESS:R DataWidth:0x1 Description: Indication of MAC carrier sense event.
#define NIG_REG_SERDES1_STATUS_MAC_CRS_SIZE 1
#define NIG_REG_SERDES1_STATUS_MR_PAGE_RX 0x105c0UL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of received CL37 AN page.
#define NIG_REG_SERDES1_STATUS_MR_PAGE_RX_SIZE 1
#define NIG_REG_SERDES1_STATUS_RX_SIGDET 0x105c4UL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of Rx signal detected on its pins.
#define NIG_REG_SERDES1_STATUS_RX_SIGDET_SIZE 1
#define NIG_REG_SERDES1_STATUS_SPEED_10 0x105c8UL //ACCESS:R DataWidth:0x1 Description: When set SERDES1 link speed is 10M
#define NIG_REG_SERDES1_STATUS_SPEED_10_SIZE 1
#define NIG_REG_SERDES1_STATUS_SPEED_100 0x105ccUL //ACCESS:R DataWidth:0x1 Description: When set SERDES1 link speed is 100M
#define NIG_REG_SERDES1_STATUS_SPEED_100_SIZE 1
#define NIG_REG_SERDES1_STATUS_SPEED_1000 0x105d0UL //ACCESS:R DataWidth:0x1 Description: When set SERDES1 link speed is 1G
#define NIG_REG_SERDES1_STATUS_SPEED_1000_SIZE 1
#define NIG_REG_SERDES1_STATUS_SPEED_1000_KX 0x105d4UL //ACCESS:R DataWidth:0x1 Description: When set SERDES1 link speed is 1G-KX
#define NIG_REG_SERDES1_STATUS_SPEED_1000_KX_SIZE 1
#define NIG_REG_SERDES1_STATUS_SPEED_2500 0x105d8UL //ACCESS:R DataWidth:0x1 Description: When set SERDES1 link speed is 2.5G
#define NIG_REG_SERDES1_STATUS_SPEED_2500_SIZE 1
#define NIG_REG_SERDES1_STATUS_TXPLL_LOCK 0x105dcUL //ACCESS:R DataWidth:0x1 Description: when set SERDES1 TX PLL is locked.
#define NIG_REG_SERDES1_STATUS_TXPLL_LOCK_SIZE 1
#define NIG_REG_SLOW_LLFC0_WR_EMPTY 0x105e0UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in LLFC0 push block
#define NIG_REG_SLOW_LLFC0_WR_EMPTY_SIZE 1
#define NIG_REG_SLOW_LLFC0_WR_FULL 0x105e4UL //ACCESS:R DataWidth:0x1 Description: FIFO full in LLFC0 push block
#define NIG_REG_SLOW_LLFC0_WR_FULL_SIZE 1
#define NIG_REG_SLOW_LLFC1_WR_EMPTY 0x105e8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in LLFC1 push block
#define NIG_REG_SLOW_LLFC1_WR_EMPTY_SIZE 1
#define NIG_REG_SLOW_LLFC1_WR_FULL 0x105ecUL //ACCESS:R DataWidth:0x1 Description: FIFO full in LLFC1 push block
#define NIG_REG_SLOW_LLFC1_WR_FULL_SIZE 1
#define NIG_REG_STAT0_BRB_DISCARD 0x105f0UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : In user packets discarded due to BRB backpressure for port 0 COS0
#define NIG_REG_STAT0_BRB_DISCARD_SIZE 1
#define NIG_REG_STAT0_BRB_PACKET 0x105f4UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : User packets received (transferred to BRB) for port0
#define NIG_REG_STAT0_BRB_PACKET_SIZE 1
#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : In user packets truncated due to BRB backpressure for port 0 COS0
#define NIG_REG_STAT0_BRB_TRUNCATE_SIZE 1
#define NIG_REG_STAT0_FLOW_CTRL_DISCARD 0x105fcUL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Flow control messages to XCM discarded due to backpressure from XCM for port0 from LLH
#define NIG_REG_STAT0_FLOW_CTRL_DISCARD_SIZE 1
#define NIG_REG_STAT0_FLOW_CTRL_OCTETS 0x10600UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Flow control octets received for port0 from LLH
#define NIG_REG_STAT0_FLOW_CTRL_OCTETS_SIZE 1
#define NIG_REG_STAT0_FLOW_CTRL_PACKET 0x10604UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Flow control packets received (MAC control frames with opcode != 1; BCN; SAFC) for port0 from LLH
#define NIG_REG_STAT0_FLOW_CTRL_PACKET_SIZE 1
#define NIG_REG_STAT0_MNG_DISCARD 0x10608UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Management packets discarded due to lack of buffer space for port0
#define NIG_REG_STAT0_MNG_DISCARD_SIZE 1
#define NIG_REG_STAT0_MNG_OCTET_INP 0x1060cUL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Management octets received for port0 from LLH
#define NIG_REG_STAT0_MNG_OCTET_INP_SIZE 1
#define NIG_REG_STAT0_MNG_OCTET_OUT 0x10610UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : Management octets transmitted for port0
#define NIG_REG_STAT0_MNG_OCTET_OUT_SIZE 1
#define NIG_REG_STAT0_MNG_PACKET_INP 0x10614UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Management packets received for port0 from LLH
#define NIG_REG_STAT0_MNG_PACKET_INP_SIZE 1
#define NIG_REG_STAT0_MNG_PACKET_OUT 0x10618UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : Management packets transmitted for port0
#define NIG_REG_STAT0_MNG_PACKET_OUT_SIZE 1
#define NIG_REG_STAT0_PBF_OCTETS 0x1061cUL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User octets transmitted from PBF for port0
#define NIG_REG_STAT0_PBF_OCTETS_SIZE 1
#define NIG_REG_STAT0_PBF_PACKET 0x10620UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User packets transmitted from PBF for port0
#define NIG_REG_STAT0_PBF_PACKET_SIZE 1
#define NIG_REG_STAT0_SAFC_INP 0x10624UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : SAFC frames received for port0 from LLH
#define NIG_REG_STAT0_SAFC_INP_SIZE 1
#define NIG_REG_STAT1_BRB_DISCARD 0x10628UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : In user packets discarded due to BRB backpressure for port 1 COS0
#define NIG_REG_STAT1_BRB_DISCARD_SIZE 1
#define NIG_REG_STAT1_BRB_PACKET 0x1062cUL //ACCESS:R DataWidth:0x20 Description: Rx statistics : User packets received (transferred to BRB) for port1
#define NIG_REG_STAT1_BRB_PACKET_SIZE 1
#define NIG_REG_STAT1_BRB_TRUNCATE 0x10630UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : In user packets truncated due to BRB backpressure for port 1 COS0
#define NIG_REG_STAT1_BRB_TRUNCATE_SIZE 1
#define NIG_REG_STAT1_FLOW_CTRL_DISCARD 0x10634UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Flow control messages to XCM discarded due to backpressure from XCM for port1
#define NIG_REG_STAT1_FLOW_CTRL_DISCARD_SIZE 1
#define NIG_REG_STAT1_FLOW_CTRL_OCTETS 0x10638UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Flow control octets received for port1
#define NIG_REG_STAT1_FLOW_CTRL_OCTETS_SIZE 1
#define NIG_REG_STAT1_FLOW_CTRL_PACKET 0x1063cUL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Flow control packets received (MAC control frames with opcode != 1; BCN; SAFC) for port1
#define NIG_REG_STAT1_FLOW_CTRL_PACKET_SIZE 1
#define NIG_REG_STAT1_MNG_DISCARD 0x10640UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Management packets discarded due to lack of buffer space for port1
#define NIG_REG_STAT1_MNG_DISCARD_SIZE 1
#define NIG_REG_STAT1_MNG_OCTET_INP 0x10644UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Management octets received for port1
#define NIG_REG_STAT1_MNG_OCTET_INP_SIZE 1
#define NIG_REG_STAT1_MNG_OCTET_OUT 0x10648UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : Management octets transmitted for port1
#define NIG_REG_STAT1_MNG_OCTET_OUT_SIZE 1
#define NIG_REG_STAT1_MNG_PACKET_INP 0x1064cUL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Management packets received for port1
#define NIG_REG_STAT1_MNG_PACKET_INP_SIZE 1
#define NIG_REG_STAT1_MNG_PACKET_OUT 0x10650UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : Management packets transmitted for port1
#define NIG_REG_STAT1_MNG_PACKET_OUT_SIZE 1
#define NIG_REG_STAT1_PBF_OCTETS 0x10654UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User octets transmitted from PBF for port1
#define NIG_REG_STAT1_PBF_OCTETS_SIZE 1
#define NIG_REG_STAT1_PBF_PACKET 0x10658UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User packets transmitted from PBF for port1
#define NIG_REG_STAT1_PBF_PACKET_SIZE 1
#define NIG_REG_STAT1_SAFC_INP 0x1065cUL //ACCESS:R DataWidth:0x20 Description: Rx statistics : SAFC frames received for port1
#define NIG_REG_STAT1_SAFC_INP_SIZE 1
#define NIG_REG_STAT2_BRB_PACKET 0x10660UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : User packets received (transferred to BRB) for LP
#define NIG_REG_STAT2_BRB_PACKET_SIZE 1
#define NIG_REG_STAT_PBF_LB_FULL 0x10664UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : Number of cycles that the full signal was asserted on the loopback port towards the PBF (due to BRB backpressure)
#define NIG_REG_STAT_PBF_LB_FULL_SIZE 1
#define NIG_REG_TIMER0_COUNTER 0x10668UL //ACCESS:R DataWidth:0x20 Description: Value of timer counter in NIG_TX_PORT0. This timer counts when there is no read request from MAC when data to it is ready. Timeout event will generate an interrupt to the host when this timer equal to ~nig_registers_timer0_max.timer0_max
#define NIG_REG_TIMER0_COUNTER_SIZE 1
#define NIG_REG_TIMER1_COUNTER 0x1066cUL //ACCESS:R DataWidth:0x20 Description: Value of timer counter in NIG_TX_PORT1. This timer counts when there is no read request from MAC when data to it is ready. Timeout event will generate an interrupt to the host when this timer equal to ~nig_registers_timer1_max.timer1_max
#define NIG_REG_TIMER1_COUNTER_SIZE 1
#define NIG_REG_XGXS0_STATUS_AUTONEG_COMPLETE 0x10670UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of CL37 AN complete.
#define NIG_REG_XGXS0_STATUS_AUTONEG_COMPLETE_SIZE 1
#define NIG_REG_XGXS0_STATUS_CL73_AN_COMPLETE 0x10674UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of CL73 AN complete
#define NIG_REG_XGXS0_STATUS_CL73_AN_COMPLETE_SIZE 1
#define NIG_REG_XGXS0_STATUS_CL73_MR_PAGE_RX 0x10678UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of received CL73 AN page.
#define NIG_REG_XGXS0_STATUS_CL73_MR_PAGE_RX_SIZE 1
#define NIG_REG_XGXS0_STATUS_FIBER_RXACT 0x1067cUL //ACCESS:R DataWidth:0x1 Description: Detection of Fiber RX activity.
#define NIG_REG_XGXS0_STATUS_FIBER_RXACT_SIZE 1
#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of link10g.
#define NIG_REG_XGXS0_STATUS_LINK10G_SIZE 1
#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684UL //ACCESS:R DataWidth:0x4 Description: status from xgxs0 that inputs to interrupt logic of link status
#define NIG_REG_XGXS0_STATUS_LINK_STATUS_SIZE 1
#define NIG_REG_XGXS0_STATUS_MAC_COL 0x10688UL //ACCESS:R DataWidth:0x1 Description: Indication of MAC collision. Valid upon half duplex link.
#define NIG_REG_XGXS0_STATUS_MAC_COL_SIZE 1
#define NIG_REG_XGXS0_STATUS_MAC_CRS 0x1068cUL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of mac crs
#define NIG_REG_XGXS0_STATUS_MAC_CRS_SIZE 1
#define NIG_REG_XGXS0_STATUS_MR_PAGE_RX 0x10690UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of received CL37 AN page.
#define NIG_REG_XGXS0_STATUS_MR_PAGE_RX_SIZE 1
#define NIG_REG_XGXS0_STATUS_REMOTEMDIOREQ 0x10694UL //ACCESS:R DataWidth:0x1 Description: status from xgxs port 0 of remote mdio request
#define NIG_REG_XGXS0_STATUS_REMOTEMDIOREQ_SIZE 1
#define NIG_REG_XGXS0_STATUS_RX_SIGDET 0x10698UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of Rx signal detected on its pins.
#define NIG_REG_XGXS0_STATUS_RX_SIGDET_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_10 0x1069cUL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 10M
#define NIG_REG_XGXS0_STATUS_SPEED_10_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_100 0x106a0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 100M
#define NIG_REG_XGXS0_STATUS_SPEED_100_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_1000 0x106a4UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 1G
#define NIG_REG_XGXS0_STATUS_SPEED_1000_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_10000 0x106a8UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 10GHiG
#define NIG_REG_XGXS0_STATUS_SPEED_10000_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_10000_CX4 0x106acUL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 10G-CX4
#define NIG_REG_XGXS0_STATUS_SPEED_10000_CX4_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_10000_KR 0x106b0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 10G-KR
#define NIG_REG_XGXS0_STATUS_SPEED_10000_KR_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_10000_KX4 0x106b4UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 10G-KX4
#define NIG_REG_XGXS0_STATUS_SPEED_10000_KX4_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_1000_KX 0x106b8UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 1G-KX
#define NIG_REG_XGXS0_STATUS_SPEED_1000_KX_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_12000 0x106bcUL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 12G
#define NIG_REG_XGXS0_STATUS_SPEED_12000_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_12500 0x106c0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 12.5GHiG
#define NIG_REG_XGXS0_STATUS_SPEED_12500_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_13000 0x106c4UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 13G
#define NIG_REG_XGXS0_STATUS_SPEED_13000_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_15000 0x106c8UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 15G
#define NIG_REG_XGXS0_STATUS_SPEED_15000_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_16000 0x106ccUL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 16G
#define NIG_REG_XGXS0_STATUS_SPEED_16000_SIZE 1
#define NIG_REG_XGXS0_STATUS_SPEED_2500 0x106d0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 2.5G
#define NIG_REG_XGXS0_STATUS_SPEED_2500_SIZE 1
#define NIG_REG_XGXS0_STATUS_TXPLL_LOCK 0x106d4UL //ACCESS:R DataWidth:0x1 Description: when set; XGXS0 TX PLL is locked.
#define NIG_REG_XGXS0_STATUS_TXPLL_LOCK_SIZE 1
#define NIG_REG_XGXS1_STATUS_AUTONEG_COMPLETE 0x106d8UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of CL37 AN complete.
#define NIG_REG_XGXS1_STATUS_AUTONEG_COMPLETE_SIZE 1
#define NIG_REG_XGXS1_STATUS_CL73_AN_COMPLETE 0x106dcUL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of CL73 AN complete
#define NIG_REG_XGXS1_STATUS_CL73_AN_COMPLETE_SIZE 1
#define NIG_REG_XGXS1_STATUS_CL73_MR_PAGE_RX 0x106e0UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of received CL73 AN page.
#define NIG_REG_XGXS1_STATUS_CL73_MR_PAGE_RX_SIZE 1
#define NIG_REG_XGXS1_STATUS_FIBER_RXACT 0x106e4UL //ACCESS:R DataWidth:0x1 Description: Detection of Fiber RX activity.
#define NIG_REG_XGXS1_STATUS_FIBER_RXACT_SIZE 1
#define NIG_REG_XGXS1_STATUS_LINK10G 0x106e8UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of link10g
#define NIG_REG_XGXS1_STATUS_LINK10G_SIZE 1
#define NIG_REG_XGXS1_STATUS_LINK_STATUS 0x106ecUL //ACCESS:R DataWidth:0x4 Description: status from xgxs1 that inputs to interrupt logic of link status
#define NIG_REG_XGXS1_STATUS_LINK_STATUS_SIZE 1
#define NIG_REG_XGXS1_STATUS_MAC_COL 0x106f0UL //ACCESS:R DataWidth:0x1 Description: Indication of MAC collision. Valid upon half duplex link.
#define NIG_REG_XGXS1_STATUS_MAC_COL_SIZE 1
#define NIG_REG_XGXS1_STATUS_MAC_CRS 0x106f4UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of mac crs
#define NIG_REG_XGXS1_STATUS_MAC_CRS_SIZE 1
#define NIG_REG_XGXS1_STATUS_MR_PAGE_RX 0x106f8UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of received CL37 AN page.
#define NIG_REG_XGXS1_STATUS_MR_PAGE_RX_SIZE 1
#define NIG_REG_XGXS1_STATUS_REMOTEMDIOREQ 0x106fcUL //ACCESS:R DataWidth:0x1 Description: status from xgxs port 1 of remote mdio request
#define NIG_REG_XGXS1_STATUS_REMOTEMDIOREQ_SIZE 1
#define NIG_REG_XGXS1_STATUS_RX_SIGDET 0x10700UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of Rx signal detected on its pins.
#define NIG_REG_XGXS1_STATUS_RX_SIGDET_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_10 0x10704UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 10M
#define NIG_REG_XGXS1_STATUS_SPEED_10_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_100 0x10708UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 100M
#define NIG_REG_XGXS1_STATUS_SPEED_100_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_1000 0x1070cUL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 1G
#define NIG_REG_XGXS1_STATUS_SPEED_1000_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_10000 0x10710UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 10GHiG
#define NIG_REG_XGXS1_STATUS_SPEED_10000_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_10000_CX4 0x10714UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 10G-CX4
#define NIG_REG_XGXS1_STATUS_SPEED_10000_CX4_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_10000_KR 0x10718UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 10G-KR
#define NIG_REG_XGXS1_STATUS_SPEED_10000_KR_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_10000_KX4 0x1071cUL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 10G-KX4
#define NIG_REG_XGXS1_STATUS_SPEED_10000_KX4_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_1000_KX 0x10720UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 1G-KX
#define NIG_REG_XGXS1_STATUS_SPEED_1000_KX_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_12000 0x10724UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 12G
#define NIG_REG_XGXS1_STATUS_SPEED_12000_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_12500 0x10728UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 12.5GHiG
#define NIG_REG_XGXS1_STATUS_SPEED_12500_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_13000 0x1072cUL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 13G
#define NIG_REG_XGXS1_STATUS_SPEED_13000_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_15000 0x10730UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 15G
#define NIG_REG_XGXS1_STATUS_SPEED_15000_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_16000 0x10734UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 16G
#define NIG_REG_XGXS1_STATUS_SPEED_16000_SIZE 1
#define NIG_REG_XGXS1_STATUS_SPEED_2500 0x10738UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 2.5G
#define NIG_REG_XGXS1_STATUS_SPEED_2500_SIZE 1
#define NIG_REG_XGXS1_STATUS_TXPLL_LOCK 0x1073cUL //ACCESS:R DataWidth:0x1 Description: when set XGXS0 TX PLL is locked.
#define NIG_REG_XGXS1_STATUS_TXPLL_LOCK_SIZE 1
#define NIG_REG_STAT0_BRB_OCTET 0x10740UL //ACCESS:WB_R DataWidth:0x40 Description: Rx statistics : User octets received for port0
#define NIG_REG_STAT0_BRB_OCTET_SIZE 2
#define NIG_REG_STAT1_BRB_OCTET 0x10790UL //ACCESS:WB_R DataWidth:0x40 Description: Rx statistics : User octets received for port1
#define NIG_REG_STAT1_BRB_OCTET_SIZE 2
#define NIG_REG_STAT2_BRB_OCTET 0x107e0UL //ACCESS:WB_R DataWidth:0x40 Description: Rx statistics : User octets received for LP
#define NIG_REG_STAT2_BRB_OCTET_SIZE 2
#define NIG_REG_DEBUG_PACKET_LB 0x10800UL //ACCESS:WB_W DataWidth:0x5a Description: Debug packet to LP from RBC; Data spelling:[63:0] data;[64] error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id;[71]flush;[72:73]-vnic_num;[89:74]-sideband_info
#define NIG_REG_DEBUG_PACKET_LB_SIZE 3
#define NIG_REG_DEBUG_PACKET_PORT0 0x10820UL //ACCESS:WB_W DataWidth:0x47 Description: Debug packet to port0 from RBC; Data spelling: [63:0] data; [64]error; [67:65]eop_bvalid - number of valid bytes in the last cycle (0=all bytes are valid); [68]eop - active on the last cycle of the packet; [69]sop - active on the first cycle of the packet; [70]parity - parity is active for all bits [69:0];
#define NIG_REG_DEBUG_PACKET_PORT0_SIZE 3
#define NIG_REG_DEBUG_PACKET_PORT1 0x10840UL //ACCESS:WB_W DataWidth:0x47 Description: Debug packet to port1 from RBC; Data spelling: [63:0] data; [64]error; [67:65]eop_bvalid - number of valid bytes in the last cycle (0=all bytes are valid); [68]eop - active on the last cycle of the packet; [69]sop - active on the first cycle of the packet; [70]parity - parity is active for all bits [69:0];
#define NIG_REG_DEBUG_PACKET_PORT1_SIZE 3
#define NIG_REG_LLH0_ACPI_BE_MEM_DATA 0x10880UL //ACCESS:WB DataWidth:0x40 SPLIT:4 Description: byte enable memory for 8 ACPI patterns.
#define NIG_REG_LLH0_ACPI_BE_MEM_DATA_SIZE 32
#define NIG_REG_LLH1_ACPI_BE_MEM_DATA 0x10900UL //ACCESS:WB DataWidth:0x40 SPLIT:4 Description: byte enable memory for 8 ACPI patterns.
#define NIG_REG_LLH1_ACPI_BE_MEM_DATA_SIZE 32
#define NIG_REG_INGRESS_MNG0_FIFO 0x12000UL //ACCESS:RW DataWidth:0x20 Description: Debug only. RX_MNG_PORT0_FIFO in NIG_RX_RMP.
#define NIG_REG_INGRESS_MNG0_FIFO_SIZE 1552
#define NIG_REG_INGRESS_MNG1_FIFO 0x14000UL //ACCESS:RW DataWidth:0x20 Description: Debug only.RX_MNG_PORT1_FIFO in NIG_RX_RMP.
#define NIG_REG_INGRESS_MNG1_FIFO_SIZE 1552
#define NIG_REG_LLFC_STATUS_BRB1_0 0x160e4UL //ACCESS:R DataWidth:0x10 Description: LLFC status for BRB1 input per port
#define NIG_REG_LLFC_STATUS_BRB1_0_SIZE 1
#define NIG_REG_LLFC_STATUS_BRB1_1 0x160e8UL //ACCESS:R DataWidth:0x10 Description: LLFC status for BRB1 input per port
#define NIG_REG_LLFC_STATUS_BRB1_1_SIZE 1
#define NIG_REG_LLFC_STATUS_TSDM_0 0x160ecUL //ACCESS:R DataWidth:0x10 Description: LLFC status for TSDM input per port
#define NIG_REG_LLFC_STATUS_TSDM_0_SIZE 1
#define NIG_REG_LLFC_STATUS_TSDM_1 0x160f0UL //ACCESS:R DataWidth:0x10 Description: LLFC status for TSDM input per port
#define NIG_REG_LLFC_STATUS_TSDM_1_SIZE 1
#define NIG_REG_LLFC_STATUS_USDM_0 0x160f4UL //ACCESS:R DataWidth:0x10 Description: LLFC status for USDM input per port
#define NIG_REG_LLFC_STATUS_USDM_0_SIZE 1
#define NIG_REG_LLFC_STATUS_USDM_1 0x160f8UL //ACCESS:R DataWidth:0x10 Description: LLFC status for USDM input per port
#define NIG_REG_LLFC_STATUS_USDM_1_SIZE 1
#define NIG_REG_LLH0_FUNC_EN 0x160fcUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: VLAN ID enabler. This is the per-function enabler for VNIC classification based on VLAN.
#define NIG_REG_LLH0_FUNC_EN_SIZE 1
#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100UL //ACCESS:RW DataWidth:0xc SPLIT:4 Description: VLAN ID for classification before ACPI search.
#define NIG_REG_LLH0_FUNC_VLAN_ID_SIZE 1
#define NIG_REG_LLH1_FUNC_EN 0x16104UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: VLAN ID enabler. This is the per-function enabler for VNIC classification based on VLAN.
#define NIG_REG_LLH1_FUNC_EN_SIZE 1
#define NIG_REG_LLH1_FUNC_VLAN_ID 0x16108UL //ACCESS:RW DataWidth:0xc SPLIT:4 Description: VLAN ID for classification before ACPI search.
#define NIG_REG_LLH1_FUNC_VLAN_ID_SIZE 1
#define NIG_REG_PAUSE_STATUS_BRB1_0 0x16114UL //ACCESS:R DataWidth:0x1 Description: pause status for BRB1 input per port
#define NIG_REG_PAUSE_STATUS_BRB1_0_SIZE 1
#define NIG_REG_PAUSE_STATUS_BRB1_1 0x16118UL //ACCESS:R DataWidth:0x1 Description: pause status for BRB1 input per port
#define NIG_REG_PAUSE_STATUS_BRB1_1_SIZE 1
#define NIG_REG_PAUSE_STATUS_TSDM_0 0x1611cUL //ACCESS:R DataWidth:0x1 Description: pause status for TSDM input per port
#define NIG_REG_PAUSE_STATUS_TSDM_0_SIZE 1
#define NIG_REG_PAUSE_STATUS_TSDM_1 0x16120UL //ACCESS:R DataWidth:0x1 Description: pause status for TSDM input per port
#define NIG_REG_PAUSE_STATUS_TSDM_1_SIZE 1
#define NIG_REG_PAUSE_STATUS_USDM_0 0x16124UL //ACCESS:R DataWidth:0x1 Description: pause status for USDM input per port
#define NIG_REG_PAUSE_STATUS_USDM_0_SIZE 1
#define NIG_REG_PAUSE_STATUS_USDM_1 0x16128UL //ACCESS:R DataWidth:0x1 Description: pause status for USDM input per port
#define NIG_REG_PAUSE_STATUS_USDM_1_SIZE 1
#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for MAC addresses to be matched with the VLAN ID for function identification.
#define NIG_REG_LLH0_FUNC_MEM_ENABLE_SIZE 8
#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for MAC addresses to be matched with the VLAN ID for function identification.
#define NIG_REG_LLH1_FUNC_MEM_ENABLE_SIZE 8
#define NIG_REG_LLH0_FUNC_MEM 0x16180UL //ACCESS:WB DataWidth:0x30 SPLIT:4 Description: MAC addresses to be matched with the VLAN ID for function identification.
#define NIG_REG_LLH0_FUNC_MEM_SIZE 16
#define NIG_REG_LLH1_FUNC_MEM 0x161c0UL //ACCESS:WB DataWidth:0x30 SPLIT:4 Description: MAC addresses to be matched with the VLAN ID for function identification.
#define NIG_REG_LLH1_FUNC_MEM_SIZE 16
#define NIG_REG_LATCH_STATUS_0 0x18000UL //ACCESS:RW DataWidth:0x1b Description: Latch for each interrupt from Unicore.b[0] status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete; b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status; b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn; b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete; b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status; b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete; b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet; b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g; b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact; b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx; b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx; b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs
#define NIG_REG_LATCH_STATUS_0_SIZE 2
#define NIG_REG_LATCH_STATUS_1 0x18008UL //ACCESS:RW DataWidth:0x1b Description: Latch for each interrupt from Unicore.b[0] status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete; b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status; b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn; b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete; b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status; b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete; b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet; b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g; b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact; b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx; b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx; b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs
#define NIG_REG_LATCH_STATUS_1_SIZE 2
#define NIG_REG_P0_LLH_ACPI_TAG_RM 0x180c8UL //ACCESS:RW DataWidth:0x6 SPLIT:4 Description: L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0 - outer VLAN; bit 1 - inner VLAN; bit 2 - LLC/SNAP; bit 3 - tag 0; bit 4 - tag 1; bit 5 - tag 2. Set these bits to 1's to enable the removal of the corresponding L2 tags when they are present in the receive packet. Clear the bit to keep the tag in the receive packet. This configuration is per function. This configuration replaces llh0_acpi_tag_strip.
#define NIG_REG_P0_LLH_ACPI_TAG_RM_SIZE 1
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_0 0x180d0UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 0.
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_0_SIZE 1
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_1 0x180d4UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 1.
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_1_SIZE 1
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_2 0x180d8UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 2.
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_2_SIZE 1
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_3 0x180dcUL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 3.
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_3_SIZE 1
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_4 0x180e0UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 4.
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_4_SIZE 1
#define NIG_REG_P1_LLH_ACPI_TAG_RM 0x18154UL //ACCESS:RW DataWidth:0x6 SPLIT:4 Description: L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0 - outer VLAN; bit 1 - inner VLAN; bit 2 - LLC/SNAP; bit 3 - tag 0; bit 4 - tag 1; bit 5 - tag 2. Set these bits to 1's to enable the removal of the corresponding L2 tags when they are present in the receive packet. Clear the bit to keep the tag in the receive packet. This configuration is per function. This configuration replaces llh0_acpi_tag_strip.
#define NIG_REG_P1_LLH_ACPI_TAG_RM_SIZE 1
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_0 0x18158UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 0.
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_0_SIZE 1
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_1 0x1815cUL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 1.
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_1_SIZE 1
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_2 0x18160UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 2.
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_2_SIZE 1
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_3 0x18164UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 3.
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_3_SIZE 1
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_4 0x18168UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 4.
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_4_SIZE 1
#define NIG_REG_STAT0_COS1_BRB_DISCARD 0x18278UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : In user packets discarded due to BRB backpressure for port 0 COS1
#define NIG_REG_STAT0_COS1_BRB_DISCARD_SIZE 1
#define NIG_REG_STAT0_COS1_BRB_TRUNCATE 0x1827cUL //ACCESS:R DataWidth:0x20 Description: Rx statistics : In user packets truncated due to BRB backpressure for port 0 COS1
#define NIG_REG_STAT0_COS1_BRB_TRUNCATE_SIZE 1
#define NIG_REG_STAT1_COS1_BRB_DISCARD 0x18280UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : In user packets discarded due to BRB backpressure for port 1 COS1
#define NIG_REG_STAT1_COS1_BRB_DISCARD_SIZE 1
#define NIG_REG_STAT1_COS1_BRB_TRUNCATE 0x18284UL //ACCESS:R DataWidth:0x20 Description: Rx statistics : In user packets truncated due to BRB backpressure for port 1 COS1
#define NIG_REG_STAT1_COS1_BRB_TRUNCATE_SIZE 1
#define NIG_REG_DBG_OUT_DATA_LSB 0x18294UL //ACCESS:R DataWidth:0x20 Description: Debug only: The 32 lower bits of nig_rbc_dbg_data output from nig_dbgmux to the DBG block.
#define NIG_REG_DBG_OUT_DATA_LSB_SIZE 1
#define NIG_REG_DBG_OUT_DATA_MSB 0x18298UL //ACCESS:R DataWidth:0x20 Description: Debug only: The 32 upper bits of nig_rbc_dbg_data output from nig_dbgmux to the DBG block.
#define NIG_REG_DBG_OUT_DATA_MSB_SIZE 1
#define NIG_REG_DBG_OUT_FRAME 0x1829cUL //ACCESS:R DataWidth:0x4 Description: Debug only: The 4 frame bits that go to the DBG block. Bit 0 is the frame of data byte 0. Bit 3 is the frame of data byte 3.
#define NIG_REG_DBG_OUT_FRAME_SIZE 1
#define NIG_REG_DBG_OUT_VALID 0x182a0UL //ACCESS:R DataWidth:0x4 Description: Debug only: The 4 valid bits that go to the DBG block. Bit 0 validates data byte 0. Bit 3 validates data byte 3.
#define NIG_REG_DBG_OUT_VALID_SIZE 1
#define NIG_REG_P0_TX_MNG_HOST_FIFO_FULL 0x182a4UL //ACCESS:R DataWidth:0x1 Description: FIFO full status of the MCP TX FIFO used for storing MCP packets forwarded to the host.
#define NIG_REG_P0_TX_MNG_HOST_FIFO_FULL_SIZE 1
#define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY 0x182a8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty status of the MCP TX FIFO used for storing MCP packets forwarded to the host.
#define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY_SIZE 1
#define NIG_REG_P0_STAT_MNG_HOST_PACKET_OUT 0x182acUL //ACCESS:R DataWidth:0x20 Description: Tx statistics : number of packets loaded into MCP TX FIFO for forwarding to the host.
#define NIG_REG_P0_STAT_MNG_HOST_PACKET_OUT_SIZE 1
#define NIG_REG_P0_STAT_MNG_HOST_OCTET_OUT 0x182b0UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : number of bytes loaded into MCP TX FIFO for forwarding to the host.
#define NIG_REG_P0_STAT_MNG_HOST_OCTET_OUT_SIZE 1
#define NIG_REG_P1_TX_MNG_HOST_FIFO_FULL 0x182b4UL //ACCESS:R DataWidth:0x1 Description: FIFO full status of the MCP TX FIFO used for storing MCP packets forwarded to the host.
#define NIG_REG_P1_TX_MNG_HOST_FIFO_FULL_SIZE 1
#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty status of the MCP TX FIFO used for storing MCP packets forwarded to the host.
#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY_SIZE 1
#define NIG_REG_P1_STAT_MNG_HOST_PACKET_OUT 0x182bcUL //ACCESS:R DataWidth:0x20 Description: Tx statistics : number of packets loaded into MCP TX FIFO for forwarding to the host.
#define NIG_REG_P1_STAT_MNG_HOST_PACKET_OUT_SIZE 1
#define NIG_REG_P1_STAT_MNG_HOST_OCTET_OUT 0x182c0UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : number of bytes loaded into MCP TX FIFO for forwarding to the host.
#define NIG_REG_P1_STAT_MNG_HOST_OCTET_OUT_SIZE 1
#define NIG_REG_P0_STAT_MNG_HOST_PACKET_DISCARD 0x182e4UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : number of packets from MCP to be forwarded to the host that got dropped due to BRB LB full backpressure.
#define NIG_REG_P0_STAT_MNG_HOST_PACKET_DISCARD_SIZE 1
#define NIG_REG_P0_STAT_MNG_HOST_PACKET_TRUNCATE 0x182e8UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : number of packets from MCP to be forwarded to the host that got truncated due to BRB LB full backpressure.
#define NIG_REG_P0_STAT_MNG_HOST_PACKET_TRUNCATE_SIZE 1
#define NIG_REG_P1_STAT_MNG_HOST_PACKET_DISCARD 0x182ecUL //ACCESS:R DataWidth:0x20 Description: Tx statistics : number of packets from MCP to be forwarded to the host that got dropped due to BRB LB full backpressure.
#define NIG_REG_P1_STAT_MNG_HOST_PACKET_DISCARD_SIZE 1
#define NIG_REG_P1_STAT_MNG_HOST_PACKET_TRUNCATE 0x182f0UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : number of packets from MCP to be forwarded to the host that got truncated due to BRB LB full backpressure.
#define NIG_REG_P1_STAT_MNG_HOST_PACKET_TRUNCATE_SIZE 1
#define NIG_REG_P0_STAT_TLLH_MNG_PKT_RCVD 0x182fcUL //ACCESS:R DataWidth:0x20 Description: Tx statistics : Management packets received in TLLH
#define NIG_REG_P0_STAT_TLLH_MNG_PKT_RCVD_SIZE 1
#define NIG_REG_P0_STAT_TLLH_MNG_OCTETS_RCVD 0x18300UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : Management octets received in TLLH
#define NIG_REG_P0_STAT_TLLH_MNG_OCTETS_RCVD_SIZE 1
#define NIG_REG_P0_STAT_HBUF_PACKET_DISCARD 0x18304UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : Management packets discarded due to lack of buffer space in HBUF.
#define NIG_REG_P0_STAT_HBUF_PACKET_DISCARD_SIZE 1
#define NIG_REG_P0_TLLH_FIFO_EMPTY 0x18308UL //ACCESS:R DataWidth:0x1 Description: TLLH FIFO is empty.
#define NIG_REG_P0_TLLH_FIFO_EMPTY_SIZE 1
#define NIG_REG_P0_TLLH_FIFO_FULL 0x1830cUL //ACCESS:R DataWidth:0x1 Description: TLLH FIFO is full.
#define NIG_REG_P0_TLLH_FIFO_FULL_SIZE 1
#define NIG_REG_P0_TLLH_RSLT_BUF_FULL 0x18310UL //ACCESS:R DataWidth:0x1 Description: TLLH local parsing result buffer is full.
#define NIG_REG_P0_TLLH_RSLT_BUF_FULL_SIZE 1
#define NIG_REG_P0_HBUF_DSCR_FULL 0x18314UL //ACCESS:R DataWidth:0x1 Description: Indication that HBUF descriptor FIFO is full.
#define NIG_REG_P0_HBUF_DSCR_FULL_SIZE 1
#define NIG_REG_P0_HBUF_DSCR_EMPTY 0x18318UL //ACCESS:R DataWidth:0x1 Description: Indication that HBUF descriptor FIFO is empty.
#define NIG_REG_P0_HBUF_DSCR_EMPTY_SIZE 1
#define NIG_REG_P0_HBUF_CONTEXT0 0x1831cUL //ACCESS:R DataWidth:0xc Description: Context of management packet buffer 0 of HBUF: {error[11]; eop_byte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_P0_HBUF_CONTEXT0_SIZE 1
#define NIG_REG_P0_HBUF_CONTEXT1 0x18320UL //ACCESS:R DataWidth:0xc Description: Context of management packet buffer 1 of HBUF: {error[11]; eop_byte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_P0_HBUF_CONTEXT1_SIZE 1
#define NIG_REG_P0_HBUF_CONTEXT2 0x18324UL //ACCESS:R DataWidth:0xc Description: Context of management packet buffer 2 of HBUF: {error[11]; eop_byte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_P0_HBUF_CONTEXT2_SIZE 1
#define NIG_REG_P0_HBUF_CONTEXT3 0x18328UL //ACCESS:R DataWidth:0xc Description: Context of management packet buffer 3 of HBUF: {error[11]; eop_byte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_P0_HBUF_CONTEXT3_SIZE 1
#define NIG_REG_P1_STAT_TLLH_MNG_PKT_RCVD 0x1832cUL //ACCESS:R DataWidth:0x20 Description: Tx statistics : Management packets received in TLLH
#define NIG_REG_P1_STAT_TLLH_MNG_PKT_RCVD_SIZE 1
#define NIG_REG_P1_STAT_TLLH_MNG_OCTETS_RCVD 0x18330UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : Management octets received in TLLH
#define NIG_REG_P1_STAT_TLLH_MNG_OCTETS_RCVD_SIZE 1
#define NIG_REG_P1_STAT_HBUF_PACKET_DISCARD 0x18334UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : Management packets discarded due to lack of buffer space in HBUF.
#define NIG_REG_P1_STAT_HBUF_PACKET_DISCARD_SIZE 1
#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338UL //ACCESS:R DataWidth:0x1 Description: TLLH FIFO is empty.
#define NIG_REG_P1_TLLH_FIFO_EMPTY_SIZE 1
#define NIG_REG_P1_TLLH_FIFO_FULL 0x1833cUL //ACCESS:R DataWidth:0x1 Description: TLLH FIFO is full.
#define NIG_REG_P1_TLLH_FIFO_FULL_SIZE 1
#define NIG_REG_P1_TLLH_RSLT_BUF_FULL 0x18340UL //ACCESS:R DataWidth:0x1 Description: TLLH local parsing result buffer is full.
#define NIG_REG_P1_TLLH_RSLT_BUF_FULL_SIZE 1
#define NIG_REG_P1_HBUF_DSCR_FULL 0x18344UL //ACCESS:R DataWidth:0x1 Description: Indication that HBUF descriptor FIFO is full.
#define NIG_REG_P1_HBUF_DSCR_FULL_SIZE 1
#define NIG_REG_P1_HBUF_DSCR_EMPTY 0x18348UL //ACCESS:R DataWidth:0x1 Description: Indication that HBUF descriptor FIFO is empty.
#define NIG_REG_P1_HBUF_DSCR_EMPTY_SIZE 1
#define NIG_REG_P1_HBUF_CONTEXT0 0x1834cUL //ACCESS:R DataWidth:0xc Description: Context of management packet buffer 0 of HBUF: {error[11]; eop_byte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_P1_HBUF_CONTEXT0_SIZE 1
#define NIG_REG_P1_HBUF_CONTEXT1 0x18350UL //ACCESS:R DataWidth:0xc Description: Context of management packet buffer 1 of HBUF: {error[11]; eop_byte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_P1_HBUF_CONTEXT1_SIZE 1
#define NIG_REG_P1_HBUF_CONTEXT2 0x18354UL //ACCESS:R DataWidth:0xc Description: Context of management packet buffer 2 of HBUF: {error[11]; eop_byte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_P1_HBUF_CONTEXT2_SIZE 1
#define NIG_REG_P1_HBUF_CONTEXT3 0x18358UL //ACCESS:R DataWidth:0xc Description: Context of management packet buffer 3 of HBUF: {error[11]; eop_byte_valid[10:8]; last cycle addr[7:0]}
#define NIG_REG_P1_HBUF_CONTEXT3_SIZE 1
#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for MAC addresses to be used for VNIC classification. These are the enable bits for addresses 8-15 of the 16 MAC addresses of each function.
#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE_SIZE 8
#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for MAC addresses to be used for VNIC classification. These are the enable bits for addresses 8-15 of the 16 MAC addresses of each function.
#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE_SIZE 8
#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480UL //ACCESS:WB DataWidth:0x30 SPLIT:4 Description: MAC addresses to be used for VNIC classification. These are addresses 8-15 of the 16 MAC addresses of each function.
#define NIG_REG_P0_LLH_FUNC_MEM2_SIZE 16
#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0UL //ACCESS:WB DataWidth:0x30 SPLIT:4 Description: MAC addresses to be used for VNIC classification. These are addresses 8-15 of the 16 MAC addresses of each function.
#define NIG_REG_P1_LLH_FUNC_MEM2_SIZE 16
#define NIG_REG_P0_RX_MACFIFO_EMPTY 0x18570UL //ACCESS:R DataWidth:0x1 Description: RX FIFO for receiving data from MAC is empty.
#define NIG_REG_P0_RX_MACFIFO_EMPTY_SIZE 1
#define NIG_REG_P0_RX_MACFIFO_FULL 0x18574UL //ACCESS:R DataWidth:0x1 Description: RX FIFO for receiving data from MAC is full.
#define NIG_REG_P0_RX_MACFIFO_FULL_SIZE 1
#define NIG_REG_P0_TX_MACFIFO_EMPTY 0x18578UL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is empty.
#define NIG_REG_P0_TX_MACFIFO_EMPTY_SIZE 1
#define NIG_REG_P0_TX_MACFIFO_FULL 0x1857cUL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is full.
#define NIG_REG_P0_TX_MACFIFO_FULL_SIZE 1
#define NIG_REG_P0_TX_MACFIFO_ALM_FULL 0x18580UL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is almost full.
#define NIG_REG_P0_TX_MACFIFO_ALM_FULL_SIZE 1
#define NIG_REG_P0_LLFC_STATUS_TO_MAC 0x18584UL //ACCESS:R DataWidth:0x10 Description: Current value of LLFC signal sent to MAC.
#define NIG_REG_P0_LLFC_STATUS_TO_MAC_SIZE 1
#define NIG_REG_P0_PAUSE_STATUS_TO_MAC 0x18588UL //ACCESS:R DataWidth:0x1 Description: Current value of PAUSE signal sent to MAC.
#define NIG_REG_P0_PAUSE_STATUS_TO_MAC_SIZE 1
#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858cUL //ACCESS:R DataWidth:0x1 Description: RX FIFO for receiving data from MAC is empty.
#define NIG_REG_P1_RX_MACFIFO_EMPTY_SIZE 1
#define NIG_REG_P1_RX_MACFIFO_FULL 0x18590UL //ACCESS:R DataWidth:0x1 Description: RX FIFO for receiving data from MAC is full.
#define NIG_REG_P1_RX_MACFIFO_FULL_SIZE 1
#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594UL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is empty.
#define NIG_REG_P1_TX_MACFIFO_EMPTY_SIZE 1
#define NIG_REG_P1_TX_MACFIFO_FULL 0x18598UL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is full.
#define NIG_REG_P1_TX_MACFIFO_FULL_SIZE 1
#define NIG_REG_P1_TX_MACFIFO_ALM_FULL 0x1859cUL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is almost full.
#define NIG_REG_P1_TX_MACFIFO_ALM_FULL_SIZE 1
#define NIG_REG_P1_LLFC_STATUS_TO_MAC 0x185a0UL //ACCESS:R DataWidth:0x10 Description: Current value of LLFC signal sent to MAC.
#define NIG_REG_P1_LLFC_STATUS_TO_MAC_SIZE 1
#define NIG_REG_P1_PAUSE_STATUS_TO_MAC 0x185a4UL //ACCESS:R DataWidth:0x1 Description: Current value of PAUSE signal sent to MAC.
#define NIG_REG_P1_PAUSE_STATUS_TO_MAC_SIZE 1
#define NIG_REG_XGXS0_SPEED_10000_LR_SR 0x185d4UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 10G-LR/SR.
#define NIG_REG_XGXS0_SPEED_10000_LR_SR_SIZE 1
#define NIG_REG_XGXS0_SPEED_10000_XFI 0x185d8UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 10G-XFI.
#define NIG_REG_XGXS0_SPEED_10000_XFI_SIZE 1
#define NIG_REG_XGXS0_SPEED_20000_CX4 0x185dcUL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 20G-CX4.
#define NIG_REG_XGXS0_SPEED_20000_CX4_SIZE 1
#define NIG_REG_XGXS0_SPEED_20000 0x185e0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 20G.
#define NIG_REG_XGXS0_SPEED_20000_SIZE 1
#define NIG_REG_XGXS0_FIBER_TXACT 0x185e4UL //ACCESS:R DataWidth:0x1 Description: Indicate TX traffic activity for the link.
#define NIG_REG_XGXS0_FIBER_TXACT_SIZE 1
#define NIG_REG_XGXS1_SPEED_10000_LR_SR 0x185e8UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 10G-LR/SR.
#define NIG_REG_XGXS1_SPEED_10000_LR_SR_SIZE 1
#define NIG_REG_XGXS1_SPEED_10000_XFI 0x185ecUL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 10G-XFI.
#define NIG_REG_XGXS1_SPEED_10000_XFI_SIZE 1
#define NIG_REG_XGXS1_SPEED_20000_CX4 0x185f0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 20G-CX4.
#define NIG_REG_XGXS1_SPEED_20000_CX4_SIZE 1
#define NIG_REG_XGXS1_SPEED_20000 0x185f4UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 20G.
#define NIG_REG_XGXS1_SPEED_20000_SIZE 1
#define NIG_REG_XGXS1_FIBER_TXACT 0x185f8UL //ACCESS:R DataWidth:0x1 Description: Indicate TX traffic activity for the link.
#define NIG_REG_XGXS1_FIBER_TXACT_SIZE 1
#define NIG_REG_XGXS0_LINK10G_DXGXS1 0x1860cUL //ACCESS:R DataWidth:0x1 Description: A '1' indicates that the second DXGXS has acquired link.
#define NIG_REG_XGXS0_LINK10G_DXGXS1_SIZE 1
#define NIG_REG_XGXS1_LINK10G_DXGXS1 0x18610UL //ACCESS:R DataWidth:0x1 Description: A '1' indicates that the second DXGXS has acquired link.
#define NIG_REG_XGXS1_LINK10G_DXGXS1_SIZE 1
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_5 0x18618UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 5.
#define NIG_REG_P1_TX_ARB_CURRENT_CREDIT_5_SIZE 1
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_5 0x1861cUL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 5.
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_5_SIZE 1
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_6 0x18620UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 6.
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_6_SIZE 1
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_7 0x18624UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 7.
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_7_SIZE 1
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_8 0x18628UL //ACCESS:R DataWidth:0x20 Description: Current upper 32 bits of the 33-bit value in TX arbiter credit register 8.
#define NIG_REG_P0_TX_ARB_CURRENT_CREDIT_8_SIZE 1
#define NIG_REG_EGRESS_DELAY2_EMPTY 0x1862cUL //ACCESS:R DataWidth:0x1 Description: PBF FIFO empty flag.
#define NIG_REG_EGRESS_DELAY2_EMPTY_SIZE 1
#define NIG_REG_EGRESS_DELAY3_EMPTY 0x18630UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO empty flag.
#define NIG_REG_EGRESS_DELAY3_EMPTY_SIZE 1
#define NIG_REG_EGRESS_DELAY4_EMPTY 0x18634UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO empty flag.
#define NIG_REG_EGRESS_DELAY4_EMPTY_SIZE 1
#define NIG_REG_EGRESS_DELAY5_EMPTY 0x18638UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO empty flag.
#define NIG_REG_EGRESS_DELAY5_EMPTY_SIZE 1
#define NIG_REG_EGRESS_DELAY2_FULL 0x1863cUL //ACCESS:R DataWidth:0x1 Description: PBF FIFO full flag.
#define NIG_REG_EGRESS_DELAY2_FULL_SIZE 1
#define NIG_REG_EGRESS_DELAY3_FULL 0x18640UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO full flag.
#define NIG_REG_EGRESS_DELAY3_FULL_SIZE 1
#define NIG_REG_EGRESS_DELAY4_FULL 0x18644UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO full flag.
#define NIG_REG_EGRESS_DELAY4_FULL_SIZE 1
#define NIG_REG_EGRESS_DELAY5_FULL 0x18648UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO full flag.
#define NIG_REG_EGRESS_DELAY5_FULL_SIZE 1
#define NIG_REG_STAT2_PBF_OCTETS 0x1864cUL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User octets transmitted from PBF
#define NIG_REG_STAT2_PBF_OCTETS_SIZE 1
#define NIG_REG_STAT3_PBF_OCTETS 0x18650UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User octets transmitted from PBF
#define NIG_REG_STAT3_PBF_OCTETS_SIZE 1
#define NIG_REG_STAT4_PBF_OCTETS 0x18654UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User octets transmitted from PBF
#define NIG_REG_STAT4_PBF_OCTETS_SIZE 1
#define NIG_REG_STAT5_PBF_OCTETS 0x18658UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User octets transmitted from PBF
#define NIG_REG_STAT5_PBF_OCTETS_SIZE 1
#define NIG_REG_STAT2_PBF_PACKET 0x1865cUL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User packets transmitted from PBF
#define NIG_REG_STAT2_PBF_PACKET_SIZE 1
#define NIG_REG_STAT3_PBF_PACKET 0x18660UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User packets transmitted from PBF
#define NIG_REG_STAT3_PBF_PACKET_SIZE 1
#define NIG_REG_STAT4_PBF_PACKET 0x18664UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User packets transmitted from PBF
#define NIG_REG_STAT4_PBF_PACKET_SIZE 1
#define NIG_REG_STAT5_PBF_PACKET 0x18668UL //ACCESS:R DataWidth:0x20 Description: Tx statistics : User packets transmitted from PBF
#define NIG_REG_STAT5_PBF_PACKET_SIZE 1
#define NIG_REG_P0_LLH_FUNC_DST_VIF0 0x1866cUL //ACCESS:RW DataWidth:0xe SPLIT:4 Description: Destination virtual interface value to be used for VNTAG classification.
#define NIG_REG_P0_LLH_FUNC_DST_VIF0_SIZE 1
#define NIG_REG_P0_LLH_FUNC_DST_VIF1 0x18670UL //ACCESS:RW DataWidth:0xe SPLIT:4 Description: Destination virtual interface value to be used for VNTAG classification.
#define NIG_REG_P0_LLH_FUNC_DST_VIF1_SIZE 1
#define NIG_REG_P1_LLH_FUNC_DST_VIF0 0x18674UL //ACCESS:RW DataWidth:0xe SPLIT:4 Description: Destination virtual interface value to be used for VNTAG classification.
#define NIG_REG_P1_LLH_FUNC_DST_VIF0_SIZE 1
#define NIG_REG_P1_LLH_FUNC_DST_VIF1 0x18678UL //ACCESS:RW DataWidth:0xe SPLIT:4 Description: Destination virtual interface value to be used for VNTAG classification.
#define NIG_REG_P1_LLH_FUNC_DST_VIF1_SIZE 1
#define NIG_REG_P0_LLH_PTP_MCP_BUF_TS_LSB 0x18748UL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. This location returns the lower 32 bits of timestamp value.
#define NIG_REG_P0_LLH_PTP_MCP_BUF_TS_LSB_SIZE 1
#define NIG_REG_P0_LLH_PTP_MCP_BUF_TS_MSB 0x1874cUL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. This location returns the upper 32 bits of timestamp value.
#define NIG_REG_P0_LLH_PTP_MCP_BUF_TS_MSB_SIZE 1
#define NIG_REG_P0_LLH_PTP_MCP_BUF_SEQID 0x18750UL //ACCESS:RW DataWidth:0x11 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. Bits [15:0] return the sequence ID of the packet. Bit 16 indicates the validity of the data in the buffer. Writing a 1 to bit 16 will clear the buffer.
#define NIG_REG_P0_LLH_PTP_MCP_BUF_SEQID_SIZE 1
#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB 0x18754UL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for the host. This location returns the lower 32 bits of timestamp value.
#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB_SIZE 1
#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB 0x18758UL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for the host. This location returns the upper 32 bits of timestamp value.
#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB_SIZE 1
#define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID 0x1875cUL //ACCESS:RW DataWidth:0x11 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for the host. Bits [15:0] return the sequence ID of the packet. Bit 16 indicates the validity of the data in the buffer. Writing a 1 to bit 16 will clear the buffer.
#define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID_SIZE 1
#define NIG_REG_P1_LLH_PTP_MCP_BUF_TS_LSB 0x18760UL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. This location returns the lower 32 bits of timestamp value.
#define NIG_REG_P1_LLH_PTP_MCP_BUF_TS_LSB_SIZE 1
#define NIG_REG_P1_LLH_PTP_MCP_BUF_TS_MSB 0x18764UL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. This location returns the upper 32 bits of timestamp value.
#define NIG_REG_P1_LLH_PTP_MCP_BUF_TS_MSB_SIZE 1
#define NIG_REG_P1_LLH_PTP_MCP_BUF_SEQID 0x18768UL //ACCESS:RW DataWidth:0x11 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. Bits [15:0] return the sequence ID of the packet. Bit 16 indicates the validity of the data in the buffer. Writing a 1 to bit 16 will clear the buffer.
#define NIG_REG_P1_LLH_PTP_MCP_BUF_SEQID_SIZE 1
#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB 0x1876cUL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for the host. This location returns the lower 32 bits of timestamp value.
#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB_SIZE 1
#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB 0x18770UL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for the host. This location returns the upper 32 bits of timestamp value.
#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB_SIZE 1
#define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID 0x18774UL //ACCESS:RW DataWidth:0x11 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for the host. Bits [15:0] return the sequence ID of the packet. Bit 16 indicates the validity of the data in the buffer. Writing a 1 to bit 16 will clear the buffer.
#define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID_SIZE 1
#define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB 0x187d8UL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. This location returns the lower 32 bits of timestamp value.
#define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB_SIZE 1
#define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB 0x187dcUL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. This location returns the upper 32 bits of timestamp value.
#define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB_SIZE 1
#define NIG_REG_P0_TLLH_PTP_BUF_SEQID 0x187e0UL //ACCESS:RW DataWidth:0x13 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 indicates the validity of the data in the buffer. Bit 17 indicates that the sequence ID is valid and it is waiting for the TX timestamp value. Bit 18 indicates whether the timestamp is from a SW request (value of 1) or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
#define NIG_REG_P0_TLLH_PTP_BUF_SEQID_SIZE 1
#define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB 0x187e4UL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. This location returns the lower 32 bits of timestamp value.
#define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB_SIZE 1
#define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB 0x187e8UL //ACCESS:R DataWidth:0x20 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. This location returns the upper 32 bits of timestamp value.
#define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB_SIZE 1
#define NIG_REG_P1_TLLH_PTP_BUF_SEQID 0x187ecUL //ACCESS:RW DataWidth:0x13 Description: Packet TimeSync information that is buffered in 1-deep FIFOs for TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 indicates the validity of the data in the buffer. Bit 17 indicates that the sequence ID is valid and it is waiting for the TX timestamp value. Bit 18 indicates whether the timestamp is from a SW request (value of 1) or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
#define NIG_REG_P1_TLLH_PTP_BUF_SEQID_SIZE 1
#define NIG_REG_TIMESYNC_GEN_REG 0x18800UL //ACCESS:WB DataWidth:0x40 Description: Addresses for TimeSync related registers in the timesync generator sub-module.
#define NIG_REG_TIMESYNC_GEN_REG_SIZE 64
#define NIG_REG_P0_RX_FC_STATUS 0x18a00UL //ACCESS:R DataWidth:0x10 Description: Current latched flow control (PFC/LLFC) priorities from the MAC.
#define NIG_REG_P0_RX_FC_STATUS_SIZE 1
#define NIG_REG_P1_RX_FC_STATUS 0x18a04UL //ACCESS:R DataWidth:0x10 Description: Current latched flow control (PFC/LLFC) priorities from the MAC.
#define NIG_REG_P1_RX_FC_STATUS_SIZE 1
#define NIG_REG_P0_LLH_FUNC_DST_VIF0_EN 0x18a08UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for the destination virtual interface value to be used for VNTAG classification.
#define NIG_REG_P0_LLH_FUNC_DST_VIF0_EN_SIZE 1
#define NIG_REG_P0_LLH_FUNC_DST_VIF1_EN 0x18a0cUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for the destination virtual interface value to be used for VNTAG classification.
#define NIG_REG_P0_LLH_FUNC_DST_VIF1_EN_SIZE 1
#define NIG_REG_P1_LLH_FUNC_DST_VIF0_EN 0x18a10UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for the destination virtual interface value to be used for VNTAG classification.
#define NIG_REG_P1_LLH_FUNC_DST_VIF0_EN_SIZE 1
#define NIG_REG_P1_LLH_FUNC_DST_VIF1_EN 0x18a14UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for the destination virtual interface value to be used for VNTAG classification.
#define NIG_REG_P1_LLH_FUNC_DST_VIF1_EN_SIZE 1
#define NIG_REG_P0_RX_PTP_TS_MSB_ERR 0x18a60UL //ACCESS:RW DataWidth:0x6 Description: Error detected in adjustment of the upper 32-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp value and the current free-running time are different by 2. Bits 1:0 reflects MAC timestamp value 31:30. Bits 3:2 reflects current time value 31:30. Bit 4 indicates that no adjustment is made to the upper 32-bit time from the current time. Bit 5 indicates that the upper 32-bit time is the decremented value from the current time. The error status is latched until cleared by writing a '1' to bit 0.
#define NIG_REG_P0_RX_PTP_TS_MSB_ERR_SIZE 1
#define NIG_REG_P0_TX_PTP_TS_MSB_ERR 0x18a64UL //ACCESS:RW DataWidth:0x6 Description: Error detected in adjustment of the upper 32-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp value and the current free-running time are different by 2. Bits 1:0 reflects MAC timestamp value 31:30. Bits 3:2 reflects current time value 31:30. Bit 4 indicates that no adjustment is made to the upper 32-bit time from the current time. Bit 5 indicates that the upper 32-bit time is the decremented value from the current time. The error status is latched until cleared by writing a '1' to bit 0.
#define NIG_REG_P0_TX_PTP_TS_MSB_ERR_SIZE 1
#define NIG_REG_P1_RX_PTP_TS_MSB_ERR 0x18a68UL //ACCESS:RW DataWidth:0x6 Description: Error detected in adjustment of the upper 32-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp value and the current free-running time are different by 2. Bits 1:0 reflects MAC timestamp value 31:30. Bits 3:2 reflects current time value 31:30. Bit 4 indicates that no adjustment is made to the upper 32-bit time from the current time. Bit 5 indicates that the upper 32-bit time is the decremented value from the current time. The error status is latched until cleared by writing a '1' to bit 0.
#define NIG_REG_P1_RX_PTP_TS_MSB_ERR_SIZE 1
#define NIG_REG_P1_TX_PTP_TS_MSB_ERR 0x18a6cUL //ACCESS:RW DataWidth:0x6 Description: Error detected in adjustment of the upper 32-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp value and the current free-running time are different by 2. Bits 1:0 reflects MAC timestamp value 31:30. Bits 3:2 reflects current time value 31:30. Bit 4 indicates that no adjustment is made to the upper 32-bit time from the current time. Bit 5 indicates that the upper 32-bit time is the decremented value from the current time. The error status is latched until cleared by writing a '1' to bit 0.
#define NIG_REG_P1_TX_PTP_TS_MSB_ERR_SIZE 1
#define NIG_REG_P0_LLH_FUNC_VLAN_ID1 0x18a70UL //ACCESS:RW DataWidth:0xc SPLIT:4 Description: Per-function outer VLAN ID to be used in VNIC classification. There are 4 VLAN IDs for each function. The legacy llh0/1_func_vlan_id register is used to specify VLAN ID 0.
#define NIG_REG_P0_LLH_FUNC_VLAN_ID1_SIZE 1
#define NIG_REG_P0_LLH_FUNC_VLAN_ID2 0x18a74UL //ACCESS:RW DataWidth:0xc SPLIT:4 Description: Per-function outer VLAN ID to be used in VNIC classification. There are 4 VLAN IDs for each function. The legacy llh0/1_func_vlan_id register is used to specify VLAN ID 0.
#define NIG_REG_P0_LLH_FUNC_VLAN_ID2_SIZE 1
#define NIG_REG_P0_LLH_FUNC_VLAN_ID3 0x18a78UL //ACCESS:RW DataWidth:0xc SPLIT:4 Description: Per-function outer VLAN ID to be used in VNIC classification. There are 4 VLAN IDs for each function. The legacy llh0/1_func_vlan_id register is used to specify VLAN ID 0.
#define NIG_REG_P0_LLH_FUNC_VLAN_ID3_SIZE 1
#define NIG_REG_P0_LLH_FUNC_VLAN_ID1_EN 0x18a7cUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
#define NIG_REG_P0_LLH_FUNC_VLAN_ID1_EN_SIZE 1
#define NIG_REG_P0_LLH_FUNC_VLAN_ID2_EN 0x18a80UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
#define NIG_REG_P0_LLH_FUNC_VLAN_ID2_EN_SIZE 1
#define NIG_REG_P0_LLH_FUNC_VLAN_ID3_EN 0x18a84UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
#define NIG_REG_P0_LLH_FUNC_VLAN_ID3_EN_SIZE 1
#define NIG_REG_P0_LLH_FUNC_VLAN_ID0_NOVLAN 0x18a88UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
#define NIG_REG_P0_LLH_FUNC_VLAN_ID0_NOVLAN_SIZE 1
#define NIG_REG_P0_LLH_FUNC_VLAN_ID1_NOVLAN 0x18a8cUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
#define NIG_REG_P0_LLH_FUNC_VLAN_ID1_NOVLAN_SIZE 1
#define NIG_REG_P0_LLH_FUNC_VLAN_ID2_NOVLAN 0x18a90UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
#define NIG_REG_P0_LLH_FUNC_VLAN_ID2_NOVLAN_SIZE 1
#define NIG_REG_P0_LLH_FUNC_VLAN_ID3_NOVLAN 0x18a94UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
#define NIG_REG_P0_LLH_FUNC_VLAN_ID3_NOVLAN_SIZE 1
#define NIG_REG_P1_LLH_FUNC_VLAN_ID1 0x18a98UL //ACCESS:RW DataWidth:0xc SPLIT:4 Description: Per-function outer VLAN ID to be used in VNIC classification. There are 4 VLAN IDs for each function. The legacy llh0/1_func_vlan_id register is used to specify VLAN ID 0.
#define NIG_REG_P1_LLH_FUNC_VLAN_ID1_SIZE 1
#define NIG_REG_P1_LLH_FUNC_VLAN_ID2 0x18a9cUL //ACCESS:RW DataWidth:0xc SPLIT:4 Description: Per-function outer VLAN ID to be used in VNIC classification. There are 4 VLAN IDs for each function. The legacy llh0/1_func_vlan_id register is used to specify VLAN ID 0.
#define NIG_REG_P1_LLH_FUNC_VLAN_ID2_SIZE 1
#define NIG_REG_P1_LLH_FUNC_VLAN_ID3 0x18aa0UL //ACCESS:RW DataWidth:0xc SPLIT:4 Description: Per-function outer VLAN ID to be used in VNIC classification. There are 4 VLAN IDs for each function. The legacy llh0/1_func_vlan_id register is used to specify VLAN ID 0.
#define NIG_REG_P1_LLH_FUNC_VLAN_ID3_SIZE 1
#define NIG_REG_P1_LLH_FUNC_VLAN_ID1_EN 0x18aa4UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
#define NIG_REG_P1_LLH_FUNC_VLAN_ID1_EN_SIZE 1
#define NIG_REG_P1_LLH_FUNC_VLAN_ID2_EN 0x18aa8UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
#define NIG_REG_P1_LLH_FUNC_VLAN_ID2_EN_SIZE 1
#define NIG_REG_P1_LLH_FUNC_VLAN_ID3_EN 0x18aacUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
#define NIG_REG_P1_LLH_FUNC_VLAN_ID3_EN_SIZE 1
#define NIG_REG_P1_LLH_FUNC_VLAN_ID0_NOVLAN 0x18ab0UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
#define NIG_REG_P1_LLH_FUNC_VLAN_ID0_NOVLAN_SIZE 1
#define NIG_REG_P1_LLH_FUNC_VLAN_ID1_NOVLAN 0x18ab4UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
#define NIG_REG_P1_LLH_FUNC_VLAN_ID1_NOVLAN_SIZE 1
#define NIG_REG_P1_LLH_FUNC_VLAN_ID2_NOVLAN 0x18ab8UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
#define NIG_REG_P1_LLH_FUNC_VLAN_ID2_NOVLAN_SIZE 1
#define NIG_REG_P1_LLH_FUNC_VLAN_ID3_NOVLAN 0x18abcUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
#define NIG_REG_P1_LLH_FUNC_VLAN_ID3_NOVLAN_SIZE 1
#define NIG_REG_EGRESS_BMAC_PUSH_ALM_FULL 0x10024UL //ACCESS:R DataWidth:0x4 Description: Almoust full for BMAC FIFO in NIG_TX_PORT0 and NIG_TX_PORT1
#define NIG_REG_EGRESS_BMAC_PUSH_ALM_FULL_SIZE 1
#define NIG_REG_NIG_EMAC0_EN 0x1003cUL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to EMAC0. When set enables the EMAC0 block.
#define NIG_REG_NIG_EMAC0_EN_SIZE 1
#define NIG_REG_NIG_EMAC1_EN 0x10040UL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to EMAC1. When set enables the EMAC1 block.
#define NIG_REG_NIG_EMAC1_EN_SIZE 1
#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044UL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to TX_EMAC0. When set indicates to the EMAC0 to strip the CRC from the ingress packets.
#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC_SIZE 1
#define NIG_REG_NIG_INGRESS_EMAC1_NO_CRC 0x10048UL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to TX_EMAC1. When set indicates to the EMAC1 to strip the CRC from the ingress packets.
#define NIG_REG_NIG_INGRESS_EMAC1_NO_CRC_SIZE 1
#define NIG_REG_NIG_EGRESS_EMAC0_NO_CRC 0x1004cUL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to TX_EMAC0. When set indicates to the EMAC0 not to append CRC to the egress packets.
#define NIG_REG_NIG_EGRESS_EMAC0_NO_CRC_SIZE 1
#define NIG_REG_NIG_EGRESS_EMAC1_NO_CRC 0x10050UL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to TX_EMAC1. When set indicates to the EMAC1 not to append CRC to the egress packets.
#define NIG_REG_NIG_EGRESS_EMAC1_NO_CRC_SIZE 1
#define NIG_REG_EMAC0_IN_EN 0x100a4UL //ACCESS:R DataWidth:0x1 Description: Input enable for RX_EMAC0 IF
#define NIG_REG_EMAC0_IN_EN_SIZE 1
#define NIG_REG_EMAC1_IN_EN 0x100a8UL //ACCESS:R DataWidth:0x1 Description: Input enable for RX_EMAC1 IF
#define NIG_REG_EMAC1_IN_EN_SIZE 1
#define NIG_REG_BMAC0_IN_EN 0x100acUL //ACCESS:R DataWidth:0x1 Description: Input enable for RX_BMAC0 IF
#define NIG_REG_BMAC0_IN_EN_SIZE 1
#define NIG_REG_BMAC1_IN_EN 0x100b0UL //ACCESS:R DataWidth:0x1 Description: Input enable for RX_BMAC1 IF
#define NIG_REG_BMAC1_IN_EN_SIZE 1
#define NIG_REG_BMAC0_OUT_EN 0x100e0UL //ACCESS:R DataWidth:0x1 Description: output enable for TX_BMAC0 IF
#define NIG_REG_BMAC0_OUT_EN_SIZE 1
#define NIG_REG_BMAC1_OUT_EN 0x100e4UL //ACCESS:R DataWidth:0x1 Description: output enable for TX_BMAC1 IF
#define NIG_REG_BMAC1_OUT_EN_SIZE 1
#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8UL //ACCESS:R DataWidth:0x1 Description: output enable for RX_BMAC0_REGS IF
#define NIG_REG_BMAC0_REGS_OUT_EN_SIZE 1
#define NIG_REG_BMAC1_REGS_OUT_EN 0x100ecUL //ACCESS:R DataWidth:0x1 Description: output enable for RX_BMAC1_REGS IF
#define NIG_REG_BMAC1_REGS_OUT_EN_SIZE 1
#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110UL //ACCESS:R DataWidth:0x1 Description: output enable for TX BMAC pause port 0 IF
#define NIG_REG_BMAC0_PAUSE_OUT_EN_SIZE 1
#define NIG_REG_BMAC1_PAUSE_OUT_EN 0x10114UL //ACCESS:R DataWidth:0x1 Description: output enable for TX BMAC pause port 1 IF
#define NIG_REG_BMAC1_PAUSE_OUT_EN_SIZE 1
#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118UL //ACCESS:R DataWidth:0x1 Description: output enable for TX EMAC pause port 0 IF
#define NIG_REG_EMAC0_PAUSE_OUT_EN_SIZE 1
#define NIG_REG_EMAC1_PAUSE_OUT_EN 0x1011cUL //ACCESS:R DataWidth:0x1 Description: output enable for TX EMAC pause port 1 IF
#define NIG_REG_EMAC1_PAUSE_OUT_EN_SIZE 1
#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120UL //ACCESS:R DataWidth:0x1 Description: Output enable to EMAC0
#define NIG_REG_EGRESS_EMAC0_OUT_EN_SIZE 1
#define NIG_REG_EGRESS_EMAC1_OUT_EN 0x10124UL //ACCESS:R DataWidth:0x1 Description: Output enable to EMAC1
#define NIG_REG_EGRESS_EMAC1_OUT_EN_SIZE 1
#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0UL //ACCESS:R DataWidth:0x1 Description: selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS
#define NIG_REG_XGXS_SERDES0_MODE_SEL_SIZE 1
#define NIG_REG_XGXS_SERDES1_MODE_SEL 0x102e4UL //ACCESS:R DataWidth:0x1 Description: selection for port1 for NIG_MUX block : 0 = SerDes; 1 = XGXS
#define NIG_REG_XGXS_SERDES1_MODE_SEL_SIZE 1
#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8UL //ACCESS:R DataWidth:0x2 Description: selection for XGXS lane of port 0 in NIG_MUX block
#define NIG_REG_XGXS_LANE_SEL_P0_SIZE 1
#define NIG_REG_XGXS_LANE_SEL_P1 0x102ecUL //ACCESS:R DataWidth:0x2 Description: selection for XGXS lane of port 1 in NIG_MUX block
#define NIG_REG_XGXS_LANE_SEL_P1_SIZE 1
#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338UL //ACCESS:R DataWidth:0x1 Description: control to xgxs; 0 - clause 45; 1 - clause 22
#define NIG_REG_XGXS0_CTRL_MD_ST_SIZE 1
#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033cUL //ACCESS:R DataWidth:0x5 Description: control to xgxs - CL45 DEVAD
#define NIG_REG_XGXS0_CTRL_MD_DEVAD_SIZE 1
#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340UL //ACCESS:R DataWidth:0x5 Description: control to xgxs - CL22 PHY_ADD and CL45 PRTAD
#define NIG_REG_XGXS0_CTRL_PHY_ADDR_SIZE 1
#define NIG_REG_XGXS0_CTRL_REMOTEMDIOEN 0x10344UL //ACCESS:R DataWidth:0x1 Description: control to xgxs - remote PHY in-band MDIO
#define NIG_REG_XGXS0_CTRL_REMOTEMDIOEN_SIZE 1
#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348UL //ACCESS:R DataWidth:0x1 Description: control to xgxs - remote PHY in-band MDIO
#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST_SIZE 1
#define NIG_REG_XGXS0_CTRL_PLL_BYPASS 0x1034cUL //ACCESS:R DataWidth:0x1 Description: control to xgxs - PLL bypass
#define NIG_REG_XGXS0_CTRL_PLL_BYPASS_SIZE 1
#define NIG_REG_XGXS1_CTRL_MD_ST 0x10350UL //ACCESS:R DataWidth:0x1 Description: control to xgxs; 0 - clause 45; 1 - clause 22
#define NIG_REG_XGXS1_CTRL_MD_ST_SIZE 1
#define NIG_REG_XGXS1_CTRL_MD_DEVAD 0x10354UL //ACCESS:R DataWidth:0x5 Description: control to xgxs - CL45 DEVAD
#define NIG_REG_XGXS1_CTRL_MD_DEVAD_SIZE 1
#define NIG_REG_XGXS1_CTRL_PHY_ADDR 0x10358UL //ACCESS:R DataWidth:0x5 Description: control to xgxs - CL22 PHY_ADD and CL45 PRTAD
#define NIG_REG_XGXS1_CTRL_PHY_ADDR_SIZE 1
#define NIG_REG_XGXS1_CTRL_REMOTEMDIOEN 0x1035cUL //ACCESS:R DataWidth:0x1 Description: control to xgxs - remote PHY in-band MDIO
#define NIG_REG_XGXS1_CTRL_REMOTEMDIOEN_SIZE 1
#define NIG_REG_XGXS1_CTRL_EXTREMOTEMDIOST 0x10360UL //ACCESS:R DataWidth:0x1 Description: control to xgxs - remote PHY in-band MDIO
#define NIG_REG_XGXS1_CTRL_EXTREMOTEMDIOST_SIZE 1
#define NIG_REG_XGXS1_CTRL_PLL_BYPASS 0x10364UL //ACCESS:R DataWidth:0x1 Description: control to xgxs - PLL bypass
#define NIG_REG_XGXS1_CTRL_PLL_BYPASS_SIZE 1
#define NIG_REG_SERDES0_CTRL_PLL_BYPASS 0x10368UL //ACCESS:R DataWidth:0x1 Description: control to serdes - PLL bypass
#define NIG_REG_SERDES0_CTRL_PLL_BYPASS_SIZE 1
#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036cUL //ACCESS:R DataWidth:0x1 Description: control to serdes; 0 - clause 45; 1 - clause 22
#define NIG_REG_SERDES0_CTRL_MD_ST_SIZE 1
#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370UL //ACCESS:R DataWidth:0x5 Description: control to serdes - CL45 DEVAD
#define NIG_REG_SERDES0_CTRL_MD_DEVAD_SIZE 1
#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374UL //ACCESS:R DataWidth:0x5 Description: control to serdes - CL22 PHY_ADD and CL45 PRTAD
#define NIG_REG_SERDES0_CTRL_PHY_ADDR_SIZE 1
#define NIG_REG_SERDES1_CTRL_PLL_BYPASS 0x10378UL //ACCESS:R DataWidth:0x1 Description: control to serdes - PLL bypass
#define NIG_REG_SERDES1_CTRL_PLL_BYPASS_SIZE 1
#define NIG_REG_SERDES1_CTRL_MD_ST 0x1037cUL //ACCESS:R DataWidth:0x1 Description: control to serdes; 0 - clause 45; 1 - clause 22
#define NIG_REG_SERDES1_CTRL_MD_ST_SIZE 1
#define NIG_REG_SERDES1_CTRL_MD_DEVAD 0x10380UL //ACCESS:R DataWidth:0x5 Description: control to serdes - CL45 DEVAD
#define NIG_REG_SERDES1_CTRL_MD_DEVAD_SIZE 1
#define NIG_REG_SERDES1_CTRL_PHY_ADDR 0x10384UL //ACCESS:R DataWidth:0x5 Description: control to serdes - CL22 PHY_ADD and CL45 PRTAD
#define NIG_REG_SERDES1_CTRL_PHY_ADDR_SIZE 1
#define NIG_REG_NIG_PRTY_STS 0x103d0UL //ACCESS:R DataWidth:0x20 Description: Legacy E1 and E1H location for parity error status register.
#define NIG_REG_NIG_PRTY_STS_SIZE 1
#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4UL //ACCESS:R DataWidth:0x20 Description: Legacy E1 and E1H location for parity error status clear register.
#define NIG_REG_NIG_PRTY_STS_CLR_SIZE 1
#define NIG_REG_NIG_PRTY_STS_WR 0x103d8UL //ACCESS:R DataWidth:0x20 Description: Legacy E1 and E1H location for parity error status write register.
#define NIG_REG_NIG_PRTY_STS_WR_SIZE 1
#define NIG_REG_NIG_PRTY_MASK 0x103dcUL //ACCESS:R DataWidth:0x20 Description: Legacy E1 and E1H location for parity error mask register.
#define NIG_REG_NIG_PRTY_MASK_SIZE 1
#define NIG_REG_EGRESS_BMAC0_ALM_FULL 0x10400UL //ACCESS:R DataWidth:0x1 Description: FIFO almost full in BMAC_FIFO in NIG_TX_PORT0
#define NIG_REG_EGRESS_BMAC0_ALM_FULL_SIZE 1
#define NIG_REG_EGRESS_BMAC0_EMPTY 0x10404UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in BMAC_FIFO in NIG_TX_PORT0
#define NIG_REG_EGRESS_BMAC0_EMPTY_SIZE 1
#define NIG_REG_EGRESS_BMAC0_FULL 0x10408UL //ACCESS:R DataWidth:0x1 Description: FIFO full in BMAC_FIFO in NIG_TX_PORT0
#define NIG_REG_EGRESS_BMAC0_FULL_SIZE 1
#define NIG_REG_EGRESS_BMAC1_ALM_FULL 0x1040cUL //ACCESS:R DataWidth:0x1 Description: FIFO almost full in BMAC_FIFO in NIG_TX_PORT1
#define NIG_REG_EGRESS_BMAC1_ALM_FULL_SIZE 1
#define NIG_REG_EGRESS_BMAC1_EMPTY 0x10410UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in BMAC_FIFO in NIG_TX_PORT1
#define NIG_REG_EGRESS_BMAC1_EMPTY_SIZE 1
#define NIG_REG_EGRESS_BMAC1_FULL 0x10414UL //ACCESS:R DataWidth:0x1 Description: FIFO full in BMAC_FIFO in NIG_TX_PORT1
#define NIG_REG_EGRESS_BMAC1_FULL_SIZE 1
#define NIG_REG_EGRESS_EMAC0_POP_EMPTY 0x10430UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_POP_FIFO in NIG_TX_EMAC0
#define NIG_REG_EGRESS_EMAC0_POP_EMPTY_SIZE 1
#define NIG_REG_EGRESS_EMAC0_POP_FULL 0x10434UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_POP_FIFO in NIG_TX_EMAC0
#define NIG_REG_EGRESS_EMAC0_POP_FULL_SIZE 1
#define NIG_REG_EGRESS_EMAC0_PUSH_ALM_FULL 0x10438UL //ACCESS:R DataWidth:0x1 Description: FIFO almost full in emac_FIFO in NIG_TX_PORT0
#define NIG_REG_EGRESS_EMAC0_PUSH_ALM_FULL_SIZE 1
#define NIG_REG_EGRESS_EMAC0_PUSH_EMPTY 0x1043cUL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_PUSH_FIFO in NIG_TX_PORT0
#define NIG_REG_EGRESS_EMAC0_PUSH_EMPTY_SIZE 1
#define NIG_REG_EGRESS_EMAC0_PUSH_FULL 0x10440UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_PUSH_FIFO in NIG_TX_PORT0
#define NIG_REG_EGRESS_EMAC0_PUSH_FULL_SIZE 1
#define NIG_REG_EGRESS_EMAC1_POP_EMPTY 0x10444UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_POP_FIFO in NIG_TX_EMAC1
#define NIG_REG_EGRESS_EMAC1_POP_EMPTY_SIZE 1
#define NIG_REG_EGRESS_EMAC1_POP_FULL 0x10448UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_POP_FIFO in NIG_TX_EMAC1
#define NIG_REG_EGRESS_EMAC1_POP_FULL_SIZE 1
#define NIG_REG_EGRESS_EMAC1_PUSH_ALM_FULL 0x1044cUL //ACCESS:R DataWidth:0x1 Description: FIFO almost full in emac_FIFO in NIG_TX_PORT1
#define NIG_REG_EGRESS_EMAC1_PUSH_ALM_FULL_SIZE 1
#define NIG_REG_EGRESS_EMAC1_PUSH_EMPTY 0x10450UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_PUSH_FIFO in NIG_TX_PORT1
#define NIG_REG_EGRESS_EMAC1_PUSH_EMPTY_SIZE 1
#define NIG_REG_EGRESS_EMAC1_PUSH_FULL 0x10454UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_PUSH_FIFO in NIG_TX_PORT1
#define NIG_REG_EGRESS_EMAC1_PUSH_FULL_SIZE 1
#define NIG_REG_INGRESS_BMAC0_EMPTY 0x104b0UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in BMAC_FIFO in NIG_RX_PORT0
#define NIG_REG_INGRESS_BMAC0_EMPTY_SIZE 1
#define NIG_REG_INGRESS_BMAC0_FULL 0x104b4UL //ACCESS:R DataWidth:0x1 Description: FIFO full in BMAC_FIFO in NIG_RX_PORT0
#define NIG_REG_INGRESS_BMAC0_FULL_SIZE 1
#define NIG_REG_INGRESS_BMAC1_EMPTY 0x104b8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in BMAC_FIFO in NIG_RX_PORT1
#define NIG_REG_INGRESS_BMAC1_EMPTY_SIZE 1
#define NIG_REG_INGRESS_BMAC1_FULL 0x104bcUL //ACCESS:R DataWidth:0x1 Description: FIFO full in BMAC_FIFO in NIG_RX_PORT1
#define NIG_REG_INGRESS_BMAC1_FULL_SIZE 1
#define NIG_REG_INGRESS_EMAC0_POP_EMPTY 0x104c0UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_POP_FIFO in NIG_RX_PORT0
#define NIG_REG_INGRESS_EMAC0_POP_EMPTY_SIZE 1
#define NIG_REG_INGRESS_EMAC0_POP_FULL 0x104c4UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_POP_FIFO in NIG_RX_PORT0
#define NIG_REG_INGRESS_EMAC0_POP_FULL_SIZE 1
#define NIG_REG_INGRESS_EMAC0_PUSH_EMPTY 0x104c8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_PUSH_FIFO in NIG_RX_EMAC0
#define NIG_REG_INGRESS_EMAC0_PUSH_EMPTY_SIZE 1
#define NIG_REG_INGRESS_EMAC0_PUSH_FULL 0x104ccUL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_PUSH_FIFO in NIG_RX_EMAC0
#define NIG_REG_INGRESS_EMAC0_PUSH_FULL_SIZE 1
#define NIG_REG_INGRESS_EMAC1_POP_EMPTY 0x104d0UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_POP_FIFO in NIG_RX_PORT1
#define NIG_REG_INGRESS_EMAC1_POP_EMPTY_SIZE 1
#define NIG_REG_INGRESS_EMAC1_POP_FULL 0x104d4UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_POP_FIFO in NIG_RX_PORT1
#define NIG_REG_INGRESS_EMAC1_POP_FULL_SIZE 1
#define NIG_REG_INGRESS_EMAC1_PUSH_EMPTY 0x104d8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_PUSH_FIFO in NIG_RX_EMAC1
#define NIG_REG_INGRESS_EMAC1_PUSH_EMPTY_SIZE 1
#define NIG_REG_INGRESS_EMAC1_PUSH_FULL 0x104dcUL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_PUSH_FIFO in NIG_RX_EMAC1
#define NIG_REG_INGRESS_EMAC1_PUSH_FULL_SIZE 1
#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750UL //ACCESS:WB_R DataWidth:0x24 Description: Tx statistics : Number of packets from emac0 or bmac0 that between 1024 and 1522 bytes for port0
#define NIG_REG_STAT0_EGRESS_MAC_PKT0_SIZE 2
#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760UL //ACCESS:WB_R DataWidth:0x24 Description: Tx statistics : Number of packets from emac0 or bmac0 that between 1523 bytes and above for port0
#define NIG_REG_STAT0_EGRESS_MAC_PKT1_SIZE 2
#define NIG_REG_STAT0_INGRESS_MAC_PKT0 0x10770UL //ACCESS:WB_R DataWidth:0x24 Description: Rx statistics : Number of packets from emac0 or bmac0 that between 1024 and 1522 bytes for port0
#define NIG_REG_STAT0_INGRESS_MAC_PKT0_SIZE 2
#define NIG_REG_STAT0_INGRESS_MAC_PKT1 0x10780UL //ACCESS:WB_R DataWidth:0x24 Description: Rx statistics : Number of packets from emac0 or bmac0 that between 1523 bytes and above for port0
#define NIG_REG_STAT0_INGRESS_MAC_PKT1_SIZE 2
#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0UL //ACCESS:WB_R DataWidth:0x24 Description: Tx statistics : Number of packets from emac1 or bmac1 that between 1024 and 1522 bytes for port1
#define NIG_REG_STAT1_EGRESS_MAC_PKT0_SIZE 2
#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0UL //ACCESS:WB_R DataWidth:0x24 Description: Tx statistics : Number of packets from emac1 or bmac1 that between 1523 bytes and above for port1
#define NIG_REG_STAT1_EGRESS_MAC_PKT1_SIZE 2
#define NIG_REG_STAT1_INGRESS_MAC_PKT0 0x107c0UL //ACCESS:WB_R DataWidth:0x24 Description: Rx statistics : Number of packets from emac1 or bmac1 that between 1024 and 1522 bytes for port1
#define NIG_REG_STAT1_INGRESS_MAC_PKT0_SIZE 2
#define NIG_REG_STAT1_INGRESS_MAC_PKT1 0x107d0UL //ACCESS:WB_R DataWidth:0x24 Description: Rx statistics : Number of packets from emac1 or bmac1 that between 1523 bytes and above for port1
#define NIG_REG_STAT1_INGRESS_MAC_PKT1_SIZE 2
#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00UL //ACCESS:R DataWidth:0x30 Description: This address space contains BMAC0 registers. The BMAC registers are described in appendix A. In order to access the BMAC0 registers; the base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be added to each BMAC register offset
#define NIG_REG_INGRESS_BMAC0_MEM_SIZE 256
#define NIG_REG_INGRESS_BMAC1_MEM 0x11000UL //ACCESS:R DataWidth:0x30 Description: This address space contains BMAC1 registers. The BMAC registers are described in appendix A. In order to access the BMAC0 registers; the base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be added to each BMAC register offset
#define NIG_REG_INGRESS_BMAC1_MEM_SIZE 256
#define NIG_REG_EGRESS_EMAC_PUSH_ALM_FULL 0x16000UL //ACCESS:R DataWidth:0x4 Description: Almoust full for EMAC SYNC FIFO in NIG_TX_PORT0 and NIG_TX_PORT1
#define NIG_REG_EGRESS_EMAC_PUSH_ALM_FULL_SIZE 1
#define NIG_REG_EGRESS_OUTER_VLAN_HEADER_0 0x16090UL //ACCESS:R DataWidth:0x20 Description: Ouetr vlan header for management packets in TX for port0
#define NIG_REG_EGRESS_OUTER_VLAN_HEADER_0_SIZE 1
#define NIG_REG_EGRESS_OUTER_VLAN_HEADER_1 0x16094UL //ACCESS:R DataWidth:0x20 Description: Ouetr vlan header for management packets in TX for port1
#define NIG_REG_EGRESS_OUTER_VLAN_HEADER_1_SIZE 1
#define NIG_REG_EGRESS_OUTER_VLAN_HEADER_INSERT_0 0x16098UL //ACCESS:R DataWidth:0x1 Description: Enable for insert outer vlan header ~egress_outer_vlan_header.egress_outer_vlan_header for port0
#define NIG_REG_EGRESS_OUTER_VLAN_HEADER_INSERT_0_SIZE 1
#define NIG_REG_EGRESS_OUTER_VLAN_HEADER_INSERT_1 0x1609cUL //ACCESS:R DataWidth:0x1 Description: Enable for insert outer vlan header ~egress_outer_vlan_header.egress_outer_vlan_header for port1
#define NIG_REG_EGRESS_OUTER_VLAN_HEADER_INSERT_1_SIZE 1
#define NIG_REG_LLFC_STATUS_BMAC_0 0x160dcUL //ACCESS:R DataWidth:0x10 Description: LLFC status for BMAC output port
#define NIG_REG_LLFC_STATUS_BMAC_0_SIZE 1
#define NIG_REG_LLFC_STATUS_BMAC_1 0x160e0UL //ACCESS:R DataWidth:0x10 Description: LLFC status for BMAC output port
#define NIG_REG_LLFC_STATUS_BMAC_1_SIZE 1
#define NIG_REG_PAUSE_STATUS_BMAC_0 0x1610cUL //ACCESS:R DataWidth:0x1 Description: pause status for BMAC output port
#define NIG_REG_PAUSE_STATUS_BMAC_0_SIZE 1
#define NIG_REG_PAUSE_STATUS_BMAC_1 0x16110UL //ACCESS:R DataWidth:0x1 Description: pause status for BMAC output port
#define NIG_REG_PAUSE_STATUS_BMAC_1_SIZE 1
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4UL //ACCESS:R DataWidth:0xf Description: Specify the client number to be assigned to each priority of the strict priority arbiter. Priority 0 is the highest priority. Bits [2:0] are for priority 0 client; bits [14:12] are for priority 4 client. The clients are assigned the following IDs: 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000) for management at priority 0; debug traffic at priorities 1 and 2; COS0 traffic at priority 3; and COS1 traffic at priority 4.
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT_SIZE 1
#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0UL //ACCESS:R DataWidth:0xf Description: Specify which of the credit registers the client is to be mapped to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For clients that are not subject to WFQ credit blocking - their specifications here are not used.
#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP_SIZE 1
#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT 0x18230UL //ACCESS:R DataWidth:0xf Description: Specify the client number to be assigned to each priority of the strict priority arbiter. Priority 0 is the highest priority. Bits [2:0] are for priority 0 client; bits [14:12] are for priority 4 client. The clients are assigned the following IDs: 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000) for management at priority 0; debug traffic at priorities 1 and 2; COS0 traffic at priority 3; and COS1 traffic at priority 4.
#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT_SIZE 1
#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP 0x1823cUL //ACCESS:R DataWidth:0xf Description: Specify which of the credit registers the client is to be mapped to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For clients that are not subject to WFQ credit blocking - their specifications here are not used.
#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP_SIZE 1
#define NIG_REG_PORT4MODE_EN 0x18274UL //ACCESS:R DataWidth:0x1 Description: Set this bit to indicate that this path is used for 4-port mode. Clear this bit to select 2-port mode. This bit is used to decide how th route the two traffic flows from PBF to ports 0 and 1 of this path. In 2-port mode - both flows goes to port 0. In 4-port mode - IF0 flow goes to port 0; IF1 flow goes to port 1.
#define NIG_REG_PORT4MODE_EN_SIZE 1
#define NIG_REG_NIG_UNUSED_EMPTY_0 0x103e0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_0_SIZE 8
#define NIG_REG_NIG_UNUSED_EMPTY_1 0x107f0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_1_SIZE 4
#define NIG_REG_NIG_UNUSED_EMPTY_2 0x10860UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_2_SIZE 8
#define NIG_REG_NIG_UNUSED_EMPTY_3 0x10980UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_3_SIZE 160
#define NIG_REG_NIG_UNUSED_EMPTY_4 0x11400UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_4_SIZE 768
#define NIG_REG_NIG_UNUSED_EMPTY_5 0x16068UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_5_SIZE 2
#define NIG_REG_NIG_UNUSED_EMPTY_6 0x160b8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_6_SIZE 2
#define NIG_REG_NIG_UNUSED_EMPTY_7 0x1612cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_7_SIZE 5
#define NIG_REG_NIG_UNUSED_EMPTY_8 0x16200UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_8_SIZE 1
#define NIG_REG_NIG_UNUSED_EMPTY_9 0x16218UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_9_SIZE 1914
#define NIG_REG_NIG_UNUSED_EMPTY_10 0x1809cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_10_SIZE 2
#define NIG_REG_NIG_UNUSED_EMPTY_11 0x180acUL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_11_SIZE 5
#define NIG_REG_NIG_UNUSED_EMPTY_12 0x183dcUL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_12_SIZE 25
#define NIG_REG_NIG_UNUSED_EMPTY_13 0x1853cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_13_SIZE 13
#define NIG_REG_NIG_UNUSED_EMPTY_14 0x1867cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_14_SIZE 1
#define NIG_REG_NIG_UNUSED_EMPTY_15 0x18730UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_15_SIZE 6
#define NIG_REG_NIG_UNUSED_EMPTY_16 0x18778UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_16_SIZE 4
#define NIG_REG_NIG_UNUSED_EMPTY_17 0x1878cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_17_SIZE 4
#define NIG_REG_NIG_UNUSED_EMPTY_18 0x187b4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_18_SIZE 4
#define NIG_REG_NIG_UNUSED_EMPTY_19 0x18900UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_19_SIZE 64
#define NIG_REG_NIG_UNUSED_EMPTY_20 0x18ac0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_REG_NIG_UNUSED_EMPTY_20_SIZE 7504
#define NIG_TSGEN_REG_NIG_TSGEN_INT_STS 0xc0UL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
#define NIG_TSGEN_NIG_TSGEN_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define NIG_TSGEN_NIG_TSGEN_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define NIG_TSGEN_REG_NIG_TSGEN_INT_STS_CLR 0xc4UL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
#define NIG_TSGEN_NIG_TSGEN_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define NIG_TSGEN_NIG_TSGEN_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define NIG_TSGEN_REG_NIG_TSGEN_INT_STS_WR 0xc8UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
#define NIG_TSGEN_NIG_TSGEN_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define NIG_TSGEN_NIG_TSGEN_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define NIG_TSGEN_REG_NIG_TSGEN_INT_MASK 0xccUL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
#define NIG_TSGEN_NIG_TSGEN_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define NIG_TSGEN_NIG_TSGEN_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define NIG_TSGEN_REG_TSGEN_CTRL 0UL //ACCESS:WB DataWidth:0x40 Description: Control register. Bit 0 resets the Free Running Counter to 0. This is a self-clearing bit. Bit 1 pauses the Free Running Counter. Bit 2 writes the Free Running Counter with the value stored in TSGEN_WRITEVAL. This is a self-clearing bit. Bits 63:3 are not used and are read-only bits (read as zeroes).
#define NIG_TSGEN_REG_TSGEN_CTRL_SIZE 2
#define NIG_TSGEN_REG_TSGEN_WRITEVAL 0x8UL //ACCESS:WB DataWidth:0x40 Description: This value is written to the Free Running Counter when FreeCount_Write in TSGEN_CTRL is asserted
#define NIG_TSGEN_REG_TSGEN_WRITEVAL_SIZE 2
#define NIG_TSGEN_REG_TSGEN_FREECOUNT 0x10UL //ACCESS:WB_R DataWidth:0x40 Description: This is the current value of the Free Running Counter. This is a read-only register.
#define NIG_TSGEN_REG_TSGEN_FREECOUNT_SIZE 2
#define NIG_TSGEN_REG_TSGEN_TSIO_OUTPUT_CONTROL 0x18UL //ACCESS:WB DataWidth:0x40 Description: TSIO Output Control register. Bits 3:0 are the active-high output enables for the TSIO Output pins 3:0. Bits 7:4 are not used and are read-only bits (read as zeroes). Bits 11:8 reflect the current value of the TSIO Output Signals. These bits are read-only. Bits 15:12 are not used and are read-only bits (read as zeroes). Bits 19:16 are for setting the corresponding TSIO output signals to 1. Bits 23:20 are not used and are read-only bits (read as zeroes). Bits 27:24 are for clearing the corresponding TSIO output signals to 0's when these bits are set to 1's. Bits 63:28 are not used and are read-only bits (read as zeroes).
#define NIG_TSGEN_REG_TSGEN_TSIO_OUTPUT_CONTROL_SIZE 2
#define NIG_TSGEN_REG_TSGEN_SYNCTIME_T0 0x20UL //ACCESS:WB_R DataWidth:0x40 Description: This is the synchronized time for Timer 0. This is equal to the Free Running Counter +/- the Offset value. This is a read-only register.
#define NIG_TSGEN_REG_TSGEN_SYNCTIME_T0_SIZE 2
#define NIG_TSGEN_REG_TSGEN_OFFSET_T0 0x28UL //ACCESS:WB DataWidth:0x40 Description: This is the Offset for Timer 0. It is added or subtracted from the Free Running Counter to create the synchronized time. It is updated by the Drift Compenstation logic.
#define NIG_TSGEN_REG_TSGEN_OFFSET_T0_SIZE 2
#define NIG_TSGEN_REG_TSGEN_DRIFT_T0 0x30UL //ACCESS:WB DataWidth:0x40 Description: Drift register. Bits 24:0 specify how many microseconds to wait before making a Drift adjustment to the TSGEN_OFFSET_T0 register. Bits 29:25 specify how many ns to add or subtract from the TSGEN_OFFSET_T0 register when making a Drift adjustment. Bit 30 controls whether the Adjustment_Value is added (1'b1) or subtracted (1'b0) from the TSGEN_OFFSET_T0 register when making a Drift adjustment. Bit 31 controls whether the offset in TSGEN_OFFSET_T0 is added (1'b1) or subtracted (1'b0) from the Free Running Counter to create TSGEN_SYNCTIME_T0. Bits 63:32 are not used and are read-only bits (read as zeroes).
#define NIG_TSGEN_REG_TSGEN_DRIFT_T0_SIZE 2
#define NIG_TSGEN_REG_TSGEN_TSIO_INCTL_T0 0x38UL //ACCESS:WB DataWidth:0x40 Description: TSIO Input Control register. Bits 3:0 are used to select which TSIO Input signals are used to latch the synchronized time for Timer 0 in TSGEN_TSIO_INTIMEVAL_T0. Bits 7:4 are not used and are read-only bits (read as zeroes). Bit 8 is set if a positive edge on the TSIO Input Signals should be used to capture the synchronized time. Bit 9 is set if a negative edge on the TSIO Input Signals should be used to capture the synchronized time. Bits 15:10 are not used and are read-only bits (read as zeroes). Bits 19:16 are set by HW when a TSIO Input Signal has caused the Timer Value to be captured in TSGEN_TSIO_INTIMEVAL_T0. Write 1's to these bits to clear the corresponding event. Bits 23:20 are not used and are read-only bits (read as zeroes). Bits 27:24 allow the user to read the current value on the TSIO Input Signals. These bits are read-only. Bits 63:28 are not used and are read-only bits (read as zeroes).
#define NIG_TSGEN_REG_TSGEN_TSIO_INCTL_T0_SIZE 2
#define NIG_TSGEN_REG_TSGEN_TSIO_INTIMEVAL_T0 0x40UL //ACCESS:WB_R DataWidth:0x40 Description: This is the synchronized time that was captured by an event on the TSIO Input Signals.These bits are read-only.
#define NIG_TSGEN_REG_TSGEN_TSIO_INTIMEVAL_T0_SIZE 2
#define NIG_TSGEN_REG_TSGEN_TSIO_OUTCTL_T0 0x48UL //ACCESS:WB DataWidth:0x40 Description: TSIO Output Control register. Bits 3:0 are used to select which TSIO Output Signals will be toggled when the syncronized timer increments above TSGEN_TSIO_OUTTIMEVAL_T0. Bits 15:4 are not used and are read-only bits (read as zeroes). Bit 16 is set when the synchronized timer has incremented above TSGEN_TSIO_OUTTIMEVAL_T0. Writing 1'b1 to this bit will clear the event. Bits 63:17 are not used and are read-only bits (read as zeroes).
#define NIG_TSGEN_REG_TSGEN_TSIO_OUTCTL_T0_SIZE 2
#define NIG_TSGEN_REG_TSGEN_TSIO_OUTTIMEVAL_T0 0x50UL //ACCESS:WB DataWidth:0x40 Description: When the T0 synchronized timer increments above this value, the selected TSIO Output Signals are toggled.
#define NIG_TSGEN_REG_TSGEN_TSIO_OUTTIMEVAL_T0_SIZE 2
#define NIG_TSGEN_REG_TSGEN_SYNCTIME_T1 0x58UL //ACCESS:WB_R DataWidth:0x40 Description: This is the synchronized time for Timer 0. This is equal to the Free Running Counter +/- the Offset value. This is a read-only register.
#define NIG_TSGEN_REG_TSGEN_SYNCTIME_T1_SIZE 2
#define NIG_TSGEN_REG_TSGEN_OFFSET_T1 0x60UL //ACCESS:WB DataWidth:0x40 Description: This is the Offset for Timer 0. It is added or subtracted from the Free Running Counter to create the synchronized time. It is updated by the Drift Compenstation logic.
#define NIG_TSGEN_REG_TSGEN_OFFSET_T1_SIZE 2
#define NIG_TSGEN_REG_TSGEN_DRIFT_T1 0x68UL //ACCESS:WB DataWidth:0x40 Description: Drift register. Bits 24:0 specify how many microseconds to wait before making a Drift adjustment to the TSGEN_OFFSET_T0 register. Bits 29:25 specify how many ns to add or subtract from the TSGEN_OFFSET_T0 register when making a Drift adjustment. Bit 30 controls whether the Adjustment_Value is added (1'b1) or subtracted (1'b0) from the TSGEN_OFFSET_T0 register when making a Drift adjustment. Bit 31 controls whether the offset in TSGEN_OFFSET_T0 is added (1'b1) or subtracted (1'b0) from the Free Running Counter to create TSGEN_SYNCTIME_T0. Bits 63:32 are not used and are read-only bits (read as zeroes).
#define NIG_TSGEN_REG_TSGEN_DRIFT_T1_SIZE 2
#define NIG_TSGEN_REG_TSGEN_TSIO_INCTL_T1 0x70UL //ACCESS:WB DataWidth:0x40 Description: TSIO Input Control register. Bits 3:0 are used to select which TSIO Input signals are used to latch the synchronized time for Timer 0 in TSGEN_TSIO_INTIMEVAL_T0. Bits 7:4 are not used and are read-only bits (read as zeroes). Bit 8 is set if a positive edge on the TSIO Input Signals should be used to capture the synchronized time. Bit 9 is set if a negative edge on the TSIO Input Signals should be used to capture the synchronized time. Bits 15:10 are not used and are read-only bits (read as zeroes). Bits 19:16 are set by HW when a TSIO Input Signal has caused the Timer Value to be captured in TSGEN_TSIO_INTIMEVAL_T0. Write 1's to these bits to clear the corresponding event. Bits 23:20 are not used and are read-only bits (read as zeroes). Bits 27:24 allow the user to read the current value on the TSIO Input Signals. These bits are read-only. Bits 63:28 are not used and are read-only bits (read as zeroes).
#define NIG_TSGEN_REG_TSGEN_TSIO_INCTL_T1_SIZE 2
#define NIG_TSGEN_REG_TSGEN_TSIO_INTIMEVAL_T1 0x78UL //ACCESS:WB_R DataWidth:0x40 Description: This is the synchronized time that was captured by an event on the TSIO Input Signals.These bits are read-only.
#define NIG_TSGEN_REG_TSGEN_TSIO_INTIMEVAL_T1_SIZE 2
#define NIG_TSGEN_REG_TSGEN_TSIO_OUTCTL_T1 0x80UL //ACCESS:WB DataWidth:0x40 Description: TSIO Output Control register. Bits 3:0 are used to select which TSIO Output Signals will be toggled when the syncronized timer increments above TSGEN_TSIO_OUTTIMEVAL_T0. Bits 15:4 are not used and are read-only bits (read as zeroes). Bit 16 is set when the synchronized timer has incremented above TSGEN_TSIO_OUTTIMEVAL_T0. Writing 1'b1 to this bit will clear the event. Bits 63:17 are not used and are read-only bits (read as zeroes).
#define NIG_TSGEN_REG_TSGEN_TSIO_OUTCTL_T1_SIZE 2
#define NIG_TSGEN_REG_TSGEN_TSIO_OUTTIMEVAL_T1 0x88UL //ACCESS:WB DataWidth:0x40 Description: When the T0 synchronized timer increments above this value, the selected TSIO Output Signals are toggled.
#define NIG_TSGEN_REG_TSGEN_TSIO_OUTTIMEVAL_T1_SIZE 2
#define NIG_TSGEN_REG_NIG_TSGEN_UNUSED_EMPTY_0 0x90UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_TSGEN_REG_NIG_TSGEN_UNUSED_EMPTY_0_SIZE 12
#define NIG_TSGEN_REG_NIG_TSGEN_UNUSED_EMPTY_1 0xd0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define NIG_TSGEN_REG_NIG_TSGEN_UNUSED_EMPTY_1_SIZE 12
#define PBF_REG_INIT 0x140000UL //ACCESS:RW DataWidth:0x1 Description: Init bit. When set the initial credits are copied to the credit registers (except the port credits). Should be set and then reset after the configuration of the block has ended.
#define PBF_REG_CRC_BYTE_REVERSE 0x140028UL //ACCESS:RW DataWidth:0x1 Description: If set the CRC result will be byte reversed before inserting to the packet.
#define PBF_REG_DBG_CMP_SEND_MAX 0x14002cUL //ACCESS:RW DataWidth:0x1 Description: If set then SendMax check for debug will be enabled.
#define PBF_REG_MAC_IF0_ENABLE 0x140030UL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 0.
#define PBF_REG_MAC_IF1_ENABLE 0x140034UL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 1.
#define PBF_REG_MAC_IF2_ENABLE 0x140038UL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 2.
#define PBF_REG_MAC_IF3_ENABLE 0x14003cUL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 3.
#define PBF_REG_MAC_LB_ENABLE 0x140040UL //ACCESS:RW DataWidth:0x1 Description: Enable for the loopback interface.
#define PBF_REG_IF_ENABLE_REG 0x140044UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PBF_IF_ENABLE_REG_REG_XSDM_IF_ENABLE (0x1<<0)
#define PBF_IF_ENABLE_REG_REG_XSDM_IF_ENABLE_SIZE 0
#define PBF_IF_ENABLE_REG_REG_PB_REQ_IF_ENABLE (0x1<<1)
#define PBF_IF_ENABLE_REG_REG_PB_REQ_IF_ENABLE_SIZE 1
#define PBF_IF_ENABLE_REG_REG_DATA_FROM_PB_IF_ENABLE (0x1<<2)
#define PBF_IF_ENABLE_REG_REG_DATA_FROM_PB_IF_ENABLE_SIZE 2
#define PBF_IF_ENABLE_REG_REG_DATA2PB_IF_ENABLE (0x1<<3)
#define PBF_IF_ENABLE_REG_REG_DATA2PB_IF_ENABLE_SIZE 3
#define PBF_IF_ENABLE_REG_REG_CCM_IF_ENABLE (0x1<<4)
#define PBF_IF_ENABLE_REG_REG_CCM_IF_ENABLE_SIZE 4
#define PBF_IF_ENABLE_REG_REG_XCM_IF_ENABLE (0x1<<5)
#define PBF_IF_ENABLE_REG_REG_XCM_IF_ENABLE_SIZE 5
#define PBF_IF_ENABLE_REG_REG_TCM_IF_ENABLE (0x1<<6)
#define PBF_IF_ENABLE_REG_REG_TCM_IF_ENABLE_SIZE 6
#define PBF_IF_ENABLE_REG_REG_CFC_IF_ENABLE (0x1<<7)
#define PBF_IF_ENABLE_REG_REG_CFC_IF_ENABLE_SIZE 7
#define PBF_IF_ENABLE_REG_REG_TM_IF_ENABLE (0x1<<8)
#define PBF_IF_ENABLE_REG_REG_TM_IF_ENABLE_SIZE 8
#define PBF_IF_ENABLE_REG_REG_XQM_CMD_CREDIT_IF_ENABLE (0x1<<9)
#define PBF_IF_ENABLE_REG_REG_XQM_CMD_CREDIT_IF_ENABLE_SIZE 9
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF0_ENABLE (0x1<<10)
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF0_ENABLE_SIZE 10
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF1_ENABLE (0x1<<11)
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF1_ENABLE_SIZE 11
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF2_ENABLE (0x1<<12)
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF2_ENABLE_SIZE 12
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF3_ENABLE (0x1<<13)
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF3_ENABLE_SIZE 13
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF4_ENABLE (0x1<<14)
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF4_ENABLE_SIZE 14
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF5_ENABLE (0x1<<15)
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF5_ENABLE_SIZE 15
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_LB_ENABLE (0x1<<16)
#define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_LB_ENABLE_SIZE 16
#define PBF_IF_ENABLE_REG_REG_PCI_REQ_IF_ENABLE (0x1<<17)
#define PBF_IF_ENABLE_REG_REG_PCI_REQ_IF_ENABLE_SIZE 17
#define PBF_IF_ENABLE_REG_REG_PCI_DATA_IF_ENABLE (0x1<<18)
#define PBF_IF_ENABLE_REG_REG_PCI_DATA_IF_ENABLE_SIZE 18
#define PBF_IF_ENABLE_REG_REG_PCI_INTER_WR_IF_ENABLE (0x1<<19)
#define PBF_IF_ENABLE_REG_REG_PCI_INTER_WR_IF_ENABLE_SIZE 19
#define PBF_REG_SOFT_RESET 0x140070UL //ACCESS:RW DataWidth:0x5 Multi Field Register
#define PBF_SOFT_RESET_REG_PB_OUT_FIFO_INIT (0x1<<0)
#define PBF_SOFT_RESET_REG_PB_OUT_FIFO_INIT_SIZE 0
#define PBF_SOFT_RESET_REG_HA_CMD_Q_INIT (0x1<<1)
#define PBF_SOFT_RESET_REG_HA_CMD_Q_INIT_SIZE 1
#define PBF_SOFT_RESET_REG_SDM_IN_Q_INIT (0x1<<2)
#define PBF_SOFT_RESET_REG_SDM_IN_Q_INIT_SIZE 2
#define PBF_SOFT_RESET_REG_HEADER_BUFFER_INIT (0x1<<3)
#define PBF_SOFT_RESET_REG_HEADER_BUFFER_INIT_SIZE 3
#define PBF_SOFT_RESET_REG_CRACKER_INFO_FIFO_INIT (0x1<<4)
#define PBF_SOFT_RESET_REG_CRACKER_INFO_FIFO_INIT_SIZE 4
#define PBF_REG_SDM_IN_Q_THRSH 0x14009cUL //ACCESS:RW DataWidth:0x4 Description: Almost full threshold for the SDM input command Q.
#define PBF_REG_PCI_VOQ_ID 0x1400b4UL //ACCESS:RW DataWidth:0x5 Description: PCI VOQ ID used in read request to PCI.
#define PBF_REG_PCI_REQ_INIT_CRD 0x1400b8UL //ACCESS:RW DataWidth:0x3 Description: PCI read request interafce initial credit - transoriented. Default is 2.
#define PBF_REG_XQM_INIT_CRD 0x1400bcUL //ACCESS:RW DataWidth:0x2 Description: XQM interafce initial credit. Default is 2.
#define PBF_REG_CCM_INIT_CRD 0x1400c0UL //ACCESS:RW DataWidth:0x4 Description: CCM initial credit.
#define PBF_REG_TCM_INIT_CRD 0x1400c4UL //ACCESS:RW DataWidth:0x4 Description: TCM initial credit.
#define PBF_REG_XCM_INIT_CRD 0x1400c8UL //ACCESS:RW DataWidth:0x4 Description: CCM initial credit.
#define PBF_REG_TM_INIT_CRD 0x1400ccUL //ACCESS:RW DataWidth:0x4 Description: Timer initial credit.
#define PBF_REG_PB_OUT_FIFO_THRSH 0x1400f8UL //ACCESS:RW DataWidth:0x5 Description: Almost full threshold for the fifo located at the output of the PB.
#define PBF_REG_HA_CMD_Q_THRSH 0x1400fcUL //ACCESS:RW DataWidth:0x4 Description: Almost full threshold for the HA command Q.
#define PBF_REG_TCM_HDR 0x140128UL //ACCESS:RW DataWidth:0x1c Description: Header in TCM messages.
#define PBF_REG_CCM_HDR 0x14012cUL //ACCESS:RW DataWidth:0xc Description: Header in CCM messages.
#define PBF_REG_CCM_AGG_DEC_TYPE 0x140130UL //ACCESS:RW DataWidth:0x4 Description: CCM aggregation dec type.
#define PBF_REG_XCM_HDR 0x140134UL //ACCESS:RW DataWidth:0xc Description: Header in XCM messages.
#define PBF_REG_XCM_AGG_DEC_TYPE 0x140138UL //ACCESS:RW DataWidth:0x4 Description: XCM aggregation dec type.
#define PBF_REG_LAST_FLAG_MASK 0x14013cUL //ACCESS:RW DataWidth:0x20 Description: The bit mask value used to set the last flag.
#define PBF_REG_IP_ID_MASK 0x140140UL //ACCESS:RW DataWidth:0x10 Description: 1st bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.
#define PBF_REG_XCM_MSG_CNT 0x140168UL //ACCESS:ST DataWidth:0x18 Description: Number of messages sent to XCM.
#define PBF_REG_CCM_MSG_CNT 0x14016cUL //ACCESS:ST DataWidth:0x18 Description: Number of messages sent to CCM.
#define PBF_REG_TCM_MSG_CNT 0x140170UL //ACCESS:ST DataWidth:0x18 Description: Number of messages sent to TCM.
#define PBF_REG_TIMER_MSG_CNT 0x140174UL //ACCESS:ST DataWidth:0x18 Description: Number of messages sent to timer.
#define PBF_REG_PCI_INT_MSG_CNT 0x140178UL //ACCESS:ST DataWidth:0x18 Description: Number of messages sent to PCI internal write interface.
#define PBF_REG_PCI_AGGR_CNT 0x14017cUL //ACCESS:ST DataWidth:0x10 Description: The number of messages which were overwritten because of the aggregation mechanism on the PCI internal write interface.
#define PBF_REG_PCI_RD_REQ_CNT 0x140180UL //ACCESS:ST DataWidth:0x18 Description: Number PCI read requests sent.
#define PBF_REG_NUM_FULL_CYCLES_2PCI 0x140184UL //ACCESS:ST DataWidth:0x18 Description: Number of cycles in which the full signal towards the PCI was high.
#define PBF_REG_NUM_FULL_CYCLES_2SDM 0x140194UL //ACCESS:ST DataWidth:0x18 Description: Number of cycles in which the full signal towards the SDM was high.
#define PBF_REG_SEQ_ERR_CID 0x140198UL //ACCESS:RC DataWidth:0x18 Description: Holds the CID of the first command that generated a sequence error.
#define PBF_REG_TX_MEM_A_EVEN_TM 0x14019cUL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_A_ODD_TM 0x1401a0UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_B_EVEN_TM 0x1401a4UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_B_ODD_TM 0x1401a8UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_C_EVEN_TM 0x1401acUL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_C_ODD_TM 0x1401b0UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TQ_MEM_EVEN_TM 0x1401b4UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TQ_MEM_ODD_TM 0x1401b8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PBF_TQ_MEM_ODD_TM_REG_TQ_MEM_ODD_MEM_TM (0x1f<<0)
#define PBF_TQ_MEM_ODD_TM_REG_TQ_MEM_ODD_MEM_TM_SIZE 0
#define PBF_TQ_MEM_ODD_TM_REG_LRA_HA_CMD_Q_TM (0xff<<5)
#define PBF_TQ_MEM_ODD_TM_REG_LRA_HA_CMD_Q_TM_SIZE 5
#define PBF_TQ_MEM_ODD_TM_REG_HD_HEADERS_MEM_TM (0x1f<<13)
#define PBF_TQ_MEM_ODD_TM_REG_HD_HEADERS_MEM_TM_SIZE 13
#define PBF_TQ_MEM_ODD_TM_REG_SMG_CMD_Q_TM (0x3<<18)
#define PBF_TQ_MEM_ODD_TM_REG_SMG_CMD_Q_TM_SIZE 18
#define PBF_REG_DBG_SELECT 0x1401bcUL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PBF to the DBG block) - for selecting a line to output to the DBG block
#define PBF_REG_DBG_BYTE_ENABLE 0x1401c0UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PBF to the DBG block) - for enabling bytes in the selected line (after the select before the shift)
#define PBF_REG_DBG_SHIFT 0x1401c4UL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from PBF to the DBG block) - for circular right shifting of the selected line (after the enabling)
#define PBF_REG_PBF_INT_STS 0x1401c8UL //ACCESS:R DataWidth:0x7 Description: Interrupt register #0 read
#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define PBF_PBF_INT_STS_REG_SEQ_CHECK_ERROR (0x1<<1)
#define PBF_PBF_INT_STS_REG_SEQ_CHECK_ERROR_SIZE 1
#define PBF_PBF_INT_STS_REG_SDM_IN_Q_ERROR (0x1<<2)
#define PBF_PBF_INT_STS_REG_SDM_IN_Q_ERROR_SIZE 2
#define PBF_PBF_INT_STS_REG_MCU_DATA_FIFO_ERROR (0x1<<3)
#define PBF_PBF_INT_STS_REG_MCU_DATA_FIFO_ERROR_SIZE 3
#define PBF_PBF_INT_STS_REG_HA_CMD_Q_ERROR (0x1<<4)
#define PBF_PBF_INT_STS_REG_HA_CMD_Q_ERROR_SIZE 4
#define PBF_PBF_INT_STS_REG_HEADER_BUFFER_ERROR (0x1<<5)
#define PBF_PBF_INT_STS_REG_HEADER_BUFFER_ERROR_SIZE 5
#define PBF_PBF_INT_STS_REG_CRACKER_INFO_FIFO_ERROR (0x1<<6)
#define PBF_PBF_INT_STS_REG_CRACKER_INFO_FIFO_ERROR_SIZE 6
#define PBF_REG_PBF_INT_STS_CLR 0x1401ccUL //ACCESS:RC DataWidth:0x7 Description: Interrupt register #0 read clear
#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define PBF_PBF_INT_STS_CLR_REG_SEQ_CHECK_ERROR (0x1<<1)
#define PBF_PBF_INT_STS_CLR_REG_SEQ_CHECK_ERROR_SIZE 1
#define PBF_PBF_INT_STS_CLR_REG_SDM_IN_Q_ERROR (0x1<<2)
#define PBF_PBF_INT_STS_CLR_REG_SDM_IN_Q_ERROR_SIZE 2
#define PBF_PBF_INT_STS_CLR_REG_MCU_DATA_FIFO_ERROR (0x1<<3)
#define PBF_PBF_INT_STS_CLR_REG_MCU_DATA_FIFO_ERROR_SIZE 3
#define PBF_PBF_INT_STS_CLR_REG_HA_CMD_Q_ERROR (0x1<<4)
#define PBF_PBF_INT_STS_CLR_REG_HA_CMD_Q_ERROR_SIZE 4
#define PBF_PBF_INT_STS_CLR_REG_HEADER_BUFFER_ERROR (0x1<<5)
#define PBF_PBF_INT_STS_CLR_REG_HEADER_BUFFER_ERROR_SIZE 5
#define PBF_PBF_INT_STS_CLR_REG_CRACKER_INFO_FIFO_ERROR (0x1<<6)
#define PBF_PBF_INT_STS_CLR_REG_CRACKER_INFO_FIFO_ERROR_SIZE 6
#define PBF_REG_PBF_INT_STS_WR 0x1401d0UL //ACCESS:WR DataWidth:0x7 Description: Interrupt register #0 bit set or clear
#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define PBF_PBF_INT_STS_WR_REG_SEQ_CHECK_ERROR (0x1<<1)
#define PBF_PBF_INT_STS_WR_REG_SEQ_CHECK_ERROR_SIZE 1
#define PBF_PBF_INT_STS_WR_REG_SDM_IN_Q_ERROR (0x1<<2)
#define PBF_PBF_INT_STS_WR_REG_SDM_IN_Q_ERROR_SIZE 2
#define PBF_PBF_INT_STS_WR_REG_MCU_DATA_FIFO_ERROR (0x1<<3)
#define PBF_PBF_INT_STS_WR_REG_MCU_DATA_FIFO_ERROR_SIZE 3
#define PBF_PBF_INT_STS_WR_REG_HA_CMD_Q_ERROR (0x1<<4)
#define PBF_PBF_INT_STS_WR_REG_HA_CMD_Q_ERROR_SIZE 4
#define PBF_PBF_INT_STS_WR_REG_HEADER_BUFFER_ERROR (0x1<<5)
#define PBF_PBF_INT_STS_WR_REG_HEADER_BUFFER_ERROR_SIZE 5
#define PBF_PBF_INT_STS_WR_REG_CRACKER_INFO_FIFO_ERROR (0x1<<6)
#define PBF_PBF_INT_STS_WR_REG_CRACKER_INFO_FIFO_ERROR_SIZE 6
#define PBF_REG_PBF_INT_MASK 0x1401d4UL //ACCESS:RW DataWidth:0x7 Description: Interrupt mask register #0 read/write
#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define PBF_PBF_INT_MASK_REG_SEQ_CHECK_ERROR (0x1<<1)
#define PBF_PBF_INT_MASK_REG_SEQ_CHECK_ERROR_SIZE 1
#define PBF_PBF_INT_MASK_REG_SDM_IN_Q_ERROR (0x1<<2)
#define PBF_PBF_INT_MASK_REG_SDM_IN_Q_ERROR_SIZE 2
#define PBF_PBF_INT_MASK_REG_MCU_DATA_FIFO_ERROR (0x1<<3)
#define PBF_PBF_INT_MASK_REG_MCU_DATA_FIFO_ERROR_SIZE 3
#define PBF_PBF_INT_MASK_REG_HA_CMD_Q_ERROR (0x1<<4)
#define PBF_PBF_INT_MASK_REG_HA_CMD_Q_ERROR_SIZE 4
#define PBF_PBF_INT_MASK_REG_HEADER_BUFFER_ERROR (0x1<<5)
#define PBF_PBF_INT_MASK_REG_HEADER_BUFFER_ERROR_SIZE 5
#define PBF_PBF_INT_MASK_REG_CRACKER_INFO_FIFO_ERROR (0x1<<6)
#define PBF_PBF_INT_MASK_REG_CRACKER_INFO_FIFO_ERROR_SIZE 6
#define PBF_REG_PBF_PRTY_STS 0x1401d8UL //ACCESS:R DataWidth:0x1c Description: Parity register #0 read
#define PBF_PBF_PRTY_STS_REG_PARITY (0x1<<0)
#define PBF_PBF_PRTY_STS_REG_PARITY_SIZE 0
#define PBF_PBF_PRTY_STS_REG_TQ_EVEN (0x1<<1)
#define PBF_PBF_PRTY_STS_REG_TQ_EVEN_SIZE 1
#define PBF_PBF_PRTY_STS_REG_TQ_ODD (0x1<<2)
#define PBF_PBF_PRTY_STS_REG_TQ_ODD_SIZE 2
#define PBF_PBF_PRTY_STS_REG_PBUF_A_EVEN (0x1<<3)
#define PBF_PBF_PRTY_STS_REG_PBUF_A_EVEN_SIZE 3
#define PBF_PBF_PRTY_STS_REG_PBUF_A_ODD (0x1<<4)
#define PBF_PBF_PRTY_STS_REG_PBUF_A_ODD_SIZE 4
#define PBF_PBF_PRTY_STS_REG_PBUF_B_EVEN (0x1<<5)
#define PBF_PBF_PRTY_STS_REG_PBUF_B_EVEN_SIZE 5
#define PBF_PBF_PRTY_STS_REG_PBUF_B_ODD (0x1<<6)
#define PBF_PBF_PRTY_STS_REG_PBUF_B_ODD_SIZE 6
#define PBF_PBF_PRTY_STS_REG_PBUF_C_EVEN (0x1<<7)
#define PBF_PBF_PRTY_STS_REG_PBUF_C_EVEN_SIZE 7
#define PBF_PBF_PRTY_STS_REG_PBUF_C_ODD (0x1<<8)
#define PBF_PBF_PRTY_STS_REG_PBUF_C_ODD_SIZE 8
#define PBF_PBF_PRTY_STS_REG_SMG_IN_Q (0x1<<9)
#define PBF_PBF_PRTY_STS_REG_SMG_IN_Q_SIZE 9
#define PBF_PBF_PRTY_STS_REG_SMG_CMD_Q (0x1<<10)
#define PBF_PBF_PRTY_STS_REG_SMG_CMD_Q_SIZE 10
#define PBF_PBF_PRTY_STS_REG_SMG_CURR_CMD (0x1<<11)
#define PBF_PBF_PRTY_STS_REG_SMG_CURR_CMD_SIZE 11
#define PBF_PBF_PRTY_STS_REG_PB_OUT_Q (0x1<<12)
#define PBF_PBF_PRTY_STS_REG_PB_OUT_Q_SIZE 12
#define PBF_PBF_PRTY_STS_REG_HA_CMD_Q (0x1<<13)
#define PBF_PBF_PRTY_STS_REG_HA_CMD_Q_SIZE 13
#define PBF_PBF_PRTY_STS_REG_HD_HDRS_MEM (0x1<<14)
#define PBF_PBF_PRTY_STS_REG_HD_HDRS_MEM_SIZE 14
#define PBF_PBF_PRTY_STS_REG_HD_CMD_Q (0x1<<15)
#define PBF_PBF_PRTY_STS_REG_HD_CMD_Q_SIZE 15
#define PBF_PBF_PRTY_STS_REG_SDM_IN_Q (0x1<<16)
#define PBF_PBF_PRTY_STS_REG_SDM_IN_Q_SIZE 16
#define PBF_PBF_PRTY_STS_REG_HM_CMD_Q (0x1<<17)
#define PBF_PBF_PRTY_STS_REG_HM_CMD_Q_SIZE 17
#define PBF_PBF_PRTY_STS_REG_HEADER_BUFFER (0x1<<18)
#define PBF_PBF_PRTY_STS_REG_HEADER_BUFFER_SIZE 18
#define PBF_PBF_PRTY_STS_REG_CRACKER_INFO_FIFO (0x1<<19)
#define PBF_PBF_PRTY_STS_REG_CRACKER_INFO_FIFO_SIZE 19
#define PBF_PBF_PRTY_STS_REG_PBUF_D_EVEN (0x1<<20)
#define PBF_PBF_PRTY_STS_REG_PBUF_D_EVEN_SIZE 20
#define PBF_PBF_PRTY_STS_REG_PBUF_D_ODD (0x1<<21)
#define PBF_PBF_PRTY_STS_REG_PBUF_D_ODD_SIZE 21
#define PBF_PBF_PRTY_STS_REG_PBUF_E_EVEN (0x1<<22)
#define PBF_PBF_PRTY_STS_REG_PBUF_E_EVEN_SIZE 22
#define PBF_PBF_PRTY_STS_REG_PBUF_E_ODD (0x1<<23)
#define PBF_PBF_PRTY_STS_REG_PBUF_E_ODD_SIZE 23
#define PBF_PBF_PRTY_STS_REG_PBUF_F_EVEN (0x1<<24)
#define PBF_PBF_PRTY_STS_REG_PBUF_F_EVEN_SIZE 24
#define PBF_PBF_PRTY_STS_REG_PBUF_F_ODD (0x1<<25)
#define PBF_PBF_PRTY_STS_REG_PBUF_F_ODD_SIZE 25
#define PBF_PBF_PRTY_STS_REG_PBUF_G_EVEN (0x1<<26)
#define PBF_PBF_PRTY_STS_REG_PBUF_G_EVEN_SIZE 26
#define PBF_PBF_PRTY_STS_REG_PBUF_G_ODD (0x1<<27)
#define PBF_PBF_PRTY_STS_REG_PBUF_G_ODD_SIZE 27
#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dcUL //ACCESS:RC DataWidth:0x1c Description: Parity register #0 read clear
#define PBF_PBF_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define PBF_PBF_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define PBF_PBF_PRTY_STS_CLR_REG_TQ_EVEN (0x1<<1)
#define PBF_PBF_PRTY_STS_CLR_REG_TQ_EVEN_SIZE 1
#define PBF_PBF_PRTY_STS_CLR_REG_TQ_ODD (0x1<<2)
#define PBF_PBF_PRTY_STS_CLR_REG_TQ_ODD_SIZE 2
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_A_EVEN (0x1<<3)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_A_EVEN_SIZE 3
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_A_ODD (0x1<<4)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_A_ODD_SIZE 4
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_B_EVEN (0x1<<5)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_B_EVEN_SIZE 5
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_B_ODD (0x1<<6)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_B_ODD_SIZE 6
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_C_EVEN (0x1<<7)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_C_EVEN_SIZE 7
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_C_ODD (0x1<<8)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_C_ODD_SIZE 8
#define PBF_PBF_PRTY_STS_CLR_REG_SMG_IN_Q (0x1<<9)
#define PBF_PBF_PRTY_STS_CLR_REG_SMG_IN_Q_SIZE 9
#define PBF_PBF_PRTY_STS_CLR_REG_SMG_CMD_Q (0x1<<10)
#define PBF_PBF_PRTY_STS_CLR_REG_SMG_CMD_Q_SIZE 10
#define PBF_PBF_PRTY_STS_CLR_REG_SMG_CURR_CMD (0x1<<11)
#define PBF_PBF_PRTY_STS_CLR_REG_SMG_CURR_CMD_SIZE 11
#define PBF_PBF_PRTY_STS_CLR_REG_PB_OUT_Q (0x1<<12)
#define PBF_PBF_PRTY_STS_CLR_REG_PB_OUT_Q_SIZE 12
#define PBF_PBF_PRTY_STS_CLR_REG_HA_CMD_Q (0x1<<13)
#define PBF_PBF_PRTY_STS_CLR_REG_HA_CMD_Q_SIZE 13
#define PBF_PBF_PRTY_STS_CLR_REG_HD_HDRS_MEM (0x1<<14)
#define PBF_PBF_PRTY_STS_CLR_REG_HD_HDRS_MEM_SIZE 14
#define PBF_PBF_PRTY_STS_CLR_REG_HD_CMD_Q (0x1<<15)
#define PBF_PBF_PRTY_STS_CLR_REG_HD_CMD_Q_SIZE 15
#define PBF_PBF_PRTY_STS_CLR_REG_SDM_IN_Q (0x1<<16)
#define PBF_PBF_PRTY_STS_CLR_REG_SDM_IN_Q_SIZE 16
#define PBF_PBF_PRTY_STS_CLR_REG_HM_CMD_Q (0x1<<17)
#define PBF_PBF_PRTY_STS_CLR_REG_HM_CMD_Q_SIZE 17
#define PBF_PBF_PRTY_STS_CLR_REG_HEADER_BUFFER (0x1<<18)
#define PBF_PBF_PRTY_STS_CLR_REG_HEADER_BUFFER_SIZE 18
#define PBF_PBF_PRTY_STS_CLR_REG_CRACKER_INFO_FIFO (0x1<<19)
#define PBF_PBF_PRTY_STS_CLR_REG_CRACKER_INFO_FIFO_SIZE 19
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_D_EVEN (0x1<<20)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_D_EVEN_SIZE 20
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_D_ODD (0x1<<21)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_D_ODD_SIZE 21
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_E_EVEN (0x1<<22)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_E_EVEN_SIZE 22
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_E_ODD (0x1<<23)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_E_ODD_SIZE 23
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_F_EVEN (0x1<<24)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_F_EVEN_SIZE 24
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_F_ODD (0x1<<25)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_F_ODD_SIZE 25
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_G_EVEN (0x1<<26)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_G_EVEN_SIZE 26
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_G_ODD (0x1<<27)
#define PBF_PBF_PRTY_STS_CLR_REG_PBUF_G_ODD_SIZE 27
#define PBF_REG_PBF_PRTY_STS_WR 0x1401e0UL //ACCESS:WR DataWidth:0x1c Description: Parity register #0 bit set or clear
#define PBF_PBF_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define PBF_PBF_PRTY_STS_WR_REG_PARITY_SIZE 0
#define PBF_PBF_PRTY_STS_WR_REG_TQ_EVEN (0x1<<1)
#define PBF_PBF_PRTY_STS_WR_REG_TQ_EVEN_SIZE 1
#define PBF_PBF_PRTY_STS_WR_REG_TQ_ODD (0x1<<2)
#define PBF_PBF_PRTY_STS_WR_REG_TQ_ODD_SIZE 2
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_A_EVEN (0x1<<3)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_A_EVEN_SIZE 3
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_A_ODD (0x1<<4)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_A_ODD_SIZE 4
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_B_EVEN (0x1<<5)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_B_EVEN_SIZE 5
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_B_ODD (0x1<<6)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_B_ODD_SIZE 6
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_C_EVEN (0x1<<7)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_C_EVEN_SIZE 7
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_C_ODD (0x1<<8)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_C_ODD_SIZE 8
#define PBF_PBF_PRTY_STS_WR_REG_SMG_IN_Q (0x1<<9)
#define PBF_PBF_PRTY_STS_WR_REG_SMG_IN_Q_SIZE 9
#define PBF_PBF_PRTY_STS_WR_REG_SMG_CMD_Q (0x1<<10)
#define PBF_PBF_PRTY_STS_WR_REG_SMG_CMD_Q_SIZE 10
#define PBF_PBF_PRTY_STS_WR_REG_SMG_CURR_CMD (0x1<<11)
#define PBF_PBF_PRTY_STS_WR_REG_SMG_CURR_CMD_SIZE 11
#define PBF_PBF_PRTY_STS_WR_REG_PB_OUT_Q (0x1<<12)
#define PBF_PBF_PRTY_STS_WR_REG_PB_OUT_Q_SIZE 12
#define PBF_PBF_PRTY_STS_WR_REG_HA_CMD_Q (0x1<<13)
#define PBF_PBF_PRTY_STS_WR_REG_HA_CMD_Q_SIZE 13
#define PBF_PBF_PRTY_STS_WR_REG_HD_HDRS_MEM (0x1<<14)
#define PBF_PBF_PRTY_STS_WR_REG_HD_HDRS_MEM_SIZE 14
#define PBF_PBF_PRTY_STS_WR_REG_HD_CMD_Q (0x1<<15)
#define PBF_PBF_PRTY_STS_WR_REG_HD_CMD_Q_SIZE 15
#define PBF_PBF_PRTY_STS_WR_REG_SDM_IN_Q (0x1<<16)
#define PBF_PBF_PRTY_STS_WR_REG_SDM_IN_Q_SIZE 16
#define PBF_PBF_PRTY_STS_WR_REG_HM_CMD_Q (0x1<<17)
#define PBF_PBF_PRTY_STS_WR_REG_HM_CMD_Q_SIZE 17
#define PBF_PBF_PRTY_STS_WR_REG_HEADER_BUFFER (0x1<<18)
#define PBF_PBF_PRTY_STS_WR_REG_HEADER_BUFFER_SIZE 18
#define PBF_PBF_PRTY_STS_WR_REG_CRACKER_INFO_FIFO (0x1<<19)
#define PBF_PBF_PRTY_STS_WR_REG_CRACKER_INFO_FIFO_SIZE 19
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_D_EVEN (0x1<<20)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_D_EVEN_SIZE 20
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_D_ODD (0x1<<21)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_D_ODD_SIZE 21
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_E_EVEN (0x1<<22)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_E_EVEN_SIZE 22
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_E_ODD (0x1<<23)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_E_ODD_SIZE 23
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_F_EVEN (0x1<<24)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_F_EVEN_SIZE 24
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_F_ODD (0x1<<25)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_F_ODD_SIZE 25
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_G_EVEN (0x1<<26)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_G_EVEN_SIZE 26
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_G_ODD (0x1<<27)
#define PBF_PBF_PRTY_STS_WR_REG_PBUF_G_ODD_SIZE 27
#define PBF_REG_PBF_PRTY_MASK 0x1401e4UL //ACCESS:RW DataWidth:0x1c Description: Parity mask register #0 read/write
#define PBF_PBF_PRTY_MASK_REG_PARITY (0x1<<0)
#define PBF_PBF_PRTY_MASK_REG_PARITY_SIZE 0
#define PBF_PBF_PRTY_MASK_REG_TQ_EVEN (0x1<<1)
#define PBF_PBF_PRTY_MASK_REG_TQ_EVEN_SIZE 1
#define PBF_PBF_PRTY_MASK_REG_TQ_ODD (0x1<<2)
#define PBF_PBF_PRTY_MASK_REG_TQ_ODD_SIZE 2
#define PBF_PBF_PRTY_MASK_REG_PBUF_A_EVEN (0x1<<3)
#define PBF_PBF_PRTY_MASK_REG_PBUF_A_EVEN_SIZE 3
#define PBF_PBF_PRTY_MASK_REG_PBUF_A_ODD (0x1<<4)
#define PBF_PBF_PRTY_MASK_REG_PBUF_A_ODD_SIZE 4
#define PBF_PBF_PRTY_MASK_REG_PBUF_B_EVEN (0x1<<5)
#define PBF_PBF_PRTY_MASK_REG_PBUF_B_EVEN_SIZE 5
#define PBF_PBF_PRTY_MASK_REG_PBUF_B_ODD (0x1<<6)
#define PBF_PBF_PRTY_MASK_REG_PBUF_B_ODD_SIZE 6
#define PBF_PBF_PRTY_MASK_REG_PBUF_C_EVEN (0x1<<7)
#define PBF_PBF_PRTY_MASK_REG_PBUF_C_EVEN_SIZE 7
#define PBF_PBF_PRTY_MASK_REG_PBUF_C_ODD (0x1<<8)
#define PBF_PBF_PRTY_MASK_REG_PBUF_C_ODD_SIZE 8
#define PBF_PBF_PRTY_MASK_REG_SMG_IN_Q (0x1<<9)
#define PBF_PBF_PRTY_MASK_REG_SMG_IN_Q_SIZE 9
#define PBF_PBF_PRTY_MASK_REG_SMG_CMD_Q (0x1<<10)
#define PBF_PBF_PRTY_MASK_REG_SMG_CMD_Q_SIZE 10
#define PBF_PBF_PRTY_MASK_REG_SMG_CURR_CMD (0x1<<11)
#define PBF_PBF_PRTY_MASK_REG_SMG_CURR_CMD_SIZE 11
#define PBF_PBF_PRTY_MASK_REG_PB_OUT_Q (0x1<<12)
#define PBF_PBF_PRTY_MASK_REG_PB_OUT_Q_SIZE 12
#define PBF_PBF_PRTY_MASK_REG_HA_CMD_Q (0x1<<13)
#define PBF_PBF_PRTY_MASK_REG_HA_CMD_Q_SIZE 13
#define PBF_PBF_PRTY_MASK_REG_HD_HDRS_MEM (0x1<<14)
#define PBF_PBF_PRTY_MASK_REG_HD_HDRS_MEM_SIZE 14
#define PBF_PBF_PRTY_MASK_REG_HD_CMD_Q (0x1<<15)
#define PBF_PBF_PRTY_MASK_REG_HD_CMD_Q_SIZE 15
#define PBF_PBF_PRTY_MASK_REG_SDM_IN_Q (0x1<<16)
#define PBF_PBF_PRTY_MASK_REG_SDM_IN_Q_SIZE 16
#define PBF_PBF_PRTY_MASK_REG_HM_CMD_Q (0x1<<17)
#define PBF_PBF_PRTY_MASK_REG_HM_CMD_Q_SIZE 17
#define PBF_PBF_PRTY_MASK_REG_HEADER_BUFFER (0x1<<18)
#define PBF_PBF_PRTY_MASK_REG_HEADER_BUFFER_SIZE 18
#define PBF_PBF_PRTY_MASK_REG_CRACKER_INFO_FIFO (0x1<<19)
#define PBF_PBF_PRTY_MASK_REG_CRACKER_INFO_FIFO_SIZE 19
#define PBF_PBF_PRTY_MASK_REG_PBUF_D_EVEN (0x1<<20)
#define PBF_PBF_PRTY_MASK_REG_PBUF_D_EVEN_SIZE 20
#define PBF_PBF_PRTY_MASK_REG_PBUF_D_ODD (0x1<<21)
#define PBF_PBF_PRTY_MASK_REG_PBUF_D_ODD_SIZE 21
#define PBF_PBF_PRTY_MASK_REG_PBUF_E_EVEN (0x1<<22)
#define PBF_PBF_PRTY_MASK_REG_PBUF_E_EVEN_SIZE 22
#define PBF_PBF_PRTY_MASK_REG_PBUF_E_ODD (0x1<<23)
#define PBF_PBF_PRTY_MASK_REG_PBUF_E_ODD_SIZE 23
#define PBF_PBF_PRTY_MASK_REG_PBUF_F_EVEN (0x1<<24)
#define PBF_PBF_PRTY_MASK_REG_PBUF_F_EVEN_SIZE 24
#define PBF_PBF_PRTY_MASK_REG_PBUF_F_ODD (0x1<<25)
#define PBF_PBF_PRTY_MASK_REG_PBUF_F_ODD_SIZE 25
#define PBF_PBF_PRTY_MASK_REG_PBUF_G_EVEN (0x1<<26)
#define PBF_PBF_PRTY_MASK_REG_PBUF_G_EVEN_SIZE 26
#define PBF_PBF_PRTY_MASK_REG_PBUF_G_ODD (0x1<<27)
#define PBF_PBF_PRTY_MASK_REG_PBUF_G_ODD_SIZE 27
#define PBF_REG_LLC_JUMBO_THRSH 0x15c000UL //ACCESS:RW DataWidth:0xe Description: The threshold used for deciding whether the type/length field in an LLC SNAP packet is equal to the length or to llc_jumbo_type.
#define PBF_REG_LLC_JUMBO_TYPE 0x15c004UL //ACCESS:RW DataWidth:0x10 Description: The value of the type/length in the case of a LLC SNAP packet which is a jumbo packet.
#define PBF_REG_ECO_RESERVED 0x15c020UL //ACCESS:RW DataWidth:0x8 Description: Reserved for ECO future implementations.
#define PBF_REG_E15_FW_COMPAT_MODE 0x15c024UL //ACCESS:RW DataWidth:0x1 Description: E1.5 FW backward compatibility mode. If set then backward compatible to E1.5.
#define PBF_REG_LB_TRANSMIT_WINDOW 0x15c028UL //ACCESS:RW DataWidth:0x5 Description: Number of cycles in a transmit window for pacing the LB traffic.
#define PBF_REG_LB_IDLE_WINDOW 0x15c02cUL //ACCESS:RW DataWidth:0x5 Description: Number of cycles in a non-transmit window for pacing the LB traffic.
#define PBF_REG_HEADER_BUFFER_THRSH 0x15c030UL //ACCESS:RW DataWidth:0x7 Description: Almost full threshold for the header buffer fifo.
#define PBF_REG_CRACKER_INFO_FIFO_THRSH 0x15c034UL //ACCESS:RW DataWidth:0x5 Description: Almost full threshold for the cracker info fifo.
#define PBF_REG_LIMIT_OUTSTANDING_READ_DATA 0x15c038UL //ACCESS:RW DataWidth:0x1 Description: If set enables limitting the outstanding read data from the PCI.
#define PBF_REG_MAX_OUTSTANDING_READ_DATA 0x15c03cUL //ACCESS:RW DataWidth:0xe Description: If limit_outstanding_read_data is set; limits the outstanding PCI read data to this value which is in 16B lines.
#define PBF_REG_LB_PACKETS_WRR_WEIGHT 0x15c044UL //ACCESS:RW DataWidth:0x3 Description: WRR weight of commands destined to the LB in the command arbiter
#define PBF_REG_WRR_BURST_MODE 0x15c048UL //ACCESS:RW DataWidth:0x1 Description: If set; in the command queue arbiter; the WRR arbiters pointer will stay on the winning input; instead of moving to the next one. This allows burstiness.
#define PBF_REG_VLAN_TYPE_0 0x15c06cUL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PBF_REG_VLAN_TYPE_1 0x15c070UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PBF_REG_VLAN_TYPE_2 0x15c074UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PBF_REG_VLAN_TYPE_3 0x15c078UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PBF_REG_VLAN_TYPE_4 0x15c07cUL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PBF_REG_VLAN_TYPE_5 0x15c080UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PBF_REG_VLAN_TYPE_6 0x15c084UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PBF_REG_VLAN_TYPE_7 0x15c088UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PBF_REG_FCOE_TYPE 0x15c08cUL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for first FCoE type
#define PBF_REG_TAG_ETHERTYPE_0 0x15c090UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 0
#define PBF_REG_TAG_ETHERTYPE_1 0x15c094UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 1
#define PBF_REG_TAG_ETHERTYPE_2 0x15c098UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 2
#define PBF_REG_TAG_LEN_0 0x15c09cUL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 0. The length is between 2B and 14B; in 2B granularity
#define PBF_REG_TAG_LEN_1 0x15c0a0UL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 1. The length is between 2B and 14B; in 2B granularity
#define PBF_REG_TAG_LEN_2 0x15c0a4UL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 2. The length is between 2B and 14B; in 2B granularity
#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.
#define PBF_REG_HDRS_AFTER_OUTER_VLAN 0x15c0acUL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the outer VLAN header.
#define PBF_REG_HDRS_AFTER_INNER_VLAN 0x15c0b0UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the inner VLAN header.
#define PBF_REG_HDRS_AFTER_LLC 0x15c0b4UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the LLC header.
#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 0
#define PBF_REG_HDRS_AFTER_TAG_1 0x15c0bcUL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 1
#define PBF_REG_HDRS_AFTER_TAG_2 0x15c0c0UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 2
#define PBF_REG_MUST_HAVE_HDRS 0x15c0c4UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which headers must appear in the packet
#define PBF_REG_IP_ID_MASK_1 0x15c0c8UL //ACCESS:RW DataWidth:0x10 Description: 2nd bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.
#define PBF_REG_IP_ID_MASK_2 0x15c0ccUL //ACCESS:RW DataWidth:0x10 Description: 3rd bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.
#define PBF_REG_IP_ID_MASK_3 0x15c0d0UL //ACCESS:RW DataWidth:0x10 Description: 4th bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.
#define PBF_REG_ACK_FLG_MODE 0x15c0d4UL //ACCESS:RW DataWidth:0x2 Description: Update mode for the ACK flag
#define PBF_REG_CWR_FLG_MODE 0x15c0d8UL //ACCESS:RW DataWidth:0x2 Description: Update mode for the CWR flag
#define PBF_REG_ECE_FLG_MODE 0x15c0dcUL //ACCESS:RW DataWidth:0x2 Description: Update mode for the ECE flag
#define PBF_REG_FIN_FLG_MODE 0x15c0e0UL //ACCESS:RW DataWidth:0x2 Description: Update mode for the FIN flag
#define PBF_REG_NS_FLG_MODE 0x15c0e4UL //ACCESS:RW DataWidth:0x2 Description: Update mode for the NS flag
#define PBF_REG_PUSH_FLG_MODE 0x15c0e8UL //ACCESS:RW DataWidth:0x2 Description: Update mode for the PUSH flag
#define PBF_REG_RST_FLG_MODE 0x15c0ecUL //ACCESS:RW DataWidth:0x2 Description: Update mode for the RST flag
#define PBF_REG_SYN_FLG_MODE 0x15c0f0UL //ACCESS:RW DataWidth:0x2 Description: Update mode for the SYN flag
#define PBF_REG_URG_FLG_MODE 0x15c0f4UL //ACCESS:RW DataWidth:0x2 Description: Update mode for the URG flag
#define PBF_REG_NO_ERR_ON_PRS_ERR 0x15c0f8UL //ACCESS:RW DataWidth:0x8 Multi Field Register
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_PRS_BAD_IPV_ERR (0x1<<0)
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_PRS_BAD_IPV_ERR_SIZE 0
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_PRS_BAD_IP_HDR_LEN_ERR (0x1<<1)
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_PRS_BAD_IP_HDR_LEN_ERR_SIZE 1
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_PRS_PKT_TOO_SMALL_ERR (0x1<<2)
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_PRS_PKT_TOO_SMALL_ERR_SIZE 2
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_TCP_HDR_PTR_INV_ERR (0x1<<3)
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_TCP_HDR_PTR_INV_ERR_SIZE 3
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_UNKNOWN_OVER_IPV4_ERR (0x1<<4)
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_UNKNOWN_OVER_IPV4_ERR_SIZE 4
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_UNKNOWN_OVER_ETH_ERR (0x1<<5)
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_UNKNOWN_OVER_ETH_ERR_SIZE 5
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_OVERIP_HM_4NON_1ST_FRAG_ERR (0x1<<6)
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_OVERIP_HM_4NON_1ST_FRAG_ERR_SIZE 6
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_TCP_UDP_CHK_PTR_BEYOND_PKT_ERR (0x1<<7)
#define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_TCP_UDP_CHK_PTR_BEYOND_PKT_ERR_SIZE 7
#define PBF_REG_PRS_ERRORS_MASK 0x15c0fcUL //ACCESS:RW DataWidth:0x8 Multi Field Register
#define PBF_PRS_ERRORS_MASK_REG_MASK_PRS_BAD_IPV_ERR (0x1<<0)
#define PBF_PRS_ERRORS_MASK_REG_MASK_PRS_BAD_IPV_ERR_SIZE 0
#define PBF_PRS_ERRORS_MASK_REG_MASK_PRS_BAD_IP_HDR_LEN_ERR (0x1<<1)
#define PBF_PRS_ERRORS_MASK_REG_MASK_PRS_BAD_IP_HDR_LEN_ERR_SIZE 1
#define PBF_PRS_ERRORS_MASK_REG_MASK_PRS_PKT_TOO_SMALL_ERR (0x1<<2)
#define PBF_PRS_ERRORS_MASK_REG_MASK_PRS_PKT_TOO_SMALL_ERR_SIZE 2
#define PBF_PRS_ERRORS_MASK_REG_MASK_TCP_HDR_PTR_INV_ERR (0x1<<3)
#define PBF_PRS_ERRORS_MASK_REG_MASK_TCP_HDR_PTR_INV_ERR_SIZE 3
#define PBF_PRS_ERRORS_MASK_REG_MASK_UNKNOWN_OVER_IPV4_ERR (0x1<<4)
#define PBF_PRS_ERRORS_MASK_REG_MASK_UNKNOWN_OVER_IPV4_ERR_SIZE 4
#define PBF_PRS_ERRORS_MASK_REG_MASK_UNKNOWN_OVER_ETH_ERR (0x1<<5)
#define PBF_PRS_ERRORS_MASK_REG_MASK_UNKNOWN_OVER_ETH_ERR_SIZE 5
#define PBF_PRS_ERRORS_MASK_REG_MASK_OVERIP_HM_4NON_1ST_FRAG_ERR (0x1<<6)
#define PBF_PRS_ERRORS_MASK_REG_MASK_OVERIP_HM_4NON_1ST_FRAG_ERR_SIZE 6
#define PBF_PRS_ERRORS_MASK_REG_MASK_TCP_UDP_CHK_PTR_BEYOND_PKT_ERR (0x1<<7)
#define PBF_PRS_ERRORS_MASK_REG_MASK_TCP_UDP_CHK_PTR_BEYOND_PKT_ERR_SIZE 7
#define PBF_REG_DROP_PKT_UPON_ERR 0x15c100UL //ACCESS:RW DataWidth:0x1 Description: if set; packets with error will be dropped; otherwise transmitted with error to the NIG (FCS).
#define PBF_REG_NO_PAD_IN_PKT 0x15c104UL //ACCESS:RW DataWidth:0x1 Description: if set; there is no expected L2 padding in the packet.
#define PBF_REG_NUM_PRS_BAD_IPV_ERRORS 0x15c108UL //ACCESS:ST DataWidth:0x8 Description: Number of packets with bad IPV error.
#define PBF_REG_NUM_PRS_BAD_IP_HDR_LEN_ERRORS 0x15c10cUL //ACCESS:ST DataWidth:0x8 Description: Number of packets with bad IP header length.
#define PBF_REG_NUM_PRS_PKT_TOO_SMALL_ERRORS 0x15c110UL //ACCESS:ST DataWidth:0x8 Description: Number of packets with packet too small error.
#define PBF_REG_NUM_TCP_HDR_PTR_INV_ERRORS 0x15c114UL //ACCESS:ST DataWidth:0x8 Description: Number of packets with an invalid TCP header pointer.
#define PBF_REG_NUM_UNKNOWN_OVER_IPV4_ERRORS 0x15c118UL //ACCESS:ST DataWidth:0x8 Description: Number of packets which were identified to have an unknown over IPV4 protocol error.
#define PBF_REG_NUM_UNKNOWN_OVER_ETH_ERRORS 0x15c11cUL //ACCESS:ST DataWidth:0x8 Description: if set; a packet which was identified to have an unknown over ethernet protocol error will not be transmitted with an error/dropped.
#define PBF_REG_NUM_OVERIP_HM_4NON_1ST_FRAG_ERRORS 0x15c120UL //ACCESS:ST DataWidth:0x8 Description: Number of packets which were identified to have a non-first fragment error.
#define PBF_REG_NUM_TCP_UDP_CHK_PTR_BEYOND_PKT_ERRORS 0x15c124UL //ACCESS:ST DataWidth:0x8 Description: Number of packets which were identified to have a TCP/UDP checksum pointer beyond the packet error.
#define PBF_REG_NUM_PCI_ERRORS 0x15c130UL //ACCESS:ST DataWidth:0x10 Description: Number of errors from the PCI read interface.
#define PBF_REG_TXP_MEM_ADDR 0x15c134UL //ACCESS:RW DataWidth:0xb Description: Address for accessing the TXP memories. Should be written before reading/writing through the WB registers.
#define PBF_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD 0x15c138UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define PBF_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD 0x15c13cUL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define PBF_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD 0x15c140UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define PBF_REG_CPU_MBIST_MEMCTRL_0_STATUS_0 0x15c144UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define PBF_REG_CPU_MBIST_MEMCTRL_1_STATUS_0 0x15c148UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define PBF_REG_CPU_MBIST_MEMCTRL_2_STATUS_0 0x15c14cUL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define PBF_REG_HIGIG_HDR_SIZE_P0 0x15c150UL //ACCESS:RW DataWidth:0x4 Description: HiGiG header size in DWORDS for PBF port 0.
#define PBF_REG_HIGIG_HDR_SIZE_P1 0x15c154UL //ACCESS:RW DataWidth:0x4 Description: HiGiG header size in DWORDS for PBF port 1.
#define PBF_REG_INIT_Q0 0x15c160UL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 0. When set the initial credit of queue 0 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
#define PBF_REG_INIT_Q1 0x15c164UL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 1. When set the initial credit of queue 1 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
#define PBF_REG_INIT_Q2 0x15c168UL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 2. When set the initial credit of queue 2 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
#define PBF_REG_INIT_Q3 0x15c16cUL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 3. When set the initial credit of queue 3 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
#define PBF_REG_INIT_Q4 0x15c170UL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 4. When set the initial credit of queue 4 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
#define PBF_REG_INIT_Q5 0x15c174UL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 5. When set the initial credit of queue 5 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
#define PBF_REG_INIT_LB_Q 0x15c178UL //ACCESS:RW DataWidth:0x1 Description: Init bit for LB queue. When set the initial credit of the LB queue is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
#define PBF_REG_PAUSE_ENABLE_Q0 0x15c17cUL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 0.
#define PBF_REG_PAUSE_ENABLE_Q1 0x15c180UL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 1.
#define PBF_REG_PAUSE_ENABLE_Q2 0x15c184UL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 2.
#define PBF_REG_PAUSE_ENABLE_Q3 0x15c188UL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 3.
#define PBF_REG_PAUSE_ENABLE_Q4 0x15c18cUL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 4.
#define PBF_REG_PAUSE_ENABLE_Q5 0x15c190UL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 5.
#define PBF_REG_PAUSE_ENABLE_LB_Q 0x15c194UL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 6.
#define PBF_REG_MAC_IF4_ENABLE 0x15c198UL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 4.
#define PBF_REG_MAC_IF5_ENABLE 0x15c19cUL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 5.
#define PBF_REG_DISABLE_WR2TQ_Q0 0x15c1a0UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 0.
#define PBF_REG_DISABLE_WR2TQ_Q1 0x15c1a4UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 1.
#define PBF_REG_DISABLE_WR2TQ_Q2 0x15c1a8UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 2.
#define PBF_REG_DISABLE_WR2TQ_Q3 0x15c1acUL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 3.
#define PBF_REG_DISABLE_WR2TQ_Q4 0x15c1b0UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 4.
#define PBF_REG_DISABLE_WR2TQ_Q5 0x15c1b4UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 5.
#define PBF_REG_DISABLE_WR2TQ_LB_Q 0x15c1b8UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to the LB queue.
#define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 0x15c1bcUL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 0x15c1c0UL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 0x15c1c4UL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 0x15c1c8UL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 0x15c1ccUL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 0x15c1d0UL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_LB_Q 0x15c1d4UL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
#define PBF_REG_TQ_NUM_LINES_Q0 0x15c1d8UL //ACCESS:RW DataWidth:0xc Description: Number of 16 byte lines in the task Q reserved for queue 0.
#define PBF_REG_TQ_NUM_LINES_Q1 0x15c1dcUL //ACCESS:RW DataWidth:0xc Description: Number of 16 byte lines in the task Q reserved for queue 1.
#define PBF_REG_TQ_NUM_LINES_Q2 0x15c1e0UL //ACCESS:RW DataWidth:0xc Description: Number of 16 byte lines in the task Q reserved for queue 2.
#define PBF_REG_TQ_NUM_LINES_Q3 0x15c1e4UL //ACCESS:RW DataWidth:0xc Description: Number of 16 byte lines in the task Q reserved for queue 3.
#define PBF_REG_TQ_NUM_LINES_Q4 0x15c1e8UL //ACCESS:RW DataWidth:0xc Description: Number of 16 byte lines in the task Q reserved for queue 4.
#define PBF_REG_TQ_NUM_LINES_Q5 0x15c1ecUL //ACCESS:RW DataWidth:0xc Description: Number of 16 byte lines in the task Q reserved for queue 5.
#define PBF_REG_TQ_NUM_LINES_LB_Q 0x15c1f0UL //ACCESS:RW DataWidth:0xc Description: Number of 16 byte lines in the task Q reserved for the LB queue.
#define PBF_REG_XSDM_ADDR_0_Q_NUM 0x15c1f4UL //ACCESS:RW DataWidth:0x3 Description: The queue number to which address 0 from XSDM mapps to.
#define PBF_REG_XSDM_ADDR_1_Q_NUM 0x15c1f8UL //ACCESS:RW DataWidth:0x3 Description: The queue number to which address 1 from XSDM mapps to.
#define PBF_REG_XSDM_ADDR_2_Q_NUM 0x15c1fcUL //ACCESS:RW DataWidth:0x3 Description: The queue number to which address 2 from XSDM mapps to.
#define PBF_REG_XSDM_ADDR_3_Q_NUM 0x15c200UL //ACCESS:RW DataWidth:0x3 Description: The queue number to which address 3 from XSDM mapps to.
#define PBF_REG_XSDM_ADDR_4_Q_NUM 0x15c204UL //ACCESS:RW DataWidth:0x3 Description: The queue number to which address 4 from XSDM mapps to.
#define PBF_REG_XSDM_ADDR_5_Q_NUM 0x15c208UL //ACCESS:RW DataWidth:0x3 Description: The queue number to which address 5 from XSDM mapps to.
#define PBF_REG_XSDM_ADDR_6_Q_NUM 0x15c20cUL //ACCESS:RW DataWidth:0x3 Description: The queue number to which address 6 from XSDM mapps to.
#define PBF_REG_XSDM_ADDR_7_Q_NUM 0x15c210UL //ACCESS:RW DataWidth:0x3 Description: The queue number to which address 7 from XSDM mapps to.
#define PBF_REG_TQ_THRSH_Q0 0x15c214UL //ACCESS:RW DataWidth:0x5 Description: Almost full threshold for queue 0 in task Q in 16 byte lines.
#define PBF_REG_TQ_THRSH_Q1 0x15c218UL //ACCESS:RW DataWidth:0x5 Description: Almost full threshold for queue 1 in task Q in 16 byte lines.
#define PBF_REG_TQ_THRSH_Q2 0x15c21cUL //ACCESS:RW DataWidth:0x5 Description: Almost full threshold for queue 2 in task Q in 16 byte lines.
#define PBF_REG_TQ_THRSH_Q3 0x15c220UL //ACCESS:RW DataWidth:0x5 Description: Almost full threshold for queue 3 in task Q in 16 byte lines.
#define PBF_REG_TQ_THRSH_Q4 0x15c224UL //ACCESS:RW DataWidth:0x5 Description: Almost full threshold for queue 4 in task Q in 16 byte lines.
#define PBF_REG_TQ_THRSH_Q5 0x15c228UL //ACCESS:RW DataWidth:0x5 Description: Almost full threshold for queue 5 in task Q in 16 byte lines.
#define PBF_REG_TQ_THRSH_LB_Q 0x15c22cUL //ACCESS:RW DataWidth:0x5 Description: Almost full threshold for the LB queue in task Q in 16 byte lines.
#define PBF_REG_INIT_CRD_Q0 0x15c230UL //ACCESS:RW DataWidth:0xb Description: Initial credit for queue 0 in the tx port buffers in 16 byte lines.
#define PBF_REG_INIT_CRD_Q1 0x15c234UL //ACCESS:RW DataWidth:0xb Description: Initial credit for queue 1 in the tx port buffers in 16 byte lines.
#define PBF_REG_INIT_CRD_Q2 0x15c238UL //ACCESS:RW DataWidth:0xb Description: Initial credit for queue 2 in the tx port buffers in 16 byte lines.
#define PBF_REG_INIT_CRD_Q3 0x15c23cUL //ACCESS:RW DataWidth:0xb Description: Initial credit for queue 3 in the tx port buffers in 16 byte lines.
#define PBF_REG_INIT_CRD_Q4 0x15c240UL //ACCESS:RW DataWidth:0xb Description: Initial credit for queue 4 in the tx port buffers in 16 byte lines.
#define PBF_REG_INIT_CRD_Q5 0x15c244UL //ACCESS:RW DataWidth:0xb Description: Initial credit for queue 5 in the tx port buffers in 16 byte lines.
#define PBF_REG_INIT_CRD_LB_Q 0x15c248UL //ACCESS:RW DataWidth:0xb Description: Initial credit for the LB queue in the tx port buffers in 16 byte lines.
#define PBF_REG_ARB_THRSH_Q0 0x15c24cUL //ACCESS:RW DataWidth:0xb Description: Queue 0 threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_ARB_THRSH_Q1 0x15c250UL //ACCESS:RW DataWidth:0xb Description: Queue 1 threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_ARB_THRSH_Q2 0x15c254UL //ACCESS:RW DataWidth:0xb Description: Queue 2 threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_ARB_THRSH_Q3 0x15c258UL //ACCESS:RW DataWidth:0xb Description: Queue 3 threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_ARB_THRSH_Q4 0x15c25cUL //ACCESS:RW DataWidth:0xb Description: Queue 4 threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_ARB_THRSH_Q5 0x15c260UL //ACCESS:RW DataWidth:0xb Description: Queue 5 threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_ARB_THRSH_LB_Q 0x15c264UL //ACCESS:RW DataWidth:0xb Description: LB Queue threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_P0_PACKETS_WRR_WEIGHT 0x15c268UL //ACCESS:RW DataWidth:0x3 Description: WRR weight of commands destined to port 0 in the command arbiter
#define PBF_REG_P1_PACKETS_WRR_WEIGHT 0x15c26cUL //ACCESS:RW DataWidth:0x3 Description: WRR weight of commands destined to port 1 in the command arbiter
#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270UL //ACCESS:RW DataWidth:0x12 Description: For port 0: Indicates which client is connected to each priority in the strict-priority arbiter. Priority 0 is the highest priority, and priority 5 is the lowest; to which the RR output is connected to (this is not configurable).
#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274UL //ACCESS:RW DataWidth:0x9 Description: For port 1: Indicates which client is connected to each priority in the strict-priority arbiter. Priority 0 is the highest priority, and priority 5 is the lowest; to which the RR output is connected to (this is not configurable).
#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278UL //ACCESS:RW DataWidth:0x6 Description: For port 0: Bit per client to indicate if the client competes in the strict priority arbiter directly (corresponding bit = 1); or first goes to the RR arbiter (corresponding bit = 0); and then competes in the lowest priority in the strict-priority arbiter.
#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27cUL //ACCESS:RW DataWidth:0x3 Description: For port 1: Bit per client to indicate if the client competes in the strict priority arbiter directly (corresponding bit = 1); or first goes to the RR arbiter (corresponding bit = 0); and then competes in the lowest priority in the strict-priority arbiter.
#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280UL //ACCESS:RW DataWidth:0x6 Description: For port 0: Bit per client to indicate if the client is subject to WFQ credit blocking (corresponding bit = 1).
#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284UL //ACCESS:RW DataWidth:0x3 Description: For port 0: Bit per client to indicate if the client is subject to WFQ credit blocking (corresponding bit = 1).
#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288UL //ACCESS:RW DataWidth:0x12 Description: For port 0: For each client that is subject to WFQ (the corresponding bit is 1); indicates to which of the credit registers this client is mapped. For clients which are not credit blocked; their mapping is dont care.
#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28cUL //ACCESS:RW DataWidth:0x9 Description: For port 1: For each client that is subject to WFQ (the corresponding bit is 1); indicates to which of the credit registers this client is mapped. For clients which are not credit blocked; their mapping is dont care.
#define PBF_REG_ETS_ARB_RR_BURST_MODE_P0 0x15c290UL //ACCESS:RW DataWidth:0x1 Description: For port 0: If set; the round robin arbiters pointer will stay on the winning input; instead of moving to the next one. This allows burstiness. This mode should be carefully used; since in certain arbitration configurations it can cause starvation.
#define PBF_REG_ETS_ARB_RR_BURST_MODE_P1 0x15c294UL //ACCESS:RW DataWidth:0x1 Description: For port 1: If set; the round robin arbiters pointer will stay on the winning input; instead of moving to the next one. This allows burstiness. This mode should be carefully used; since in certain arbitration configurations it can cause starvation.
#define PBF_REG_ETS_ARB_SPWAS_BURST_MODE_P0 0x15c298UL //ACCESS:RW DataWidth:0x1 Description: For port 0: If set; the round robin arbiter within the strict priority w/ anti-starvation arbiter; will stay on the winning input; instead of moving to the next one. This allows burstiness. This mode should be carefully used; since in certain arbitration configurations it can cause starvation.
#define PBF_REG_ETS_ARB_SPWAS_BURST_MODE_P1 0x15c29cUL //ACCESS:RW DataWidth:0x1 Description: For port 1: If set; the round robin arbiter within the strict priority w/ anti-starvation arbiter; will stay on the winning input; instead of moving to the next one. This allows burstiness. This mode should be carefully used; since in certain arbitration configurations it can cause starvation.
#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0UL //ACCESS:RW DataWidth:0x10 Description: For port 0: The number of strict priority arbitration slots between 2 RR arbitration slots. A value of 0 means no strict priority cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR arbiter.
#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4UL //ACCESS:RW DataWidth:0x10 Description: For port 1: The number of strict priority arbitration slots between 2 RR arbitration slots. A value of 0 means no strict priority cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR arbiter.
#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8UL //ACCESS:RW DataWidth:0x1f Description: The weight of COS0 in port 0 ETS command arbiter.
#define PBF_REG_COS1_WEIGHT_P0 0x15c2acUL //ACCESS:RW DataWidth:0x1f Description: The weight of COS1 in port 0 ETS command arbiter.
#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0UL //ACCESS:RW DataWidth:0x1f Description: The weight of COS2 in port 0 ETS command arbiter.
#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4UL //ACCESS:RW DataWidth:0x1f Description: The weight of COS3 in port 0 ETS command arbiter.
#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8UL //ACCESS:RW DataWidth:0x1f Description: The weight of COS4 in port 0 ETS command arbiter.
#define PBF_REG_COS5_WEIGHT_P0 0x15c2bcUL //ACCESS:RW DataWidth:0x1f Description: The weight of COS5 in port 0 ETS command arbiter.
#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0UL //ACCESS:RW DataWidth:0x1f Description: The weight of COS0 in port 1 ETS command arbiter.
#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4UL //ACCESS:RW DataWidth:0x1f Description: The weight of COS1 in port 1 ETS command arbiter.
#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8UL //ACCESS:RW DataWidth:0x1f Description: The weight of COS2 in port 1 ETS command arbiter.
#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2ccUL //ACCESS:RW DataWidth:0x1f Description: The upper bound of the weight of COS0 in the ETS command arbiter of port 0.
#define PBF_REG_COS1_UPPER_BOUND_P0 0x15c2d0UL //ACCESS:RW DataWidth:0x1f Description: The upper bound of the weight of COS1 in the ETS command arbiter of port 0.
#define PBF_REG_COS2_UPPER_BOUND_P0 0x15c2d4UL //ACCESS:RW DataWidth:0x1f Description: The upper bound of the weight of COS2 in the ETS command arbiter of port 0.
#define PBF_REG_COS3_UPPER_BOUND_P0 0x15c2d8UL //ACCESS:RW DataWidth:0x1f Description: The upper bound of the weight of COS3 in the ETS command arbiter of port 0.
#define PBF_REG_COS4_UPPER_BOUND_P0 0x15c2dcUL //ACCESS:RW DataWidth:0x1f Description: The upper bound of the weight of COS4 in the ETS command arbiter of port 0.
#define PBF_REG_COS5_UPPER_BOUND_P0 0x15c2e0UL //ACCESS:RW DataWidth:0x1f Description: The upper bound of the weight of COS5 in the ETS command arbiter of port 0.
#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4UL //ACCESS:RW DataWidth:0x1f Description: The upper bound of the weight of COS0 in the ETS command arbiter of port 1.
#define PBF_REG_COS1_UPPER_BOUND_P1 0x15c2e8UL //ACCESS:RW DataWidth:0x1f Description: The upper bound of the weight of COS1 in the ETS command arbiter of port 1.
#define PBF_REG_COS2_UPPER_BOUND_P1 0x15c2ecUL //ACCESS:RW DataWidth:0x1f Description: The upper bound of the weight of COS2 in the ETS command arbiter of port 1.
#define PBF_REG_TXP_THRSH_Q0 0x15c2f0UL //ACCESS:RW DataWidth:0x4 Description: Tx queue 0 almost full threshold in 16 byte lines.
#define PBF_REG_TXP_THRSH_Q1 0x15c2f4UL //ACCESS:RW DataWidth:0x4 Description: Tx queue 1 almost full threshold in 16 byte lines.
#define PBF_REG_TXP_THRSH_Q2 0x15c2f8UL //ACCESS:RW DataWidth:0x4 Description: Tx queue 2 almost full threshold in 16 byte lines.
#define PBF_REG_TXP_THRSH_Q3 0x15c2fcUL //ACCESS:RW DataWidth:0x4 Description: Tx queue 3 almost full threshold in 16 byte lines.
#define PBF_REG_TXP_THRSH_Q4 0x15c300UL //ACCESS:RW DataWidth:0x4 Description: Tx queue 4 almost full threshold in 16 byte lines.
#define PBF_REG_TXP_THRSH_Q5 0x15c304UL //ACCESS:RW DataWidth:0x4 Description: Tx queue 5 almost full threshold in 16 byte lines.
#define PBF_REG_TXP_LB_Q 0x15c308UL //ACCESS:RW DataWidth:0x4 Description: Tx LB queue almost full threshold in 16 byte lines.
#define PBF_REG_NUM_SENT_BYTES_Q0 0x15c30cUL //ACCESS:ST DataWidth:0x20 Description: Number of bytes transmitted on queue 0.
#define PBF_REG_NUM_SENT_BYTES_Q1 0x15c310UL //ACCESS:ST DataWidth:0x20 Description: Number of bytes transmitted on queue 1.
#define PBF_REG_NUM_SENT_BYTES_Q2 0x15c314UL //ACCESS:ST DataWidth:0x20 Description: Number of bytes transmitted on queue 2.
#define PBF_REG_NUM_SENT_BYTES_Q3 0x15c318UL //ACCESS:ST DataWidth:0x20 Description: Number of bytes transmitted on queue 3.
#define PBF_REG_NUM_SENT_BYTES_Q4 0x15c31cUL //ACCESS:ST DataWidth:0x20 Description: Number of bytes transmitted on queue 4.
#define PBF_REG_NUM_SENT_BYTES_Q5 0x15c320UL //ACCESS:ST DataWidth:0x20 Description: Number of bytes transmitted on queue 5.
#define PBF_REG_NUM_SENT_BYTES_LB_Q 0x15c324UL //ACCESS:ST DataWidth:0x20 Description: Number of bytes transmitted on the LB queue.
#define PBF_REG_NUM_SENT_PKTS_Q0 0x15c328UL //ACCESS:ST DataWidth:0x18 Description: Number of packets transmitted on queue 0.
#define PBF_REG_NUM_SENT_PKTS_Q1 0x15c32cUL //ACCESS:ST DataWidth:0x18 Description: Number of packets transmitted on queue 1.
#define PBF_REG_NUM_SENT_PKTS_Q2 0x15c330UL //ACCESS:ST DataWidth:0x18 Description: Number of packets transmitted on queue 2.
#define PBF_REG_NUM_SENT_PKTS_Q3 0x15c334UL //ACCESS:ST DataWidth:0x18 Description: Number of packets transmitted on queue 3.
#define PBF_REG_NUM_SENT_PKTS_Q4 0x15c338UL //ACCESS:ST DataWidth:0x18 Description: Number of packets transmitted on queue 4.
#define PBF_REG_NUM_SENT_PKTS_Q5 0x15c33cUL //ACCESS:ST DataWidth:0x18 Description: Number of packets transmitted on queue 5.
#define PBF_REG_NUM_SENT_PKTS_LB_Q 0x15c340UL //ACCESS:ST DataWidth:0x18 Description: Number of packets transmitted on the LB queue.
#define PBF_REG_NUM_ERR_SENT_PKTS_Q0 0x15c344UL //ACCESS:ST DataWidth:0x8 Description: Number of packets with error transmitted on queue 0.
#define PBF_REG_NUM_ERR_SENT_PKTS_Q1 0x15c348UL //ACCESS:ST DataWidth:0x8 Description: Number of packets with error transmitted on queue 1.
#define PBF_REG_NUM_ERR_SENT_PKTS_Q2 0x15c34cUL //ACCESS:ST DataWidth:0x8 Description: Number of packets with error transmitted on queue 2.
#define PBF_REG_NUM_ERR_SENT_PKTS_Q3 0x15c350UL //ACCESS:ST DataWidth:0x8 Description: Number of packets with error transmitted on queue 3.
#define PBF_REG_NUM_ERR_SENT_PKTS_Q4 0x15c354UL //ACCESS:ST DataWidth:0x8 Description: Number of packets with error transmitted on queue 4.
#define PBF_REG_NUM_ERR_SENT_PKTS_Q5 0x15c358UL //ACCESS:ST DataWidth:0x8 Description: Number of packets with error transmitted on queue 5.
#define PBF_REG_NUM_ERR_SENT_PKTS_LB_Q 0x15c35cUL //ACCESS:ST DataWidth:0x8 Description: Number of packets with error transmitted on the LB queue.
#define PBF_REG_LAST_CID_W_ERROR_Q0 0x15c360UL //ACCESS:R DataWidth:0xa Description: last CID with either parsing or PCI error which was transmitted with error or dropped on queue 0.
#define PBF_REG_LAST_CID_W_ERROR_Q1 0x15c364UL //ACCESS:R DataWidth:0xa Description: last CID with either parsing or PCI error which was transmitted with error or dropped on queue 1.
#define PBF_REG_LAST_CID_W_ERROR_Q2 0x15c368UL //ACCESS:R DataWidth:0xa Description: last CID with either parsing or PCI error which was transmitted with error or dropped on queue 2.
#define PBF_REG_LAST_CID_W_ERROR_Q3 0x15c36cUL //ACCESS:R DataWidth:0xa Description: last CID with either parsing or PCI error which was transmitted with error or dropped on queue 3.
#define PBF_REG_LAST_CID_W_ERROR_Q4 0x15c370UL //ACCESS:R DataWidth:0xa Description: last CID with either parsing or PCI error which was transmitted with error or dropped on queue 4.
#define PBF_REG_LAST_CID_W_ERROR_Q5 0x15c374UL //ACCESS:R DataWidth:0xa Description: last CID with either parsing or PCI error which was transmitted with error or dropped on queue 5.
#define PBF_REG_CMDS_RCVD_ON_Q0 0x15c378UL //ACCESS:ST DataWidth:0x18 Description: Number of commands received on queue 0 from STORM.
#define PBF_REG_CMDS_RCVD_ON_Q1 0x15c37cUL //ACCESS:ST DataWidth:0x18 Description: Number of commands received on queue 1 from STORM.
#define PBF_REG_CMDS_RCVD_ON_Q2 0x15c380UL //ACCESS:ST DataWidth:0x18 Description: Number of commands received on queue 2 from STORM.
#define PBF_REG_CMDS_RCVD_ON_Q3 0x15c384UL //ACCESS:ST DataWidth:0x18 Description: Number of commands received on queue 3 from STORM.
#define PBF_REG_CMDS_RCVD_ON_Q4 0x15c388UL //ACCESS:ST DataWidth:0x18 Description: Number of commands received on queue 4 from STORM.
#define PBF_REG_CMDS_RCVD_ON_Q5 0x15c38cUL //ACCESS:ST DataWidth:0x18 Description: Number of commands received on queue 5 from STORM.
#define PBF_REG_CMDS_RCVD_ON_LB_Q 0x15c390UL //ACCESS:ST DataWidth:0x18 Description: Number of commands received on the LB queue from STORM.
#define PBF_REG_TX_MEM_D_EVEN_TM 0x15c394UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_D_ODD_TM 0x15c398UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_E_EVEN_TM 0x15c39cUL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_E_ODD_TM 0x15c3a0UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_F_EVEN_TM 0x15c3a4UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_F_ODD_TM 0x15c3a8UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_G_EVEN_TM 0x15c3acUL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_TX_MEM_G_ODD_TM 0x15c3b0UL //ACCESS:RW DataWidth:0x5 Description: Test mode input port for memory instance.
#define PBF_REG_DISABLE_PF 0x1402e8UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Disable a PF from transmitting.
#define PBF_REG_DISABLE_PF_SIZE 1
#define PBF_REG_DISABLE_VF 0x1402ecUL //ACCESS:RW DataWidth:0x1 SPLIT:64 Description: Disable a VF from transmitting.
#define PBF_REG_DISABLE_VF_SIZE 1
#define PBF_REG_COS0_WFQ_CREDIT_P0 0x140314UL //ACCESS:R DataWidth:0x20 Description: current WFQ credit of COS0 in port 0 ETS arbiter.
#define PBF_REG_COS0_WFQ_CREDIT_P0_SIZE 1
#define PBF_REG_COS0_WFQ_CREDIT_P1 0x140318UL //ACCESS:R DataWidth:0x20 Description: current WFQ credit of COS0 in port 1 ETS arbiter.
#define PBF_REG_COS0_WFQ_CREDIT_P1_SIZE 1
#define PBF_REG_COS1_WFQ_CREDIT_P0 0x14031cUL //ACCESS:R DataWidth:0x20 Description: current WFQ credit of COS1 in port 0 ETS arbiter.
#define PBF_REG_COS1_WFQ_CREDIT_P0_SIZE 1
#define PBF_REG_COS1_WFQ_CREDIT_P1 0x140320UL //ACCESS:R DataWidth:0x20 Description: current WFQ credit of COS1 in port 1 ETS arbiter.
#define PBF_REG_COS1_WFQ_CREDIT_P1_SIZE 1
#define PBF_REG_COS2_WFQ_CREDIT_P0 0x140324UL //ACCESS:R DataWidth:0x20 Description: current WFQ credit of COS2 in port 0 ETS arbiter.
#define PBF_REG_COS2_WFQ_CREDIT_P0_SIZE 1
#define PBF_REG_COS2_WFQ_CREDIT_P1 0x140328UL //ACCESS:R DataWidth:0x20 Description: current WFQ credit of COS2 in port 1 ETS arbiter.
#define PBF_REG_COS2_WFQ_CREDIT_P1_SIZE 1
#define PBF_REG_COS3_WFQ_CREDIT_P0 0x14032cUL //ACCESS:R DataWidth:0x20 Description: current WFQ credit of COS3 in port 0 ETS arbiter.
#define PBF_REG_COS3_WFQ_CREDIT_P0_SIZE 1
#define PBF_REG_COS4_WFQ_CREDIT_P0 0x140330UL //ACCESS:R DataWidth:0x20 Description: current WFQ credit of COS4 in port 0 ETS arbiter.
#define PBF_REG_COS4_WFQ_CREDIT_P0_SIZE 1
#define PBF_REG_COS5_WFQ_CREDIT_P0 0x140334UL //ACCESS:R DataWidth:0x20 Description: current WFQ credit of COS5 in port 0 ETS arbiter.
#define PBF_REG_COS5_WFQ_CREDIT_P0_SIZE 1
#define PBF_REG_CREDIT_LB_Q 0x140338UL //ACCESS:R DataWidth:0xb Description: Current credit for the LB queue in the tx port buffers in 16 byte lines.
#define PBF_REG_CREDIT_LB_Q_SIZE 1
#define PBF_REG_CREDIT_Q0 0x14033cUL //ACCESS:R DataWidth:0xb Description: Current credit for queue 0 in the tx port buffers in 16 byte lines.
#define PBF_REG_CREDIT_Q0_SIZE 1
#define PBF_REG_CREDIT_Q1 0x140340UL //ACCESS:R DataWidth:0xb Description: Current credit for queue 1 in the tx port buffers in 16 byte lines.
#define PBF_REG_CREDIT_Q1_SIZE 1
#define PBF_REG_CREDIT_Q2 0x140344UL //ACCESS:R DataWidth:0xb Description: Current credit for queue 2 in the tx port buffers in 16 byte lines.
#define PBF_REG_CREDIT_Q2_SIZE 1
#define PBF_REG_CREDIT_Q3 0x140348UL //ACCESS:R DataWidth:0xb Description: Current credit for queue 3 in the tx port buffers in 16 byte lines.
#define PBF_REG_CREDIT_Q3_SIZE 1
#define PBF_REG_CREDIT_Q4 0x14034cUL //ACCESS:R DataWidth:0xb Description: Current credit for queue 4 in the tx port buffers in 16 byte lines.
#define PBF_REG_CREDIT_Q4_SIZE 1
#define PBF_REG_CREDIT_Q5 0x140350UL //ACCESS:R DataWidth:0xb Description: Current credit for queue 5 in the tx port buffers in 16 byte lines.
#define PBF_REG_CREDIT_Q5_SIZE 1
#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for the amount credits in 16 bytes lines added for the LB queue. Reset upon init.
#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q_SIZE 1
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for the amount credits in 16 bytes lines added for queue 0. Reset upon init.
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0_SIZE 1
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035cUL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for the amount credits in 16 bytes lines added for queue 1. Reset upon init.
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1_SIZE 1
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q2 0x140360UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for the amount credits in 16 bytes lines added for queue 2. Reset upon init.
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q2_SIZE 1
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q3 0x140364UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for the amount credits in 16 bytes lines added for queue 3. Reset upon init.
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q3_SIZE 1
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q4 0x140368UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for the amount credits in 16 bytes lines added for queue 4. Reset upon init.
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q4_SIZE 1
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q5 0x14036cUL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for the amount credits in 16 bytes lines added for queue 5. Reset upon init.
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q5_SIZE 1
#define PBF_REG_TASK_CNT_LB_Q 0x140370UL //ACCESS:R DataWidth:0x8 Description: Number of tasks in queue 0 task queue.
#define PBF_REG_TASK_CNT_LB_Q_SIZE 1
#define PBF_REG_TASK_CNT_Q0 0x140374UL //ACCESS:R DataWidth:0x8 Description: Number of tasks in queue 0 task queue.
#define PBF_REG_TASK_CNT_Q0_SIZE 1
#define PBF_REG_TASK_CNT_Q1 0x140378UL //ACCESS:R DataWidth:0x8 Description: Number of tasks in queue 0 task queue.
#define PBF_REG_TASK_CNT_Q1_SIZE 1
#define PBF_REG_TASK_CNT_Q2 0x14037cUL //ACCESS:R DataWidth:0x8 Description: Number of tasks in queue 0 task queue.
#define PBF_REG_TASK_CNT_Q2_SIZE 1
#define PBF_REG_TASK_CNT_Q3 0x140380UL //ACCESS:R DataWidth:0x8 Description: Number of tasks in queue 0 task queue.
#define PBF_REG_TASK_CNT_Q3_SIZE 1
#define PBF_REG_TASK_CNT_Q4 0x140384UL //ACCESS:R DataWidth:0x8 Description: Number of tasks in queue 0 task queue.
#define PBF_REG_TASK_CNT_Q4_SIZE 1
#define PBF_REG_TASK_CNT_Q5 0x140388UL //ACCESS:R DataWidth:0x8 Description: Number of tasks in queue 0 task queue.
#define PBF_REG_TASK_CNT_Q5_SIZE 1
#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038cUL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for number of 8 byte lines freed from the LB task queue. Reset upon init.
#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q_SIZE 1
#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for number of 8 byte lines freed from the task queue 0. Reset upon init.
#define PBF_REG_TQ_LINES_FREED_CNT_Q0_SIZE 1
#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for number of 8 byte lines freed from task queue 1. Reset upon init.
#define PBF_REG_TQ_LINES_FREED_CNT_Q1_SIZE 1
#define PBF_REG_TQ_LINES_FREED_CNT_Q2 0x140398UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for number of 8 byte lines freed from task queue 2. Reset upon init.
#define PBF_REG_TQ_LINES_FREED_CNT_Q2_SIZE 1
#define PBF_REG_TQ_LINES_FREED_CNT_Q3 0x14039cUL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for number of 8 byte lines freed from task queue 3. Reset upon init.
#define PBF_REG_TQ_LINES_FREED_CNT_Q3_SIZE 1
#define PBF_REG_TQ_LINES_FREED_CNT_Q4 0x1403a0UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for number of 8 byte lines freed from task queue 4. Reset upon init.
#define PBF_REG_TQ_LINES_FREED_CNT_Q4_SIZE 1
#define PBF_REG_TQ_LINES_FREED_CNT_Q5 0x1403a4UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for number of 8 byte lines freed from task queue 5. Reset upon init.
#define PBF_REG_TQ_LINES_FREED_CNT_Q5_SIZE 1
#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8UL //ACCESS:R DataWidth:0xd Description: Number of 8 bytes lines occupied in the task queue of the LB queue.
#define PBF_REG_TQ_OCCUPANCY_LB_Q_SIZE 1
#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403acUL //ACCESS:R DataWidth:0xd Description: Number of 8 bytes lines occupied in the task queue of queue 0.
#define PBF_REG_TQ_OCCUPANCY_Q0_SIZE 1
#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0UL //ACCESS:R DataWidth:0xd Description: Number of 8 bytes lines occupied in the task queue of queue 1.
#define PBF_REG_TQ_OCCUPANCY_Q1_SIZE 1
#define PBF_REG_TQ_OCCUPANCY_Q2 0x1403b4UL //ACCESS:R DataWidth:0xd Description: Number of 8 bytes lines occupied in the task queue of queue 2.
#define PBF_REG_TQ_OCCUPANCY_Q2_SIZE 1
#define PBF_REG_TQ_OCCUPANCY_Q3 0x1403b8UL //ACCESS:R DataWidth:0xd Description: Number of 8 bytes lines occupied in the task queue of queue 3.
#define PBF_REG_TQ_OCCUPANCY_Q3_SIZE 1
#define PBF_REG_TQ_OCCUPANCY_Q4 0x1403bcUL //ACCESS:R DataWidth:0xd Description: Number of 8 bytes lines occupied in the task queue of queue 4.
#define PBF_REG_TQ_OCCUPANCY_Q4_SIZE 1
#define PBF_REG_TQ_OCCUPANCY_Q5 0x1403c0UL //ACCESS:R DataWidth:0xd Description: Number of 8 bytes lines occupied in the task queue of queue 5.
#define PBF_REG_TQ_OCCUPANCY_Q5_SIZE 1
#define PBF_REG_EVEN_TXP_MEM_LB_Q 0x1403d0UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_EVEN_TXP_MEM_LB_Q_SIZE 3
#define PBF_REG_EVEN_TXP_MEM_Q0 0x1403e0UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_EVEN_TXP_MEM_Q0_SIZE 3
#define PBF_REG_EVEN_TXP_MEM_Q1 0x1403f0UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_EVEN_TXP_MEM_Q1_SIZE 3
#define PBF_REG_EVEN_TXP_MEM_Q2 0x140400UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_EVEN_TXP_MEM_Q2_SIZE 3
#define PBF_REG_EVEN_TXP_MEM_Q3 0x140410UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_EVEN_TXP_MEM_Q3_SIZE 3
#define PBF_REG_EVEN_TXP_MEM_Q4 0x140420UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_EVEN_TXP_MEM_Q4_SIZE 3
#define PBF_REG_EVEN_TXP_MEM_Q5 0x140430UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_EVEN_TXP_MEM_Q5_SIZE 3
#define PBF_REG_ODD_TXP_MEM_LB_Q 0x140440UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_ODD_TXP_MEM_LB_Q_SIZE 3
#define PBF_REG_ODD_TXP_MEM_Q0 0x140450UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_ODD_TXP_MEM_Q0_SIZE 3
#define PBF_REG_ODD_TXP_MEM_Q1 0x140460UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_ODD_TXP_MEM_Q1_SIZE 3
#define PBF_REG_ODD_TXP_MEM_Q2 0x140470UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_ODD_TXP_MEM_Q2_SIZE 3
#define PBF_REG_ODD_TXP_MEM_Q3 0x140480UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_ODD_TXP_MEM_Q3_SIZE 3
#define PBF_REG_ODD_TXP_MEM_Q4 0x140490UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_ODD_TXP_MEM_Q4_SIZE 3
#define PBF_REG_ODD_TXP_MEM_Q5 0x1404a0UL //ACCESS:WB DataWidth:0x41 Description: Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_ODD_TXP_MEM_Q5_SIZE 3
#define PBF_REG_TXP_OCCUPANCY_Q0 0x1404b0UL //ACCESS:R DataWidth:0xc Description: Number of 8 bytes lines occupied in the TX port buffer of queue 0.
#define PBF_REG_TXP_OCCUPANCY_Q0_SIZE 1
#define PBF_REG_TXP_OCCUPANCY_Q1 0x1404b4UL //ACCESS:R DataWidth:0xc Description: Number of 8 bytes lines occupied in the TX port buffer of queue 1.
#define PBF_REG_TXP_OCCUPANCY_Q1_SIZE 1
#define PBF_REG_TXP_OCCUPANCY_Q2 0x1404b8UL //ACCESS:R DataWidth:0xc Description: Number of 8 bytes lines occupied in the TX port buffer of queue 2.
#define PBF_REG_TXP_OCCUPANCY_Q2_SIZE 1
#define PBF_REG_TXP_OCCUPANCY_Q3 0x1404bcUL //ACCESS:R DataWidth:0xc Description: Number of 8 bytes lines occupied in the TX port buffer of queue 3.
#define PBF_REG_TXP_OCCUPANCY_Q3_SIZE 1
#define PBF_REG_TXP_OCCUPANCY_Q4 0x1404c0UL //ACCESS:R DataWidth:0xc Description: Number of 8 bytes lines occupied in the TX port buffer of queue 4.
#define PBF_REG_TXP_OCCUPANCY_Q4_SIZE 1
#define PBF_REG_TXP_OCCUPANCY_Q5 0x1404c4UL //ACCESS:R DataWidth:0xc Description: Number of 8 bytes lines occupied in the TX port buffer of queue 5.
#define PBF_REG_TXP_OCCUPANCY_Q5_SIZE 1
#define PBF_REG_TXP_OCCUPANCY_LB_Q 0x1404c8UL //ACCESS:R DataWidth:0xc Description: Number of 8 bytes lines occupied in the TX port buffer of the LB queue.
#define PBF_REG_TXP_OCCUPANCY_LB_Q_SIZE 1
#define PBF_REG_TXP_NUM_PACKETS_Q0 0x1404ccUL //ACCESS:R DataWidth:0xb Description: Number packets in the TX port buffer of queue 0.
#define PBF_REG_TXP_NUM_PACKETS_Q0_SIZE 1
#define PBF_REG_TXP_NUM_PACKETS_Q1 0x1404d0UL //ACCESS:R DataWidth:0xb Description: Number packets in the TX port buffer of queue 1.
#define PBF_REG_TXP_NUM_PACKETS_Q1_SIZE 1
#define PBF_REG_TXP_NUM_PACKETS_Q2 0x1404d4UL //ACCESS:R DataWidth:0xb Description: Number packets in the TX port buffer of queue 2.
#define PBF_REG_TXP_NUM_PACKETS_Q2_SIZE 1
#define PBF_REG_TXP_NUM_PACKETS_Q3 0x1404d8UL //ACCESS:R DataWidth:0xb Description: Number packets in the TX port buffer of queue 3.
#define PBF_REG_TXP_NUM_PACKETS_Q3_SIZE 1
#define PBF_REG_TXP_NUM_PACKETS_Q4 0x1404dcUL //ACCESS:R DataWidth:0xb Description: Number packets in the TX port buffer of queue 4.
#define PBF_REG_TXP_NUM_PACKETS_Q4_SIZE 1
#define PBF_REG_TXP_NUM_PACKETS_Q5 0x1404e0UL //ACCESS:R DataWidth:0xb Description: Number packets in the TX port buffer of queue 5.
#define PBF_REG_TXP_NUM_PACKETS_Q5_SIZE 1
#define PBF_REG_TXP_NUM_PACKETS_LB_Q 0x1404e4UL //ACCESS:R DataWidth:0xb Description: Number packets in the TX port buffer of the LB queue.
#define PBF_REG_TXP_NUM_PACKETS_LB_Q_SIZE 1
#define PBF_REG_INIT_P0 0x140004UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Init bit for port 0. When set the initial credit of port 0 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
#define PBF_REG_INIT_P0_SIZE 1
#define PBF_REG_INIT_P1 0x140008UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Init bit for port 1. When set the initial credit of port 1 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
#define PBF_REG_INIT_P1_SIZE 1
#define PBF_REG_INIT_P4 0x14000cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Init bit for port 4. When set the initial credit of port 4 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
#define PBF_REG_INIT_P4_SIZE 1
#define PBF_REG_PORT_MODE 0x140010UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - 0 - the device is in 2 port mode; 1 - 4 port mode.
#define PBF_REG_PORT_MODE_SIZE 1
#define PBF_REG_P0_PAUSE_ENABLE 0x140014UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indication that pause is enabled for port 0.
#define PBF_REG_P0_PAUSE_ENABLE_SIZE 1
#define PBF_REG_P1_PAUSE_ENABLE 0x140018UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indication that pause is enabled for port 1.
#define PBF_REG_P1_PAUSE_ENABLE_SIZE 1
#define PBF_REG_P2_PAUSE_ENABLE 0x14001cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indication that pause is enabled for port 2.
#define PBF_REG_P2_PAUSE_ENABLE_SIZE 1
#define PBF_REG_P3_PAUSE_ENABLE 0x140020UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indication that pause is enabled for port 3.
#define PBF_REG_P3_PAUSE_ENABLE_SIZE 1
#define PBF_REG_P4_PAUSE_ENABLE 0x140024UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indication that pause is enabled for port 4.
#define PBF_REG_P4_PAUSE_ENABLE_SIZE 1
#define PBF_REG_DISABLE_WR2TQ_P0 0x140048UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable bit per port 0 for the write interface of the STORM to that port task Q.
#define PBF_REG_DISABLE_WR2TQ_P0_SIZE 1
#define PBF_REG_DISABLE_WR2TQ_P1 0x14004cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable bit per port 1 for the write interface of the STORM to that port task Q.
#define PBF_REG_DISABLE_WR2TQ_P1_SIZE 1
#define PBF_REG_DISABLE_WR2TQ_P2 0x140050UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable bit per port 2 for the write interface of the STORM to that port task Q.
#define PBF_REG_DISABLE_WR2TQ_P2_SIZE 1
#define PBF_REG_DISABLE_WR2TQ_P3 0x140054UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable bit per port 3 for the write interface of the STORM to that port task Q.
#define PBF_REG_DISABLE_WR2TQ_P3_SIZE 1
#define PBF_REG_DISABLE_WR2TQ_P4 0x140058UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable bit per port 4 for the write interface of the STORM to that port task Q.
#define PBF_REG_DISABLE_WR2TQ_P4_SIZE 1
#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable processing further tasks from port 0 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_P0_SIZE 1
#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable processing further tasks from port 1 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_P1_SIZE 1
#define PBF_REG_DISABLE_NEW_TASK_PROC_P2 0x140064UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable processing further tasks from port 2 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_P2_SIZE 1
#define PBF_REG_DISABLE_NEW_TASK_PROC_P3 0x140068UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable processing further tasks from port 3 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_P3_SIZE 1
#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable processing further tasks from port 4 (after ending the current task in process).
#define PBF_REG_DISABLE_NEW_TASK_PROC_P4_SIZE 1
#define PBF_REG_TQ_P0_NUM_LINES 0x140074UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Number of 16 byte lines in the task Q reserved for port 0.
#define PBF_REG_TQ_P0_NUM_LINES_SIZE 1
#define PBF_REG_TQ_P1_NUM_LINES 0x140078UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Number of 16 byte lines in the task Q reserved for port 1.
#define PBF_REG_TQ_P1_NUM_LINES_SIZE 1
#define PBF_REG_TQ_P2_NUM_LINES 0x14007cUL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Number of 16 byte lines in the task Q reserved for port 2.
#define PBF_REG_TQ_P2_NUM_LINES_SIZE 1
#define PBF_REG_TQ_P3_NUM_LINES 0x140080UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Number of 16 byte lines in the task Q reserved for port 3.
#define PBF_REG_TQ_P3_NUM_LINES_SIZE 1
#define PBF_REG_TQ_P4_NUM_LINES 0x140084UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Number of 16 byte lines in the task Q reserved for port 4.
#define PBF_REG_TQ_P4_NUM_LINES_SIZE 1
#define PBF_REG_XSDM_ADDR_P0 0x140088UL //ACCESS:R DataWidth:0x5 Description: Removed for E3 B0 - Xsdm hi address when sending a task for port 0.
#define PBF_REG_XSDM_ADDR_P0_SIZE 1
#define PBF_REG_XSDM_ADDR_P1 0x14008cUL //ACCESS:R DataWidth:0x5 Description: Removed for E3 B0 - Xsdm hi address when sending a task for port 0.
#define PBF_REG_XSDM_ADDR_P1_SIZE 1
#define PBF_REG_XSDM_ADDR_P2 0x140090UL //ACCESS:R DataWidth:0x5 Description: Removed for E3 B0 - Xsdm hi address when sending a task for port 0.
#define PBF_REG_XSDM_ADDR_P2_SIZE 1
#define PBF_REG_XSDM_ADDR_P3 0x140094UL //ACCESS:R DataWidth:0x5 Description: Removed for E3 B0 - Xsdm hi address when sending a task for port 0.
#define PBF_REG_XSDM_ADDR_P3_SIZE 1
#define PBF_REG_XSDM_ADDR_P4 0x140098UL //ACCESS:R DataWidth:0x5 Description: Removed for E3 B0 - Xsdm hi address when sending a task for port 0.
#define PBF_REG_XSDM_ADDR_P4_SIZE 1
#define PBF_REG_P0_TQ_THRSH 0x1400a0UL //ACCESS:R DataWidth:0x5 Description: Removed for E3 B0 - Almost full threshold for port 0 in task Q in 16 byte lines.
#define PBF_REG_P0_TQ_THRSH_SIZE 1
#define PBF_REG_P1_TQ_THRSH 0x1400a4UL //ACCESS:R DataWidth:0x5 Description: Removed for E3 B0 - Almost full threshold for port 1 in task Q in 16 byte lines.
#define PBF_REG_P1_TQ_THRSH_SIZE 1
#define PBF_REG_P2_TQ_THRSH 0x1400a8UL //ACCESS:R DataWidth:0x5 Description: Removed for E3 B0 - Almost full threshold for port 2 in task Q in 16 byte lines.
#define PBF_REG_P2_TQ_THRSH_SIZE 1
#define PBF_REG_P3_TQ_THRSH 0x1400acUL //ACCESS:R DataWidth:0x5 Description: Removed for E3 B0 - Almost full threshold for port 3 in task Q in 16 byte lines.
#define PBF_REG_P3_TQ_THRSH_SIZE 1
#define PBF_REG_P4_TQ_THRSH 0x1400b0UL //ACCESS:R DataWidth:0x5 Description: Removed for E3 B0 - Almost full threshold for port 4 in task Q in 16 byte lines.
#define PBF_REG_P4_TQ_THRSH_SIZE 1
#define PBF_REG_P0_INIT_CRD 0x1400d0UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Initial credit for port 0 in the tx port buffers in 16 byte lines.
#define PBF_REG_P0_INIT_CRD_SIZE 1
#define PBF_REG_P1_INIT_CRD 0x1400d4UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Initial credit for port 0 in the tx port buffers in 16 byte lines.
#define PBF_REG_P1_INIT_CRD_SIZE 1
#define PBF_REG_P2_INIT_CRD 0x1400d8UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Initial credit for port 0 in the tx port buffers in 16 byte lines.
#define PBF_REG_P2_INIT_CRD_SIZE 1
#define PBF_REG_P3_INIT_CRD 0x1400dcUL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Initial credit for port 0 in the tx port buffers in 16 byte lines.
#define PBF_REG_P3_INIT_CRD_SIZE 1
#define PBF_REG_P4_INIT_CRD 0x1400e0UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Initial credit for port 0 in the tx port buffers in 16 byte lines.
#define PBF_REG_P4_INIT_CRD_SIZE 1
#define PBF_REG_P0_ARB_THRSH 0x1400e4UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Port 0 threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_P0_ARB_THRSH_SIZE 1
#define PBF_REG_P1_ARB_THRSH 0x1400e8UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Port 1 threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_P1_ARB_THRSH_SIZE 1
#define PBF_REG_P2_ARB_THRSH 0x1400ecUL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Port 2 threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_P2_ARB_THRSH_SIZE 1
#define PBF_REG_P3_ARB_THRSH 0x1400f0UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Port 3 threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_P3_ARB_THRSH_SIZE 1
#define PBF_REG_P4_ARB_THRSH 0x1400f4UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Port 04threshold used by arbiter in 16 byte lines used when pause not suppoterd.
#define PBF_REG_P4_ARB_THRSH_SIZE 1
#define PBF_REG_P0_WEIGHT 0x140100UL //ACCESS:R DataWidth:0x2 Description: Removed for E3 B0 - Weight of port 0 in the arbitration.
#define PBF_REG_P0_WEIGHT_SIZE 1
#define PBF_REG_P1_WEIGHT 0x140104UL //ACCESS:R DataWidth:0x2 Description: Removed for E3 B0 - Weight of port 1 in the arbitration.
#define PBF_REG_P1_WEIGHT_SIZE 1
#define PBF_REG_P2_WEIGHT 0x140108UL //ACCESS:R DataWidth:0x2 Description: Removed for E3 B0 - Weight of port 2 in the arbitration.
#define PBF_REG_P2_WEIGHT_SIZE 1
#define PBF_REG_P3_WEIGHT 0x14010cUL //ACCESS:R DataWidth:0x2 Description: Removed for E3 B0 -Weight of port 3 in the arbitration.
#define PBF_REG_P3_WEIGHT_SIZE 1
#define PBF_REG_P4_WEIGHT 0x140110UL //ACCESS:R DataWidth:0x2 Description: Removed for E3 B0 - Weight of port 4 in the arbitration.
#define PBF_REG_P4_WEIGHT_SIZE 1
#define PBF_REG_P0_TXP_THRSH 0x140114UL //ACCESS:R DataWidth:0x4 Description: Removed for E3 B0 - Tx port 0 almost full threshold in 16 byte lines.
#define PBF_REG_P0_TXP_THRSH_SIZE 1
#define PBF_REG_P1_TXP_THRSH 0x140118UL //ACCESS:R DataWidth:0x4 Description: Removed for E3 B0 - Tx port 1 almost full threshold in 16 byte lines.
#define PBF_REG_P1_TXP_THRSH_SIZE 1
#define PBF_REG_P2_TXP_THRSH 0x14011cUL //ACCESS:R DataWidth:0x4 Description: Removed for E3 B0 - Tx port 2 almost full threshold in 16 byte lines.
#define PBF_REG_P2_TXP_THRSH_SIZE 1
#define PBF_REG_P3_TXP_THRSH 0x140120UL //ACCESS:R DataWidth:0x4 Description: Removed for E3 B0 - Tx port 3 almost full threshold in 16 byte lines.
#define PBF_REG_P3_TXP_THRSH_SIZE 1
#define PBF_REG_P4_TXP_THRSH 0x140124UL //ACCESS:R DataWidth:0x4 Description: Removed for E3 B0 - Tx port 4 almost full threshold in 16 byte lines.
#define PBF_REG_P4_TXP_THRSH_SIZE 1
#define PBF_REG_NUM_SENT_BYTES_P0 0x140144UL //ACCESS:R DataWidth:0x20 Description: Removed for E3 B0 - Number of bytes transmitted on port 0.
#define PBF_REG_NUM_SENT_BYTES_P0_SIZE 1
#define PBF_REG_NUM_SENT_BYTES_P1 0x140148UL //ACCESS:R DataWidth:0x20 Description: Removed for E3 B0 - Number of bytes transmitted on port 1.
#define PBF_REG_NUM_SENT_BYTES_P1_SIZE 1
#define PBF_REG_NUM_SENT_BYTES_P4 0x14014cUL //ACCESS:R DataWidth:0x20 Description: Removed for E3 B0 - Number of bytes transmitted on port 4.
#define PBF_REG_NUM_SENT_BYTES_P4_SIZE 1
#define PBF_REG_NUM_SENT_PKTS_P0 0x140150UL //ACCESS:R DataWidth:0x18 Description: Removed for E3 B0 - Number of packets transmitted on port 0.
#define PBF_REG_NUM_SENT_PKTS_P0_SIZE 1
#define PBF_REG_NUM_SENT_PKTS_P1 0x140154UL //ACCESS:R DataWidth:0x18 Description: Removed for E3 B0 - Number of packets transmitted on port 1.
#define PBF_REG_NUM_SENT_PKTS_P1_SIZE 1
#define PBF_REG_NUM_SENT_PKTS_P4 0x140158UL //ACCESS:R DataWidth:0x18 Description: Removed for E3 B0 - Number of packets transmitted on port 4.
#define PBF_REG_NUM_SENT_PKTS_P4_SIZE 1
#define PBF_REG_NUM_ERR_SENT_PKTS_P0 0x14015cUL //ACCESS:R DataWidth:0x8 Description: Removed for E3 B0 - Number of packets with error transmitted on port 0.
#define PBF_REG_NUM_ERR_SENT_PKTS_P0_SIZE 1
#define PBF_REG_NUM_ERR_SENT_PKTS_P1 0x140160UL //ACCESS:R DataWidth:0x8 Description: Removed for E3 B0 - Number of packets with error transmitted on port 1.
#define PBF_REG_NUM_ERR_SENT_PKTS_P1_SIZE 1
#define PBF_REG_NUM_ERR_SENT_PKTS_P4 0x140164UL //ACCESS:R DataWidth:0x8 Description: Removed for E3 B0 - Number of packets with error transmitted on port 4.
#define PBF_REG_NUM_ERR_SENT_PKTS_P4_SIZE 1
#define PBF_REG_CMDS_RCVD_ON_P0 0x140188UL //ACCESS:R DataWidth:0x18 Description: Removed for E3 B0 - Number of commands received on port 0 from STORM.
#define PBF_REG_CMDS_RCVD_ON_P0_SIZE 1
#define PBF_REG_CMDS_RCVD_ON_P1 0x14018cUL //ACCESS:R DataWidth:0x18 Description: Removed for E3 B0 - Number of commands received on port 1 from STORM.
#define PBF_REG_CMDS_RCVD_ON_P1_SIZE 1
#define PBF_REG_CMDS_RCVD_ON_P4 0x140190UL //ACCESS:R DataWidth:0x18 Description: Removed for E3 B0 - Number of commands received on port 4 from STORM.
#define PBF_REG_CMDS_RCVD_ON_P4_SIZE 1
#define PBF_REG_P0_CREDIT 0x140200UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Current credit for port 0 in the tx port buffers in 16 byte lines.
#define PBF_REG_P0_CREDIT_SIZE 1
#define PBF_REG_P0_TASK_CNT 0x140204UL //ACCESS:R DataWidth:0x8 Description: Removed for E3 B0 - Number of tasks in port 0 task queue.
#define PBF_REG_P0_TASK_CNT_SIZE 1
#define PBF_REG_P1_CREDIT 0x140208UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Current credit for port 1 in the tx port buffers in 16 byte lines.
#define PBF_REG_P1_CREDIT_SIZE 1
#define PBF_REG_P1_TASK_CNT 0x14020cUL //ACCESS:R DataWidth:0x8 Description: Removed for E3 B0 - Number of tasks in port 1 task queue.
#define PBF_REG_P1_TASK_CNT_SIZE 1
#define PBF_REG_P4_CREDIT 0x140210UL //ACCESS:R DataWidth:0xb Description: Removed for E3 B0 - Current credit for port 4 in the tx port buffers in 16 byte lines.
#define PBF_REG_P4_CREDIT_SIZE 1
#define PBF_REG_P4_TASK_CNT 0x140214UL //ACCESS:R DataWidth:0x8 Description: Removed for E3 B0 - Number of tasks in port 4 task queue.
#define PBF_REG_P4_TASK_CNT_SIZE 1
#define PBF_REG_P0_EVEN_TXP_MEM 0x140220UL //ACCESS:R DataWidth:0x41 Description: Removed for E3 B0 - Read & write access to even tx port memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_P0_EVEN_TXP_MEM_SIZE 3
#define PBF_REG_P0_ODD_TXP_MEM 0x140240UL //ACCESS:R DataWidth:0x41 Description: Removed for E3 B0 - Read & write access to odd tx port 0 memory; for test accessibility. Only when the PBf is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_P0_ODD_TXP_MEM_SIZE 3
#define PBF_REG_P1_EVEN_TXP_MEM 0x140260UL //ACCESS:R DataWidth:0x41 Description: Removed for E3 B0 - Read & write access to even tx port 1 memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_P1_EVEN_TXP_MEM_SIZE 3
#define PBF_REG_P1_ODD_TXP_MEM 0x140280UL //ACCESS:R DataWidth:0x41 Description: Removed for E3 B0 - Read & write access to odd tx port 1 memory; for test accessibility. Only when the PBF is idle. There are 800 addresses pointing to 65 bits.
#define PBF_REG_P1_ODD_TXP_MEM_SIZE 3
#define PBF_REG_P4_EVEN_TXP_MEM 0x1402a0UL //ACCESS:R DataWidth:0x41 Description: Removed for E3 B0 - Read & write access to even tx port 4 memory; for test accessibility. Only when the PBF is idle. There are 672 addresses pointing to 65 bits.
#define PBF_REG_P4_EVEN_TXP_MEM_SIZE 3
#define PBF_REG_P4_ODD_TXP_MEM 0x1402c0UL //ACCESS:R DataWidth:0x41 Description: Removed for E3 B0 - Read & write access to odd tx port 4 memory; for test accessibility. Only when the PBF is idle. There are 672 addresses pointing to 65 bits.
#define PBF_REG_P4_ODD_TXP_MEM_SIZE 3
#define PBF_REG_COS0_WFQ_CREDIT 0x1402e0UL //ACCESS:R DataWidth:0x20 Description: Removed for E3 B0 - current WFQ credit of COS0
#define PBF_REG_COS0_WFQ_CREDIT_SIZE 1
#define PBF_REG_COS1_WFQ_CREDIT 0x1402e4UL //ACCESS:R DataWidth:0x20 Description: Removed for E3 B0 - current WFQ credit of COS1
#define PBF_REG_COS1_WFQ_CREDIT_SIZE 1
#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0UL //ACCESS:R DataWidth:0x20 Description: Removed for E3 B0 - Cyclic counter for number of 8 byte lines freed from the task queue of port 0. Reset upon init.
#define PBF_REG_P0_TQ_LINES_FREED_CNT_SIZE 1
#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4UL //ACCESS:R DataWidth:0x20 Description: Removed for E3 B0 - Cyclic counter for number of 8 byte lines freed from the task queue of port 1. Reset upon init.
#define PBF_REG_P1_TQ_LINES_FREED_CNT_SIZE 1
#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8UL //ACCESS:R DataWidth:0x20 Description: Removed for E3 B0 - Cyclic counter for number of 8 byte lines freed from the task queue of port 4. Reset upon init.
#define PBF_REG_P4_TQ_LINES_FREED_CNT_SIZE 1
#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fcUL //ACCESS:R DataWidth:0xc Description: Number of 8 bytes lines occupied in the task queue of port 0.
#define PBF_REG_P0_TQ_OCCUPANCY_SIZE 1
#define PBF_REG_P1_TQ_OCCUPANCY 0x140300UL //ACCESS:R DataWidth:0xc Description: Number of 8 bytes lines occupied in the task queue of port 1.
#define PBF_REG_P1_TQ_OCCUPANCY_SIZE 1
#define PBF_REG_P4_TQ_OCCUPANCY 0x140304UL //ACCESS:R DataWidth:0xc Description: Number of 8 bytes lines occupied in the task queue of port 4.
#define PBF_REG_P4_TQ_OCCUPANCY_SIZE 1
#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for the amount credits in 16 bytes lines added for port 0. Reset upon init.
#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT_SIZE 1
#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030cUL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for the amount credits in 16 bytes lines added for port 1. Reset upon init.
#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT_SIZE 1
#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310UL //ACCESS:R DataWidth:0x20 Description: Cyclic counter for the amount credits in 16 bytes lines added for port 4. Reset upon init.
#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT_SIZE 1
#define PBF_REG_PBF_TX_MBIST1_CNTRL_CMD 0x15c008UL //ACCESS:R DataWidth:0x5 Description: Bit 0 - bist_override Bit 1 - mbist_en Bit 2 - mbist_async_reset Bits 4:3 - bist_setup[1:0]
#define PBF_REG_PBF_TX_MBIST1_CNTRL_CMD_SIZE 1
#define PBF_REG_TX_CLK_MBIST1_CNTRL_PBF_STATUS_0 0x15c00cUL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done Bit 1 - mbist_go Bits 31:2 - mbist_go0[29:0]
#define PBF_REG_TX_CLK_MBIST1_CNTRL_PBF_STATUS_0_SIZE 1
#define PBF_REG_TX_CLK_MBIST1_CNTRL_PBF_STATUS_1 0x15c010UL //ACCESS:R DataWidth:0x20 Description: Bits 2:0 - mbist_go0[32:30]; Bits 31:3 - mbist_go1[28:0]
#define PBF_REG_TX_CLK_MBIST1_CNTRL_PBF_STATUS_1_SIZE 1
#define PBF_REG_XSEM_PD_CLK_ST_MBIST1_CNTRL_PBF_STATUS_0 0x15c014UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done ; Bit 1 - mbist_go ; Bits 8:2 - mbist_go0[6:0] ; Bits 12:9 - mbist_go1[3:0] ; Bits [31:13] - reserved
#define PBF_REG_XSEM_PD_CLK_ST_MBIST1_CNTRL_PBF_STATUS_0_SIZE 1
#define PBF_REG_XSEM_PD_CLK_CAM_ST_MBIST1_CNTRL_PBF_STATUS_0 0x15c018UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done ; Bit 1 - mbist_go ; Bit 2 - mbist_go0 ; Bits 31:3 - reserved
#define PBF_REG_XSEM_PD_CLK_CAM_ST_MBIST1_CNTRL_PBF_STATUS_0_SIZE 1
#define PBF_REG_TX_CLK_MBIST1_CNTRL_PBF_STATUS_2 0x15c01cUL //ACCESS:R DataWidth:0x20 Description: Bits 1:0 - mbist_go1[30:29] ; Bits 31:2 - reserved
#define PBF_REG_TX_CLK_MBIST1_CNTRL_PBF_STATUS_2_SIZE 1
#define PBF_REG_NETWORK_PACKETS_WRR_WEIGHT 0x15c040UL //ACCESS:R DataWidth:0x3 Description: Removed for E3 B0 - WRR weight of commands destined to the network in the command arbiter
#define PBF_REG_NETWORK_PACKETS_WRR_WEIGHT_SIZE 1
#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indicates which COS is conncted to the highest priority in the command arbiter.
#define PBF_REG_HIGH_PRIORITY_COS_NUM_SIZE 1
#define PBF_REG_ETS_ENABLED 0x15c050UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indicates that ETS is performed between the COSes in the command arbiter. If reset strict priority w/ anti-starvation will be performed w/o WFQ.
#define PBF_REG_ETS_ENABLED_SIZE 1
#define PBF_REG_COS0_WEIGHT 0x15c054UL //ACCESS:R DataWidth:0x1f Description: Removed for E3 B0 - The weight of COS0 in the ETS command arbiter.
#define PBF_REG_COS0_WEIGHT_SIZE 1
#define PBF_REG_COS1_WEIGHT 0x15c058UL //ACCESS:R DataWidth:0x1f Description: Removed for E3 B0 - The weight of COS1 in the ETS command arbiter.
#define PBF_REG_COS1_WEIGHT_SIZE 1
#define PBF_REG_COS0_UPPER_BOUND 0x15c05cUL //ACCESS:R DataWidth:0x1f Description: Removed for E3 B0 -The upper bound of the weight of COS0 in the ETS command arbiter.
#define PBF_REG_COS0_UPPER_BOUND_SIZE 1
#define PBF_REG_COS1_UPPER_BOUND 0x15c060UL //ACCESS:R DataWidth:0x1f Description: Removed for E3 B0 -The upper bound of the weight of COS1 in the ETS command arbiter.
#define PBF_REG_COS1_UPPER_BOUND_SIZE 1
#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064UL //ACCESS:R DataWidth:0x10 Description: Removed for E3 B0 - The number of strict priority arbitration slots between 2 RR arbitration slots. A value of 0 means no strict priority cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR arbiter.
#define PBF_REG_NUM_STRICT_ARB_SLOTS_SIZE 1
#define PBF_REG_ETS_BURST_MODE 0x15c068UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - If set; in the command queue arbiter; the round robin arbiters pointer will stay on the winning input; instead of moving to the next one. This allows burstiness. This bit can be set only when ETS is enabled.
#define PBF_REG_ETS_BURST_MODE_SIZE 1
#define PBF_REG_LAST_CID_W_ERROR_P0 0x15c128UL //ACCESS:R DataWidth:0xa Description: last CID with either parsing or PCI error which was transmitted with error or dropped on port 0.
#define PBF_REG_LAST_CID_W_ERROR_P0_SIZE 1
#define PBF_REG_LAST_CID_W_ERROR_P1 0x15c12cUL //ACCESS:R DataWidth:0xa Description: last CID with either parsing or PCI error which was transmitted with error or dropped on port 1.
#define PBF_REG_LAST_CID_W_ERROR_P1_SIZE 1
#define PBF_REG_HDR_DUP_QWORDS_P0 0x15c158UL //ACCESS:R DataWidth:0x7 Description: Removed for E3 B0 - The number of QWORDS allocated in the header duplication memory for PBF port 0.
#define PBF_REG_HDR_DUP_QWORDS_P0_SIZE 1
#define PBF_REG_HDR_DUP_QWORDS_P1 0x15c15cUL //ACCESS:R DataWidth:0x7 Description: Removed for E3 B0 - The number of QWORDS allocated in the header duplication memory for PBF port 1.
#define PBF_REG_HDR_DUP_QWORDS_P1_SIZE 1
#define PBF_REG_PBF_UNUSED_EMPTY_0 0x1401e8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_0_SIZE 6
#define PBF_REG_PBF_UNUSED_EMPTY_1 0x140218UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_1_SIZE 2
#define PBF_REG_PBF_UNUSED_EMPTY_2 0x140230UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_2_SIZE 4
#define PBF_REG_PBF_UNUSED_EMPTY_3 0x140250UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_3_SIZE 4
#define PBF_REG_PBF_UNUSED_EMPTY_4 0x140270UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_4_SIZE 4
#define PBF_REG_PBF_UNUSED_EMPTY_5 0x140290UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_5_SIZE 4
#define PBF_REG_PBF_UNUSED_EMPTY_6 0x1402b0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_6_SIZE 4
#define PBF_REG_PBF_UNUSED_EMPTY_7 0x1402d0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_7_SIZE 4
#define PBF_REG_PBF_UNUSED_EMPTY_8 0x1403c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_8_SIZE 3
#define PBF_REG_PBF_UNUSED_EMPTY_9 0x1404e8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_9_SIZE 28358
#define PBF_REG_PBF_UNUSED_EMPTY_10 0x15c3b4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PBF_REG_PBF_UNUSED_EMPTY_10_SIZE 3859
#define PB_REG_CONTROL 0UL //ACCESS:RW DataWidth:0xc Multi Field Register
#define PB_CONTROL_REG_BYTE_ORDER_SWITCH (0x1<<0)
#define PB_CONTROL_REG_BYTE_ORDER_SWITCH_SIZE 0
#define PB_CONTROL_REG_DB_IGNORE_ERROR (0x1<<1)
#define PB_CONTROL_REG_DB_IGNORE_ERROR_SIZE 1
#define PB_CONTROL_REG_DONT_PASS_ERROR (0x1<<2)
#define PB_CONTROL_REG_DONT_PASS_ERROR_SIZE 2
#define PB_CONTROL_REG_EOP_CHECK_DISABLE (0x1<<3)
#define PB_CONTROL_REG_EOP_CHECK_DISABLE_SIZE 3
#define PB_CONTROL_REG_CRC_COMPARE_DISABLE (0x1<<4)
#define PB_CONTROL_REG_CRC_COMPARE_DISABLE_SIZE 4
#define PB_CONTROL_REG_EN_INPUTS (0x1<<5)
#define PB_CONTROL_REG_EN_INPUTS_SIZE 5
#define PB_CONTROL_REG_DISABLE_PB (0x1<<6)
#define PB_CONTROL_REG_DISABLE_PB_SIZE 6
#define PB_CONTROL_REG_DEBUG_SELECT (0xf<<7)
#define PB_CONTROL_REG_DEBUG_SELECT_SIZE 7
#define PB_CONTROL_REG_RELAX_TH (0x1<<11)
#define PB_CONTROL_REG_RELAX_TH_SIZE 11
#define PB_REG_THRESHOLDS 0x4UL //ACCESS:RW DataWidth:0xf Multi Field Register
#define PB_THRESHOLDS_REG_TQ_AF_THRESH (0x1ff<<0)
#define PB_THRESHOLDS_REG_TQ_AF_THRESH_SIZE 0
#define PB_THRESHOLDS_REG_DB_AF_THRESH (0x3f<<9)
#define PB_THRESHOLDS_REG_DB_AF_THRESH_SIZE 9
#define PB_REG_L1_TM 0x8UL //ACCESS:RW DataWidth:0x5 Description: TM bits of L1 memory; Not used in E65
#define PB_REG_TQ_TM 0xcUL //ACCESS:RW DataWidth:0x8 Description: TM bits of TQ memory (relevant for PPB only)
#define PB_REG_DBG_SELECT 0x10UL //ACCESS:RW DataWidth:0x8 Description: For dbgmux usage (debug data that goes from PB to the DBG block) - for selecting a line to output to the DBG block.
#define PB_REG_DBG_BYTE_ENABLE 0x14UL //ACCESS:RW DataWidth:0x8 Description: For dbgmux usage (debug data that goes from PB to the DBG block) - for enabling bytes in the selected line (after the select and before the shift)
#define PB_REG_DBG_SHIFT 0x18UL //ACCESS:RW DataWidth:0x3 Description: For dbgmux usage (debug data that goes from PB to the DBG block) - for circular right shifting of the selected line (after the enabling)
#define PB_REG_PB_INT_STS 0x1cUL //ACCESS:R DataWidth:0x2 Description: Interrupt register #0 read
#define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define PB_PB_INT_STS_REG_EOP_ERROR (0x1<<1)
#define PB_PB_INT_STS_REG_EOP_ERROR_SIZE 1
#define PB_REG_PB_INT_STS_CLR 0x20UL //ACCESS:RC DataWidth:0x2 Description: Interrupt register #0 read clear
#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define PB_PB_INT_STS_CLR_REG_EOP_ERROR (0x1<<1)
#define PB_PB_INT_STS_CLR_REG_EOP_ERROR_SIZE 1
#define PB_REG_PB_INT_STS_WR 0x24UL //ACCESS:WR DataWidth:0x2 Description: Interrupt register #0 bit set or clear
#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define PB_PB_INT_STS_WR_REG_EOP_ERROR (0x1<<1)
#define PB_PB_INT_STS_WR_REG_EOP_ERROR_SIZE 1
#define PB_REG_PB_INT_MASK 0x28UL //ACCESS:RW DataWidth:0x2 Description: Interrupt mask register #0 read/write
#define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define PB_PB_INT_MASK_REG_EOP_ERROR (0x1<<1)
#define PB_PB_INT_MASK_REG_EOP_ERROR_SIZE 1
#define PB_REG_PB_PRTY_STS 0x2cUL //ACCESS:R DataWidth:0x4 Description: Parity register #0 read
#define PB_PB_PRTY_STS_REG_PARITY (0x1<<0)
#define PB_PB_PRTY_STS_REG_PARITY_SIZE 0
#define PB_PB_PRTY_STS_REG_DB (0x1<<1)
#define PB_PB_PRTY_STS_REG_DB_SIZE 1
#define PB_PB_PRTY_STS_REG_TQ (0x1<<2)
#define PB_PB_PRTY_STS_REG_TQ_SIZE 2
#define PB_PB_PRTY_STS_REG_L1 (0x1<<3)
#define PB_PB_PRTY_STS_REG_L1_SIZE 3
#define PB_REG_PB_PRTY_STS_CLR 0x30UL //ACCESS:RC DataWidth:0x4 Description: Parity register #0 read clear
#define PB_PB_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define PB_PB_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define PB_PB_PRTY_STS_CLR_REG_DB (0x1<<1)
#define PB_PB_PRTY_STS_CLR_REG_DB_SIZE 1
#define PB_PB_PRTY_STS_CLR_REG_TQ (0x1<<2)
#define PB_PB_PRTY_STS_CLR_REG_TQ_SIZE 2
#define PB_PB_PRTY_STS_CLR_REG_L1 (0x1<<3)
#define PB_PB_PRTY_STS_CLR_REG_L1_SIZE 3
#define PB_REG_PB_PRTY_STS_WR 0x34UL //ACCESS:WR DataWidth:0x4 Description: Parity register #0 bit set or clear
#define PB_PB_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define PB_PB_PRTY_STS_WR_REG_PARITY_SIZE 0
#define PB_PB_PRTY_STS_WR_REG_DB (0x1<<1)
#define PB_PB_PRTY_STS_WR_REG_DB_SIZE 1
#define PB_PB_PRTY_STS_WR_REG_TQ (0x1<<2)
#define PB_PB_PRTY_STS_WR_REG_TQ_SIZE 2
#define PB_PB_PRTY_STS_WR_REG_L1 (0x1<<3)
#define PB_PB_PRTY_STS_WR_REG_L1_SIZE 3
#define PB_REG_PB_PRTY_MASK 0x38UL //ACCESS:RW DataWidth:0x4 Description: Parity mask register #0 read/write
#define PB_PB_PRTY_MASK_REG_PARITY (0x1<<0)
#define PB_PB_PRTY_MASK_REG_PARITY_SIZE 0
#define PB_PB_PRTY_MASK_REG_DB (0x1<<1)
#define PB_PB_PRTY_MASK_REG_DB_SIZE 1
#define PB_PB_PRTY_MASK_REG_TQ (0x1<<2)
#define PB_PB_PRTY_MASK_REG_TQ_SIZE 2
#define PB_PB_PRTY_MASK_REG_L1 (0x1<<3)
#define PB_PB_PRTY_MASK_REG_L1_SIZE 3
#define PB_REG_ECO_RESERVED 0x3cUL //ACCESS:RW DataWidth:0x8 Description: for future eco
#define PB_REG_DB_TM 0x40UL //ACCESS:RW DataWidth:0x2 Description: TM bits of DB memory (relevant for PPB only)
#define PB_REG_L1 0x800UL //ACCESS:WB DataWidth:0x40 Description: L1 CRC memory access
#define PB_REG_L1_SIZE 512
#define PB_REG_PB_UNUSED_EMPTY_0 0x44UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PB_REG_PB_UNUSED_EMPTY_0_SIZE 495
#define PGLUE_B_REG_CFG_SPACE_A_ADDRESS 0x9000UL //ACCESS:RW DataWidth:0x6 Description: Address[12:7] in PCI configuration space of the first register on which config space A attention is generated. Note that this register is in 128-byte units.
#define PGLUE_B_REG_CFG_SPACE_A_ENABLE 0x9004UL //ACCESS:RW DataWidth:0x20 Description: Indicates which of the 32 registers starting in address cfg_space_a_address generates an attention. If bit N is set - a CSSNOOP cycle with address {cfg_space_a_address; 7b0}+4*N will generate a config space A attention.
#define PGLUE_B_REG_CFG_SPACE_B_ADDRESS 0x9008UL //ACCESS:RW DataWidth:0x6 Description: Address[12:7] in PCI configuration space of the first register on which config space B attention is generated. Note that this register is in 128-byte units.
#define PGLUE_B_REG_CFG_SPACE_B_ENABLE 0x900cUL //ACCESS:RW DataWidth:0x20 Description: Indicates which of the 32 registers starting in address cfg_space_b_address generates an attention. If bit N is set - a CSSNOOP cycle with address {cfg_space_b_address; 7b0}+4*N will generate a config space B attention.
#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010UL //ACCESS:R DataWidth:0x8 Description: Config space A attention dirty bits. Each bit indicates that the corresponding PF generates config space A attention. Set by PXP. Reset by MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits from both paths.
#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014UL //ACCESS:R DataWidth:0x8 Description: Config space B attention dirty bits. Each bit indicates that the corresponding PF generates config space B attention. Set by PXP. Reset by MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits from both paths.
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018UL //ACCESS:R DataWidth:0x20 Description: FLR request attention dirty bits for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901cUL //ACCESS:R DataWidth:0x20 Description: FLR request attention dirty bits for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020UL //ACCESS:R DataWidth:0x20 Description: FLR request attention dirty bits for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024UL //ACCESS:R DataWidth:0x20 Description: FLR request attention dirty bits for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr.
#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028UL //ACCESS:R DataWidth:0x8 Description: FLR request attention dirty bits for PFs 0 to 7. Each bit indicates that the FLR register of the corresponding PF was set. Set by PXP. Reset by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits from both paths.
#define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED 0x902cUL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define PGLUE_B_DISABLE_FLR_SRIOV_DISABLED_REG_DISABLE_FLR_REQUEST (0x1<<0)
#define PGLUE_B_DISABLE_FLR_SRIOV_DISABLED_REG_DISABLE_FLR_REQUEST_SIZE 0
#define PGLUE_B_DISABLE_FLR_SRIOV_DISABLED_REG_DISABLE_SRIOV_DISABLED_REQUEST (0x1<<1)
#define PGLUE_B_DISABLE_FLR_SRIOV_DISABLED_REG_DISABLE_SRIOV_DISABLED_REQUEST_SIZE 1
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030UL //ACCESS:R DataWidth:0x8 Description: SR IOV disabled attention dirty bits. Each bit indicates that the VF enable register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writing 1 to sr_iov_disabled_request_clr. Note: register contains bits from both paths.
#define PGLUE_B_REG_SHADOW_BME_VF_31_0 0x9034UL //ACCESS:R DataWidth:0x20 Description: Shadow BME register for VFs 0 to 31. Each bit indicates if the corresponding VF is enabled.
#define PGLUE_B_REG_SHADOW_BME_VF_63_32 0x9038UL //ACCESS:R DataWidth:0x20 Description: Shadow BME register for VFs 32 to 63. Each bit indicates if the corresponding VF is enabled.
#define PGLUE_B_REG_SHADOW_BME_VF_95_64 0x903cUL //ACCESS:R DataWidth:0x20 Description: Shadow BME register for VFs 64 to 95. Each bit indicates if the corresponding VF is enabled.
#define PGLUE_B_REG_SHADOW_BME_VF_127_96 0x9040UL //ACCESS:R DataWidth:0x20 Description: Shadow BME register for VFs 96 to 127. Each bit indicates if the corresponding VF is enabled.
#define PGLUE_B_REG_SHADOW_BME_PF_7_0 0x9044UL //ACCESS:R DataWidth:0x8 Description: Shadow BME register for PFs 0 to 7. Each bit indicates if the corresponding PF is enabled. Note: register contains bits from both paths.
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_31_0 0x9048UL //ACCESS:R DataWidth:0x20 Description: Shadow ats_enable register for VFs 0 to 31. Each bit indicates if ATS for the corresponding VF is enabled.
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_63_32 0x904cUL //ACCESS:R DataWidth:0x20 Description: Shadow ats_enable register for VFs 32 to 63. Each bit indicates if ATS for the corresponding VF is enabled.
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_95_64 0x9050UL //ACCESS:R DataWidth:0x20 Description: Shadow ats_enable register for VFs 64 to 95. Each bit indicates if ATS for the corresponding VF is enabled.
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_127_96 0x9054UL //ACCESS:R DataWidth:0x20 Description: Shadow ats_enable register for VFs 96 to 127. Each bit indicates if ATS for the corresponding VF is enabled.
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_PF_7_0 0x9058UL //ACCESS:R DataWidth:0x8 Description: Shadow ats_enable register for PFs 0 to 7. Each bit indicates if ATS for the corresponding PF is enabled. Note: register contains bits from both paths.
#define PGLUE_B_REG_SHADOW_VF_ENABLE_PF_7_0 0x905cUL //ACCESS:R DataWidth:0x8 Description: Shadow vf_enable register for PFs 0 to 7. Each bit indicates if SR-IOV for the corresponding PF is enabled. Note: register contains bits from both paths.
#define PGLUE_B_REG_SHADOW_IDO_BITS 0x9060UL //ACCESS:R DataWidth:0x10 Description: Shadow ido bits register for PFs 0 to 7. [7:0] : Each bit indicates if IDO_REQ_ENABLE bit for the corresponding PF is set. [15:8] : Each bit indicates if IDO_CPL_ENABLE bit for the corresponding PF is set. Note: register contains bits from both paths.
#define PGLUE_B_REG_DISABLE_ATS_EN_CLEARING 0x9064UL //ACCESS:RW DataWidth:0x1 Description: Debug only: PGLUE automatically clears ATC enable for a function if a TCPL arrived for that function with Unsupported Request error. Setting this register to 1 disables this automatic clearing.
#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068UL //ACCESS:R DataWidth:0x8 Description: Each bit indicates an incorrect behavior in user RX interface. Bit 0 - Target memory read arrived with a correctable error. Bit 1 - Target memory read arrived with an uncorrectable error. Bit 2 - Configuration RW arrived with a correctable error. Bit 3 - Configuration RW arrived with an uncorrectable error. Bit 4 - Completion with Configuration Request Retry Status. Bit 5 - Expansion ROM access received with a write request. Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010; and pcie_rx_last not asserted.
#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906cUL //ACCESS:R DataWidth:0x20 Description: Was_error indication dirty bits for VFs 0 to 31. Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_31_0_clr.
#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070UL //ACCESS:R DataWidth:0x20 Description: Was_error indication dirty bits for VFs 32 to 63. Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_63_32_clr.
#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074UL //ACCESS:R DataWidth:0x20 Description: Was_error indication dirty bits for VFs 64 to 95. Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_95_64_clr.
#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078UL //ACCESS:R DataWidth:0x20 Description: Was_error indication dirty bits for VFs 96 to 127. Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_127_96_clr.
#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907cUL //ACCESS:R DataWidth:0x8 Description: Was_error indication dirty bits for PFs 0 to 7. Each bit indicates that there was a completion with uncorrectable error for the corresponding PF. Set by PXP. Reset by MCP writing 1 to was_error_pf_7_0_clr.
#define PGLUE_B_REG_RX_ERR_DETAILS 0x9080UL //ACCESS:R DataWidth:0xd Description: Details of first request received with error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - completer abort. 3 - Illegal value for this field. [12] valid - indicates if there was a completion error since the last time this register was cleared.
#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084UL //ACCESS:R DataWidth:0x12 Description: Details of first ATS Translation Completion request received with error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - completer abort. 3 - Illegal value for this field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a completion error since the last time this register was cleared.
#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088UL //ACCESS:R DataWidth:0x20 Description: Address [31:0] of first write request not submitted due to error
#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908cUL //ACCESS:R DataWidth:0x20 Description: Address [63:32] of first write request not submitted due to error
#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090UL //ACCESS:R DataWidth:0x1f Description: Details of first write request not submitted due to error. [4:0] VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] - VFID.
#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094UL //ACCESS:R DataWidth:0x1a Description: Details of first write request not submitted due to error. [15:0] Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - indicates if there was a request not submitted due to error since the last time this register was cleared.
#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098UL //ACCESS:R DataWidth:0x20 Description: Address [31:0] of first read request not submitted due to error
#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909cUL //ACCESS:R DataWidth:0x20 Description: Address [63:32] of first read request not submitted due to error
#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0UL //ACCESS:R DataWidth:0x1f Description: Details of first read request not submitted due to error. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] - VFID.
#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4UL //ACCESS:R DataWidth:0x1a Description: Details of first read request not submitted due to error. [15:0] Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - indicates if there was a request not submitted due to error since the last time this register was cleared.
#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL 0x90a8UL //ACCESS:R DataWidth:0x15 Description: Details of first Invalidation Completion message submitted during a TX error condition. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [14:10] - ITAG Index. [19:16] - Error type - [16] - Indicates was_error was set; [17] - Indicates BME was cleared; [18] - Indicates FID_enable was cleared; [19] - Indicates VF with parent PF FLR_request or IOV_disable_request dirty bit is set. [20] valid - indicates if there was an Invalidation Completion message submitted during a TX error condition since the last time this register was cleared.
#define PGLUE_B_REG_TX_ERR_E15_MODE 0x90acUL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define PGLUE_B_TX_ERR_E15_MODE_REG_TX_ERR_E15_MODE_PF (0x1<<0)
#define PGLUE_B_TX_ERR_E15_MODE_REG_TX_ERR_E15_MODE_PF_SIZE 0
#define PGLUE_B_TX_ERR_E15_MODE_REG_TX_ERR_E15_MODE_VF (0x1<<1)
#define PGLUE_B_TX_ERR_E15_MODE_REG_TX_ERR_E15_MODE_VF_SIZE 1
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_31_0_VALUE 0x90b0UL //ACCESS:R DataWidth:0x20 Description: A global view of internal_vfid_enable register for VFs 0 to 31.
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_63_32_VALUE 0x90b4UL //ACCESS:R DataWidth:0x20 Description: A global view of internal_vfid_enable register for VFs 32 to 63.
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_95_64_VALUE 0x90b8UL //ACCESS:R DataWidth:0x20 Description: A global view of internal_vfid_enable register for VFs 64 to 95.
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_127_96_VALUE 0x90bcUL //ACCESS:R DataWidth:0x20 Description: A global view of internal_vfid_enable register for VFs 96 to 127.
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_VALUE 0x90c0UL //ACCESS:R DataWidth:0x18 Description: A global view of internal_pfid_enable registers. Bits [7:0] - internal_pfid_enable_master; Bits [15:8] = internal_pfid_enable_target_write; Bits [23:16] = internal_pfid_enable_target_read
#define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4UL //ACCESS:RW DataWidth:0x10 Description: Start offset of TSDM zone A (queue zone) in the internal RAM
#define PGLUE_B_REG_TSDM_OFFSET_MASK_A 0x90c8UL //ACCESS:RW DataWidth:0x5 Description: Offset mask of TSDM zone A (queue zone) in the internal RAM
#define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90ccUL //ACCESS:RW DataWidth:0x10 Description: Start offset of TSDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_TSDM_OFFSET_MASK_B 0x90d0UL //ACCESS:RW DataWidth:0x9 Description: Offset mask of TSDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4UL //ACCESS:RW DataWidth:0x5 Description: VF Shift of TSDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8UL //ACCESS:RW DataWidth:0x10 Description: Start offset of USDM zone A (queue zone) in the internal RAM
#define PGLUE_B_REG_USDM_OFFSET_MASK_A 0x90dcUL //ACCESS:RW DataWidth:0x5 Description: Offset mask of USDM zone A (queue zone) in the internal RAM
#define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0UL //ACCESS:RW DataWidth:0x10 Description: Start offset of USDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_USDM_OFFSET_MASK_B 0x90e4UL //ACCESS:RW DataWidth:0x9 Description: Offset mask of USDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8UL //ACCESS:RW DataWidth:0x5 Description: VF Shift of USDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ecUL //ACCESS:RW DataWidth:0x10 Description: Start offset of XSDM zone A (queue zone) in the internal RAM
#define PGLUE_B_REG_XSDM_OFFSET_MASK_A 0x90f0UL //ACCESS:RW DataWidth:0x5 Description: Offset mask of XSDM zone A (queue zone) in the internal RAM
#define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4UL //ACCESS:RW DataWidth:0x10 Description: Start offset of XSDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_XSDM_OFFSET_MASK_B 0x90f8UL //ACCESS:RW DataWidth:0x9 Description: Offset mask of XSDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fcUL //ACCESS:RW DataWidth:0x5 Description: VF Shift of XSDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100UL //ACCESS:RW DataWidth:0x10 Description: Start offset of CSDM zone A (queue zone) in the internal RAM
#define PGLUE_B_REG_CSDM_OFFSET_MASK_A 0x9104UL //ACCESS:RW DataWidth:0x5 Description: Offset mask of CSDM zone A (queue zone) in the internal RAM
#define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108UL //ACCESS:RW DataWidth:0x10 Description: Start offset of CSDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_CSDM_OFFSET_MASK_B 0x910cUL //ACCESS:RW DataWidth:0x9 Description: Offset mask of CSDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110UL //ACCESS:RW DataWidth:0x5 Description: VF Shift of CSDM zone B (legacy zone) in the internal RAM
#define PGLUE_B_REG_TSDM_INB_INT_A_0 0x9114UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for TSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_TSDM_INB_INT_A_1 0x9118UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for TSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_TSDM_INB_INT_A_2 0x911cUL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for TSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_TSDM_INB_INT_A_3 0x9120UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for TSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_TSDM_INB_INT_B_VF 0x9124UL //ACCESS:RW DataWidth:0x12 Description: Type B VF inbound interrupt table for TSDM: bits[17:9]-mask;bits[8:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_USDM_INB_INT_A_1 0x912cUL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_USDM_INB_INT_A_5 0x913cUL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_USDM_INB_INT_B_VF 0x9144UL //ACCESS:RW DataWidth:0x12 Description: Type B VF inbound interrupt table for USDM: bits[17:9]-mask;bits[8:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PGLUE_B_REG_XSDM_INB_INT_A_0 0x9148UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for XSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_XSDM_INB_INT_A_1 0x914cUL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for XSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_XSDM_INB_INT_A_2 0x9150UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for XSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_XSDM_INB_INT_A_3 0x9154UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for XSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_XSDM_INB_INT_B_VF 0x9158UL //ACCESS:RW DataWidth:0x12 Description: Type B VF inbound interrupt table for XSDM: bits[17:9]-mask;bits[8:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PGLUE_B_REG_CSDM_INB_INT_A_0 0x915cUL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for CSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_CSDM_INB_INT_A_1 0x9160UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for CSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_CSDM_INB_INT_A_2 0x9164UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for CSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_CSDM_INB_INT_A_3 0x9168UL //ACCESS:RW DataWidth:0xa Description: Type A PF/VF inbound interrupt table for CSDM: bits[9:5]-mask;bits[4:0]-address relative to start_offset_a. Bits [1:0] can have any value (Byte resolution address).
#define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916cUL //ACCESS:RW DataWidth:0x12 Description: Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;bits[8:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170UL //ACCESS:RW DataWidth:0x1 Description: Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_TSDM_INB_INT_A_VF_ENABLE 0x9174UL //ACCESS:RW DataWidth:0x1 Description: Type A VF enable inbound interrupt table for TSDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_TSDM_INB_INT_B_VF_ENABLE 0x9178UL //ACCESS:RW DataWidth:0x1 Description: Type B VF enable inbound interrupt table for TSDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917cUL //ACCESS:RW DataWidth:0x1 Description: Type A PF enable inbound interrupt table for USDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180UL //ACCESS:RW DataWidth:0x1 Description: Type A VF enable inbound interrupt table for USDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184UL //ACCESS:RW DataWidth:0x1 Description: Type B VF enable inbound interrupt table for USDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188UL //ACCESS:RW DataWidth:0x1 Description: Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_XSDM_INB_INT_A_VF_ENABLE 0x918cUL //ACCESS:RW DataWidth:0x1 Description: Type A VF enable inbound interrupt table for XSDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_XSDM_INB_INT_B_VF_ENABLE 0x9190UL //ACCESS:RW DataWidth:0x1 Description: Type B VF enable inbound interrupt table for XSDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194UL //ACCESS:RW DataWidth:0x1 Description: Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_CSDM_INB_INT_A_VF_ENABLE 0x9198UL //ACCESS:RW DataWidth:0x1 Description: Type A VF enable inbound interrupt table for CSDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919cUL //ACCESS:RW DataWidth:0x1 Description: Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1 - enable.
#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0UL //ACCESS:RW DataWidth:0x1 Description: 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B.
#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4UL //ACCESS:RW DataWidth:0x1 Description: 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B.
#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8UL //ACCESS:RW DataWidth:0x1 Description: 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B.
#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91acUL //ACCESS:RW DataWidth:0x1 Description: 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_0 0x91b0UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_0 0x91b4UL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_1 0x91b8UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_1 0x91bcUL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_2 0x91c0UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_2 0x91c4UL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_3 0x91c8UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_3 0x91ccUL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_4 0x91d0UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_4 0x91d4UL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_5 0x91d8UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_5 0x91dcUL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_6 0x91e0UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_6 0x91e4UL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_7 0x91e8UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_7 0x91ecUL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_8 0x91f0UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_8 0x91f4UL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_9 0x91f8UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_9 0x91fcUL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_10 0x9200UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_10 0x9204UL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_11 0x9208UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_11 0x920cUL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_12 0x9210UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_12 0x9214UL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_13 0x9218UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_13 0x921cUL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_14 0x9220UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_14 0x9224UL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_15 0x9228UL //ACCESS:RW DataWidth:0x17 Description: Part1 of VF GRC access register. Bits [22:20] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 means that only the GRC base can be accessed. Bits [19:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_15 0x922cUL //ACCESS:RW DataWidth:0x14 Description: Part2 of VF GRC access register. Bits [19:16] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [15] - Absolute func index. 0 - Path-relative func index should be used - a number between 0 and 63. 1 - Absolute func index should be used - a number between 0 and 127. Bits [14] - Add func index. 1 - Function index should be added to the GRC address.Bits [13] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [12:4] - Allowed func ID. [12:10] - PFID. [9:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within port. 3 - All VFs within PF. 4 - Specific VF.
#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230UL //ACCESS:R DataWidth:0x1f Description: Details of first target VF request with length violation (too many DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30] valid - indicates if there was a request with length violation since the last time this register was cleared. Length violations: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW.
#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234UL //ACCESS:R DataWidth:0x1a Description: Details of first target VF request accessing VF GRC space that failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a request accessing VF GRC space that failed permission check since the last time this register was cleared. Permission checks are: function permission; R/W permission; address range permission.
#define PGLUE_B_REG_IDO_ENABLE_MASTER_RW 0x9238UL //ACCESS:RW DataWidth:0x20 Description: Each bit when set indicates that IDO bit towards PGLUE should be set for this VQ
#define PGLUE_B_REG_IDO_ENABLE_MASTER_RW2 0x923cUL //ACCESS:RW DataWidth:0x1 Description: bit 0 - when set indicates that IDO bit towards PGLUE should be set for Translation Requests
#define PGLUE_B_REG_IDO_ENABLE_TARGET_CPL 0x9240UL //ACCESS:RW DataWidth:0x1 Description: bit 0 - when set indicates that IDO bit towards PGLUE should be set for Target Completions
#define PGLUE_B_REG_TAGS_63_32 0x9244UL //ACCESS:R DataWidth:0x20 Description: Indicates the status of tags 32-63. 0 - tags is used - read completion did not return yet. 1 - tag is unused. Same functionality as pxp2_registers_pgl_exp_rom_data2 for tags 0-31.
#define PGLUE_B_REG_IGU_BYPASS_ON_ERR 0x9248UL //ACCESS:RW DataWidth:0x1 Description: 1 - Do not discard IGU master transactions for PF when the corresponding was_error bit is set.
#define PGLUE_B_REG_ALLOW_MSIX_ACCESS_IN_BAR0 0x9250UL //ACCESS:RW DataWidth:0x1 Description: 0 - Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value is configured; BAR2 size for PFs and VFs should be configured to 8KB to allow ONLY MSIX table and PBA access. 1 - All IGU space in BAR 0 is accessible; including the first 8KB. When this value is configured; BAR2 size for PFs can be configured to 64KB and for VFs to 16KB to allow all IGU space to be accessed in BAR2 as well.
#define PGLUE_B_REG_DISABLE_HIGHER_BW 0x9254UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define PGLUE_B_DISABLE_HIGHER_BW_REG_DISABLE_HIGHER_BW_WAW (0x1<<0)
#define PGLUE_B_DISABLE_HIGHER_BW_REG_DISABLE_HIGHER_BW_WAW_SIZE 0
#define PGLUE_B_DISABLE_HIGHER_BW_REG_DISABLE_TWO_PENDING_REQUESTS (0x1<<1)
#define PGLUE_B_DISABLE_HIGHER_BW_REG_DISABLE_TWO_PENDING_REQUESTS_SIZE 1
#define PGLUE_B_DISABLE_HIGHER_BW_REG_DISABLE_TWO_PENDING_WR_REQUESTS (0x1<<2)
#define PGLUE_B_DISABLE_HIGHER_BW_REG_DISABLE_TWO_PENDING_WR_REQUESTS_SIZE 2
#define PGLUE_B_REG_DISABLE_RAM1_BAR_ACCESS 0x9258UL //ACCESS:RW DataWidth:0x1 Description: 0 - RAM1 PF BAR accesses are enabled. 1 - RAM1 PF BAR accesses are disabled.
#define PGLUE_B_REG_TCPL_IN_TWO_RCBS_DETAILS 0x925cUL //ACCESS:R DataWidth:0x10 Description: Details of first ATS Translation Completion received in two rcbs (packets). Logging is triggered by a Translation Completion with length different than 2 DWs. Such a case is unsupported and the Translation completion is considered erroneous. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [14:10] - OTB EntryID. [15] valid - indicates if there was a Translation Completion received in two rcbs since the last time this register was cleared.
#define PGLUE_B_REG_PCIE_ERR_STATUS 0x9260UL //ACCESS:R DataWidth:0x4 Description: Details of PCIe core error status. Valid when pgl_pcie_attn in pxp2 is set. 0 - Unsupported Request or Completer Abort on User RX Interface. 1 - Reception of a poisoned TLP on RX Lanes. 2 - Completion timeout. 3 - Unexpected Completion on RX Lanes. 4 - Detected Unsupported Request on RX Lanes. 5 - ECRC error on RX Lanes. 6 - Reserved. 7 - Reserved. 8 - Illegal operation size on User TX Interface. 9 - Detected Unsupported Request on User TX Interface (Bridge Forwarding Error). 10 - Unsupported header type on User TX Interface. 11 - Reserved. 12 - NP TAG value on User TX Interface already in use. 13 - Completion RTAG value on User TX Interface unexpected. 14 - User TX Interface Overflow Error (Too many req wo/ack). 15 - reserved.
#define PGLUE_B_REG_CSSNOOP_ALMOST_FULL_THR 0x9264UL //ACCESS:RW DataWidth:0x2 Description: Debug only: If more than this Number of entries are occupied in the cssnoop clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
#define PGLUE_B_REG_PGL_TM0 0x9268UL //ACCESS:RW DataWidth:0x8 Multi Field Register
#define PGLUE_B_PGL_TM0_REG_PGL_CPL1_TM (0x3<<0)
#define PGLUE_B_PGL_TM0_REG_PGL_CPL1_TM_SIZE 0
#define PGLUE_B_PGL_TM0_REG_PGL_CPL2_TM (0x3<<2)
#define PGLUE_B_PGL_TM0_REG_PGL_CPL2_TM_SIZE 2
#define PGLUE_B_PGL_TM0_REG_PGL_TAG_DB_TM (0x3<<4)
#define PGLUE_B_PGL_TM0_REG_PGL_TAG_DB_TM_SIZE 4
#define PGLUE_B_PGL_TM0_REG_PGL_PCIE_REPLAY_ADDR_TM (0x3<<6)
#define PGLUE_B_PGL_TM0_REG_PGL_PCIE_REPLAY_ADDR_TM_SIZE 6
#define PGLUE_B_REG_PGL_ECO_RESERVED 0x926cUL //ACCESS:RW DataWidth:0x20 Description: debug only: Reserved bits for ECO. Bit 0: Used as chicken bit for CQ43407 fix. Bit 1: Used as chicken bit for CQ43411 fix.
#define PGLUE_B_REG_PGL_ECO_RESERVED2 0x9270UL //ACCESS:RW DataWidth:0x20 Description: debug only: Reserved bits for ECO
#define PGLUE_B_REG_DBGSYN_ALMOST_FULL_THR 0x9274UL //ACCESS:RW DataWidth:0x4 Description: Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
#define PGLUE_B_REG_DBGBUS_PATH_SELECT 0x9278UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define PGLUE_B_DBGBUS_PATH_SELECT_REG_DBGBUS_PATH_SELECT_E0 (0x1<<0)
#define PGLUE_B_DBGBUS_PATH_SELECT_REG_DBGBUS_PATH_SELECT_E0_SIZE 0
#define PGLUE_B_DBGBUS_PATH_SELECT_REG_DBGBUS_PATH_SELECT_E1 (0x1<<1)
#define PGLUE_B_DBGBUS_PATH_SELECT_REG_DBGBUS_PATH_SELECT_E1_SIZE 1
#define PGLUE_B_REG_DBG_SELECT 0x927cUL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PGLUE to the DBG block) - for selecting a line to output to the DBG block.
#define PGLUE_B_REG_DBG_BYTE_ENABLE 0x9280UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PGLUE to the DBG block) - for enabling bytes in the selected line (after the select and before the shift)
#define PGLUE_B_REG_DBG_SHIFT 0x9284UL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from PGLUE to the DBG block) - for circular right shifting of the selected line (after the enabling)
#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD 0x9288UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD 0x928cUL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_0_STATUS_0 0x9290UL //ACCESS:R DataWidth:0xb Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits;
#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_1_STATUS_0 0x9294UL //ACCESS:R DataWidth:0xb Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits;
#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298UL //ACCESS:R DataWidth:0xb Description: Interrupt register #0 read
#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR_SIZE 1
#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN_SIZE 2
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN_SIZE 3
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN_SIZE 4
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN_SIZE 5
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN_SIZE 6
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN_SIZE 7
#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW_SIZE 8
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<9)
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_TRANSLATION_SIZE_DIFFERENT_SIZE 9
#define PGLUE_B_PGLUE_B_INT_STS_REG_PCIE_RX_L0S_TIMEOUT (0x1<<10)
#define PGLUE_B_PGLUE_B_INT_STS_REG_PCIE_RX_L0S_TIMEOUT_SIZE 10
#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929cUL //ACCESS:RC DataWidth:0xb Description: Interrupt register #0 read clear
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_INCORRECT_RCV_BEHAVIOR_SIZE 1
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_WAS_ERROR_ATTN (0x1<<2)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_WAS_ERROR_ATTN_SIZE 2
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_VF_LENGTH_VIOLATION_ATTN_SIZE 3
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_VF_GRC_SPACE_VIOLATION_ATTN_SIZE 4
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_VF_MSIX_BAR_VIOLATION_ATTN_SIZE 5
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_TCPL_ERROR_ATTN (0x1<<6)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_TCPL_ERROR_ATTN_SIZE 6
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_TCPL_IN_TWO_RCBS_ATTN_SIZE 7
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_CSSNOOP_FIFO_OVERFLOW_SIZE 8
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<9)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_TCPL_TRANSLATION_SIZE_DIFFERENT_SIZE 9
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_PCIE_RX_L0S_TIMEOUT (0x1<<10)
#define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_PCIE_RX_L0S_TIMEOUT_SIZE 10
#define PGLUE_B_REG_PGLUE_B_INT_STS_WR 0x92a0UL //ACCESS:WR DataWidth:0xb Description: Interrupt register #0 bit set or clear
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_INCORRECT_RCV_BEHAVIOR_SIZE 1
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_WAS_ERROR_ATTN (0x1<<2)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_WAS_ERROR_ATTN_SIZE 2
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_VF_LENGTH_VIOLATION_ATTN_SIZE 3
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_VF_GRC_SPACE_VIOLATION_ATTN_SIZE 4
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_VF_MSIX_BAR_VIOLATION_ATTN_SIZE 5
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_TCPL_ERROR_ATTN (0x1<<6)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_TCPL_ERROR_ATTN_SIZE 6
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_TCPL_IN_TWO_RCBS_ATTN_SIZE 7
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_CSSNOOP_FIFO_OVERFLOW_SIZE 8
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<9)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_TCPL_TRANSLATION_SIZE_DIFFERENT_SIZE 9
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_PCIE_RX_L0S_TIMEOUT (0x1<<10)
#define PGLUE_B_PGLUE_B_INT_STS_WR_REG_PCIE_RX_L0S_TIMEOUT_SIZE 10
#define PGLUE_B_REG_PGLUE_B_INT_MASK 0x92a4UL //ACCESS:RW DataWidth:0xb Description: Interrupt mask register #0 read/write
#define PGLUE_B_PGLUE_B_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define PGLUE_B_PGLUE_B_INT_MASK_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_INCORRECT_RCV_BEHAVIOR_SIZE 1
#define PGLUE_B_PGLUE_B_INT_MASK_REG_WAS_ERROR_ATTN (0x1<<2)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_WAS_ERROR_ATTN_SIZE 2
#define PGLUE_B_PGLUE_B_INT_MASK_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_VF_LENGTH_VIOLATION_ATTN_SIZE 3
#define PGLUE_B_PGLUE_B_INT_MASK_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_VF_GRC_SPACE_VIOLATION_ATTN_SIZE 4
#define PGLUE_B_PGLUE_B_INT_MASK_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_VF_MSIX_BAR_VIOLATION_ATTN_SIZE 5
#define PGLUE_B_PGLUE_B_INT_MASK_REG_TCPL_ERROR_ATTN (0x1<<6)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_TCPL_ERROR_ATTN_SIZE 6
#define PGLUE_B_PGLUE_B_INT_MASK_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_TCPL_IN_TWO_RCBS_ATTN_SIZE 7
#define PGLUE_B_PGLUE_B_INT_MASK_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_CSSNOOP_FIFO_OVERFLOW_SIZE 8
#define PGLUE_B_PGLUE_B_INT_MASK_REG_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<9)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_TCPL_TRANSLATION_SIZE_DIFFERENT_SIZE 9
#define PGLUE_B_PGLUE_B_INT_MASK_REG_PCIE_RX_L0S_TIMEOUT (0x1<<10)
#define PGLUE_B_PGLUE_B_INT_MASK_REG_PCIE_RX_L0S_TIMEOUT_SIZE 10
#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8UL //ACCESS:R DataWidth:0x2 Description: Parity register #0 read
#define PGLUE_B_PGLUE_B_PRTY_STS_REG_PARITY (0x1<<0)
#define PGLUE_B_PGLUE_B_PRTY_STS_REG_PARITY_SIZE 0
#define PGLUE_B_PGLUE_B_PRTY_STS_REG_TAG_DB (0x1<<1)
#define PGLUE_B_PGLUE_B_PRTY_STS_REG_TAG_DB_SIZE 1
#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92acUL //ACCESS:RC DataWidth:0x2 Description: Parity register #0 read clear
#define PGLUE_B_PGLUE_B_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define PGLUE_B_PGLUE_B_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define PGLUE_B_PGLUE_B_PRTY_STS_CLR_REG_TAG_DB (0x1<<1)
#define PGLUE_B_PGLUE_B_PRTY_STS_CLR_REG_TAG_DB_SIZE 1
#define PGLUE_B_REG_PGLUE_B_PRTY_STS_WR 0x92b0UL //ACCESS:WR DataWidth:0x2 Description: Parity register #0 bit set or clear
#define PGLUE_B_PGLUE_B_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define PGLUE_B_PGLUE_B_PRTY_STS_WR_REG_PARITY_SIZE 0
#define PGLUE_B_PGLUE_B_PRTY_STS_WR_REG_TAG_DB (0x1<<1)
#define PGLUE_B_PGLUE_B_PRTY_STS_WR_REG_TAG_DB_SIZE 1
#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4UL //ACCESS:RW DataWidth:0x2 Description: Parity mask register #0 read/write
#define PGLUE_B_PGLUE_B_PRTY_MASK_REG_PARITY (0x1<<0)
#define PGLUE_B_PGLUE_B_PRTY_MASK_REG_PARITY_SIZE 0
#define PGLUE_B_PGLUE_B_PRTY_MASK_REG_TAG_DB (0x1<<1)
#define PGLUE_B_PGLUE_B_PRTY_MASK_REG_TAG_DB_SIZE 1
#define PGLUE_B_REG_DISABLE_TCPL_TRANSLATION_SIZE_CHECK 0x9484UL //ACCESS:RW DataWidth:0x1 Description: Debug only: 0 - Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation Size field smaller than the Function programmed STU value; clear the ATS_en shadow bit and send UR to the ATC. 1 - Disable the fix for CQ45220.
#define PGLUE_B_REG_PGL_TM1_E3 0x9488UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define PGLUE_B_PGL_TM1_E3_REG_PGL_PCIE_DLP2TLP_BUF_TMA (0xff<<0)
#define PGLUE_B_PGL_TM1_E3_REG_PGL_PCIE_DLP2TLP_BUF_TMA_SIZE 0
#define PGLUE_B_PGL_TM1_E3_REG_PGL_PCIE_DLP2TLP_BUF_TMB (0xff<<8)
#define PGLUE_B_PGL_TM1_E3_REG_PGL_PCIE_DLP2TLP_BUF_TMB_SIZE 8
#define PGLUE_B_PGL_TM1_E3_REG_PGL_PCIE_DLP2TLP_BUF_TMC (0xff<<16)
#define PGLUE_B_PGL_TM1_E3_REG_PGL_PCIE_DLP2TLP_BUF_TMC_SIZE 16
#define PGLUE_B_PGL_TM1_E3_REG_PGL_PCIE_DLP2TLP_BUF_TMD (0xff<<24)
#define PGLUE_B_PGL_TM1_E3_REG_PGL_PCIE_DLP2TLP_BUF_TMD_SIZE 24
#define PGLUE_B_REG_PGL_TM2_E3 0x948cUL //ACCESS:RW DataWidth:0x18 Multi Field Register
#define PGLUE_B_PGL_TM2_E3_REG_PGL_PCIE_TLP2DLP_BUF_TMA (0xff<<0)
#define PGLUE_B_PGL_TM2_E3_REG_PGL_PCIE_TLP2DLP_BUF_TMA_SIZE 0
#define PGLUE_B_PGL_TM2_E3_REG_PGL_PCIE_TLP2DLP_BUF_TMB (0xff<<8)
#define PGLUE_B_PGL_TM2_E3_REG_PGL_PCIE_TLP2DLP_BUF_TMB_SIZE 8
#define PGLUE_B_PGL_TM2_E3_REG_PGL_PCIE_TLP2DLP_BUF_TMC (0xff<<16)
#define PGLUE_B_PGL_TM2_E3_REG_PGL_PCIE_TLP2DLP_BUF_TMC_SIZE 16
#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD 0x9490UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_3_CNTRL_CMD 0x9494UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_2_STATUS_0 0x9498UL //ACCESS:R DataWidth:0xb Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits;
#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_3_STATUS_0 0x949cUL //ACCESS:R DataWidth:0xb Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits;
#define PGLUE_B_REG_CFG_SPACE_A_REQUEST_CLR 0x9400UL //ACCESS:W DataWidth:0x8 Description: Config space A attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in cfg_space_a_request register. Note: register contains bits from both paths. Note: Need to re-read the enabled registers after clearing the dirty bit and then check the dirty bit is still clear since they may have been written again during the scan.
#define PGLUE_B_REG_CFG_SPACE_A_REQUEST_CLR_SIZE 1
#define PGLUE_B_REG_CFG_SPACE_B_REQUEST_CLR 0x9404UL //ACCESS:W DataWidth:0x8 Description: Config space B attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in cfg_space_b_request register. Note: register contains bits from both paths. Note: Need to re-read the enabled registers after clearing the dirty bit and then check the dirty bit is still clear since they may have been written again during the scan.
#define PGLUE_B_REG_CFG_SPACE_B_REQUEST_CLR_SIZE 1
#define PGLUE_B_REG_DBG_OUT_DATA_LSB 0x9408UL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from PGLUE_B to the DBG block) - The 32 lsb data that goes to the DBG block.
#define PGLUE_B_REG_DBG_OUT_DATA_LSB_SIZE 1
#define PGLUE_B_REG_DBG_OUT_DATA_MSB 0x940cUL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from PGLUE_B to the DBG block) - The 32 msb data that goes to the DBG block.
#define PGLUE_B_REG_DBG_OUT_DATA_MSB_SIZE 1
#define PGLUE_B_REG_DBG_OUT_FRAME 0x9410UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from PGLUE_B to the DBG block) - The 4 frame bits that goes to the DBG block. Bit0 is the frame of data byte0; Bit1 is the frame of data byte1; Bit2 is the frame of data byte2; Bit3 is the frame of data byte4
#define PGLUE_B_REG_DBG_OUT_FRAME_SIZE 1
#define PGLUE_B_REG_DBG_OUT_VALID 0x9414UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from PGLUE_B to the DBG block) - The 4 valid bits that goes to the DBG block. Bit0 validtes data byte0; Bit1 validates data byte1; Bit2 validates data byte2; Bit3 validates data byte4
#define PGLUE_B_REG_DBG_OUT_VALID_SIZE 1
#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418UL //ACCESS:W DataWidth:0x8 Description: FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_7_0 register. Note: register contains bits from both paths.
#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR_SIZE 1
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96_CLR 0x941cUL //ACCESS:W DataWidth:0x20 Description: FLR request attention dirty bits clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_127_96 register.
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96_CLR_SIZE 1
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0_CLR 0x9420UL //ACCESS:W DataWidth:0x20 Description: FLR request attention dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_31_0 register.
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0_CLR_SIZE 1
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32_CLR 0x9424UL //ACCESS:W DataWidth:0x20 Description: FLR request attention dirty bits clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_63_32 register.
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32_CLR_SIZE 1
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64_CLR 0x9428UL //ACCESS:W DataWidth:0x20 Description: FLR request attention dirty bits clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_95_64 register.
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64_CLR_SIZE 1
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942cUL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Internal FID_enable configuration per-PF for master transactions.
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER_SIZE 1
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Internal FID_enable configuration per-PF for target read transactions.
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ_SIZE 1
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Internal FID_enable configuration per-PF for target write transactions.
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE_SIZE 1
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438UL //ACCESS:RW DataWidth:0x1 SPLIT:128 Description: Internal FID_enable configuration per-VF for master and target transactions.
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_SIZE 1
#define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x943cUL //ACCESS:W DataWidth:0x7 Description: Writing 1 to each bit in this register clears a corresponding error details register and enables logging new error details. Bit 0 - clears INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32 TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 - clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6 - clears TCPL_IN_TWO_RCBS_DETAILS.
#define PGLUE_B_REG_LATCHED_ERRORS_CLR_SIZE 1
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_PF_7_0_CLR 0x9440UL //ACCESS:W DataWidth:0x8 Description: Debug only - Shadow ATS_ENABLE bits clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the corresponding bit in shadow_ats_enable_pf_7_0 register. MCP should never use this unless a work-around is needed. Note: register contains bits from both paths.
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_PF_7_0_CLR_SIZE 1
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_127_96_CLR 0x9444UL //ACCESS:W DataWidth:0x20 Description: Shadow ATS_ENABLE bits clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the corresponding bit in shadow_ats_enable_vf_127_95 register. MCP should do this in PF-FLR and SR-IOV-disabled events.
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_127_96_CLR_SIZE 1
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_31_0_CLR 0x9448UL //ACCESS:W DataWidth:0x20 Description: Shadow ATS_ENABLE bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in shadow_ats_enable_vf_31_0 register. MCP should do this in PF-FLR and SR-IOV-disabled events.
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_31_0_CLR_SIZE 1
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_63_32_CLR 0x944cUL //ACCESS:W DataWidth:0x20 Description: Shadow ATS_ENABLE bits clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the corresponding bit in shadow_ats_enable_vf_63_32 register. MCP should do this in PF-FLR and SR-IOV-disabled events.
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_63_32_CLR_SIZE 1
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_95_64_CLR 0x9450UL //ACCESS:W DataWidth:0x20 Description: Shadow ATS_ENABLE bits clear for VFs64 to 95. MCP writes 1 to a bit in this register in order to clear the corresponding bit in shadow_ats_enable_vf_95_64 register. MCP should do this in PF-FLR and SR-IOV-disabled events.
#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_95_64_CLR_SIZE 1
#define PGLUE_B_REG_SHADOW_ATS_STU 0x9454UL //ACCESS:WB_R DataWidth:0x5 SPLIT:8 Description: Read only. Shadow ATS_STU register. (2^ATS_STU)*4KB is ATC translation address granularity.
#define PGLUE_B_REG_SHADOW_ATS_STU_SIZE 1
#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458UL //ACCESS:W DataWidth:0x8 Description: Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the corresponding bit in shadow_bme_pf_7_0 register. MCP should never use this unless a work-around is needed. Note: register contains bits from both paths.
#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR_SIZE 1
#define PGLUE_B_REG_SHADOW_BME_VF_127_96_CLR 0x945cUL //ACCESS:W DataWidth:0x20 Description: Shadow BME bits clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the corresponding bit in shadow_bme_vf_127_95 register. MCP should do this in PF-FLR and SR-IOV-disabled events.
#define PGLUE_B_REG_SHADOW_BME_VF_127_96_CLR_SIZE 1
#define PGLUE_B_REG_SHADOW_BME_VF_31_0_CLR 0x9460UL //ACCESS:W DataWidth:0x20 Description: Shadow BME bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in shadow_bme_vf_31_0 register. MCP should do this in PF-FLR and SR-IOV-disabled events.
#define PGLUE_B_REG_SHADOW_BME_VF_31_0_CLR_SIZE 1
#define PGLUE_B_REG_SHADOW_BME_VF_63_32_CLR 0x9464UL //ACCESS:W DataWidth:0x20 Description: Shadow BME bits clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the corresponding bit in shadow_bme_vf_63_32 register. MCP should do this in PF-FLR and SR-IOV-disabled events.
#define PGLUE_B_REG_SHADOW_BME_VF_63_32_CLR_SIZE 1
#define PGLUE_B_REG_SHADOW_BME_VF_95_64_CLR 0x9468UL //ACCESS:W DataWidth:0x20 Description: Shadow BME bits clear for VFs64 to 95. MCP writes 1 to a bit in this register in order to clear the corresponding bit in shadow_bme_vf_95_64 register. MCP should do this in PF-FLR and SR-IOV-disabled events.
#define PGLUE_B_REG_SHADOW_BME_VF_95_64_CLR_SIZE 1
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x946cUL //ACCESS:W DataWidth:0x8 Description: SR IOV disabled attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in sr_iov_disabled_request register. Note: register contains bits from both paths.
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR_SIZE 1
#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470UL //ACCESS:W DataWidth:0x8 Description: Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_7_0 register.
#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR_SIZE 1
#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474UL //ACCESS:W DataWidth:0x20 Description: Was_error indication dirty bits clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_127_96 register.
#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR_SIZE 1
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478UL //ACCESS:W DataWidth:0x20 Description: Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_31_0 register.
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR_SIZE 1
#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947cUL //ACCESS:W DataWidth:0x20 Description: Was_error indication dirty bits clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_63_32 register.
#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR_SIZE 1
#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480UL //ACCESS:W DataWidth:0x20 Description: Was_error indication dirty bits clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_95_64 register.
#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR_SIZE 1
#define PGLUE_B_REG_PORT4MODE_EN 0x924cUL //ACCESS:R DataWidth:0x1 Description: 0 - Work in two ports mode (one port per engine). 1 - Work in 4 port mode (2 ports per engine). This affects PFID translation. This register is removed for E3; where this information is received as an input from MISC block.
#define PGLUE_B_REG_PORT4MODE_EN_SIZE 1
#define PGLUE_B_REG_PGLUE_B_UNUSED_EMPTY_0 0x92b8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PGLUE_B_REG_PGLUE_B_UNUSED_EMPTY_0_SIZE 82
#define PGLUE_B_REG_PGLUE_B_UNUSED_EMPTY_1 0x94a0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PGLUE_B_REG_PGLUE_B_UNUSED_EMPTY_1_SIZE 728
#define PRS_REG_TSDM_INITIAL_CREDIT 0x40000UL //ACCESS:RW DataWidth:0x8 Description: The initial credit in the packet end message to the TSDM interface. Credit is transaction based.
#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004UL //ACCESS:RW DataWidth:0x8 Description: Context region for flush packet with packet type 0. Used in CFC load request message.
#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008UL //ACCESS:RW DataWidth:0x8 Description: Context region for flush packet with packet type 1. Used in CFC load request message.
#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000cUL //ACCESS:RW DataWidth:0x8 Description: Context region for flush packet with packet type 2. Used in CFC load request message.
#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010UL //ACCESS:RW DataWidth:0x8 Description: Context region for flush packet with packet type 3. Used in CFC load request message.
#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014UL //ACCESS:RW DataWidth:0x8 Description: Context region for flush packet with packet type4. Used in CFC load request message.
#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018UL //ACCESS:RW DataWidth:0x8 Description: Context region for flush packet with packet type 5. Used in CFC load request message.
#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001cUL //ACCESS:RW DataWidth:0x8 Description: Context region for flush packet with packet type 6. Used in CFC load request message.
#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020UL //ACCESS:RW DataWidth:0x8 Description: Context region for flush packet with packet type7. Used in CFC load request message.
#define PRS_REG_PURE_REGIONS 0x40024UL //ACCESS:RW DataWidth:0x8 Description: Context region for pure acknowledge packets. Used in CFC load request message
#define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028UL //ACCESS:RW DataWidth:0x8 Description: Context region for received Ethernet packet with a match and packet type 0. Used in CFC load request message
#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002cUL //ACCESS:RW DataWidth:0x8 Description: Context region for received Ethernet packet with a match and packet type 1. Used in CFC load request message
#define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030UL //ACCESS:RW DataWidth:0x8 Description: Context region for received Ethernet packet with a match and packet type 2. Used in CFC load request message
#define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034UL //ACCESS:RW DataWidth:0x8 Description: Context region for received Ethernet packet with a match and packet type 3. Used in CFC load request message
#define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038UL //ACCESS:RW DataWidth:0x8 Description: Context region for received Ethernet packet with a match and packet type 4. Used in CFC load request message
#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003cUL //ACCESS:RW DataWidth:0x8 Description: Context region for received Ethernet packet with a match and packet type 5. Used in CFC load request message
#define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040UL //ACCESS:RW DataWidth:0x8 Description: Context region for received Ethernet packet with a match and packet type 6. Used in CFC load request message
#define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044UL //ACCESS:RW DataWidth:0x8 Description: Context region for received Ethernet packet with a match and packet type 7. Used in CFC load request message
#define PRS_REG_INC_VALUE 0x40048UL //ACCESS:RW DataWidth:0x4 Description: The increment value to send in the CFC load request message
#define PRS_REG_CFC_LOAD_INITIAL_CREDIT 0x4004cUL //ACCESS:RW DataWidth:0x6 Description: The initial credit for the load message to the CFC interface. Credit is transaction based.
#define PRS_REG_EVENT_ID_0 0x40050UL //ACCESS:RW DataWidth:0x8 Description: The 8-bit event ID for a match and packet type 0. Used in packet start message to TCM.
#define PRS_REG_EVENT_ID_1 0x40054UL //ACCESS:RW DataWidth:0x8 Description: The 8-bit event ID for a match and packet type 1. Used in packet start message to TCM.
#define PRS_REG_EVENT_ID_2 0x40058UL //ACCESS:RW DataWidth:0x8 Description: The 8-bit event ID for a match and packet type 2. Used in packet start message to TCM.
#define PRS_REG_EVENT_ID_3 0x4005cUL //ACCESS:RW DataWidth:0x8 Description: The 8-bit event ID for a match and packet type 3. Used in packet start message to TCM.
#define PRS_REG_EVENT_ID_4 0x40060UL //ACCESS:RW DataWidth:0x8 Description: The 8-bit event ID for a match and packet type 4. Used in packet start message to TCM.
#define PRS_REG_EVENT_ID_5 0x40064UL //ACCESS:RW DataWidth:0x8 Description: The 8-bit event ID for a match and packet type 5. Used in packet start message to TCM.
#define PRS_REG_EVENT_ID_6 0x40068UL //ACCESS:RW DataWidth:0x8 Description: The 8-bit event ID for a match and packet type 6. Used in packet start message to TCM.
#define PRS_REG_EVENT_ID_7 0x4006cUL //ACCESS:RW DataWidth:0x8 Description: The 8-bit event ID for a match and packet type 7. Used in packet start message to TCM.
#define PRS_REG_NO_MATCH_EVENT_ID 0x40070UL //ACCESS:RW DataWidth:0x8 Description: The 8-bit event ID for cases where there is no match on the connection. Used in packet start message to TCM.
#define PRS_REG_TRCM_INITIAL_CREDIT 0x40074UL //ACCESS:RW DataWidth:0x8 Description: The initial credit in the packet start message to the TCM interface (message to STORM). Credit is cycle based.
#define PRS_REG_CM_HDR_TYPE_0 0x40078UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 0. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_TYPE_1 0x4007cUL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 1. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_TYPE_2 0x40080UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 2. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_TYPE_3 0x40084UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 3. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_TYPE_4 0x40088UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 4. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_TYPE_5 0x4008cUL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 5. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_TYPE_6 0x40090UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 6. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_TYPE_7 0x40094UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 7. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_0 0x40098UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 0 for loopback port. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009cUL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 1 for loopback port. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 2 for loopback port. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 3 for loopback port. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 4 for loopback port. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_5 0x400acUL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 5 for loopback port. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_6 0x400b0UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 6 for loopback port. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_7 0x400b4UL //ACCESS:RW DataWidth:0x20 Description: The CM header for a match and packet type 7 for loopback port. Used in packet start message to TCM.
#define PRS_REG_CM_NO_MATCH_HDR 0x400b8UL //ACCESS:RW DataWidth:0x20 Description: The CM header in case there was not a match on the connection
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bcUL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is set and packet type is 0. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is set and packet type is 1. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is set and packet type is 2. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is set and packet type is 3. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400ccUL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is set and packet type is 4. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is set and packet type is 5. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_6 0x400d4UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is set and packet type is 6. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_7 0x400d8UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is set and packet type is 7. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dcUL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is reset and packet type is 0. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is reset and packet type is 1. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is reset and packet type is 2. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is reset and packet type is 3. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ecUL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is reset and packet type is 4. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is reset and packet type is 5. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_6 0x400f4UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is reset and packet type is 6. Used in packet start message to TCM.
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_7 0x400f8UL //ACCESS:RW DataWidth:0x20 Description: The CM header for flush message where 'load existed' bit in CFC load response is reset and packet type is 7. Used in packet start message to TCM.
#define PRS_REG_CID_PORT_0 0x400fcUL //ACCESS:RW DataWidth:0x18 Description: CID for port 0 if no match
#define PRS_REG_CID_PORT_1 0x40100UL //ACCESS:RW DataWidth:0x18 Description: CID for port 1 if no match
#define PRS_REG_LCID_PORT_0 0x40104UL //ACCESS:RW DataWidth:0x8 Description: LCID for port 0 if no match
#define PRS_REG_LCID_PORT_1 0x40108UL //ACCESS:RW DataWidth:0x8 Description: LCID for port 1 if no match
#define PRS_REG_INITIAL_HEADER_SIZE 0x4010cUL //ACCESS:RW DataWidth:0x9 Description: Initial header size to read from the BRB for received packets
#define PRS_REG_FLUSH_HEADER_SIZE 0x40110UL //ACCESS:RW DataWidth:0x8 Description: Initial header size to read from the BRB for flush packets
#define PRS_REG_FLEXIBILITYPOSITION 0x40114UL //ACCESS:RW DataWidth:0x8 Description: Defines the position in bytes from the beginning of the packet from which to extract a 32-bit field.
#define PRS_REG_A_PRSU_12 0x40118UL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define PRS_A_PRSU_12_REG_TCP_SEARCH_IP_SRC (0x1<<0)
#define PRS_A_PRSU_12_REG_TCP_SEARCH_IP_SRC_SIZE 0
#define PRS_A_PRSU_12_REG_TCP_SEARCH_IP_DST (0x1<<1)
#define PRS_A_PRSU_12_REG_TCP_SEARCH_IP_DST_SIZE 1
#define PRS_A_PRSU_12_REG_TCP_SEARCH_TCP_SRC (0x1<<2)
#define PRS_A_PRSU_12_REG_TCP_SEARCH_TCP_SRC_SIZE 2
#define PRS_A_PRSU_12_REG_TCP_SEARCH_TCP_DST (0x1<<3)
#define PRS_A_PRSU_12_REG_TCP_SEARCH_TCP_DST_SIZE 3
#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011cUL //ACCESS:RW DataWidth:0x6 Description: The initial credit for the search message to the CFC interface. Credit is transaction based.
#define PRS_REG_SRC_INITIAL_CREDIT 0x40120UL //ACCESS:RW DataWidth:0x6 Description: The initial credit in the message to the Searcher interface. Credit is transaction based.
#define PRS_REG_NUM_OF_PACKETS 0x40124UL //ACCESS:ST DataWidth:0x18 Description: The number of input packets
#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128UL //ACCESS:ST DataWidth:0x18 Description: The number of input CFC flush packets
#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012cUL //ACCESS:ST DataWidth:0x18 Description: The number of input transparent flush packets
#define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130UL //ACCESS:ST DataWidth:0x20 Description: The number of cycles the Parser halted its operation since it could not allocate the next serial number
#define PRS_REG_A_PRSU_20 0x40134UL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define PRS_A_PRSU_20_REG_HASH_TCP_IPV4_PORT_0 (0x1<<0)
#define PRS_A_PRSU_20_REG_HASH_TCP_IPV4_PORT_0_SIZE 0
#define PRS_A_PRSU_20_REG_HASH_TCP_IPV4_PORT_1 (0x1<<1)
#define PRS_A_PRSU_20_REG_HASH_TCP_IPV4_PORT_1_SIZE 1
#define PRS_A_PRSU_20_REG_HASH_TCP_IPV6_PORT_0 (0x1<<2)
#define PRS_A_PRSU_20_REG_HASH_TCP_IPV6_PORT_0_SIZE 2
#define PRS_A_PRSU_20_REG_HASH_TCP_IPV6_PORT_1 (0x1<<3)
#define PRS_A_PRSU_20_REG_HASH_TCP_IPV6_PORT_1_SIZE 3
#define PRS_REG_SOFT_RST 0x4013cUL //ACCESS:RW DataWidth:0x1 Description: Soft reset - reset all FSM
#define PRS_REG_IFIFO_TMA 0x40140UL //ACCESS:RW DataWidth:0x5 Description: TM Bits of 512x35 IFIFO Memory
#define PRS_REG_IFIFO_TMB 0x40144UL //ACCESS:RW DataWidth:0x5 Description: TM Bits of 512x35 IFIFO and 400x65 PRSF Memories
#define PRS_REG_DBG_SELECT 0x40148UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PRS to the DBG block) - for selecting a line to output to the DBG block.
#define PRS_REG_DBG_BYTE_ENABLE 0x4014cUL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PRS to the DBG block) - for enabling bytes in the selected line (after the select; before the shift).
#define PRS_REG_DBG_SHIFT 0x40150UL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from PRS to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154UL //ACCESS:R DataWidth:0x20 Description: debug only: Serial number status lsb 32 bits. '1' indicates this serail number was released by SDM but cannot be used because a previous serial number was not released.
#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158UL //ACCESS:R DataWidth:0x20 Description: debug only: Serial number status msb 32 bits. '1' indicates this serail number was released by SDM but cannot be used because a previous serial number was not released.
#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015cUL //ACCESS:R DataWidth:0x8 Description: debug only: TSDM current credit. Transaction based.
#define PRS_REG_TCM_CURRENT_CREDIT 0x40160UL //ACCESS:R DataWidth:0x8 Description: debug only: TCM current credit. Cycle based.
#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164UL //ACCESS:R DataWidth:0x8 Description: debug only: CFC load request current credit. Transaction based.
#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168UL //ACCESS:R DataWidth:0x8 Description: debug only: CFC search request current credit. Transaction based.
#define PRS_REG_SRC_CURRENT_CREDIT 0x4016cUL //ACCESS:R DataWidth:0x4 Description: debug only: SRC current credit. Transaction based.
#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170UL //ACCESS:R DataWidth:0x2 Description: debug only: Number of pending requests for header parsing.
#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174UL //ACCESS:R DataWidth:0x2 Description: debug only: Number of pending requests for CAC on port 0.
#define PRS_REG_PENDING_BRB_CAC1_RQ 0x40178UL //ACCESS:R DataWidth:0x2 Description: debug only: Number of pending requests for CAC on port 1.
#define PRS_REG_PENDING_BRB_CAC2_RQ 0x4017cUL //ACCESS:R DataWidth:0x2 Description: debug only: Number of pending requests for CAC on port 2.
#define PRS_REG_PENDING_BRB_CAC3_RQ 0x40180UL //ACCESS:R DataWidth:0x2 Description: debug only: Number of pending requests for CAC on port 3.
#define PRS_REG_PENDING_BRB_CAC4_RQ 0x40184UL //ACCESS:R DataWidth:0x2 Description: debug only: Number of pending requests for CAC on port 4.
#define PRS_REG_PRS_INT_STS 0x40188UL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define PRS_REG_PRS_INT_STS_CLR 0x4018cUL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define PRS_REG_PRS_INT_STS_WR 0x40190UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define PRS_REG_PRS_INT_MASK 0x40194UL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define PRS_REG_PRS_PRTY_STS 0x40198UL //ACCESS:R DataWidth:0x8 Description: Parity register #0 read
#define PRS_PRS_PRTY_STS_REG_PARITY (0x1<<0)
#define PRS_PRS_PRTY_STS_REG_PARITY_SIZE 0
#define PRS_PRS_PRTY_STS_REG_IFIFO (0x1<<1)
#define PRS_PRS_PRTY_STS_REG_IFIFO_SIZE 1
#define PRS_PRS_PRTY_STS_REG_CACU (0x1<<2)
#define PRS_PRS_PRTY_STS_REG_CACU_SIZE 2
#define PRS_PRS_PRTY_STS_REG_CFCR (0x1<<3)
#define PRS_PRS_PRTY_STS_REG_CFCR_SIZE 3
#define PRS_PRS_PRTY_STS_REG_CFCQ (0x1<<4)
#define PRS_PRS_PRTY_STS_REG_CFCQ_SIZE 4
#define PRS_PRS_PRTY_STS_REG_CFCF (0x1<<5)
#define PRS_PRS_PRTY_STS_REG_CFCF_SIZE 5
#define PRS_PRS_PRTY_STS_REG_SRCF (0x1<<6)
#define PRS_PRS_PRTY_STS_REG_SRCF_SIZE 6
#define PRS_PRS_PRTY_STS_REG_PRSF (0x1<<7)
#define PRS_PRS_PRTY_STS_REG_PRSF_SIZE 7
#define PRS_REG_PRS_PRTY_STS_CLR 0x4019cUL //ACCESS:RC DataWidth:0x8 Description: Parity register #0 read clear
#define PRS_PRS_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define PRS_PRS_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define PRS_PRS_PRTY_STS_CLR_REG_IFIFO (0x1<<1)
#define PRS_PRS_PRTY_STS_CLR_REG_IFIFO_SIZE 1
#define PRS_PRS_PRTY_STS_CLR_REG_CACU (0x1<<2)
#define PRS_PRS_PRTY_STS_CLR_REG_CACU_SIZE 2
#define PRS_PRS_PRTY_STS_CLR_REG_CFCR (0x1<<3)
#define PRS_PRS_PRTY_STS_CLR_REG_CFCR_SIZE 3
#define PRS_PRS_PRTY_STS_CLR_REG_CFCQ (0x1<<4)
#define PRS_PRS_PRTY_STS_CLR_REG_CFCQ_SIZE 4
#define PRS_PRS_PRTY_STS_CLR_REG_CFCF (0x1<<5)
#define PRS_PRS_PRTY_STS_CLR_REG_CFCF_SIZE 5
#define PRS_PRS_PRTY_STS_CLR_REG_SRCF (0x1<<6)
#define PRS_PRS_PRTY_STS_CLR_REG_SRCF_SIZE 6
#define PRS_PRS_PRTY_STS_CLR_REG_PRSF (0x1<<7)
#define PRS_PRS_PRTY_STS_CLR_REG_PRSF_SIZE 7
#define PRS_REG_PRS_PRTY_STS_WR 0x401a0UL //ACCESS:WR DataWidth:0x8 Description: Parity register #0 bit set or clear
#define PRS_PRS_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define PRS_PRS_PRTY_STS_WR_REG_PARITY_SIZE 0
#define PRS_PRS_PRTY_STS_WR_REG_IFIFO (0x1<<1)
#define PRS_PRS_PRTY_STS_WR_REG_IFIFO_SIZE 1
#define PRS_PRS_PRTY_STS_WR_REG_CACU (0x1<<2)
#define PRS_PRS_PRTY_STS_WR_REG_CACU_SIZE 2
#define PRS_PRS_PRTY_STS_WR_REG_CFCR (0x1<<3)
#define PRS_PRS_PRTY_STS_WR_REG_CFCR_SIZE 3
#define PRS_PRS_PRTY_STS_WR_REG_CFCQ (0x1<<4)
#define PRS_PRS_PRTY_STS_WR_REG_CFCQ_SIZE 4
#define PRS_PRS_PRTY_STS_WR_REG_CFCF (0x1<<5)
#define PRS_PRS_PRTY_STS_WR_REG_CFCF_SIZE 5
#define PRS_PRS_PRTY_STS_WR_REG_SRCF (0x1<<6)
#define PRS_PRS_PRTY_STS_WR_REG_SRCF_SIZE 6
#define PRS_PRS_PRTY_STS_WR_REG_PRSF (0x1<<7)
#define PRS_PRS_PRTY_STS_WR_REG_PRSF_SIZE 7
#define PRS_REG_PRS_PRTY_MASK 0x401a4UL //ACCESS:RW DataWidth:0x8 Description: Parity mask register #0 read/write
#define PRS_PRS_PRTY_MASK_REG_PARITY (0x1<<0)
#define PRS_PRS_PRTY_MASK_REG_PARITY_SIZE 0
#define PRS_PRS_PRTY_MASK_REG_IFIFO (0x1<<1)
#define PRS_PRS_PRTY_MASK_REG_IFIFO_SIZE 1
#define PRS_PRS_PRTY_MASK_REG_CACU (0x1<<2)
#define PRS_PRS_PRTY_MASK_REG_CACU_SIZE 2
#define PRS_PRS_PRTY_MASK_REG_CFCR (0x1<<3)
#define PRS_PRS_PRTY_MASK_REG_CFCR_SIZE 3
#define PRS_PRS_PRTY_MASK_REG_CFCQ (0x1<<4)
#define PRS_PRS_PRTY_MASK_REG_CFCQ_SIZE 4
#define PRS_PRS_PRTY_MASK_REG_CFCF (0x1<<5)
#define PRS_PRS_PRTY_MASK_REG_CFCF_SIZE 5
#define PRS_PRS_PRTY_MASK_REG_SRCF (0x1<<6)
#define PRS_PRS_PRTY_MASK_REG_SRCF_SIZE 6
#define PRS_PRS_PRTY_MASK_REG_PRSF (0x1<<7)
#define PRS_PRS_PRTY_MASK_REG_PRSF_SIZE 7
#define PRS_REG_VLAN_TYPE_0 0x401a8UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PRS_REG_VLAN_TYPE_1 0x401acUL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PRS_REG_VLAN_TYPE_2 0x401b0UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PRS_REG_VLAN_TYPE_3 0x401b4UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PRS_REG_VLAN_TYPE_4 0x401b8UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PRS_REG_VLAN_TYPE_5 0x401bcUL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PRS_REG_VLAN_TYPE_6 0x401c0UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PRS_REG_VLAN_TYPE_7 0x401c4UL //ACCESS:RW DataWidth:0x10 Description: One of 8 values that should be compared to type in Ethernet parsing. If there is a match; the field after Ethernet is the first VLAN. Reset value is 0x8100 which is the standard VLAN type. Note that when checking second VLAN; type is compared only to 0x8100.
#define PRS_REG_E1HOV_MODE 0x401c8UL //ACCESS:RW DataWidth:0x1 Description: Indicates if in outer vlan mode. 0=non-outer-vlan mode; 1=outer vlan mode.
#define PRS_REG_HASH_5TH_TUPLE 0x401ccUL //ACCESS:RW DataWidth:0x1 Description: Indicates if to include the protocol field in the hash request. 0=do not include; 1=include
#define PRS_REG_FCOE_TYPE 0x401d0UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for first FCoE type
#define PRS_REG_TAG_ETHERTYPE_0 0x401d4UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 0
#define PRS_REG_TCP_SEARCH_VLAN 0x401d8UL //ACCESS:RW DataWidth:0x1 Description: Indicates whether to include inner VLAN (if present) in the TCP search. If not present, a value of 0 will be sent in its place.
#define PRS_REG_ECO_RESERVED 0x40220UL //ACCESS:RW DataWidth:0x8 Description: debug only: Reserved bits for ECO
#define PRS_REG_TAG_ETHERTYPE_1 0x40224UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 1
#define PRS_REG_TAG_ETHERTYPE_2 0x40228UL //ACCESS:RW DataWidth:0x10 Description: The Ethernet type value for L2 tag 2
#define PRS_REG_TAG_LEN_0 0x4022cUL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 0. The length is between 2B and 14B; in 2B granularity
#define PRS_REG_TAG_LEN_1 0x40230UL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 1. The length is between 2B and 14B; in 2B granularity
#define PRS_REG_TAG_LEN_2 0x40234UL //ACCESS:RW DataWidth:0x4 Description: The length of the info field for L2 tag 2. The length is between 2B and 14B; in 2B granularity
#define PRS_REG_LOAD_CANCELLED_EVENT_ID 0x40258UL //ACCESS:RW DataWidth:0x8 Description: Event ID for the load cancelled case
#define PRS_REG_CONTEXT_ERROR_EVENT_ID 0x4025cUL //ACCESS:RW DataWidth:0x8 Description: Event ID for the context error case
#define PRS_REG_CM_LOAD_CANCELLED_HDR 0x40260UL //ACCESS:RW DataWidth:0x20 Description: CM header for the load cancelled case
#define PRS_REG_CM_CONTEXT_ERROR_HDR 0x40264UL //ACCESS:RW DataWidth:0x20 Description: CM header for the context error case
#define PRS_REG_HIGIG_HDR_SIZE_0 0x40268UL //ACCESS:RW DataWidth:0x4 Description: Size of the HiGig header for port 0 (in 4B increments). If HiGig is disabled this value should be 0.
#define PRS_REG_HIGIG_HDR_SIZE_1 0x4026cUL //ACCESS:RW DataWidth:0x4 Description: Size of the HiGig header for port 1 (in 4B increments). If HiGig is disabled this value should be 0.
#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header for port 0 packets.
#define PRS_REG_HDRS_AFTER_OUTER_VLAN_PORT_0 0x40274UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the outer VLAN header for port 0 packets.
#define PRS_REG_HDRS_AFTER_INNER_VLAN_PORT_0 0x40278UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the inner VLAN header for port 0 packets.
#define PRS_REG_HDRS_AFTER_LLC_PORT_0 0x4027cUL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the LLC header for port 0 packets.
#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 0 for port 0 packets
#define PRS_REG_HDRS_AFTER_TAG_1_PORT_0 0x40284UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 1 for port 0 packets
#define PRS_REG_HDRS_AFTER_TAG_2_PORT_0 0x40288UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 2 for port 0 packets
#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028cUL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which headers must appear in the packet for port 0 packets
#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header for port 1 packets.
#define PRS_REG_HDRS_AFTER_OUTER_VLAN_PORT_1 0x40294UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the outer VLAN header for port 1 packets.
#define PRS_REG_HDRS_AFTER_INNER_VLAN_PORT_1 0x40298UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the inner VLAN header for port 1 packets.
#define PRS_REG_HDRS_AFTER_LLC_PORT_1 0x4029cUL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the LLC header for port 1 packets.
#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 0 for port 1 packets
#define PRS_REG_HDRS_AFTER_TAG_1_PORT_1 0x402a4UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 1 for port 1 packets
#define PRS_REG_HDRS_AFTER_TAG_2_PORT_1 0x402a8UL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 2 for port 1 packets
#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402acUL //ACCESS:RW DataWidth:0x6 Description: Bit-map indicating which headers must appear in the packet for port 1 packets
#define PRS_REG_TCP_SEARCH_OVLAN 0x402b0UL //ACCESS:RW DataWidth:0x1 Description: Indicates whether to include outer VLAN (if present) in the TCP search. If not present, a value of 1 will be sent in its place.
#define PRS_REG_NIC_MODE 0x40138UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: If set indicates not to send messages to CFC on received packets - one bit per PF
#define PRS_REG_NIC_MODE_SIZE 1
#define PRS_REG_INFO_VECTOR 0x40200UL //ACCESS:WB_R DataWidth:0x70 Description: The value of PARAM0; PARAM1; PARAM2 and PARAM3 [15:0] from the last message sent to the TCP-Rx STORM
#define PRS_REG_INFO_VECTOR_SIZE 4
#define PRS_REG_HDRS_AFTER_BASIC 0x40238UL //ACCESS:R DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.
#define PRS_REG_HDRS_AFTER_BASIC_SIZE 1
#define PRS_REG_HDRS_AFTER_OUTER_VLAN 0x4023cUL //ACCESS:R DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the outer VLAN header.
#define PRS_REG_HDRS_AFTER_OUTER_VLAN_SIZE 1
#define PRS_REG_HDRS_AFTER_INNER_VLAN 0x40240UL //ACCESS:R DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the inner VLAN header.
#define PRS_REG_HDRS_AFTER_INNER_VLAN_SIZE 1
#define PRS_REG_HDRS_AFTER_LLC 0x40244UL //ACCESS:R DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after the LLC header.
#define PRS_REG_HDRS_AFTER_LLC_SIZE 1
#define PRS_REG_HDRS_AFTER_TAG_0 0x40248UL //ACCESS:R DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 0
#define PRS_REG_HDRS_AFTER_TAG_0_SIZE 1
#define PRS_REG_HDRS_AFTER_TAG_1 0x4024cUL //ACCESS:R DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 1
#define PRS_REG_HDRS_AFTER_TAG_1_SIZE 1
#define PRS_REG_HDRS_AFTER_TAG_2 0x40250UL //ACCESS:R DataWidth:0x6 Description: Bit-map indicating which L2 hdrs may appear after L2 tag 2
#define PRS_REG_HDRS_AFTER_TAG_2_SIZE 1
#define PRS_REG_MUST_HAVE_HDRS 0x40254UL //ACCESS:R DataWidth:0x6 Description: Bit-map indicating which headers must appear in the packet
#define PRS_REG_MUST_HAVE_HDRS_SIZE 1
#define PRS_REG_PRS_UNUSED_EMPTY_0 0x401dcUL //ACCESS:R DataWidth:0x20 Unused empty space
#define PRS_REG_PRS_UNUSED_EMPTY_0_SIZE 9
#define PRS_REG_PRS_UNUSED_EMPTY_1 0x402b4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PRS_REG_PRS_UNUSED_EMPTY_1_SIZE 83
#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_CDU0_L2P_REG_RQ_CDU0_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_CDU0_L2P_REG_RQ_CDU0_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_CDU0_L2P_REG_RQ_CDU0_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_CDU0_L2P_REG_RQ_CDU0_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_PSWRQ_CDU1_L2P 0x120004UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_CDU1_L2P_REG_RQ_CDU1_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_CDU1_L2P_REG_RQ_CDU1_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_CDU1_L2P_REG_RQ_CDU1_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_CDU1_L2P_REG_RQ_CDU1_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for CDU module port 0
#define PXP2_REG_RQ_CDU0_ELAST_MEM_ADDR 0x12000cUL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for CDU module port 0
#define PXP2_REG_RQ_CDU1_EFIRST_MEM_ADDR 0x120010UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for CDU module port 1
#define PXP2_REG_RQ_CDU1_ELAST_MEM_ADDR 0x120014UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for CDU module port 1
#define PXP2_REG_RQ_CDU_P_SIZE 0x120018UL //ACCESS:RW DataWidth:0x4 Description: page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define PXP2_REG_PSWRQ_TM0_L2P 0x12001cUL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_TM0_L2P_REG_RQ_TM0_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_TM0_L2P_REG_RQ_TM0_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_TM0_L2P_REG_RQ_TM0_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_TM0_L2P_REG_RQ_TM0_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_PSWRQ_TM1_L2P 0x120020UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_TM1_L2P_REG_RQ_TM1_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_TM1_L2P_REG_RQ_TM1_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_TM1_L2P_REG_RQ_TM1_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_TM1_L2P_REG_RQ_TM1_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_RQ_TM0_EFIRST_MEM_ADDR 0x120024UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for TM module port 0
#define PXP2_REG_RQ_TM0_ELAST_MEM_ADDR 0x120028UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for TM module port 0
#define PXP2_REG_RQ_TM1_EFIRST_MEM_ADDR 0x12002cUL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for TM module port 1
#define PXP2_REG_RQ_TM1_ELAST_MEM_ADDR 0x120030UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for TM module port 1
#define PXP2_REG_RQ_TM_P_SIZE 0x120034UL //ACCESS:RW DataWidth:0x4 Description: page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define PXP2_REG_PSWRQ_QM0_L2P 0x120038UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_QM0_L2P_REG_RQ_QM0_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_QM0_L2P_REG_RQ_QM0_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_QM0_L2P_REG_RQ_QM0_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_QM0_L2P_REG_RQ_QM0_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_PSWRQ_QM1_L2P 0x12003cUL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_QM1_L2P_REG_RQ_QM1_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_QM1_L2P_REG_RQ_QM1_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_QM1_L2P_REG_RQ_QM1_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_QM1_L2P_REG_RQ_QM1_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_RQ_QM0_EFIRST_MEM_ADDR 0x120040UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for QM module port 0
#define PXP2_REG_RQ_QM0_ELAST_MEM_ADDR 0x120044UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for QM module port 0
#define PXP2_REG_RQ_QM1_EFIRST_MEM_ADDR 0x120048UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for QM module port 1
#define PXP2_REG_RQ_QM1_ELAST_MEM_ADDR 0x12004cUL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for QM module port 1
#define PXP2_REG_RQ_QM_P_SIZE 0x120050UL //ACCESS:RW DataWidth:0x4 Description: page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_SRC0_L2P_REG_RQ_SRC0_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_SRC0_L2P_REG_RQ_SRC0_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_SRC0_L2P_REG_RQ_SRC0_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_SRC0_L2P_REG_RQ_SRC0_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_PSWRQ_SRC1_L2P 0x120058UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_SRC1_L2P_REG_RQ_SRC1_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_SRC1_L2P_REG_RQ_SRC1_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_SRC1_L2P_REG_RQ_SRC1_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_SRC1_L2P_REG_RQ_SRC1_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_RQ_SRC0_EFIRST_MEM_ADDR 0x12005cUL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for SRC module port 0
#define PXP2_REG_RQ_SRC0_ELAST_MEM_ADDR 0x120060UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for SRC module port 0
#define PXP2_REG_RQ_SRC1_EFIRST_MEM_ADDR 0x120064UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for SRC module port 1
#define PXP2_REG_RQ_SRC1_ELAST_MEM_ADDR 0x120068UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for SRC module port 1
#define PXP2_REG_RQ_SRC_P_SIZE 0x12006cUL //ACCESS:RW DataWidth:0x4 Description: page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define PXP2_REG_PSWRQ_XSDM0_L2P 0x120070UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_XSDM0_L2P_REG_RQ_XSDM0_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_XSDM0_L2P_REG_RQ_XSDM0_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_XSDM0_L2P_REG_RQ_XSDM0_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_XSDM0_L2P_REG_RQ_XSDM0_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_PSWRQ_XSDM1_L2P 0x120074UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_XSDM1_L2P_REG_RQ_XSDM1_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_XSDM1_L2P_REG_RQ_XSDM1_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_XSDM1_L2P_REG_RQ_XSDM1_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_XSDM1_L2P_REG_RQ_XSDM1_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_RQ_XSDM0_EFIRST_MEM_ADDR 0x120078UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for XSDM module port 0
#define PXP2_REG_RQ_XSDM0_ELAST_MEM_ADDR 0x12007cUL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for XSDM module port 0
#define PXP2_REG_RQ_XSDM1_EFIRST_MEM_ADDR 0x120080UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for XSDM module port 1
#define PXP2_REG_RQ_XSDM1_ELAST_MEM_ADDR 0x120084UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for XSDM module port 1
#define PXP2_REG_RQ_XSDM_P_SIZE 0x120088UL //ACCESS:RW DataWidth:0x4 Description: page size in L2P table for XSDM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define PXP2_REG_PSWRQ_USDM0_L2P 0x12008cUL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_USDM0_L2P_REG_RQ_USDM0_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_USDM0_L2P_REG_RQ_USDM0_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_USDM0_L2P_REG_RQ_USDM0_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_USDM0_L2P_REG_RQ_USDM0_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_PSWRQ_USDM1_L2P 0x120090UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_USDM1_L2P_REG_RQ_USDM1_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_USDM1_L2P_REG_RQ_USDM1_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_USDM1_L2P_REG_RQ_USDM1_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_USDM1_L2P_REG_RQ_USDM1_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for USDM module port 0
#define PXP2_REG_RQ_USDM0_ELAST_MEM_ADDR 0x120098UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for USDM module port 0
#define PXP2_REG_RQ_USDM1_EFIRST_MEM_ADDR 0x12009cUL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for USDM module port 1
#define PXP2_REG_RQ_USDM1_ELAST_MEM_ADDR 0x1200a0UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for USDM module port 1
#define PXP2_REG_RQ_USDM_P_SIZE 0x1200a4UL //ACCESS:RW DataWidth:0x4 Description: page size in L2P table for USDM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define PXP2_REG_PSWRQ_USDMDP0_L2P 0x1200a8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_USDMDP0_L2P_REG_RQ_USDMDP0_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_USDMDP0_L2P_REG_RQ_USDMDP0_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_USDMDP0_L2P_REG_RQ_USDMDP0_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_USDMDP0_L2P_REG_RQ_USDMDP0_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_PSWRQ_USDMDP1_L2P 0x1200acUL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_USDMDP1_L2P_REG_RQ_USDMDP1_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_USDMDP1_L2P_REG_RQ_USDMDP1_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_USDMDP1_L2P_REG_RQ_USDMDP1_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_USDMDP1_L2P_REG_RQ_USDMDP1_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_RQ_USDMDP0_EFIRST_MEM_ADDR 0x1200b0UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for USDM DP module port 0
#define PXP2_REG_RQ_USDMDP0_ELAST_MEM_ADDR 0x1200b4UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for USDM DP module port 0
#define PXP2_REG_RQ_USDMDP1_EFIRST_MEM_ADDR 0x1200b8UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for USDM DP module port 1
#define PXP2_REG_RQ_USDMDP1_ELAST_MEM_ADDR 0x1200bcUL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for USDM DP module port 1
#define PXP2_REG_RQ_USDMDP_P_SIZE 0x1200c0UL //ACCESS:RW DataWidth:0x4 Description: page size in L2P table for USDM DP module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define PXP2_REG_PSWRQ_CSDM0_L2P 0x1200c4UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_CSDM0_L2P_REG_RQ_CSDM0_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_CSDM0_L2P_REG_RQ_CSDM0_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_CSDM0_L2P_REG_RQ_CSDM0_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_CSDM0_L2P_REG_RQ_CSDM0_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_PSWRQ_CSDM1_L2P 0x1200c8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_CSDM1_L2P_REG_RQ_CSDM1_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_CSDM1_L2P_REG_RQ_CSDM1_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_CSDM1_L2P_REG_RQ_CSDM1_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_CSDM1_L2P_REG_RQ_CSDM1_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_RQ_CSDM0_EFIRST_MEM_ADDR 0x1200ccUL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for CSDM module port 0
#define PXP2_REG_RQ_CSDM0_ELAST_MEM_ADDR 0x1200d0UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for CSDM module port 0
#define PXP2_REG_RQ_CSDM1_EFIRST_MEM_ADDR 0x1200d4UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for CSDM module port 1
#define PXP2_REG_RQ_CSDM1_ELAST_MEM_ADDR 0x1200d8UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for CSDM module port 1
#define PXP2_REG_RQ_CSDM_P_SIZE 0x1200dcUL //ACCESS:RW DataWidth:0x4 Description: page size in L2P table for CSDM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_TSDM0_L2P_REG_RQ_TSDM0_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_TSDM0_L2P_REG_RQ_TSDM0_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_TSDM0_L2P_REG_RQ_TSDM0_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_TSDM0_L2P_REG_RQ_TSDM0_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_PSWRQ_TSDM1_L2P 0x1200e4UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_TSDM1_L2P_REG_RQ_TSDM1_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_TSDM1_L2P_REG_RQ_TSDM1_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_TSDM1_L2P_REG_RQ_TSDM1_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_TSDM1_L2P_REG_RQ_TSDM1_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_RQ_TSDM0_EFIRST_MEM_ADDR 0x1200e8UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for TSDM module port 0
#define PXP2_REG_RQ_TSDM0_ELAST_MEM_ADDR 0x1200ecUL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for TSDM module port 0
#define PXP2_REG_RQ_TSDM1_EFIRST_MEM_ADDR 0x1200f0UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for TSDM module port 1
#define PXP2_REG_RQ_TSDM1_ELAST_MEM_ADDR 0x1200f4UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for TSDM module port 1
#define PXP2_REG_RQ_TSDM_P_SIZE 0x1200f8UL //ACCESS:RW DataWidth:0x4 Description: page size in L2P table for TSDM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define PXP2_REG_PSWRQ_DBG0_L2P 0x1200fcUL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_DBG0_L2P_REG_RQ_DBG0_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_DBG0_L2P_REG_RQ_DBG0_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_DBG0_L2P_REG_RQ_DBG0_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_DBG0_L2P_REG_RQ_DBG0_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_PSWRQ_DBG1_L2P 0x120100UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_DBG1_L2P_REG_RQ_DBG1_FIRST_MEM_ADDR (0x3ff<<0)
#define PXP2_PSWRQ_DBG1_L2P_REG_RQ_DBG1_FIRST_MEM_ADDR_SIZE 0
#define PXP2_PSWRQ_DBG1_L2P_REG_RQ_DBG1_LAST_MEM_ADDR (0x3ff<<10)
#define PXP2_PSWRQ_DBG1_L2P_REG_RQ_DBG1_LAST_MEM_ADDR_SIZE 10
#define PXP2_REG_RQ_DBG0_EFIRST_MEM_ADDR 0x120104UL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for dbg module port 0
#define PXP2_REG_RQ_DBG0_ELAST_MEM_ADDR 0x120108UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for dbg module port 0
#define PXP2_REG_RQ_DBG1_EFIRST_MEM_ADDR 0x12010cUL //ACCESS:RW DataWidth:0x12 Description: external first_mem_addr field in L2P table for dbg module port 1
#define PXP2_REG_RQ_DBG1_ELAST_MEM_ADDR 0x120110UL //ACCESS:RW DataWidth:0x12 Description: external last_mem_addr field in L2P table for dbg module port 1
#define PXP2_REG_RQ_DBG_P_SIZE 0x120114UL //ACCESS:RW DataWidth:0x4 Description: page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define PXP2_REG_PSWRQ_HOST_L2P 0x120118UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define PXP2_PSWRQ_HOST_L2P_REG_RQ_HOST_P_SIZE (0x7<<0)
#define PXP2_PSWRQ_HOST_L2P_REG_RQ_HOST_P_SIZE_SIZE 0
#define PXP2_PSWRQ_HOST_L2P_REG_RQ_HOST_TR_P_SIZE (0x7<<3)
#define PXP2_PSWRQ_HOST_L2P_REG_RQ_HOST_TR_P_SIZE_SIZE 3
#define PXP2_REG_RQ_CSDM_ENTRY_TH 0x12011cUL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to csdm in the queues
#define PXP2_REG_RQ_USDM_ENTRY_TH 0x120120UL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to usdm in the queues
#define PXP2_REG_RQ_USDMDP_ENTRY_TH 0x120124UL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to usdmdp in the queues
#define PXP2_REG_RQ_TSDM_ENTRY_TH 0x120128UL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to tsdm in the queues
#define PXP2_REG_RQ_XSDM_ENTRY_TH 0x12012cUL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to xsdm in the queues
#define PXP2_REG_RQ_DMAE_ENTRY_TH 0x120130UL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to rwh in the queues
#define PXP2_REG_RQ_CDUWR_ENTRY_TH 0x120134UL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to cduwr in the queues
#define PXP2_REG_RQ_CDURD_ENTRY_TH 0x120138UL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to cdurd in the queues
#define PXP2_REG_RQ_PBF_ENTRY_TH 0x12013cUL //ACCESS:RW DataWidth:0x5 Description: This number indicates how many entries are guaranteed to pbf in the queues
#define PXP2_REG_RQ_QM_ENTRY_TH 0x120140UL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to qm in the queues
#define PXP2_REG_RQ_TM_ENTRY_TH 0x120144UL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to tm in the queues
#define PXP2_REG_RQ_SRC_ENTRY_TH 0x120148UL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to src in the queues
#define PXP2_REG_RQ_DBG_ENTRY_TH 0x12014cUL //ACCESS:RW DataWidth:0x3 Description: This number indicates how many entries are guaranteed to debug in the queues
#define PXP2_REG_RQ_HC_ENTRY_TH 0x120150UL //ACCESS:RW DataWidth:0x2 Description: This number indicates how many entries are guaranteed to hc in the queues
#define PXP2_REG_RQ_GC_INIT_VAL 0x120154UL //ACCESS:RW DataWidth:0x8 Description: Initial value of global counter; This value MUST be 256 - sum of all clients thresholds
#define PXP2_REG_PSWRQ_UFIFO 0x120158UL //ACCESS:RW DataWidth:0x8 Multi Field Register
#define PXP2_PSWRQ_UFIFO_REG_RQ_UFIFO_LOW_TH (0xf<<0)
#define PXP2_PSWRQ_UFIFO_REG_RQ_UFIFO_LOW_TH_SIZE 0
#define PXP2_PSWRQ_UFIFO_REG_RQ_UFIFO_HIGH_TH (0xf<<4)
#define PXP2_PSWRQ_UFIFO_REG_RQ_UFIFO_HIGH_TH_SIZE 4
#define PXP2_REG_RQ_WR_MBS0 0x12015cUL //ACCESS:RW DataWidth:0x3 Description: Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010: 512B;
#define PXP2_REG_RQ_RD_MBS0 0x120160UL //ACCESS:RW DataWidth:0x3 Description: Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010: 512B;011:1K:100:2K;101:4K
#define PXP2_REG_RQ_WR_MBS1 0x120164UL //ACCESS:RW DataWidth:0x3 Description: Max burst size filed for write requests port 1; 000 - 128B; 001:256B; 010: 512B;
#define PXP2_REG_RQ_RD_MBS1 0x120168UL //ACCESS:RW DataWidth:0x3 Description: Max burst size filed for read requests port 1; 000 - 128B; 001:256B; 010: 512B;011:1K:100:2K;101:4K
#define PXP2_REG_RQ_IGNORE_BLK 0x12016cUL //ACCESS:RW DataWidth:0x1 Description: if '1'; requester will ignore the reader blk_per_client indication
#define PXP2_REG_RQ_FUNCNUM0 0x120170UL //ACCESS:RW DataWidth:0x3 Description: NOT USED
#define PXP2_REG_RQ_FUNCNUM1 0x120174UL //ACCESS:RW DataWidth:0x3 Description: NOT USED
#define PXP2_REG_PSWRQ_QM_PCI_ATTR 0x120178UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define PXP2_PSWRQ_QM_PCI_ATTR_REG_RQ_QM_RELAXED (0x1<<0)
#define PXP2_PSWRQ_QM_PCI_ATTR_REG_RQ_QM_RELAXED_SIZE 0
#define PXP2_PSWRQ_QM_PCI_ATTR_REG_RQ_QM_NOSNOOP (0x1<<1)
#define PXP2_PSWRQ_QM_PCI_ATTR_REG_RQ_QM_NOSNOOP_SIZE 1
#define PXP2_REG_PSWRQ_TM_PCI_ATTR 0x12017cUL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define PXP2_PSWRQ_TM_PCI_ATTR_REG_RQ_TM_RELAXED (0x1<<0)
#define PXP2_PSWRQ_TM_PCI_ATTR_REG_RQ_TM_RELAXED_SIZE 0
#define PXP2_PSWRQ_TM_PCI_ATTR_REG_RQ_TM_NOSNOOP (0x1<<1)
#define PXP2_PSWRQ_TM_PCI_ATTR_REG_RQ_TM_NOSNOOP_SIZE 1
#define PXP2_REG_PSWRQ_SRC_PCI_ATTR 0x120180UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define PXP2_PSWRQ_SRC_PCI_ATTR_REG_RQ_SRC_RELAXED (0x1<<0)
#define PXP2_PSWRQ_SRC_PCI_ATTR_REG_RQ_SRC_RELAXED_SIZE 0
#define PXP2_PSWRQ_SRC_PCI_ATTR_REG_RQ_SRC_NOSNOOP (0x1<<1)
#define PXP2_PSWRQ_SRC_PCI_ATTR_REG_RQ_SRC_NOSNOOP_SIZE 1
#define PXP2_REG_PSWRQ_CDU_PCI_ATTR 0x120184UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define PXP2_PSWRQ_CDU_PCI_ATTR_REG_RQ_CDU_RELAXED (0x1<<0)
#define PXP2_PSWRQ_CDU_PCI_ATTR_REG_RQ_CDU_RELAXED_SIZE 0
#define PXP2_PSWRQ_CDU_PCI_ATTR_REG_RQ_CDU_NOSNOOP (0x1<<1)
#define PXP2_PSWRQ_CDU_PCI_ATTR_REG_RQ_CDU_NOSNOOP_SIZE 1
#define PXP2_REG_PSWRQ_DBG_PCI_ATTR 0x120188UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define PXP2_PSWRQ_DBG_PCI_ATTR_REG_RQ_DBG_RELAXED (0x1<<0)
#define PXP2_PSWRQ_DBG_PCI_ATTR_REG_RQ_DBG_RELAXED_SIZE 0
#define PXP2_PSWRQ_DBG_PCI_ATTR_REG_RQ_DBG_NOSNOOP (0x1<<1)
#define PXP2_PSWRQ_DBG_PCI_ATTR_REG_RQ_DBG_NOSNOOP_SIZE 1
#define PXP2_REG_PSWRQ_HC_PCI_ATTR 0x12018cUL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define PXP2_PSWRQ_HC_PCI_ATTR_REG_RQ_HC_RELAXED (0x1<<0)
#define PXP2_PSWRQ_HC_PCI_ATTR_REG_RQ_HC_RELAXED_SIZE 0
#define PXP2_PSWRQ_HC_PCI_ATTR_REG_RQ_HC_NOSNOOP (0x1<<1)
#define PXP2_PSWRQ_HC_PCI_ATTR_REG_RQ_HC_NOSNOOP_SIZE 1
#define PXP2_REG_PSWRQ_DMAE_PCI_ATTR 0x120190UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define PXP2_PSWRQ_DMAE_PCI_ATTR_REG_RQ_DMAE_RELAXED (0x1<<0)
#define PXP2_PSWRQ_DMAE_PCI_ATTR_REG_RQ_DMAE_RELAXED_SIZE 0
#define PXP2_PSWRQ_DMAE_PCI_ATTR_REG_RQ_DMAE_NOSNOOP (0x1<<1)
#define PXP2_PSWRQ_DMAE_PCI_ATTR_REG_RQ_DMAE_NOSNOOP_SIZE 1
#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194UL //ACCESS:RW DataWidth:0x2 Description: Endian mode for qm
#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198UL //ACCESS:RW DataWidth:0x2 Description: Endian mode for tm
#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019cUL //ACCESS:RW DataWidth:0x2 Description: Endian mode for src
#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0UL //ACCESS:RW DataWidth:0x2 Description: Endian mode for cdu
#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4UL //ACCESS:RW DataWidth:0x2 Description: Endian mode for debug
#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8UL //ACCESS:RW DataWidth:0x2 Description: Endian mode for hc
#define PXP2_REG_RQ_PBF_ENDIAN_M 0x1201acUL //ACCESS:RW DataWidth:0x2 Description: Endian mode for pbf
#define PXP2_REG_RQ_RBC_DONE 0x1201b0UL //ACCESS:RW DataWidth:0x1 Description: 1' indicates that the RBC has finished configuring the PSWRQ
#define PXP2_REG_RQ_CFG_DONE 0x1201b4UL //ACCESS:R DataWidth:0x1 Description: 1' indicates that the requester has finished its internal configuration
#define PXP2_REG_RQ_DONE_FIFO_TH 0x1201b8UL //ACCESS:RW DataWidth:0x5 Description: Write Done fifo threshold; this fifo has write done indications;this threshold would not be reached unless there is a bug
#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bcUL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ0 write requests
#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_ADD1_REG_RQ_BW_RD_ADD1 (0x3ff<<0)
#define PXP2_PSWRQ_BW_ADD1_REG_RQ_BW_RD_ADD1_SIZE 0
#define PXP2_PSWRQ_BW_ADD1_REG_RQ_BW_WR_ADD1 (0x3ff<<10)
#define PXP2_PSWRQ_BW_ADD1_REG_RQ_BW_WR_ADD1_SIZE 10
#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_ADD2_REG_RQ_BW_RD_ADD2 (0x3ff<<0)
#define PXP2_PSWRQ_BW_ADD2_REG_RQ_BW_RD_ADD2_SIZE 0
#define PXP2_PSWRQ_BW_ADD2_REG_RQ_BW_WR_ADD2 (0x3ff<<10)
#define PXP2_PSWRQ_BW_ADD2_REG_RQ_BW_WR_ADD2_SIZE 10
#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_ADD3_REG_RQ_BW_RD_ADD3 (0x3ff<<0)
#define PXP2_PSWRQ_BW_ADD3_REG_RQ_BW_RD_ADD3_SIZE 0
#define PXP2_PSWRQ_BW_ADD3_REG_RQ_BW_WR_ADD3 (0x3ff<<10)
#define PXP2_PSWRQ_BW_ADD3_REG_RQ_BW_WR_ADD3_SIZE 10
#define PXP2_REG_RQ_BW_RD_ADD4 0x1201ccUL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ4 read requests
#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ5 read requests
#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_ADD6_REG_RQ_BW_RD_ADD6 (0x3ff<<0)
#define PXP2_PSWRQ_BW_ADD6_REG_RQ_BW_RD_ADD6_SIZE 0
#define PXP2_PSWRQ_BW_ADD6_REG_RQ_BW_WR_ADD6 (0x3ff<<10)
#define PXP2_PSWRQ_BW_ADD6_REG_RQ_BW_WR_ADD6_SIZE 10
#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_ADD7_REG_RQ_BW_RD_ADD7 (0x3ff<<0)
#define PXP2_PSWRQ_BW_ADD7_REG_RQ_BW_RD_ADD7_SIZE 0
#define PXP2_PSWRQ_BW_ADD7_REG_RQ_BW_WR_ADD7 (0x3ff<<10)
#define PXP2_PSWRQ_BW_ADD7_REG_RQ_BW_WR_ADD7_SIZE 10
#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dcUL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_ADD8_REG_RQ_BW_RD_ADD8 (0x3ff<<0)
#define PXP2_PSWRQ_BW_ADD8_REG_RQ_BW_RD_ADD8_SIZE 0
#define PXP2_PSWRQ_BW_ADD8_REG_RQ_BW_WR_ADD8 (0x3ff<<10)
#define PXP2_PSWRQ_BW_ADD8_REG_RQ_BW_WR_ADD8_SIZE 10
#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_ADD9_REG_RQ_BW_RD_ADD9 (0x3ff<<0)
#define PXP2_PSWRQ_BW_ADD9_REG_RQ_BW_RD_ADD9_SIZE 0
#define PXP2_PSWRQ_BW_ADD9_REG_RQ_BW_WR_ADD9 (0x3ff<<10)
#define PXP2_PSWRQ_BW_ADD9_REG_RQ_BW_WR_ADD9_SIZE 10
#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_ADD10_REG_RQ_BW_RD_ADD10 (0x3ff<<0)
#define PXP2_PSWRQ_BW_ADD10_REG_RQ_BW_RD_ADD10_SIZE 0
#define PXP2_PSWRQ_BW_ADD10_REG_RQ_BW_WR_ADD10 (0x3ff<<10)
#define PXP2_PSWRQ_BW_ADD10_REG_RQ_BW_WR_ADD10_SIZE 10
#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_ADD11_REG_RQ_BW_RD_ADD11 (0x3ff<<0)
#define PXP2_PSWRQ_BW_ADD11_REG_RQ_BW_RD_ADD11_SIZE 0
#define PXP2_PSWRQ_BW_ADD11_REG_RQ_BW_WR_ADD11 (0x3ff<<10)
#define PXP2_PSWRQ_BW_ADD11_REG_RQ_BW_WR_ADD11_SIZE 10
#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ecUL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ12 read requests
#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ13 read requests
#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ14 read requests
#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ15 read requests
#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fcUL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ16 read requests
#define PXP2_REG_RQ_BW_RD_ADD17 0x120200UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ17 read requests
#define PXP2_REG_RQ_BW_RD_ADD18 0x120204UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ18 read requests
#define PXP2_REG_RQ_BW_RD_ADD19 0x120208UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ19 read requests
#define PXP2_REG_RQ_BW_RD_ADD20 0x12020cUL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ20 read requests
#define PXP2_REG_RQ_BW_RD_ADD22 0x120210UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ22 read requests
#define PXP2_REG_RQ_BW_RD_ADD23 0x120214UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ23 read requests
#define PXP2_REG_RQ_BW_RD_ADD24 0x120218UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ24 read requests
#define PXP2_REG_RQ_BW_RD_ADD25 0x12021cUL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ25 read requests
#define PXP2_REG_RQ_BW_RD_ADD26 0x120220UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ26 read requests
#define PXP2_REG_RQ_BW_RD_ADD27 0x120224UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ27 read requests
#define PXP2_REG_PSWRQ_BW_ADD28 0x120228UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_ADD28_REG_RQ_BW_RD_ADD28 (0x3ff<<0)
#define PXP2_PSWRQ_BW_ADD28_REG_RQ_BW_RD_ADD28_SIZE 0
#define PXP2_PSWRQ_BW_ADD28_REG_RQ_BW_WR_ADD28 (0x3ff<<10)
#define PXP2_PSWRQ_BW_ADD28_REG_RQ_BW_WR_ADD28_SIZE 10
#define PXP2_REG_RQ_BW_WR_ADD29 0x12022cUL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ29 write requests
#define PXP2_REG_RQ_BW_WR_ADD30 0x120230UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ30 write requests
#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ0 read requests
#define PXP2_REG_PSWRQ_BW_UB1 0x120238UL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PSWRQ_BW_UB1_REG_RQ_BW_RD_UBOUND1 (0x7f<<0)
#define PXP2_PSWRQ_BW_UB1_REG_RQ_BW_RD_UBOUND1_SIZE 0
#define PXP2_PSWRQ_BW_UB1_REG_RQ_BW_WR_UBOUND1 (0x7f<<7)
#define PXP2_PSWRQ_BW_UB1_REG_RQ_BW_WR_UBOUND1_SIZE 7
#define PXP2_REG_PSWRQ_BW_UB2 0x12023cUL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PSWRQ_BW_UB2_REG_RQ_BW_RD_UBOUND2 (0x7f<<0)
#define PXP2_PSWRQ_BW_UB2_REG_RQ_BW_RD_UBOUND2_SIZE 0
#define PXP2_PSWRQ_BW_UB2_REG_RQ_BW_WR_UBOUND2 (0x7f<<7)
#define PXP2_PSWRQ_BW_UB2_REG_RQ_BW_WR_UBOUND2_SIZE 7
#define PXP2_REG_PSWRQ_BW_UB3 0x120240UL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PSWRQ_BW_UB3_REG_RQ_BW_RD_UBOUND3 (0x7f<<0)
#define PXP2_PSWRQ_BW_UB3_REG_RQ_BW_RD_UBOUND3_SIZE 0
#define PXP2_PSWRQ_BW_UB3_REG_RQ_BW_WR_UBOUND3 (0x7f<<7)
#define PXP2_PSWRQ_BW_UB3_REG_RQ_BW_WR_UBOUND3_SIZE 7
#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ4 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ5 read requests
#define PXP2_REG_PSWRQ_BW_UB6 0x12024cUL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PSWRQ_BW_UB6_REG_RQ_BW_RD_UBOUND6 (0x7f<<0)
#define PXP2_PSWRQ_BW_UB6_REG_RQ_BW_RD_UBOUND6_SIZE 0
#define PXP2_PSWRQ_BW_UB6_REG_RQ_BW_WR_UBOUND6 (0x7f<<7)
#define PXP2_PSWRQ_BW_UB6_REG_RQ_BW_WR_UBOUND6_SIZE 7
#define PXP2_REG_PSWRQ_BW_UB7 0x120250UL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PSWRQ_BW_UB7_REG_RQ_BW_RD_UBOUND7 (0x7f<<0)
#define PXP2_PSWRQ_BW_UB7_REG_RQ_BW_RD_UBOUND7_SIZE 0
#define PXP2_PSWRQ_BW_UB7_REG_RQ_BW_WR_UBOUND7 (0x7f<<7)
#define PXP2_PSWRQ_BW_UB7_REG_RQ_BW_WR_UBOUND7_SIZE 7
#define PXP2_REG_PSWRQ_BW_UB8 0x120254UL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PSWRQ_BW_UB8_REG_RQ_BW_RD_UBOUND8 (0x7f<<0)
#define PXP2_PSWRQ_BW_UB8_REG_RQ_BW_RD_UBOUND8_SIZE 0
#define PXP2_PSWRQ_BW_UB8_REG_RQ_BW_WR_UBOUND8 (0x7f<<7)
#define PXP2_PSWRQ_BW_UB8_REG_RQ_BW_WR_UBOUND8_SIZE 7
#define PXP2_REG_PSWRQ_BW_UB9 0x120258UL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PSWRQ_BW_UB9_REG_RQ_BW_RD_UBOUND9 (0x7f<<0)
#define PXP2_PSWRQ_BW_UB9_REG_RQ_BW_RD_UBOUND9_SIZE 0
#define PXP2_PSWRQ_BW_UB9_REG_RQ_BW_WR_UBOUND9 (0x7f<<7)
#define PXP2_PSWRQ_BW_UB9_REG_RQ_BW_WR_UBOUND9_SIZE 7
#define PXP2_REG_PSWRQ_BW_UB10 0x12025cUL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PSWRQ_BW_UB10_REG_RQ_BW_RD_UBOUND10 (0x7f<<0)
#define PXP2_PSWRQ_BW_UB10_REG_RQ_BW_RD_UBOUND10_SIZE 0
#define PXP2_PSWRQ_BW_UB10_REG_RQ_BW_WR_UBOUND10 (0x7f<<7)
#define PXP2_PSWRQ_BW_UB10_REG_RQ_BW_WR_UBOUND10_SIZE 7
#define PXP2_REG_PSWRQ_BW_UB11 0x120260UL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PSWRQ_BW_UB11_REG_RQ_BW_RD_UBOUND11 (0x7f<<0)
#define PXP2_PSWRQ_BW_UB11_REG_RQ_BW_RD_UBOUND11_SIZE 0
#define PXP2_PSWRQ_BW_UB11_REG_RQ_BW_WR_UBOUND11 (0x7f<<7)
#define PXP2_PSWRQ_BW_UB11_REG_RQ_BW_WR_UBOUND11_SIZE 7
#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ12 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ13 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026cUL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ14 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ15 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ16 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ17 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027cUL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ18 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ19 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ20 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ22 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028cUL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ23 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ24 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ25 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ26 read requests
#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029cUL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ27 read requests
#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0UL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PSWRQ_BW_UB28_REG_RQ_BW_RD_UBOUND28 (0x7f<<0)
#define PXP2_PSWRQ_BW_UB28_REG_RQ_BW_RD_UBOUND28_SIZE 0
#define PXP2_PSWRQ_BW_UB28_REG_RQ_BW_WR_UBOUND28 (0x7f<<7)
#define PXP2_PSWRQ_BW_UB28_REG_RQ_BW_WR_UBOUND28_SIZE 7
#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ29
#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8UL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound for VQ30
#define PXP2_REG_RQ_BW_RD_L0 0x1202acUL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ0 Read requests
#define PXP2_REG_PSWRQ_BW_L1 0x1202b0UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_L1_REG_RQ_BW_WR_L1 (0x3ff<<0)
#define PXP2_PSWRQ_BW_L1_REG_RQ_BW_WR_L1_SIZE 0
#define PXP2_PSWRQ_BW_L1_REG_RQ_BW_RD_L1 (0x3ff<<10)
#define PXP2_PSWRQ_BW_L1_REG_RQ_BW_RD_L1_SIZE 10
#define PXP2_REG_PSWRQ_BW_L2 0x1202b4UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_L2_REG_RQ_BW_WR_L2 (0x3ff<<0)
#define PXP2_PSWRQ_BW_L2_REG_RQ_BW_WR_L2_SIZE 0
#define PXP2_PSWRQ_BW_L2_REG_RQ_BW_RD_L2 (0x3ff<<10)
#define PXP2_PSWRQ_BW_L2_REG_RQ_BW_RD_L2_SIZE 10
#define PXP2_REG_PSWRQ_BW_L3 0x1202b8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_L3_REG_RQ_BW_WR_L3 (0x3ff<<0)
#define PXP2_PSWRQ_BW_L3_REG_RQ_BW_WR_L3_SIZE 0
#define PXP2_PSWRQ_BW_L3_REG_RQ_BW_RD_L3 (0x3ff<<10)
#define PXP2_PSWRQ_BW_L3_REG_RQ_BW_RD_L3_SIZE 10
#define PXP2_REG_RQ_BW_RD_L4 0x1202bcUL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ4 Read requests
#define PXP2_REG_RQ_BW_RD_L5 0x1202c0UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ5 Read- currently not used
#define PXP2_REG_PSWRQ_BW_L6 0x1202c4UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_L6_REG_RQ_BW_RD_L6 (0x3ff<<0)
#define PXP2_PSWRQ_BW_L6_REG_RQ_BW_RD_L6_SIZE 0
#define PXP2_PSWRQ_BW_L6_REG_RQ_BW_WR_L6 (0x3ff<<10)
#define PXP2_PSWRQ_BW_L6_REG_RQ_BW_WR_L6_SIZE 10
#define PXP2_REG_PSWRQ_BW_L7 0x1202c8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_L7_REG_RQ_BW_RD_L7 (0x3ff<<0)
#define PXP2_PSWRQ_BW_L7_REG_RQ_BW_RD_L7_SIZE 0
#define PXP2_PSWRQ_BW_L7_REG_RQ_BW_WR_L7 (0x3ff<<10)
#define PXP2_PSWRQ_BW_L7_REG_RQ_BW_WR_L7_SIZE 10
#define PXP2_REG_PSWRQ_BW_L8 0x1202ccUL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_L8_REG_RQ_BW_RD_L8 (0x3ff<<0)
#define PXP2_PSWRQ_BW_L8_REG_RQ_BW_RD_L8_SIZE 0
#define PXP2_PSWRQ_BW_L8_REG_RQ_BW_WR_L8 (0x3ff<<10)
#define PXP2_PSWRQ_BW_L8_REG_RQ_BW_WR_L8_SIZE 10
#define PXP2_REG_PSWRQ_BW_L9 0x1202d0UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_L9_REG_RQ_BW_RD_L9 (0x3ff<<0)
#define PXP2_PSWRQ_BW_L9_REG_RQ_BW_RD_L9_SIZE 0
#define PXP2_PSWRQ_BW_L9_REG_RQ_BW_WR_L9 (0x3ff<<10)
#define PXP2_PSWRQ_BW_L9_REG_RQ_BW_WR_L9_SIZE 10
#define PXP2_REG_PSWRQ_BW_L10 0x1202d4UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_L10_REG_RQ_BW_RD_L10 (0x3ff<<0)
#define PXP2_PSWRQ_BW_L10_REG_RQ_BW_RD_L10_SIZE 0
#define PXP2_PSWRQ_BW_L10_REG_RQ_BW_WR_L10 (0x3ff<<10)
#define PXP2_PSWRQ_BW_L10_REG_RQ_BW_WR_L10_SIZE 10
#define PXP2_REG_PSWRQ_BW_L11 0x1202d8UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_L11_REG_RQ_BW_RD_L11 (0x3ff<<0)
#define PXP2_PSWRQ_BW_L11_REG_RQ_BW_RD_L11_SIZE 0
#define PXP2_PSWRQ_BW_L11_REG_RQ_BW_WR_L11 (0x3ff<<10)
#define PXP2_PSWRQ_BW_L11_REG_RQ_BW_WR_L11_SIZE 10
#define PXP2_REG_RQ_BW_RD_L12 0x1202dcUL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ12 Read requests
#define PXP2_REG_RQ_BW_RD_L13 0x1202e0UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ13 Read requests
#define PXP2_REG_RQ_BW_RD_L14 0x1202e4UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ14 Read requests
#define PXP2_REG_RQ_BW_RD_L15 0x1202e8UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ15 Read requests
#define PXP2_REG_RQ_BW_RD_L16 0x1202ecUL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ16 Read requests
#define PXP2_REG_RQ_BW_RD_L17 0x1202f0UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ17 Read requests
#define PXP2_REG_RQ_BW_RD_L18 0x1202f4UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ18 Read requests
#define PXP2_REG_RQ_BW_RD_L19 0x1202f8UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ19 Read requests
#define PXP2_REG_RQ_BW_RD_L20 0x1202fcUL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ20 Read requests
#define PXP2_REG_RQ_BW_RD_L22 0x120300UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ22 Read requests
#define PXP2_REG_RQ_BW_RD_L23 0x120304UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ23 Read requests
#define PXP2_REG_RQ_BW_RD_L24 0x120308UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ24 Read requests
#define PXP2_REG_RQ_BW_RD_L25 0x12030cUL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ25 Read requests
#define PXP2_REG_RQ_BW_RD_L26 0x120310UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ26 Read requests
#define PXP2_REG_RQ_BW_RD_L27 0x120314UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ27 Read requests
#define PXP2_REG_PSWRQ_BW_L28 0x120318UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWRQ_BW_L28_REG_RQ_BW_RD_L28 (0x3ff<<0)
#define PXP2_PSWRQ_BW_L28_REG_RQ_BW_RD_L28_SIZE 0
#define PXP2_PSWRQ_BW_L28_REG_RQ_BW_WR_L28 (0x3ff<<10)
#define PXP2_PSWRQ_BW_L28_REG_RQ_BW_WR_L28_SIZE 10
#define PXP2_REG_RQ_BW_WR_L29 0x12031cUL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ29 Write requests
#define PXP2_REG_RQ_BW_WR_L30 0x120320UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L for VQ30 Write requests
#define PXP2_REG_PSWRQ_BW_RD 0x120324UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define PXP2_PSWRQ_BW_RD_REG_RQ_RD_BW_ADD (0x3ff<<0)
#define PXP2_PSWRQ_BW_RD_REG_RQ_RD_BW_ADD_SIZE 0
#define PXP2_PSWRQ_BW_RD_REG_RQ_RD_BW_UBOUND (0x7f<<10)
#define PXP2_PSWRQ_BW_RD_REG_RQ_RD_BW_UBOUND_SIZE 10
#define PXP2_PSWRQ_BW_RD_REG_RQ_RD_BW_L (0x3ff<<17)
#define PXP2_PSWRQ_BW_RD_REG_RQ_RD_BW_L_SIZE 17
#define PXP2_REG_PSWRQ_BW_WR 0x120328UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define PXP2_PSWRQ_BW_WR_REG_RQ_WR_BW_ADD (0x3ff<<0)
#define PXP2_PSWRQ_BW_WR_REG_RQ_WR_BW_ADD_SIZE 0
#define PXP2_PSWRQ_BW_WR_REG_RQ_WR_BW_UBOUND (0x7f<<10)
#define PXP2_PSWRQ_BW_WR_REG_RQ_WR_BW_UBOUND_SIZE 10
#define PXP2_PSWRQ_BW_WR_REG_RQ_WR_BW_L (0x3ff<<17)
#define PXP2_PSWRQ_BW_WR_REG_RQ_WR_BW_L_SIZE 17
#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032cUL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define PXP2_PSWRQ_BW_CREDIT_REG_RQ_READ_CREDIT (0x7<<0)
#define PXP2_PSWRQ_BW_CREDIT_REG_RQ_READ_CREDIT_SIZE 0
#define PXP2_PSWRQ_BW_CREDIT_REG_RQ_WRITE_CREDIT (0x7<<3)
#define PXP2_PSWRQ_BW_CREDIT_REG_RQ_WRITE_CREDIT_SIZE 3
#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330UL //ACCESS:RW DataWidth:0x1 Description: When '1'; requests will enter input buffers but wont get out towards the glue
#define PXP2_REG_RQ_PSWRQ_L2P_TM 0x120334UL //ACCESS:RW DataWidth:0x5 Description: tm input for l2p memory
#define PXP2_REG_RQ_SLOW_TH 0x120338UL //ACCESS:RW DataWidth:0x8 Description: when number of free entries in the context ram will be lower than this;the input clients arbiter will work in a slower pace
#define PXP2_REG_RQ_PDR_LIMIT 0x12033cUL //ACCESS:RW DataWidth:0xd Description: Pending read limiter threshold; in Dwords
#define PXP2_REG_RQ_DBG_HEAD_MUX_SEL 0x120340UL //ACCESS:RW DataWidth:0x5 Description: sets which vq head pointer to see out of queues 0-31
#define PXP2_REG_RQ_DBG_TAIL_MUX_SEL 0x120344UL //ACCESS:RW DataWidth:0x5 Description: sets which vq tail pointer to see out of queues 0-31
#define PXP2_REG_WR_USDMDP_TH 0x120348UL //ACCESS:RW DataWidth:0x9 Description: a. When pxp2.wr_th_mode_usdmdp=0 (E1.5-65 mode) should be initialized to (MPS/32); b. When pxp2.wr_th_mode_usdmdp=1 (E1.5-90; enhanced mode) and pxp2.wr_usdmdp_outst_req is different than default (3) should be initialized to (pxp2.wr_usdmdp_outst_req x MPS/32); when pxp2.wr_usdmdp_outst_req is 3 the reset value is the correct configuration
#define PXP2_REG_WR_DMAE_FULL_TH2 0x12034cUL //ACCESS:RW DataWidth:0x5 Description: if Number of entries in the dmae internal fifo is bigger than this number than full will be asserted
#define PXP2_REG_WR_CDU_FULL_TH2 0x120350UL //ACCESS:RW DataWidth:0x6 Description: if Number of entries in the cdu internal fifo is bigger than this number than full will be asserted
#define PXP2_REG_WR_USDMDP_FULL_TH2 0x120354UL //ACCESS:RW DataWidth:0x9 Description: if Number of entries in the usdmdp internal fifo is bigger than this number than full will be asserted
#define PXP2_REG_WR_USDMDP_FIFO0_TMA 0x120358UL //ACCESS:RW DataWidth:0x5 Description: tma input for fifo 0
#define PXP2_REG_WR_USDMDP_FIFO0_TMB 0x12035cUL //ACCESS:RW DataWidth:0x5 Description: tmb input for fifo 0
#define PXP2_REG_WR_USDMDP_FIFO1_TMA 0x120360UL //ACCESS:RW DataWidth:0x5 Description: tma input for fifo 1
#define PXP2_REG_WR_USDMDP_FIFO1_TMB 0x120364UL //ACCESS:RW DataWidth:0x5 Description: tmb input for fifo 1
#define PXP2_REG_WR_DMAE_TH 0x120368UL //ACCESS:RW DataWidth:0xa Description: This register is not used when pxp2.wr_rev_mode is 1. This register should have value of 63 when pxp2.wr_rev_mode is 0 to disable the threshold mechanism for DMAE. Therefore; 63 is the init value for all modes.
#define PXP2_REG_RD_START_INIT 0x12036cUL //ACCESS:RW DataWidth:0x1 Description: Signals the PSWRD block to start initializing internal memories
#define PXP2_REG_RD_INIT_DONE 0x120370UL //ACCESS:R DataWidth:0x1 Description: PSWRD internal memories initialization is done
#define PXP2_REG_RD_DISABLE_INPUTS 0x120374UL //ACCESS:RW DataWidth:0x1 Description: When '1'; inputs to the PSWRD block are ignored
#define PXP2_REG_RD_MAX_BLKS_VQ0 0x120378UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq0
#define PXP2_REG_RD_MAX_BLKS_VQ1 0x12037cUL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq1
#define PXP2_REG_RD_MAX_BLKS_VQ2 0x120380UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq2
#define PXP2_REG_RD_MAX_BLKS_VQ3 0x120384UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq3
#define PXP2_REG_RD_MAX_BLKS_VQ4 0x120388UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq4
#define PXP2_REG_RD_MAX_BLKS_VQ5 0x12038cUL //ACCESS:RW DataWidth:0x8 Description: Not used. VQ5 is not used for read
#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq6
#define PXP2_REG_RD_MAX_BLKS_VQ7 0x120394UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq7
#define PXP2_REG_RD_MAX_BLKS_VQ8 0x120398UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq8
#define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039cUL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq9
#define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq10
#define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq11
#define PXP2_REG_RD_MAX_BLKS_VQ12 0x1203a8UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq12
#define PXP2_REG_RD_MAX_BLKS_VQ13 0x1203acUL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq13
#define PXP2_REG_RD_MAX_BLKS_VQ14 0x1203b0UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq14
#define PXP2_REG_RD_MAX_BLKS_VQ15 0x1203b4UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq15
#define PXP2_REG_RD_MAX_BLKS_VQ16 0x1203b8UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq16
#define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bcUL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq17
#define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq18
#define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq19
#define PXP2_REG_RD_MAX_BLKS_VQ20 0x1203c8UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq20
#define PXP2_REG_RD_MAX_BLKS_VQ21 0x1203ccUL //ACCESS:RW DataWidth:0x8 Description: Not used. VQ21 is not used for read
#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq22
#define PXP2_REG_RD_MAX_BLKS_VQ23 0x1203d4UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq23
#define PXP2_REG_RD_MAX_BLKS_VQ24 0x1203d8UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq24
#define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dcUL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq25
#define PXP2_REG_RD_MAX_BLKS_VQ26 0x1203e0UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq26
#define PXP2_REG_RD_MAX_BLKS_VQ27 0x1203e4UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq27
#define PXP2_REG_RD_MAX_BLKS_VQ28 0x1203e8UL //ACCESS:RW DataWidth:0x8 Description: The maximum number of blocks in Tetris Buffer that can be allocated for vq28
#define PXP2_REG_RD_ARB_DELAY 0x1203ecUL //ACCESS:RW DataWidth:0x4 Description: Debug only: The arbiter delay. The delivery port waits ARB_DELAY cycles before asserting 'port_is_idle'. This value is based on implementation and should not be changed.
#define PXP2_REG_RD_PBF_IN_SEPARATE_VQ 0x1203f0UL //ACCESS:RW DataWidth:0x1 Description: 1' indicates that the PBF has a separate VQ and uses VQ4. '0' indicates it shares VQ9 with SDM clients. This field should be consistent with ~pbf_registers_pci_voq_id.pci_voq_id
#define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4UL //ACCESS:RW DataWidth:0x2 Description: PBF byte swapping mode configuration for master read requests
#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8UL //ACCESS:RW DataWidth:0x2 Description: QM byte swapping mode configuration for master read requests
#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fcUL //ACCESS:RW DataWidth:0x2 Description: TM byte swapping mode configuration for master read requests
#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400UL //ACCESS:RW DataWidth:0x2 Description: SRC byte swapping mode configuration for master read requests
#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404UL //ACCESS:RW DataWidth:0x2 Description: CDU byte swapping mode configuration for master read requests
#define PXP2_REG_RD_SR_NUM_CFG 0x120408UL //ACCESS:RW DataWidth:0x7 Description: Debug only: Total number of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed.
#define PXP2_REG_RD_BLK_NUM_CFG 0x12040cUL //ACCESS:RW DataWidth:0x8 Description: Debug only: Total number of available blocks in Tetris Buffer. Must be bigger than 6. Normally should not be changed.
#define PXP2_REG_RD_ALMOST_FULL_THR 0x120410UL //ACCESS:RW DataWidth:0x5 Description: Debug only: If more than this Number of entries are used in the clock synchronization FIFO; it asserts the 'almost full' bit. This number is common to all clock synchronization FIFOs. This value is based on implementation and should not be changed.
#define PXP2_REG_RD_SR_CNT 0x120414UL //ACCESS:R DataWidth:0x7 Description: Debug only: The SR counter - number of unused sub request ids
#define PXP2_REG_RD_BLK_CNT 0x120418UL //ACCESS:R DataWidth:0x8 Description: Debug only: The blocks counter - number of unused block ids
#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041cUL //ACCESS:R DataWidth:0x1 Description: Debug only: Indication if delivery ports are idle
#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420UL //ACCESS:R DataWidth:0x1 Description: Debug only: Indication if delivery ports are idle
#define PXP2_REG_RD_ALMOST_FULL_0 0x120424UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_ALMOST_FULL_1 0x120428UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_ALMOST_FULL_2 0x12042cUL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_ALMOST_FULL_3 0x120430UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_ALMOST_FULL_4 0x120434UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_ALMOST_FULL_5 0x120438UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_ALMOST_FULL_6 0x12043cUL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_ALMOST_FULL_7 0x120440UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_ALMOST_FULL_8 0x120444UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_ALMOST_FULL_9 0x120448UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_ALMOST_FULL_10 0x12044cUL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
#define PXP2_REG_RD_SR_MEMD_TM 0x120450UL //ACCESS:RW DataWidth:0x5 Description: TM bits of rd_sr_memd memory. Not used in E65. Increased to 5 bits in E3.
#define PXP2_REG_RD_TETRIS0_TMA 0x120454UL //ACCESS:RW DataWidth:0x5 Description: TM bits of Tetris Buffer memory. Increased to 5 bits in E3.
#define PXP2_REG_RD_TETRIS0_TMB 0x120458UL //ACCESS:RW DataWidth:0x5 Description: TM bits of Tetris Buffer memory. Increased to 5 bits in E3.
#define PXP2_REG_RD_TETRIS1_TMA 0x12045cUL //ACCESS:RW DataWidth:0x5 Description: TM bits of Tetris Buffer memory. Increased to 5 bits in E3.
#define PXP2_REG_RD_TETRIS1_TMB 0x120460UL //ACCESS:RW DataWidth:0x5 Description: TM bits of Tetris Buffer memory. Increased to 5 bits in E3.
#define PXP2_REG_RD_TETRIS2_TMA 0x120464UL //ACCESS:RW DataWidth:0x5 Description: TM bits of Tetris Buffer memory. Increased to 5 bits in E3.
#define PXP2_REG_RD_TETRIS2_TMB 0x120468UL //ACCESS:RW DataWidth:0x5 Description: TM bits of Tetris Buffer memory. Increased to 5 bits in E3.
#define PXP2_REG_RD_TETRIS3_TMA 0x12046cUL //ACCESS:RW DataWidth:0x5 Description: TM bits of Tetris Buffer memory. Increased to 5 bits in E3.
#define PXP2_REG_RD_TETRIS3_TMB 0x120470UL //ACCESS:RW DataWidth:0x5 Description: TM bits of Tetris Buffer memory. Increased to 5 bits in E3.
#define PXP2_REG_HST_DISABLE_INPUTS_PCI 0x120474UL //ACCESS:RW DataWidth:0x1 Description: Debug only: When '1'; inputs to the PSWHST block in clk_pci domain are ignored
#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478UL //ACCESS:R DataWidth:0x7 Description: Debug only: Number of used entries in the header FIFO
#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047cUL //ACCESS:R DataWidth:0x7 Description: Debug only: Number of used entries in the data FIFO
#define PXP2_REG_DBGSYN_ALMOST_FULL_THR 0x120480UL //ACCESS:RW DataWidth:0x4 Description: Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
#define PXP2_REG_DBG_SELECT 0x120484UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PXP2 to the DBG block) - for selecting a line to output to the DBG block.
#define PXP2_REG_DBG_BYTE_ENABLE 0x120488UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PXP2 to the DBG block) - for enabling bytes in the selected line (after the select and before the shift)
#define PXP2_REG_DBG_SHIFT 0x12048cUL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from PXP2 to the DBG block) - for circular right shifting of the selected line (after the enabling)
#define PXP2_REG_PGL_CONTROL0 0x120490UL //ACCESS:RW DataWidth:0x1a Multi Field Register
#define PXP2_PGL_CONTROL0_REG_PGL_CPL_AFT (0x7f<<0)
#define PXP2_PGL_CONTROL0_REG_PGL_CPL_AFT_SIZE 0
#define PXP2_PGL_CONTROL0_REG_PGL_DISABLE_INPUTS (0x1<<7)
#define PXP2_PGL_CONTROL0_REG_PGL_DISABLE_INPUTS_SIZE 7
#define PXP2_PGL_CONTROL0_REG_PGL_L2P_SWAP_MODE (0x3<<8)
#define PXP2_PGL_CONTROL0_REG_PGL_L2P_SWAP_MODE_SIZE 8
#define PXP2_PGL_CONTROL0_REG_PGL_TXW_TAG (0x1f<<10)
#define PXP2_PGL_CONTROL0_REG_PGL_TXW_TAG_SIZE 10
#define PXP2_PGL_CONTROL0_REG_PGL_TXW_CC_THRESH (0x1f<<15)
#define PXP2_PGL_CONTROL0_REG_PGL_TXW_CC_THRESH_SIZE 15
#define PXP2_PGL_CONTROL0_REG_PGL_TXW_DP_AFT (0x3f<<20)
#define PXP2_PGL_CONTROL0_REG_PGL_TXW_DP_AFT_SIZE 20
#define PXP2_REG_PGL_INT_TSDM_0 0x120494UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for TSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_TSDM_1 0x120498UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for TSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_TSDM_2 0x12049cUL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for TSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_TSDM_3 0x1204a0UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for TSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_TSDM_4 0x1204a4UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for TSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_TSDM_5 0x1204a8UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for TSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_TSDM_6 0x1204acUL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for TSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_TSDM_7 0x1204b0UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for TSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_USDM_0 0x1204b4UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for USDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_USDM_1 0x1204b8UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for USDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_USDM_2 0x1204bcUL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for USDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_USDM_3 0x1204c0UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for USDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_USDM_4 0x1204c4UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for USDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_USDM_5 0x1204c8UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for USDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_USDM_6 0x1204ccUL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for USDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_USDM_7 0x1204d0UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for USDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_XSDM_0 0x1204d4UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for XSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_XSDM_1 0x1204d8UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for XSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_XSDM_2 0x1204dcUL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for XSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_XSDM_3 0x1204e0UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for XSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_XSDM_4 0x1204e4UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for XSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_XSDM_5 0x1204e8UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for XSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_XSDM_6 0x1204ecUL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for XSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_XSDM_7 0x1204f0UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for XSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for CSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_CSDM_1 0x1204f8UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for CSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_CSDM_2 0x1204fcUL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for CSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_CSDM_3 0x120500UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for CSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_CSDM_4 0x120504UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for CSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_CSDM_5 0x120508UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for CSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_CSDM_6 0x12050cUL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for CSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_INT_CSDM_7 0x120510UL //ACCESS:RW DataWidth:0x20 Description: Legacy (type B) PF inbound interrupt table for CSDM: bits[31:16]-mask;bits[15:0]-address. Bits [1:0] must be zero (DW resolution address).
#define PXP2_REG_PGL_CONTROL1 0x120514UL //ACCESS:RW DataWidth:0xe Multi Field Register
#define PXP2_PGL_CONTROL1_REG_PGL_TGTWR_MLENGTH (0x3ff<<0)
#define PXP2_PGL_CONTROL1_REG_PGL_TGTWR_MLENGTH_SIZE 0
#define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_TSDM (0x1<<10)
#define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_TSDM_SIZE 10
#define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_USDM (0x1<<11)
#define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_USDM_SIZE 11
#define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_XSDM (0x1<<12)
#define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_XSDM_SIZE 12
#define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_CSDM (0x1<<13)
#define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_CSDM_SIZE 13
#define PXP2_REG_PGL_DQ_PREFIX2 0x120518UL //ACCESS:RW DataWidth:0x20 Description: debug only
#define PXP2_REG_PGL_PCIE_REPLAY_TM 0x12051cUL //ACCESS:RW DataWidth:0x5 Description: TM bits of pcie replay memory. Increased to 5 bits in E3.
#define PXP2_REG_PGL_DEBUG 0x120520UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define PXP2_PGL_DEBUG_REG_PGL_TXR_RELAX (0x1<<0)
#define PXP2_PGL_DEBUG_REG_PGL_TXR_RELAX_SIZE 0
#define PXP2_PGL_DEBUG_REG_PGL_TXW_RELAX (0x1<<1)
#define PXP2_PGL_DEBUG_REG_PGL_TXW_RELAX_SIZE 1
#define PXP2_PGL_DEBUG_REG_PGL_DISABLE (0x1<<2)
#define PXP2_PGL_DEBUG_REG_PGL_DISABLE_SIZE 2
#define PXP2_REG_PGL_PCIE 0x120524UL //ACCESS:RW DataWidth:0x8 Multi Field Register
#define PXP2_PGL_PCIE_REG_PGL_BAR1_SIZE (0xf<<0)
#define PXP2_PGL_PCIE_REG_PGL_BAR1_SIZE_SIZE 0
#define PXP2_PGL_PCIE_REG_PGL_BAR2_SIZE (0xf<<4)
#define PXP2_PGL_PCIE_REG_PGL_BAR2_SIZE_SIZE 4
#define PXP2_REG_PGL_TXR_CDTS 0x120528UL //ACCESS:R DataWidth:0x9 Description: debug only
#define PXP2_REG_PGL_TXW_CDTS 0x12052cUL //ACCESS:R DataWidth:0x15 Description: debug only
#define PXP2_REG_PGL_MOT 0x120530UL //ACCESS:R DataWidth:0x6 Description: debug only
#define PXP2_REG_PGL_EXP_ROM_ADDR 0x120554UL //ACCESS:R DataWidth:0x18 Description: the address to be read from expansion rom (address is in bytes according to read packet from host)
#define PXP2_REG_PGL_EXP_ROM_SIZE 0x120558UL //ACCESS:R DataWidth:0x2 Description: the size in dwords to be read from expansion rom (according to read packet from host)
#define PXP2_REG_PGL_CORE_DEBUG 0x12055cUL //ACCESS:RW DataWidth:0xb Multi Field Register
#define PXP2_PGL_CORE_DEBUG_REG_PGL_1US_DISABLE (0x1<<0)
#define PXP2_PGL_CORE_DEBUG_REG_PGL_1US_DISABLE_SIZE 0
#define PXP2_PGL_CORE_DEBUG_REG_PGL_CORE_DEBUG_SEL_1 (0xf<<1)
#define PXP2_PGL_CORE_DEBUG_REG_PGL_CORE_DEBUG_SEL_1_SIZE 1
#define PXP2_PGL_CORE_DEBUG_REG_PGL_CORE_DEBUG_SEL_2 (0xf<<5)
#define PXP2_PGL_CORE_DEBUG_REG_PGL_CORE_DEBUG_SEL_2_SIZE 5
#define PXP2_PGL_CORE_DEBUG_REG_PGL_PARITY_MODE (0x1<<9)
#define PXP2_PGL_CORE_DEBUG_REG_PGL_PARITY_MODE_SIZE 9
#define PXP2_PGL_CORE_DEBUG_REG_PGL_TXARB_SP (0x1<<10)
#define PXP2_PGL_CORE_DEBUG_REG_PGL_TXARB_SP_SIZE 10
#define PXP2_REG_PGL_PM_STATUS 0x120560UL //ACCESS:R DataWidth:0x6 Description: this field provides the following debug information: {Link_L23;pm_state1[1:0];pm_state0[1:0]
#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564UL //ACCESS:R DataWidth:0x1 Description: this bit indicates that a write request was blocked because of bus_master_en was deasserted
#define PXP2_REG_PGL_READ_BLOCKED 0x120568UL //ACCESS:R DataWidth:0x1 Description: this bit indicates that a read request was blocked because of bus_master_en was deasserted
#define PXP2_REG_PXP2_INT_STS_0 0x12056cUL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define PXP2_PXP2_INT_STS_0_REG_RQ_L2P_FIFO_OVERFLOW (0x1<<1)
#define PXP2_PXP2_INT_STS_0_REG_RQ_L2P_FIFO_OVERFLOW_SIZE 1
#define PXP2_PXP2_INT_STS_0_REG_RQ_WDFIFO_OVERFLOW (0x1<<2)
#define PXP2_PXP2_INT_STS_0_REG_RQ_WDFIFO_OVERFLOW_SIZE 2
#define PXP2_PXP2_INT_STS_0_REG_RQ_PHYADDR_FIFO_OF (0x1<<3)
#define PXP2_PXP2_INT_STS_0_REG_RQ_PHYADDR_FIFO_OF_SIZE 3
#define PXP2_PXP2_INT_STS_0_REG_RQ_L2P_VIOLATION_1 (0x1<<4)
#define PXP2_PXP2_INT_STS_0_REG_RQ_L2P_VIOLATION_1_SIZE 4
#define PXP2_PXP2_INT_STS_0_REG_RQ_L2P_VIOLATION_2 (0x1<<5)
#define PXP2_PXP2_INT_STS_0_REG_RQ_L2P_VIOLATION_2_SIZE 5
#define PXP2_PXP2_INT_STS_0_REG_RQ_FREE_LIST_EMPTY (0x1<<6)
#define PXP2_PXP2_INT_STS_0_REG_RQ_FREE_LIST_EMPTY_SIZE 6
#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR_SIZE 7
#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_UNDERFLOW (0x1<<8)
#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_UNDERFLOW_SIZE 8
#define PXP2_PXP2_INT_STS_0_REG_RD_SR_FIFO_ERROR (0x1<<9)
#define PXP2_PXP2_INT_STS_0_REG_RD_SR_FIFO_ERROR_SIZE 9
#define PXP2_PXP2_INT_STS_0_REG_RD_BLK_FIFO_ERROR (0x1<<10)
#define PXP2_PXP2_INT_STS_0_REG_RD_BLK_FIFO_ERROR_SIZE 10
#define PXP2_PXP2_INT_STS_0_REG_RD_PUSH_ERROR (0x1<<11)
#define PXP2_PXP2_INT_STS_0_REG_RD_PUSH_ERROR_SIZE 11
#define PXP2_PXP2_INT_STS_0_REG_RD_PUSH_PBF_ERROR (0x1<<12)
#define PXP2_PXP2_INT_STS_0_REG_RD_PUSH_PBF_ERROR_SIZE 12
#define PXP2_PXP2_INT_STS_0_REG_RD_COMPLETION_ERR (0x1<<13)
#define PXP2_PXP2_INT_STS_0_REG_RD_COMPLETION_ERR_SIZE 13
#define PXP2_PXP2_INT_STS_0_REG_HST_HEADER_FIFO_ERR (0x1<<14)
#define PXP2_PXP2_INT_STS_0_REG_HST_HEADER_FIFO_ERR_SIZE 14
#define PXP2_PXP2_INT_STS_0_REG_HST_DATA_FIFO_ERR (0x1<<15)
#define PXP2_PXP2_INT_STS_0_REG_HST_DATA_FIFO_ERR_SIZE 15
#define PXP2_PXP2_INT_STS_0_REG_HST_CPL_FIFO_ERR (0x1<<16)
#define PXP2_PXP2_INT_STS_0_REG_HST_CPL_FIFO_ERR_SIZE 16
#define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_ERR (0x1<<17)
#define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_ERR_SIZE 17
#define PXP2_PXP2_INT_STS_0_REG_PGL_TXW_OF (0x1<<18)
#define PXP2_PXP2_INT_STS_0_REG_PGL_TXW_OF_SIZE 18
#define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_AFT (0x1<<19)
#define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_AFT_SIZE 19
#define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_OF (0x1<<20)
#define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_OF_SIZE 20
#define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_ECRC (0x1<<21)
#define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_ECRC_SIZE 21
#define PXP2_PXP2_INT_STS_0_REG_PGL_PCIE_ATTN (0x1<<22)
#define PXP2_PXP2_INT_STS_0_REG_PGL_PCIE_ATTN_SIZE 22
#define PXP2_PXP2_INT_STS_0_REG_PGL_READ_BLOCKED (0x1<<23)
#define PXP2_PXP2_INT_STS_0_REG_PGL_READ_BLOCKED_SIZE 23
#define PXP2_PXP2_INT_STS_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
#define PXP2_PXP2_INT_STS_0_REG_PGL_WRITE_BLOCKED_SIZE 24
#define PXP2_PXP2_INT_STS_0_REG_WR_TM_UNDERFLOW (0x1<<25)
#define PXP2_PXP2_INT_STS_0_REG_WR_TM_UNDERFLOW_SIZE 25
#define PXP2_PXP2_INT_STS_0_REG_WR_QM_UNDERFLOW (0x1<<26)
#define PXP2_PXP2_INT_STS_0_REG_WR_QM_UNDERFLOW_SIZE 26
#define PXP2_PXP2_INT_STS_0_REG_WR_SRC_UNDERFLOW (0x1<<27)
#define PXP2_PXP2_INT_STS_0_REG_WR_SRC_UNDERFLOW_SIZE 27
#define PXP2_PXP2_INT_STS_0_REG_WR_USDM_UNDERFLOW (0x1<<28)
#define PXP2_PXP2_INT_STS_0_REG_WR_USDM_UNDERFLOW_SIZE 28
#define PXP2_PXP2_INT_STS_0_REG_WR_TSDM_UNDERFLOW (0x1<<29)
#define PXP2_PXP2_INT_STS_0_REG_WR_TSDM_UNDERFLOW_SIZE 29
#define PXP2_PXP2_INT_STS_0_REG_WR_CSDM_UNDERFLOW (0x1<<30)
#define PXP2_PXP2_INT_STS_0_REG_WR_CSDM_UNDERFLOW_SIZE 30
#define PXP2_PXP2_INT_STS_0_REG_WR_XSDM_UNDERFLOW (0x1<<31)
#define PXP2_PXP2_INT_STS_0_REG_WR_XSDM_UNDERFLOW_SIZE 31
#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570UL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_L2P_FIFO_OVERFLOW (0x1<<1)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_L2P_FIFO_OVERFLOW_SIZE 1
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_WDFIFO_OVERFLOW (0x1<<2)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_WDFIFO_OVERFLOW_SIZE 2
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_PHYADDR_FIFO_OF (0x1<<3)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_PHYADDR_FIFO_OF_SIZE 3
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_L2P_VIOLATION_1 (0x1<<4)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_L2P_VIOLATION_1_SIZE 4
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_L2P_VIOLATION_2 (0x1<<5)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_L2P_VIOLATION_2_SIZE 5
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_FREE_LIST_EMPTY (0x1<<6)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_FREE_LIST_EMPTY_SIZE 6
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR_SIZE 7
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_UNDERFLOW (0x1<<8)
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_UNDERFLOW_SIZE 8
#define PXP2_PXP2_INT_STS_CLR_0_REG_RD_SR_FIFO_ERROR (0x1<<9)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RD_SR_FIFO_ERROR_SIZE 9
#define PXP2_PXP2_INT_STS_CLR_0_REG_RD_BLK_FIFO_ERROR (0x1<<10)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RD_BLK_FIFO_ERROR_SIZE 10
#define PXP2_PXP2_INT_STS_CLR_0_REG_RD_PUSH_ERROR (0x1<<11)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RD_PUSH_ERROR_SIZE 11
#define PXP2_PXP2_INT_STS_CLR_0_REG_RD_PUSH_PBF_ERROR (0x1<<12)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RD_PUSH_PBF_ERROR_SIZE 12
#define PXP2_PXP2_INT_STS_CLR_0_REG_RD_COMPLETION_ERR (0x1<<13)
#define PXP2_PXP2_INT_STS_CLR_0_REG_RD_COMPLETION_ERR_SIZE 13
#define PXP2_PXP2_INT_STS_CLR_0_REG_HST_HEADER_FIFO_ERR (0x1<<14)
#define PXP2_PXP2_INT_STS_CLR_0_REG_HST_HEADER_FIFO_ERR_SIZE 14
#define PXP2_PXP2_INT_STS_CLR_0_REG_HST_DATA_FIFO_ERR (0x1<<15)
#define PXP2_PXP2_INT_STS_CLR_0_REG_HST_DATA_FIFO_ERR_SIZE 15
#define PXP2_PXP2_INT_STS_CLR_0_REG_HST_CPL_FIFO_ERR (0x1<<16)
#define PXP2_PXP2_INT_STS_CLR_0_REG_HST_CPL_FIFO_ERR_SIZE 16
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_ERR (0x1<<17)
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_ERR_SIZE 17
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_TXW_OF (0x1<<18)
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_TXW_OF_SIZE 18
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_AFT (0x1<<19)
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_AFT_SIZE 19
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_OF (0x1<<20)
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_OF_SIZE 20
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_ECRC (0x1<<21)
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_ECRC_SIZE 21
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_PCIE_ATTN (0x1<<22)
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_PCIE_ATTN_SIZE 22
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_READ_BLOCKED (0x1<<23)
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_READ_BLOCKED_SIZE 23
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
#define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_WRITE_BLOCKED_SIZE 24
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_TM_UNDERFLOW (0x1<<25)
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_TM_UNDERFLOW_SIZE 25
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_QM_UNDERFLOW (0x1<<26)
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_QM_UNDERFLOW_SIZE 26
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_SRC_UNDERFLOW (0x1<<27)
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_SRC_UNDERFLOW_SIZE 27
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_USDM_UNDERFLOW (0x1<<28)
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_USDM_UNDERFLOW_SIZE 28
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_TSDM_UNDERFLOW (0x1<<29)
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_TSDM_UNDERFLOW_SIZE 29
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_CSDM_UNDERFLOW (0x1<<30)
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_CSDM_UNDERFLOW_SIZE 30
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_XSDM_UNDERFLOW (0x1<<31)
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_XSDM_UNDERFLOW_SIZE 31
#define PXP2_REG_PXP2_INT_STS_WR_0 0x120574UL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_L2P_FIFO_OVERFLOW (0x1<<1)
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_L2P_FIFO_OVERFLOW_SIZE 1
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_WDFIFO_OVERFLOW (0x1<<2)
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_WDFIFO_OVERFLOW_SIZE 2
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_PHYADDR_FIFO_OF (0x1<<3)
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_PHYADDR_FIFO_OF_SIZE 3
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_L2P_VIOLATION_1 (0x1<<4)
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_L2P_VIOLATION_1_SIZE 4
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_L2P_VIOLATION_2 (0x1<<5)
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_L2P_VIOLATION_2_SIZE 5
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_FREE_LIST_EMPTY (0x1<<6)
#define PXP2_PXP2_INT_STS_WR_0_REG_RQ_FREE_LIST_EMPTY_SIZE 6
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_PGLUE_EOP_ERROR_SIZE 7
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_PGLUE_UNDERFLOW (0x1<<8)
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_PGLUE_UNDERFLOW_SIZE 8
#define PXP2_PXP2_INT_STS_WR_0_REG_RD_SR_FIFO_ERROR (0x1<<9)
#define PXP2_PXP2_INT_STS_WR_0_REG_RD_SR_FIFO_ERROR_SIZE 9
#define PXP2_PXP2_INT_STS_WR_0_REG_RD_BLK_FIFO_ERROR (0x1<<10)
#define PXP2_PXP2_INT_STS_WR_0_REG_RD_BLK_FIFO_ERROR_SIZE 10
#define PXP2_PXP2_INT_STS_WR_0_REG_RD_PUSH_ERROR (0x1<<11)
#define PXP2_PXP2_INT_STS_WR_0_REG_RD_PUSH_ERROR_SIZE 11
#define PXP2_PXP2_INT_STS_WR_0_REG_RD_PUSH_PBF_ERROR (0x1<<12)
#define PXP2_PXP2_INT_STS_WR_0_REG_RD_PUSH_PBF_ERROR_SIZE 12
#define PXP2_PXP2_INT_STS_WR_0_REG_RD_COMPLETION_ERR (0x1<<13)
#define PXP2_PXP2_INT_STS_WR_0_REG_RD_COMPLETION_ERR_SIZE 13
#define PXP2_PXP2_INT_STS_WR_0_REG_HST_HEADER_FIFO_ERR (0x1<<14)
#define PXP2_PXP2_INT_STS_WR_0_REG_HST_HEADER_FIFO_ERR_SIZE 14
#define PXP2_PXP2_INT_STS_WR_0_REG_HST_DATA_FIFO_ERR (0x1<<15)
#define PXP2_PXP2_INT_STS_WR_0_REG_HST_DATA_FIFO_ERR_SIZE 15
#define PXP2_PXP2_INT_STS_WR_0_REG_HST_CPL_FIFO_ERR (0x1<<16)
#define PXP2_PXP2_INT_STS_WR_0_REG_HST_CPL_FIFO_ERR_SIZE 16
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_ERR (0x1<<17)
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_ERR_SIZE 17
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_TXW_OF (0x1<<18)
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_TXW_OF_SIZE 18
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_AFT (0x1<<19)
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_AFT_SIZE 19
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_OF (0x1<<20)
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_OF_SIZE 20
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_ECRC (0x1<<21)
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_ECRC_SIZE 21
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_PCIE_ATTN (0x1<<22)
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_PCIE_ATTN_SIZE 22
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_READ_BLOCKED (0x1<<23)
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_READ_BLOCKED_SIZE 23
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
#define PXP2_PXP2_INT_STS_WR_0_REG_PGL_WRITE_BLOCKED_SIZE 24
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_TM_UNDERFLOW (0x1<<25)
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_TM_UNDERFLOW_SIZE 25
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_QM_UNDERFLOW (0x1<<26)
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_QM_UNDERFLOW_SIZE 26
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_SRC_UNDERFLOW (0x1<<27)
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_SRC_UNDERFLOW_SIZE 27
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_USDM_UNDERFLOW (0x1<<28)
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_USDM_UNDERFLOW_SIZE 28
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_TSDM_UNDERFLOW (0x1<<29)
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_TSDM_UNDERFLOW_SIZE 29
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_CSDM_UNDERFLOW (0x1<<30)
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_CSDM_UNDERFLOW_SIZE 30
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_XSDM_UNDERFLOW (0x1<<31)
#define PXP2_PXP2_INT_STS_WR_0_REG_WR_XSDM_UNDERFLOW_SIZE 31
#define PXP2_REG_PXP2_INT_MASK_0 0x120578UL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define PXP2_PXP2_INT_MASK_0_REG_RQ_L2P_FIFO_OVERFLOW (0x1<<1)
#define PXP2_PXP2_INT_MASK_0_REG_RQ_L2P_FIFO_OVERFLOW_SIZE 1
#define PXP2_PXP2_INT_MASK_0_REG_RQ_WDFIFO_OVERFLOW (0x1<<2)
#define PXP2_PXP2_INT_MASK_0_REG_RQ_WDFIFO_OVERFLOW_SIZE 2
#define PXP2_PXP2_INT_MASK_0_REG_RQ_PHYADDR_FIFO_OF (0x1<<3)
#define PXP2_PXP2_INT_MASK_0_REG_RQ_PHYADDR_FIFO_OF_SIZE 3
#define PXP2_PXP2_INT_MASK_0_REG_RQ_L2P_VIOLATION_1 (0x1<<4)
#define PXP2_PXP2_INT_MASK_0_REG_RQ_L2P_VIOLATION_1_SIZE 4
#define PXP2_PXP2_INT_MASK_0_REG_RQ_L2P_VIOLATION_2 (0x1<<5)
#define PXP2_PXP2_INT_MASK_0_REG_RQ_L2P_VIOLATION_2_SIZE 5
#define PXP2_PXP2_INT_MASK_0_REG_RQ_FREE_LIST_EMPTY (0x1<<6)
#define PXP2_PXP2_INT_MASK_0_REG_RQ_FREE_LIST_EMPTY_SIZE 6
#define PXP2_PXP2_INT_MASK_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
#define PXP2_PXP2_INT_MASK_0_REG_WR_PGLUE_EOP_ERROR_SIZE 7
#define PXP2_PXP2_INT_MASK_0_REG_WR_PGLUE_UNDERFLOW (0x1<<8)
#define PXP2_PXP2_INT_MASK_0_REG_WR_PGLUE_UNDERFLOW_SIZE 8
#define PXP2_PXP2_INT_MASK_0_REG_RD_SR_FIFO_ERROR (0x1<<9)
#define PXP2_PXP2_INT_MASK_0_REG_RD_SR_FIFO_ERROR_SIZE 9
#define PXP2_PXP2_INT_MASK_0_REG_RD_BLK_FIFO_ERROR (0x1<<10)
#define PXP2_PXP2_INT_MASK_0_REG_RD_BLK_FIFO_ERROR_SIZE 10
#define PXP2_PXP2_INT_MASK_0_REG_RD_PUSH_ERROR (0x1<<11)
#define PXP2_PXP2_INT_MASK_0_REG_RD_PUSH_ERROR_SIZE 11
#define PXP2_PXP2_INT_MASK_0_REG_RD_PUSH_PBF_ERROR (0x1<<12)
#define PXP2_PXP2_INT_MASK_0_REG_RD_PUSH_PBF_ERROR_SIZE 12
#define PXP2_PXP2_INT_MASK_0_REG_RD_COMPLETION_ERR (0x1<<13)
#define PXP2_PXP2_INT_MASK_0_REG_RD_COMPLETION_ERR_SIZE 13
#define PXP2_PXP2_INT_MASK_0_REG_HST_HEADER_FIFO_ERR (0x1<<14)
#define PXP2_PXP2_INT_MASK_0_REG_HST_HEADER_FIFO_ERR_SIZE 14
#define PXP2_PXP2_INT_MASK_0_REG_HST_DATA_FIFO_ERR (0x1<<15)
#define PXP2_PXP2_INT_MASK_0_REG_HST_DATA_FIFO_ERR_SIZE 15
#define PXP2_PXP2_INT_MASK_0_REG_HST_CPL_FIFO_ERR (0x1<<16)
#define PXP2_PXP2_INT_MASK_0_REG_HST_CPL_FIFO_ERR_SIZE 16
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_ERR (0x1<<17)
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_ERR_SIZE 17
#define PXP2_PXP2_INT_MASK_0_REG_PGL_TXW_OF (0x1<<18)
#define PXP2_PXP2_INT_MASK_0_REG_PGL_TXW_OF_SIZE 18
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT_SIZE 19
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF_SIZE 20
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_ECRC (0x1<<21)
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_ECRC_SIZE 21
#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN_SIZE 22
#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED_SIZE 23
#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED_SIZE 24
#define PXP2_PXP2_INT_MASK_0_REG_WR_TM_UNDERFLOW (0x1<<25)
#define PXP2_PXP2_INT_MASK_0_REG_WR_TM_UNDERFLOW_SIZE 25
#define PXP2_PXP2_INT_MASK_0_REG_WR_QM_UNDERFLOW (0x1<<26)
#define PXP2_PXP2_INT_MASK_0_REG_WR_QM_UNDERFLOW_SIZE 26
#define PXP2_PXP2_INT_MASK_0_REG_WR_SRC_UNDERFLOW (0x1<<27)
#define PXP2_PXP2_INT_MASK_0_REG_WR_SRC_UNDERFLOW_SIZE 27
#define PXP2_PXP2_INT_MASK_0_REG_WR_USDM_UNDERFLOW (0x1<<28)
#define PXP2_PXP2_INT_MASK_0_REG_WR_USDM_UNDERFLOW_SIZE 28
#define PXP2_PXP2_INT_MASK_0_REG_WR_TSDM_UNDERFLOW (0x1<<29)
#define PXP2_PXP2_INT_MASK_0_REG_WR_TSDM_UNDERFLOW_SIZE 29
#define PXP2_PXP2_INT_MASK_0_REG_WR_CSDM_UNDERFLOW (0x1<<30)
#define PXP2_PXP2_INT_MASK_0_REG_WR_CSDM_UNDERFLOW_SIZE 30
#define PXP2_PXP2_INT_MASK_0_REG_WR_XSDM_UNDERFLOW (0x1<<31)
#define PXP2_PXP2_INT_MASK_0_REG_WR_XSDM_UNDERFLOW_SIZE 31
#define PXP2_REG_PXP2_PRTY_STS_0 0x12057cUL //ACCESS:R DataWidth:0x20 Description: Parity register #0 read
#define PXP2_PXP2_PRTY_STS_0_REG_PARITY (0x1<<0)
#define PXP2_PXP2_PRTY_STS_0_REG_PARITY_SIZE 0
#define PXP2_PXP2_PRTY_STS_0_REG_RQ_CXR_PARITY_ERR (0x1<<1)
#define PXP2_PXP2_PRTY_STS_0_REG_RQ_CXR_PARITY_ERR_SIZE 1
#define PXP2_PXP2_PRTY_STS_0_REG_RQ_HOQ_PARITY_ERR (0x1<<2)
#define PXP2_PXP2_PRTY_STS_0_REG_RQ_HOQ_PARITY_ERR_SIZE 2
#define PXP2_PXP2_PRTY_STS_0_REG_RQ_UFIFO_PARITY_ERR (0x1<<3)
#define PXP2_PXP2_PRTY_STS_0_REG_RQ_UFIFO_PARITY_ERR_SIZE 3
#define PXP2_PXP2_PRTY_STS_0_REG_RQ_ONCHIP_PARITY_ERR (0x1<<4)
#define PXP2_PXP2_PRTY_STS_0_REG_RQ_ONCHIP_PARITY_ERR_SIZE 4
#define PXP2_PXP2_PRTY_STS_0_REG_RQ_OFFCHIP_PARITY_ERR (0x1<<5)
#define PXP2_PXP2_PRTY_STS_0_REG_RQ_OFFCHIP_PARITY_ERR_SIZE 5
#define PXP2_PXP2_PRTY_STS_0_REG_WR_SRC_FIFO_PRTY (0x1<<6)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_SRC_FIFO_PRTY_SIZE 6
#define PXP2_PXP2_PRTY_STS_0_REG_WR_QM_FIFO_PRTY (0x1<<7)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_QM_FIFO_PRTY_SIZE 7
#define PXP2_PXP2_PRTY_STS_0_REG_WR_TM_FIFO_PRTY (0x1<<8)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_TM_FIFO_PRTY_SIZE 8
#define PXP2_PXP2_PRTY_STS_0_REG_WR_USDM_FIFO_PRTY (0x1<<9)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_USDM_FIFO_PRTY_SIZE 9
#define PXP2_PXP2_PRTY_STS_0_REG_WR_USDMDP_FIFO_PRTY (0x1<<10)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_USDMDP_FIFO_PRTY_SIZE 10
#define PXP2_PXP2_PRTY_STS_0_REG_WR_XSDM_FIFO_PRTY (0x1<<11)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_XSDM_FIFO_PRTY_SIZE 11
#define PXP2_PXP2_PRTY_STS_0_REG_WR_TSDM_FIFO_PRTY (0x1<<12)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_TSDM_FIFO_PRTY_SIZE 12
#define PXP2_PXP2_PRTY_STS_0_REG_WR_CSDM_FIFO_PRTY (0x1<<13)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_CSDM_FIFO_PRTY_SIZE 13
#define PXP2_PXP2_PRTY_STS_0_REG_WR_CDUWR_FIFO_PRTY (0x1<<14)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_CDUWR_FIFO_PRTY_SIZE 14
#define PXP2_PXP2_PRTY_STS_0_REG_WR_DMAE_FIFO_PRTY (0x1<<15)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_DMAE_FIFO_PRTY_SIZE 15
#define PXP2_PXP2_PRTY_STS_0_REG_WR_DBG_FIFO_PRTY (0x1<<16)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_DBG_FIFO_PRTY_SIZE 16
#define PXP2_PXP2_PRTY_STS_0_REG_WR_HC_FIFO_PRTY (0x1<<17)
#define PXP2_PXP2_PRTY_STS_0_REG_WR_HC_FIFO_PRTY_SIZE 17
#define PXP2_PXP2_PRTY_STS_0_REG_RD_VQ_HEAD (0x1<<18)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_VQ_HEAD_SIZE 18
#define PXP2_PXP2_PRTY_STS_0_REG_RD_SR_COMPLETION (0x1<<19)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_SR_COMPLETION_SIZE 19
#define PXP2_PXP2_PRTY_STS_0_REG_RD_COMP_CTX (0x1<<20)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_COMP_CTX_SIZE 20
#define PXP2_PXP2_PRTY_STS_0_REG_RD_SR_DELIVERY1 (0x1<<21)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_SR_DELIVERY1_SIZE 21
#define PXP2_PXP2_PRTY_STS_0_REG_RD_SR_DELIVERY2 (0x1<<22)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_SR_DELIVERY2_SIZE 22
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER1 (0x1<<23)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER1_SIZE 23
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER2 (0x1<<24)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER2_SIZE 24
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER3 (0x1<<25)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER3_SIZE 25
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER4 (0x1<<26)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER4_SIZE 26
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER5 (0x1<<27)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER5_SIZE 27
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER6 (0x1<<28)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER6_SIZE 28
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER7 (0x1<<29)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER7_SIZE 29
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER8 (0x1<<30)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER8_SIZE 30
#define PXP2_PXP2_PRTY_STS_0_REG_RD_FIRST_BLK (0x1<<31)
#define PXP2_PXP2_PRTY_STS_0_REG_RD_FIRST_BLK_SIZE 31
#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580UL //ACCESS:RC DataWidth:0x20 Description: Parity register #0 read clear
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_PARITY_SIZE 0
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_CXR_PARITY_ERR (0x1<<1)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_CXR_PARITY_ERR_SIZE 1
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_HOQ_PARITY_ERR (0x1<<2)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_HOQ_PARITY_ERR_SIZE 2
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_UFIFO_PARITY_ERR (0x1<<3)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_UFIFO_PARITY_ERR_SIZE 3
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_ONCHIP_PARITY_ERR (0x1<<4)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_ONCHIP_PARITY_ERR_SIZE 4
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_OFFCHIP_PARITY_ERR (0x1<<5)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_OFFCHIP_PARITY_ERR_SIZE 5
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_SRC_FIFO_PRTY (0x1<<6)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_SRC_FIFO_PRTY_SIZE 6
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_QM_FIFO_PRTY (0x1<<7)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_QM_FIFO_PRTY_SIZE 7
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_TM_FIFO_PRTY (0x1<<8)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_TM_FIFO_PRTY_SIZE 8
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_USDM_FIFO_PRTY (0x1<<9)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_USDM_FIFO_PRTY_SIZE 9
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_USDMDP_FIFO_PRTY (0x1<<10)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_USDMDP_FIFO_PRTY_SIZE 10
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_XSDM_FIFO_PRTY (0x1<<11)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_XSDM_FIFO_PRTY_SIZE 11
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_TSDM_FIFO_PRTY (0x1<<12)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_TSDM_FIFO_PRTY_SIZE 12
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_CSDM_FIFO_PRTY (0x1<<13)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_CSDM_FIFO_PRTY_SIZE 13
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_CDUWR_FIFO_PRTY (0x1<<14)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_CDUWR_FIFO_PRTY_SIZE 14
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_DMAE_FIFO_PRTY (0x1<<15)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_DMAE_FIFO_PRTY_SIZE 15
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_DBG_FIFO_PRTY (0x1<<16)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_DBG_FIFO_PRTY_SIZE 16
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_HC_FIFO_PRTY (0x1<<17)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_HC_FIFO_PRTY_SIZE 17
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_VQ_HEAD (0x1<<18)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_VQ_HEAD_SIZE 18
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_SR_COMPLETION (0x1<<19)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_SR_COMPLETION_SIZE 19
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_COMP_CTX (0x1<<20)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_COMP_CTX_SIZE 20
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_SR_DELIVERY1 (0x1<<21)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_SR_DELIVERY1_SIZE 21
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_SR_DELIVERY2 (0x1<<22)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_SR_DELIVERY2_SIZE 22
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER1 (0x1<<23)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER1_SIZE 23
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER2 (0x1<<24)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER2_SIZE 24
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER3 (0x1<<25)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER3_SIZE 25
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER4 (0x1<<26)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER4_SIZE 26
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER5 (0x1<<27)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER5_SIZE 27
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER6 (0x1<<28)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER6_SIZE 28
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER7 (0x1<<29)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER7_SIZE 29
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER8 (0x1<<30)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER8_SIZE 30
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_FIRST_BLK (0x1<<31)
#define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_FIRST_BLK_SIZE 31
#define PXP2_REG_PXP2_PRTY_STS_WR_0 0x120584UL //ACCESS:WR DataWidth:0x20 Description: Parity register #0 bit set or clear
#define PXP2_PXP2_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_PARITY_SIZE 0
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_CXR_PARITY_ERR (0x1<<1)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_CXR_PARITY_ERR_SIZE 1
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_HOQ_PARITY_ERR (0x1<<2)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_HOQ_PARITY_ERR_SIZE 2
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_UFIFO_PARITY_ERR (0x1<<3)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_UFIFO_PARITY_ERR_SIZE 3
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_ONCHIP_PARITY_ERR (0x1<<4)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_ONCHIP_PARITY_ERR_SIZE 4
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_OFFCHIP_PARITY_ERR (0x1<<5)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_OFFCHIP_PARITY_ERR_SIZE 5
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_SRC_FIFO_PRTY (0x1<<6)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_SRC_FIFO_PRTY_SIZE 6
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_QM_FIFO_PRTY (0x1<<7)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_QM_FIFO_PRTY_SIZE 7
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_TM_FIFO_PRTY (0x1<<8)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_TM_FIFO_PRTY_SIZE 8
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_USDM_FIFO_PRTY (0x1<<9)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_USDM_FIFO_PRTY_SIZE 9
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_USDMDP_FIFO_PRTY (0x1<<10)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_USDMDP_FIFO_PRTY_SIZE 10
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_XSDM_FIFO_PRTY (0x1<<11)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_XSDM_FIFO_PRTY_SIZE 11
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_TSDM_FIFO_PRTY (0x1<<12)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_TSDM_FIFO_PRTY_SIZE 12
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_CSDM_FIFO_PRTY (0x1<<13)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_CSDM_FIFO_PRTY_SIZE 13
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_CDUWR_FIFO_PRTY (0x1<<14)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_CDUWR_FIFO_PRTY_SIZE 14
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_DMAE_FIFO_PRTY (0x1<<15)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_DMAE_FIFO_PRTY_SIZE 15
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_DBG_FIFO_PRTY (0x1<<16)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_DBG_FIFO_PRTY_SIZE 16
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_HC_FIFO_PRTY (0x1<<17)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_HC_FIFO_PRTY_SIZE 17
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_VQ_HEAD (0x1<<18)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_VQ_HEAD_SIZE 18
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_SR_COMPLETION (0x1<<19)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_SR_COMPLETION_SIZE 19
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_COMP_CTX (0x1<<20)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_COMP_CTX_SIZE 20
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_SR_DELIVERY1 (0x1<<21)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_SR_DELIVERY1_SIZE 21
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_SR_DELIVERY2 (0x1<<22)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_SR_DELIVERY2_SIZE 22
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER1 (0x1<<23)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER1_SIZE 23
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER2 (0x1<<24)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER2_SIZE 24
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER3 (0x1<<25)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER3_SIZE 25
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER4 (0x1<<26)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER4_SIZE 26
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER5 (0x1<<27)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER5_SIZE 27
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER6 (0x1<<28)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER6_SIZE 28
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER7 (0x1<<29)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER7_SIZE 29
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER8 (0x1<<30)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER8_SIZE 30
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_FIRST_BLK (0x1<<31)
#define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_FIRST_BLK_SIZE 31
#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588UL //ACCESS:RW DataWidth:0x20 Description: Parity mask register #0 read/write
#define PXP2_PXP2_PRTY_MASK_0_REG_PARITY (0x1<<0)
#define PXP2_PXP2_PRTY_MASK_0_REG_PARITY_SIZE 0
#define PXP2_PXP2_PRTY_MASK_0_REG_RQ_CXR_PARITY_ERR (0x1<<1)
#define PXP2_PXP2_PRTY_MASK_0_REG_RQ_CXR_PARITY_ERR_SIZE 1
#define PXP2_PXP2_PRTY_MASK_0_REG_RQ_HOQ_PARITY_ERR (0x1<<2)
#define PXP2_PXP2_PRTY_MASK_0_REG_RQ_HOQ_PARITY_ERR_SIZE 2
#define PXP2_PXP2_PRTY_MASK_0_REG_RQ_UFIFO_PARITY_ERR (0x1<<3)
#define PXP2_PXP2_PRTY_MASK_0_REG_RQ_UFIFO_PARITY_ERR_SIZE 3
#define PXP2_PXP2_PRTY_MASK_0_REG_RQ_ONCHIP_PARITY_ERR (0x1<<4)
#define PXP2_PXP2_PRTY_MASK_0_REG_RQ_ONCHIP_PARITY_ERR_SIZE 4
#define PXP2_PXP2_PRTY_MASK_0_REG_RQ_OFFCHIP_PARITY_ERR (0x1<<5)
#define PXP2_PXP2_PRTY_MASK_0_REG_RQ_OFFCHIP_PARITY_ERR_SIZE 5
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_SRC_FIFO_PRTY (0x1<<6)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_SRC_FIFO_PRTY_SIZE 6
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_QM_FIFO_PRTY (0x1<<7)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_QM_FIFO_PRTY_SIZE 7
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_TM_FIFO_PRTY (0x1<<8)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_TM_FIFO_PRTY_SIZE 8
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_USDM_FIFO_PRTY (0x1<<9)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_USDM_FIFO_PRTY_SIZE 9
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_USDMDP_FIFO_PRTY (0x1<<10)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_USDMDP_FIFO_PRTY_SIZE 10
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_XSDM_FIFO_PRTY (0x1<<11)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_XSDM_FIFO_PRTY_SIZE 11
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_TSDM_FIFO_PRTY (0x1<<12)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_TSDM_FIFO_PRTY_SIZE 12
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_CSDM_FIFO_PRTY (0x1<<13)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_CSDM_FIFO_PRTY_SIZE 13
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_CDUWR_FIFO_PRTY (0x1<<14)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_CDUWR_FIFO_PRTY_SIZE 14
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_DMAE_FIFO_PRTY (0x1<<15)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_DMAE_FIFO_PRTY_SIZE 15
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_DBG_FIFO_PRTY (0x1<<16)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_DBG_FIFO_PRTY_SIZE 16
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_HC_FIFO_PRTY (0x1<<17)
#define PXP2_PXP2_PRTY_MASK_0_REG_WR_HC_FIFO_PRTY_SIZE 17
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_VQ_HEAD (0x1<<18)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_VQ_HEAD_SIZE 18
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_SR_COMPLETION (0x1<<19)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_SR_COMPLETION_SIZE 19
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_COMP_CTX (0x1<<20)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_COMP_CTX_SIZE 20
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_SR_DELIVERY1 (0x1<<21)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_SR_DELIVERY1_SIZE 21
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_SR_DELIVERY2 (0x1<<22)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_SR_DELIVERY2_SIZE 22
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER1 (0x1<<23)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER1_SIZE 23
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER2 (0x1<<24)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER2_SIZE 24
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER3 (0x1<<25)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER3_SIZE 25
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER4 (0x1<<26)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER4_SIZE 26
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER5 (0x1<<27)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER5_SIZE 27
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER6 (0x1<<28)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER6_SIZE 28
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER7 (0x1<<29)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER7_SIZE 29
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER8 (0x1<<30)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER8_SIZE 30
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_FIRST_BLK (0x1<<31)
#define PXP2_PXP2_PRTY_MASK_0_REG_RD_FIRST_BLK_SIZE 31
#define PXP2_REG_PXP2_PRTY_STS_1 0x12058cUL //ACCESS:R DataWidth:0x19 Description: Parity register #1 read
#define PXP2_PXP2_PRTY_STS_1_REG_RD_NEXT_BLK_PTRS (0x1<<0)
#define PXP2_PXP2_PRTY_STS_1_REG_RD_NEXT_BLK_PTRS_SIZE 0
#define PXP2_PXP2_PRTY_STS_1_REG_RD_SR_FREE_LIST (0x1<<1)
#define PXP2_PXP2_PRTY_STS_1_REG_RD_SR_FREE_LIST_SIZE 1
#define PXP2_PXP2_PRTY_STS_1_REG_RD_BLOCK_FREE_LIST (0x1<<2)
#define PXP2_PXP2_PRTY_STS_1_REG_RD_BLOCK_FREE_LIST_SIZE 2
#define PXP2_PXP2_PRTY_STS_1_REG_HST_CPL_SYNC_FIFO (0x1<<3)
#define PXP2_PXP2_PRTY_STS_1_REG_HST_CPL_SYNC_FIFO_SIZE 3
#define PXP2_PXP2_PRTY_STS_1_REG_PGL_CPL (0x1<<4)
#define PXP2_PXP2_PRTY_STS_1_REG_PGL_CPL_SIZE 4
#define PXP2_PXP2_PRTY_STS_1_REG_PGL_TXW (0x1<<5)
#define PXP2_PXP2_PRTY_STS_1_REG_PGL_TXW_SIZE 5
#define PXP2_PXP2_PRTY_STS_1_REG_PGL_REPLAY (0x1<<6)
#define PXP2_PXP2_PRTY_STS_1_REG_PGL_REPLAY_SIZE 6
#define PXP2_PXP2_PRTY_STS_1_REG_RD_ATC_ENTRY_ID (0x1<<7)
#define PXP2_PXP2_PRTY_STS_1_REG_RD_ATC_ENTRY_ID_SIZE 7
#define PXP2_PXP2_PRTY_STS_1_REG_HST_IREQ_SYNC_FIFO (0x1<<8)
#define PXP2_PXP2_PRTY_STS_1_REG_HST_IREQ_SYNC_FIFO_SIZE 8
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_TREQ_FIFO_PARITY_ERR (0x1<<9)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_TREQ_FIFO_PARITY_ERR_SIZE 9
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_ICPL_FIFO_PARITY_ERR (0x1<<10)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_ICPL_FIFO_PARITY_ERR_SIZE 10
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_PBF_REQ_PARITY_ERR (0x1<<11)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_PBF_REQ_PARITY_ERR_SIZE 11
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_QM_REQ_PARITY_ERR (0x1<<12)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_QM_REQ_PARITY_ERR_SIZE 12
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_TM_REQ_PARITY_ERR (0x1<<13)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_TM_REQ_PARITY_ERR_SIZE 13
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_SRC_REQ_PARITY_ERR (0x1<<14)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_SRC_REQ_PARITY_ERR_SIZE 14
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_USDM_REQ_PARITY_ERR (0x1<<15)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_USDM_REQ_PARITY_ERR_SIZE 15
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_USDMDP_REQ_PARITY_ERR (0x1<<16)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_USDMDP_REQ_PARITY_ERR_SIZE 16
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_TSDM_REQ_PARITY_ERR (0x1<<17)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_TSDM_REQ_PARITY_ERR_SIZE 17
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_CSDM_REQ_PARITY_ERR (0x1<<18)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_CSDM_REQ_PARITY_ERR_SIZE 18
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_CDUWR_REQ_PARITY_ERR (0x1<<19)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_CDUWR_REQ_PARITY_ERR_SIZE 19
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_CDURD_REQ_PARITY_ERR (0x1<<20)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_CDURD_REQ_PARITY_ERR_SIZE 20
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_DMAE_REQ_PARITY_ERR (0x1<<21)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_DMAE_REQ_PARITY_ERR_SIZE 21
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_XSDM_REQ_PARITY_ERR (0x1<<22)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_XSDM_REQ_PARITY_ERR_SIZE 22
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_HC_REQ_PARITY_ERR (0x1<<23)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_HC_REQ_PARITY_ERR_SIZE 23
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_DBG_REQ_PARITY_ERR (0x1<<24)
#define PXP2_PXP2_PRTY_STS_1_REG_RQ_DBG_REQ_PARITY_ERR_SIZE 24
#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590UL //ACCESS:RC DataWidth:0x19 Description: Parity register #1 read clear
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_NEXT_BLK_PTRS (0x1<<0)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_NEXT_BLK_PTRS_SIZE 0
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_SR_FREE_LIST (0x1<<1)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_SR_FREE_LIST_SIZE 1
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_BLOCK_FREE_LIST (0x1<<2)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_BLOCK_FREE_LIST_SIZE 2
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_HST_CPL_SYNC_FIFO (0x1<<3)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_HST_CPL_SYNC_FIFO_SIZE 3
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_PGL_CPL (0x1<<4)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_PGL_CPL_SIZE 4
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_PGL_TXW (0x1<<5)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_PGL_TXW_SIZE 5
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_PGL_REPLAY (0x1<<6)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_PGL_REPLAY_SIZE 6
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_ATC_ENTRY_ID (0x1<<7)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_ATC_ENTRY_ID_SIZE 7
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_HST_IREQ_SYNC_FIFO (0x1<<8)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_HST_IREQ_SYNC_FIFO_SIZE 8
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_TREQ_FIFO_PARITY_ERR (0x1<<9)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_TREQ_FIFO_PARITY_ERR_SIZE 9
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_ICPL_FIFO_PARITY_ERR (0x1<<10)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_ICPL_FIFO_PARITY_ERR_SIZE 10
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_PBF_REQ_PARITY_ERR (0x1<<11)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_PBF_REQ_PARITY_ERR_SIZE 11
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_QM_REQ_PARITY_ERR (0x1<<12)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_QM_REQ_PARITY_ERR_SIZE 12
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_TM_REQ_PARITY_ERR (0x1<<13)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_TM_REQ_PARITY_ERR_SIZE 13
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_SRC_REQ_PARITY_ERR (0x1<<14)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_SRC_REQ_PARITY_ERR_SIZE 14
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_USDM_REQ_PARITY_ERR (0x1<<15)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_USDM_REQ_PARITY_ERR_SIZE 15
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_USDMDP_REQ_PARITY_ERR (0x1<<16)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_USDMDP_REQ_PARITY_ERR_SIZE 16
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_TSDM_REQ_PARITY_ERR (0x1<<17)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_TSDM_REQ_PARITY_ERR_SIZE 17
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_CSDM_REQ_PARITY_ERR (0x1<<18)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_CSDM_REQ_PARITY_ERR_SIZE 18
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_CDUWR_REQ_PARITY_ERR (0x1<<19)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_CDUWR_REQ_PARITY_ERR_SIZE 19
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_CDURD_REQ_PARITY_ERR (0x1<<20)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_CDURD_REQ_PARITY_ERR_SIZE 20
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_DMAE_REQ_PARITY_ERR (0x1<<21)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_DMAE_REQ_PARITY_ERR_SIZE 21
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_XSDM_REQ_PARITY_ERR (0x1<<22)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_XSDM_REQ_PARITY_ERR_SIZE 22
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_HC_REQ_PARITY_ERR (0x1<<23)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_HC_REQ_PARITY_ERR_SIZE 23
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_DBG_REQ_PARITY_ERR (0x1<<24)
#define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_DBG_REQ_PARITY_ERR_SIZE 24
#define PXP2_REG_PXP2_PRTY_STS_WR_1 0x120594UL //ACCESS:WR DataWidth:0x19 Description: Parity register #1 bit set or clear
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_NEXT_BLK_PTRS (0x1<<0)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_NEXT_BLK_PTRS_SIZE 0
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_SR_FREE_LIST (0x1<<1)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_SR_FREE_LIST_SIZE 1
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_BLOCK_FREE_LIST (0x1<<2)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_BLOCK_FREE_LIST_SIZE 2
#define PXP2_PXP2_PRTY_STS_WR_1_REG_HST_CPL_SYNC_FIFO (0x1<<3)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_HST_CPL_SYNC_FIFO_SIZE 3
#define PXP2_PXP2_PRTY_STS_WR_1_REG_PGL_CPL (0x1<<4)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_PGL_CPL_SIZE 4
#define PXP2_PXP2_PRTY_STS_WR_1_REG_PGL_TXW (0x1<<5)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_PGL_TXW_SIZE 5
#define PXP2_PXP2_PRTY_STS_WR_1_REG_PGL_REPLAY (0x1<<6)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_PGL_REPLAY_SIZE 6
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_ATC_ENTRY_ID (0x1<<7)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_ATC_ENTRY_ID_SIZE 7
#define PXP2_PXP2_PRTY_STS_WR_1_REG_HST_IREQ_SYNC_FIFO (0x1<<8)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_HST_IREQ_SYNC_FIFO_SIZE 8
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_TREQ_FIFO_PARITY_ERR (0x1<<9)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_TREQ_FIFO_PARITY_ERR_SIZE 9
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_ICPL_FIFO_PARITY_ERR (0x1<<10)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_ICPL_FIFO_PARITY_ERR_SIZE 10
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_PBF_REQ_PARITY_ERR (0x1<<11)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_PBF_REQ_PARITY_ERR_SIZE 11
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_QM_REQ_PARITY_ERR (0x1<<12)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_QM_REQ_PARITY_ERR_SIZE 12
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_TM_REQ_PARITY_ERR (0x1<<13)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_TM_REQ_PARITY_ERR_SIZE 13
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_SRC_REQ_PARITY_ERR (0x1<<14)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_SRC_REQ_PARITY_ERR_SIZE 14
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_USDM_REQ_PARITY_ERR (0x1<<15)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_USDM_REQ_PARITY_ERR_SIZE 15
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_USDMDP_REQ_PARITY_ERR (0x1<<16)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_USDMDP_REQ_PARITY_ERR_SIZE 16
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_TSDM_REQ_PARITY_ERR (0x1<<17)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_TSDM_REQ_PARITY_ERR_SIZE 17
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_CSDM_REQ_PARITY_ERR (0x1<<18)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_CSDM_REQ_PARITY_ERR_SIZE 18
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_CDUWR_REQ_PARITY_ERR (0x1<<19)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_CDUWR_REQ_PARITY_ERR_SIZE 19
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_CDURD_REQ_PARITY_ERR (0x1<<20)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_CDURD_REQ_PARITY_ERR_SIZE 20
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_DMAE_REQ_PARITY_ERR (0x1<<21)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_DMAE_REQ_PARITY_ERR_SIZE 21
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_XSDM_REQ_PARITY_ERR (0x1<<22)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_XSDM_REQ_PARITY_ERR_SIZE 22
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_HC_REQ_PARITY_ERR (0x1<<23)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_HC_REQ_PARITY_ERR_SIZE 23
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_DBG_REQ_PARITY_ERR (0x1<<24)
#define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_DBG_REQ_PARITY_ERR_SIZE 24
#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598UL //ACCESS:RW DataWidth:0x19 Description: Parity mask register #1 read/write
#define PXP2_PXP2_PRTY_MASK_1_REG_RD_NEXT_BLK_PTRS (0x1<<0)
#define PXP2_PXP2_PRTY_MASK_1_REG_RD_NEXT_BLK_PTRS_SIZE 0
#define PXP2_PXP2_PRTY_MASK_1_REG_RD_SR_FREE_LIST (0x1<<1)
#define PXP2_PXP2_PRTY_MASK_1_REG_RD_SR_FREE_LIST_SIZE 1
#define PXP2_PXP2_PRTY_MASK_1_REG_RD_BLOCK_FREE_LIST (0x1<<2)
#define PXP2_PXP2_PRTY_MASK_1_REG_RD_BLOCK_FREE_LIST_SIZE 2
#define PXP2_PXP2_PRTY_MASK_1_REG_HST_CPL_SYNC_FIFO (0x1<<3)
#define PXP2_PXP2_PRTY_MASK_1_REG_HST_CPL_SYNC_FIFO_SIZE 3
#define PXP2_PXP2_PRTY_MASK_1_REG_PGL_CPL (0x1<<4)
#define PXP2_PXP2_PRTY_MASK_1_REG_PGL_CPL_SIZE 4
#define PXP2_PXP2_PRTY_MASK_1_REG_PGL_TXW (0x1<<5)
#define PXP2_PXP2_PRTY_MASK_1_REG_PGL_TXW_SIZE 5
#define PXP2_PXP2_PRTY_MASK_1_REG_PGL_REPLAY (0x1<<6)
#define PXP2_PXP2_PRTY_MASK_1_REG_PGL_REPLAY_SIZE 6
#define PXP2_PXP2_PRTY_MASK_1_REG_RD_ATC_ENTRY_ID (0x1<<7)
#define PXP2_PXP2_PRTY_MASK_1_REG_RD_ATC_ENTRY_ID_SIZE 7
#define PXP2_PXP2_PRTY_MASK_1_REG_HST_IREQ_SYNC_FIFO (0x1<<8)
#define PXP2_PXP2_PRTY_MASK_1_REG_HST_IREQ_SYNC_FIFO_SIZE 8
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_TREQ_FIFO_PARITY_ERR (0x1<<9)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_TREQ_FIFO_PARITY_ERR_SIZE 9
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_ICPL_FIFO_PARITY_ERR (0x1<<10)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_ICPL_FIFO_PARITY_ERR_SIZE 10
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_PBF_REQ_PARITY_ERR (0x1<<11)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_PBF_REQ_PARITY_ERR_SIZE 11
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_QM_REQ_PARITY_ERR (0x1<<12)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_QM_REQ_PARITY_ERR_SIZE 12
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_TM_REQ_PARITY_ERR (0x1<<13)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_TM_REQ_PARITY_ERR_SIZE 13
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_SRC_REQ_PARITY_ERR (0x1<<14)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_SRC_REQ_PARITY_ERR_SIZE 14
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_USDM_REQ_PARITY_ERR (0x1<<15)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_USDM_REQ_PARITY_ERR_SIZE 15
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_USDMDP_REQ_PARITY_ERR (0x1<<16)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_USDMDP_REQ_PARITY_ERR_SIZE 16
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_TSDM_REQ_PARITY_ERR (0x1<<17)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_TSDM_REQ_PARITY_ERR_SIZE 17
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_CSDM_REQ_PARITY_ERR (0x1<<18)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_CSDM_REQ_PARITY_ERR_SIZE 18
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_CDUWR_REQ_PARITY_ERR (0x1<<19)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_CDUWR_REQ_PARITY_ERR_SIZE 19
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_CDURD_REQ_PARITY_ERR (0x1<<20)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_CDURD_REQ_PARITY_ERR_SIZE 20
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_DMAE_REQ_PARITY_ERR (0x1<<21)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_DMAE_REQ_PARITY_ERR_SIZE 21
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_XSDM_REQ_PARITY_ERR (0x1<<22)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_XSDM_REQ_PARITY_ERR_SIZE 22
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_HC_REQ_PARITY_ERR (0x1<<23)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_HC_REQ_PARITY_ERR_SIZE 23
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_DBG_REQ_PARITY_ERR (0x1<<24)
#define PXP2_PXP2_PRTY_MASK_1_REG_RQ_DBG_REQ_PARITY_ERR_SIZE 24
#define PXP2_REG_RD_INIT_MEMS_WITH_ZERO 0x12059cUL //ACCESS:RW DataWidth:0x1 Description: Debug only: '1' indicates that the following memories should be initialized with zeros or NULL values after 'start_init': tetris buffer; completion context memory; vq head memory; SR memory for delivery; first block pointers memory. This is a fix done in E1.5 to fix a parity error bug on these memories. '0' indicates not to initialize these memories; so 'start_init' will behave as in E1A0.
#define PXP2_REG_PGL_EXP_ROM_FUNC 0x1205a0UL //ACCESS:R DataWidth:0x3 Description: the function number of the expansion rom that is being accessed
#define PXP2_REG_PGL_VPD_FUNC 0x1205a4UL //ACCESS:R DataWidth:0x3 Description: Unused.
#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8UL //ACCESS:RW DataWidth:0x7 Multi Field Register
#define PXP2_PGL_TAGS_LIMIT_REG_PGL_MAX_TAGS (0x3f<<0)
#define PXP2_PGL_TAGS_LIMIT_REG_PGL_MAX_TAGS_SIZE 0
#define PXP2_PGL_TAGS_LIMIT_REG_PGL_MAX_TAGS_DISABLE (0x1<<6)
#define PXP2_PGL_TAGS_LIMIT_REG_PGL_MAX_TAGS_DISABLE_SIZE 6
#define PXP2_REG_RQ_L2P_MODE 0x1205acUL //ACCESS:RW DataWidth:0x1 Description: will determine how the logical address is calculated; 0: as in E1; 1:with new algorithm
#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0UL //ACCESS:RW DataWidth:0x4 Description: Determines alignment of write SRs when a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B aligned. 4 - 512B aligned.
#define PXP2_REG_RQ_ILT_MODE 0x1205b4UL //ACCESS:RW DataWidth:0x1 Description: when '0' ILT logic will work as in A0; otherwise B0; for back compatibility needs; Note that different registers are used per mode
#define PXP2_REG_RQ_ENDIANITY_00 0x1205b8UL //ACCESS:RW DataWidth:0x2 Description: Requests from all SDM's and DMAE with endian mode 0 will receive the endian mode indicated here
#define PXP2_REG_RQ_ENDIANITY_01 0x1205bcUL //ACCESS:RW DataWidth:0x2 Description: Requests from all SDM's and DMAE with endian mode 1 will receive the endian mode indicated here
#define PXP2_REG_RQ_ENDIANITY_02 0x1205c0UL //ACCESS:RW DataWidth:0x2 Description: Requests from all SDM's and DMAE with endian mode 2 will receive the endian mode indicated here
#define PXP2_REG_RQ_ENDIANITY_03 0x1205c4UL //ACCESS:RW DataWidth:0x2 Description: Requests from all SDM's and DMAE with endian mode 3 will receive the endian mode indicated here
#define PXP2_REG_WR_HC_MPS 0x1205c8UL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_USDM_MPS 0x1205ccUL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_CSDM_MPS 0x1205d0UL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_TSDM_MPS 0x1205d4UL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_XSDM_MPS 0x1205d8UL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_QM_MPS 0x1205dcUL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_TM_MPS 0x1205e0UL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_SRC_MPS 0x1205e4UL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_DBG_MPS 0x1205e8UL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_DMAE_MPS 0x1205ecUL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_CDU_MPS 0x1205f0UL //ACCESS:RW DataWidth:0x2 Description: 0 - 128B;1 - 256B;2 - 512B;3 - 1024B; when the payload in the buffer reaches this number has_payload will be asserted. 1024B is not a real MPS; it is a way of indicating that the client needs to wait for EOP before asserting has_payload. Register should be initialized according to has_payload value.
#define PXP2_REG_WR_DBG_FULL_TH2 0x1205f4UL //ACCESS:RW DataWidth:0x6 Description: if Number of entries in the dbg internal fifo is bigger than this number than full will be asserted
#define PXP2_REG_RQ_BW_RD_ADD_TREQ 0x1205f8UL //ACCESS:RW DataWidth:0xa Description: Bandwidth addition to VQ TREQ read requests
#define PXP2_REG_RQ_BW_RD_UBOUND_TREQ 0x1205fcUL //ACCESS:RW DataWidth:0x7 Description: Bandwidth upper bound to VQ TREQ read requests
#define PXP2_REG_RQ_BW_RD_L_TREQ 0x120600UL //ACCESS:RW DataWidth:0xa Description: Bandwidth Typical L to VQ TREQ read requests
#define PXP2_REG_WR_TH_MODE_USDMDP 0x120604UL //ACCESS:RW DataWidth:0x1 Description: For USDMDP - 0 - B0 mode (E1.5-65nm) - asserts has_payload when MPS bytes are in the buffer and no outstanding sub-request grants or EOP arrived; 1 - enhanced mode (E1.5-90nm) - assert has_payload when (~pxp2.wr_usdmdp_th x 32) bytes are in the buffer or EOP arrived.
#define PXP2_REG_PXP2_INT_STS_1 0x120608UL //ACCESS:R DataWidth:0x11 Description: Interrupt register #1 read
#define PXP2_PXP2_INT_STS_1_REG_WR_USDMDP_UNDERFLOW (0x1<<0)
#define PXP2_PXP2_INT_STS_1_REG_WR_USDMDP_UNDERFLOW_SIZE 0
#define PXP2_PXP2_INT_STS_1_REG_WR_CDU_UNDERFLOW (0x1<<1)
#define PXP2_PXP2_INT_STS_1_REG_WR_CDU_UNDERFLOW_SIZE 1
#define PXP2_PXP2_INT_STS_1_REG_WR_DBG_UNDERFLOW (0x1<<2)
#define PXP2_PXP2_INT_STS_1_REG_WR_DBG_UNDERFLOW_SIZE 2
#define PXP2_PXP2_INT_STS_1_REG_WR_DMAE_UNDERFLOW (0x1<<3)
#define PXP2_PXP2_INT_STS_1_REG_WR_DMAE_UNDERFLOW_SIZE 3
#define PXP2_PXP2_INT_STS_1_REG_WR_HC_UNDERFLOW (0x1<<4)
#define PXP2_PXP2_INT_STS_1_REG_WR_HC_UNDERFLOW_SIZE 4
#define PXP2_PXP2_INT_STS_1_REG_RQ_ELT_ADDR (0x1<<5)
#define PXP2_PXP2_INT_STS_1_REG_RQ_ELT_ADDR_SIZE 5
#define PXP2_PXP2_INT_STS_1_REG_RQ_L2P_VF_ERR (0x1<<6)
#define PXP2_PXP2_INT_STS_1_REG_RQ_L2P_VF_ERR_SIZE 6
#define PXP2_PXP2_INT_STS_1_REG_RQ_CORE_WDONE_OVERFLOW (0x1<<7)
#define PXP2_PXP2_INT_STS_1_REG_RQ_CORE_WDONE_OVERFLOW_SIZE 7
#define PXP2_PXP2_INT_STS_1_REG_HST_IREQ_FIFO_ERR (0x1<<8)
#define PXP2_PXP2_INT_STS_1_REG_HST_IREQ_FIFO_ERR_SIZE 8
#define PXP2_PXP2_INT_STS_1_REG_RD_SR_CNT_UNDERFLOW (0x1<<9)
#define PXP2_PXP2_INT_STS_1_REG_RD_SR_CNT_UNDERFLOW_SIZE 9
#define PXP2_PXP2_INT_STS_1_REG_RD_BLK_CNT_UNDERFLOW (0x1<<10)
#define PXP2_PXP2_INT_STS_1_REG_RD_BLK_CNT_UNDERFLOW_SIZE 10
#define PXP2_PXP2_INT_STS_1_REG_RQ_TREQ_FIFO_UNDERFLOW (0x1<<11)
#define PXP2_PXP2_INT_STS_1_REG_RQ_TREQ_FIFO_UNDERFLOW_SIZE 11
#define PXP2_PXP2_INT_STS_1_REG_RQ_TREQ_FIFO_OVERFLOW (0x1<<12)
#define PXP2_PXP2_INT_STS_1_REG_RQ_TREQ_FIFO_OVERFLOW_SIZE 12
#define PXP2_PXP2_INT_STS_1_REG_RQ_ICPL_FIFO_UNDERFLOW (0x1<<13)
#define PXP2_PXP2_INT_STS_1_REG_RQ_ICPL_FIFO_UNDERFLOW_SIZE 13
#define PXP2_PXP2_INT_STS_1_REG_RQ_ICPL_FIFO_OVERFLOW (0x1<<14)
#define PXP2_PXP2_INT_STS_1_REG_RQ_ICPL_FIFO_OVERFLOW_SIZE 14
#define PXP2_PXP2_INT_STS_1_REG_RQ_BACK2BACK_ATC_RESPONSE (0x1<<15)
#define PXP2_PXP2_INT_STS_1_REG_RQ_BACK2BACK_ATC_RESPONSE_SIZE 15
#define PXP2_PXP2_INT_STS_1_REG_WR_PGLUE_LSR_ERROR (0x1<<16)
#define PXP2_PXP2_INT_STS_1_REG_WR_PGLUE_LSR_ERROR_SIZE 16
#define PXP2_REG_PXP2_INT_STS_CLR_1 0x12060cUL //ACCESS:RC DataWidth:0x11 Description: Interrupt register #1 read clear
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_USDMDP_UNDERFLOW (0x1<<0)
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_USDMDP_UNDERFLOW_SIZE 0
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_CDU_UNDERFLOW (0x1<<1)
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_CDU_UNDERFLOW_SIZE 1
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_DBG_UNDERFLOW (0x1<<2)
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_DBG_UNDERFLOW_SIZE 2
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_DMAE_UNDERFLOW (0x1<<3)
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_DMAE_UNDERFLOW_SIZE 3
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_HC_UNDERFLOW (0x1<<4)
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_HC_UNDERFLOW_SIZE 4
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_ELT_ADDR (0x1<<5)
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_ELT_ADDR_SIZE 5
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_L2P_VF_ERR (0x1<<6)
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_L2P_VF_ERR_SIZE 6
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_CORE_WDONE_OVERFLOW (0x1<<7)
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_CORE_WDONE_OVERFLOW_SIZE 7
#define PXP2_PXP2_INT_STS_CLR_1_REG_HST_IREQ_FIFO_ERR (0x1<<8)
#define PXP2_PXP2_INT_STS_CLR_1_REG_HST_IREQ_FIFO_ERR_SIZE 8
#define PXP2_PXP2_INT_STS_CLR_1_REG_RD_SR_CNT_UNDERFLOW (0x1<<9)
#define PXP2_PXP2_INT_STS_CLR_1_REG_RD_SR_CNT_UNDERFLOW_SIZE 9
#define PXP2_PXP2_INT_STS_CLR_1_REG_RD_BLK_CNT_UNDERFLOW (0x1<<10)
#define PXP2_PXP2_INT_STS_CLR_1_REG_RD_BLK_CNT_UNDERFLOW_SIZE 10
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_TREQ_FIFO_UNDERFLOW (0x1<<11)
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_TREQ_FIFO_UNDERFLOW_SIZE 11
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_TREQ_FIFO_OVERFLOW (0x1<<12)
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_TREQ_FIFO_OVERFLOW_SIZE 12
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_ICPL_FIFO_UNDERFLOW (0x1<<13)
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_ICPL_FIFO_UNDERFLOW_SIZE 13
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_ICPL_FIFO_OVERFLOW (0x1<<14)
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_ICPL_FIFO_OVERFLOW_SIZE 14
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_BACK2BACK_ATC_RESPONSE (0x1<<15)
#define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_BACK2BACK_ATC_RESPONSE_SIZE 15
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_PGLUE_LSR_ERROR (0x1<<16)
#define PXP2_PXP2_INT_STS_CLR_1_REG_WR_PGLUE_LSR_ERROR_SIZE 16
#define PXP2_REG_PXP2_INT_STS_WR_1 0x120610UL //ACCESS:WR DataWidth:0x11 Description: Interrupt register #1 bit set or clear
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_USDMDP_UNDERFLOW (0x1<<0)
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_USDMDP_UNDERFLOW_SIZE 0
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_CDU_UNDERFLOW (0x1<<1)
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_CDU_UNDERFLOW_SIZE 1
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_DBG_UNDERFLOW (0x1<<2)
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_DBG_UNDERFLOW_SIZE 2
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_DMAE_UNDERFLOW (0x1<<3)
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_DMAE_UNDERFLOW_SIZE 3
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_HC_UNDERFLOW (0x1<<4)
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_HC_UNDERFLOW_SIZE 4
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_ELT_ADDR (0x1<<5)
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_ELT_ADDR_SIZE 5
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_L2P_VF_ERR (0x1<<6)
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_L2P_VF_ERR_SIZE 6
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_CORE_WDONE_OVERFLOW (0x1<<7)
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_CORE_WDONE_OVERFLOW_SIZE 7
#define PXP2_PXP2_INT_STS_WR_1_REG_HST_IREQ_FIFO_ERR (0x1<<8)
#define PXP2_PXP2_INT_STS_WR_1_REG_HST_IREQ_FIFO_ERR_SIZE 8
#define PXP2_PXP2_INT_STS_WR_1_REG_RD_SR_CNT_UNDERFLOW (0x1<<9)
#define PXP2_PXP2_INT_STS_WR_1_REG_RD_SR_CNT_UNDERFLOW_SIZE 9
#define PXP2_PXP2_INT_STS_WR_1_REG_RD_BLK_CNT_UNDERFLOW (0x1<<10)
#define PXP2_PXP2_INT_STS_WR_1_REG_RD_BLK_CNT_UNDERFLOW_SIZE 10
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_TREQ_FIFO_UNDERFLOW (0x1<<11)
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_TREQ_FIFO_UNDERFLOW_SIZE 11
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_TREQ_FIFO_OVERFLOW (0x1<<12)
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_TREQ_FIFO_OVERFLOW_SIZE 12
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_ICPL_FIFO_UNDERFLOW (0x1<<13)
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_ICPL_FIFO_UNDERFLOW_SIZE 13
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_ICPL_FIFO_OVERFLOW (0x1<<14)
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_ICPL_FIFO_OVERFLOW_SIZE 14
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_BACK2BACK_ATC_RESPONSE (0x1<<15)
#define PXP2_PXP2_INT_STS_WR_1_REG_RQ_BACK2BACK_ATC_RESPONSE_SIZE 15
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_PGLUE_LSR_ERROR (0x1<<16)
#define PXP2_PXP2_INT_STS_WR_1_REG_WR_PGLUE_LSR_ERROR_SIZE 16
#define PXP2_REG_PXP2_INT_MASK_1 0x120614UL //ACCESS:RW DataWidth:0x11 Description: Interrupt mask register #1 read/write
#define PXP2_PXP2_INT_MASK_1_REG_WR_USDMDP_UNDERFLOW (0x1<<0)
#define PXP2_PXP2_INT_MASK_1_REG_WR_USDMDP_UNDERFLOW_SIZE 0
#define PXP2_PXP2_INT_MASK_1_REG_WR_CDU_UNDERFLOW (0x1<<1)
#define PXP2_PXP2_INT_MASK_1_REG_WR_CDU_UNDERFLOW_SIZE 1
#define PXP2_PXP2_INT_MASK_1_REG_WR_DBG_UNDERFLOW (0x1<<2)
#define PXP2_PXP2_INT_MASK_1_REG_WR_DBG_UNDERFLOW_SIZE 2
#define PXP2_PXP2_INT_MASK_1_REG_WR_DMAE_UNDERFLOW (0x1<<3)
#define PXP2_PXP2_INT_MASK_1_REG_WR_DMAE_UNDERFLOW_SIZE 3
#define PXP2_PXP2_INT_MASK_1_REG_WR_HC_UNDERFLOW (0x1<<4)
#define PXP2_PXP2_INT_MASK_1_REG_WR_HC_UNDERFLOW_SIZE 4
#define PXP2_PXP2_INT_MASK_1_REG_RQ_ELT_ADDR (0x1<<5)
#define PXP2_PXP2_INT_MASK_1_REG_RQ_ELT_ADDR_SIZE 5
#define PXP2_PXP2_INT_MASK_1_REG_RQ_L2P_VF_ERR (0x1<<6)
#define PXP2_PXP2_INT_MASK_1_REG_RQ_L2P_VF_ERR_SIZE 6
#define PXP2_PXP2_INT_MASK_1_REG_RQ_CORE_WDONE_OVERFLOW (0x1<<7)
#define PXP2_PXP2_INT_MASK_1_REG_RQ_CORE_WDONE_OVERFLOW_SIZE 7
#define PXP2_PXP2_INT_MASK_1_REG_HST_IREQ_FIFO_ERR (0x1<<8)
#define PXP2_PXP2_INT_MASK_1_REG_HST_IREQ_FIFO_ERR_SIZE 8
#define PXP2_PXP2_INT_MASK_1_REG_RD_SR_CNT_UNDERFLOW (0x1<<9)
#define PXP2_PXP2_INT_MASK_1_REG_RD_SR_CNT_UNDERFLOW_SIZE 9
#define PXP2_PXP2_INT_MASK_1_REG_RD_BLK_CNT_UNDERFLOW (0x1<<10)
#define PXP2_PXP2_INT_MASK_1_REG_RD_BLK_CNT_UNDERFLOW_SIZE 10
#define PXP2_PXP2_INT_MASK_1_REG_RQ_TREQ_FIFO_UNDERFLOW (0x1<<11)
#define PXP2_PXP2_INT_MASK_1_REG_RQ_TREQ_FIFO_UNDERFLOW_SIZE 11
#define PXP2_PXP2_INT_MASK_1_REG_RQ_TREQ_FIFO_OVERFLOW (0x1<<12)
#define PXP2_PXP2_INT_MASK_1_REG_RQ_TREQ_FIFO_OVERFLOW_SIZE 12
#define PXP2_PXP2_INT_MASK_1_REG_RQ_ICPL_FIFO_UNDERFLOW (0x1<<13)
#define PXP2_PXP2_INT_MASK_1_REG_RQ_ICPL_FIFO_UNDERFLOW_SIZE 13
#define PXP2_PXP2_INT_MASK_1_REG_RQ_ICPL_FIFO_OVERFLOW (0x1<<14)
#define PXP2_PXP2_INT_MASK_1_REG_RQ_ICPL_FIFO_OVERFLOW_SIZE 14
#define PXP2_PXP2_INT_MASK_1_REG_RQ_BACK2BACK_ATC_RESPONSE (0x1<<15)
#define PXP2_PXP2_INT_MASK_1_REG_RQ_BACK2BACK_ATC_RESPONSE_SIZE 15
#define PXP2_PXP2_INT_MASK_1_REG_WR_PGLUE_LSR_ERROR (0x1<<16)
#define PXP2_PXP2_INT_MASK_1_REG_WR_PGLUE_LSR_ERROR_SIZE 16
#define PXP2_REG_WR_USDMDP_OUTST_REQ 0x120618UL //ACCESS:RW DataWidth:0x4 Description: Number of USDMDP PSWRQ outstanding sub-request grants that weren't yet read by PGLUE.
#define PXP2_REG_RQ_ELT_DISABLE 0x12066cUL //ACCESS:RW DataWidth:0x1 Description: If 1 ILT failiue will not result in ELT access; An interrupt will be asserted
#define PXP2_REG_WR_REV_MODE 0x120670UL //ACCESS:RW DataWidth:0x1 Description: For non-USDMDP clients. 0 - working in A0 mode - assert has_payload only when EOP arrived;1 - working in B0 mode - assert has_payload according to pxp2.wr_th_usdmdp or to EOP arrived.
#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674UL //ACCESS:RW DataWidth:0x10 Description: this field allows one function to pretend being another function when accessing any BAR mapped resource within the device. the value of the field is the number of the function that will be accessed effectively. after software write to this bit it must read it in order to know that the new value is updated. Bits [15] - force. Bits [14] - path ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits [2:0] - PFID.
#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678UL //ACCESS:RW DataWidth:0x10 Description: this field allows one function to pretend being another function when accessing any BAR mapped resource within the device. the value of the field is the number of the function that will be accessed effectively. after software write to this bit it must read it in order to know that the new value is updated. Bits [15] - force. Bits [14] - path ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits [2:0] - PFID.
#define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067cUL //ACCESS:RW DataWidth:0x10 Description: this field allows one function to pretend being another function when accessing any BAR mapped resource within the device. the value of the field is the number of the function that will be accessed effectively. after software write to this bit it must read it in order to know that the new value is updated. Bits [15] - force. Bits [14] - path ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits [2:0] - PFID.
#define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680UL //ACCESS:RW DataWidth:0x10 Description: this field allows one function to pretend being another function when accessing any BAR mapped resource within the device. the value of the field is the number of the function that will be accessed effectively. after software write to this bit it must read it in order to know that the new value is updated. Bits [15] - force. Bits [14] - path ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits [2:0] - PFID.
#define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684UL //ACCESS:RW DataWidth:0x10 Description: this field allows one function to pretend being another function when accessing any BAR mapped resource within the device. the value of the field is the number of the function that will be accessed effectively. after software write to this bit it must read it in order to know that the new value is updated. Bits [15] - force. Bits [14] - path ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits [2:0] - PFID.
#define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688UL //ACCESS:RW DataWidth:0x10 Description: this field allows one function to pretend being another function when accessing any BAR mapped resource within the device. the value of the field is the number of the function that will be accessed effectively. after software write to this bit it must read it in order to know that the new value is updated. Bits [15] - force. Bits [14] - path ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits [2:0] - PFID.
#define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068cUL //ACCESS:RW DataWidth:0x10 Description: this field allows one function to pretend being another function when accessing any BAR mapped resource within the device. the value of the field is the number of the function that will be accessed effectively. after software write to this bit it must read it in order to know that the new value is updated. Bits [15] - force. Bits [14] - path ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits [2:0] - PFID.
#define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690UL //ACCESS:RW DataWidth:0x10 Description: this field allows one function to pretend being another function when accessing any BAR mapped resource within the device. the value of the field is the number of the function that will be accessed effectively. after software write to this bit it must read it in order to know that the new value is updated. Bits [15] - force. Bits [14] - path ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits [2:0] - PFID.
#define PXP2_REG_RQ_LOW_FREE_BYP 0x120694UL //ACCESS:RW DataWidth:0x1 Description: when 1;there cannot be more than 3 pswrq_garb_gnt for reads within 8 cycles; this can prevent the low free blocks bug
#define PXP2_REG_RQ_CXR_RAM0_TM 0x120698UL //ACCESS:RW DataWidth:0x8 Description: TM bits for cxr ram0
#define PXP2_REG_RQ_CXR_RAM1_TM 0x12069cUL //ACCESS:RW DataWidth:0x8 Description: TM bits for cxr ram1
#define PXP2_REG_RQ_CLOSE_GATE_RD_CLIENT_EN 0x1206a0UL //ACCESS:RW DataWidth:0x1d Description: BW counter rd clients that are enabled during close the gates flow (bit per rd vq and bit for treq). In E2 only the msbit should be set (treq)
#define PXP2_REG_RQ_ATC_CSDM_FLAGS 0x1206a8UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_WR_DMAE_TM 0x1206acUL //ACCESS:RW DataWidth:0x4 Description: Bits [1:0] are for fifo 0;Bits [3:2] are for fifo 1
#define PXP2_REG_PXP2_ECO_RSRV 0x1206b0UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define PXP2_PXP2_ECO_RSRV_REG_RQ_ECO_RESERVED (0x3f<<0)
#define PXP2_PXP2_ECO_RSRV_REG_RQ_ECO_RESERVED_SIZE 0
#define PXP2_PXP2_ECO_RSRV_REG_WR_ECO_RESERVED (0x3f<<6)
#define PXP2_PXP2_ECO_RSRV_REG_WR_ECO_RESERVED_SIZE 6
#define PXP2_PXP2_ECO_RSRV_REG_RD_ECO_RESERVED (0xfffff<<12)
#define PXP2_PXP2_ECO_RSRV_REG_RD_ECO_RESERVED_SIZE 12
#define PXP2_REG_WR_HAS_PAYLOAD 0x1206b4UL //ACCESS:R DataWidth:0xe Description: has payload indication for all clients; bit decoding - 0 USDM; 1 CSDM; 2 XSDM; 3 TSDM; 4 PBF always 0; 5 QM; 6 TM; 7 SRC; 8 CDURD always 0; 9 DMAE; 10 USDMDP; 11 HC; 12 CDUWR; 13 DBG
#define PXP2_REG_RQ_VQ_RD_DISABLE 0x1206b8UL //ACCESS:R DataWidth:0xa Description: vq read disable as wdone was not received yet for the wr request that was sent {vq1 ; vq2 ; vq3 ; vq6 ; vq7 ; vq8 ; vq9 ; vq10 ; vq11 ; vq28}
#define PXP2_REG_RQ_QC_REG1 0x1206bcUL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_REG2 0x1206c0UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_1ENTRY 0x1206c4UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_HOQ_IS_LOGICAL 0x1206c8UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_TAIL_V 0x1206ccUL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_HEAD_V 0x1206d0UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_31_28_TAIL 0x1206d4UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_27_24_TAIL 0x1206d8UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_23_20_TAIL 0x1206dcUL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_19_16_TAIL 0x1206e0UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_15_12_TAIL 0x1206e4UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_11_8_TAIL 0x1206e8UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_7_4_TAIL 0x1206ecUL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_3_0_TAIL 0x1206f0UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_31_28_HEAD 0x1206f4UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_27_24_HEAD 0x1206f8UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_23_20_HEAD 0x1206fcUL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_19_16_HEAD 0x120700UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_15_12_HEAD 0x120704UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_11_8_HEAD 0x120708UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_7_4_HEAD 0x12070cUL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_VIQ_3_0_HEAD 0x120710UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_CMG_VQ_31_24_FUNC 0x120714UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_CMG_VQ_23_16_FUNC 0x120718UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_CMG_VQ_15_8_FUNC 0x12071cUL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_QC_CMG_VQ_7_0_FUNC 0x120720UL //ACCESS:R DataWidth:0x20 Description:
#define PXP2_REG_RQ_CMG_NEED_4K_ALIGN 0x120724UL //ACCESS:R DataWidth:0x20 Description: need 4k alignment; bit per VQ
#define PXP2_REG_RQ_CMG 0x120728UL //ACCESS:R DataWidth:0x20 Description: Status signals in pswrq_cmg module
#define PXP2_REG_RQ_CMG_HAS_PAYLOAD 0x12072cUL //ACCESS:R DataWidth:0x6 Description: has payload indication for the VQs with more than one client: {vq11 ; vq10 ; vq9 ; vq8 ; vq7 ; vq6}
#define PXP2_REG_RQ_CMG_S2_VQ_VAL 0x120730UL //ACCESS:R DataWidth:0x20 Description: bit per VQ
#define PXP2_REG_RQ_CMG_S1_VQ_VAL 0x120734UL //ACCESS:R DataWidth:0x20 Description: bit per VQ
#define PXP2_REG_RQ_CMG_VQ_RDWR_N 0x120738UL //ACCESS:R DataWidth:0xb Description: {vq28 ; vq11 ; vq10 ; vq9 ; vq8 ; vq7 ; vq6 ; vq5 ; vq3 ; vq2 ; vq1}
#define PXP2_REG_RQ_CMG_VQ_CLIENT_ID 0x12073cUL //ACCESS:R DataWidth:0x18 Description: 4 bits per client: {vq11 client_id ; vq10 client_id; vq9 client_id; vq8 client_id; vq7 client_id; vq6 client_id}
#define PXP2_REG_RQ_CMG_VQ_1ST_SR 0x120740UL //ACCESS:R DataWidth:0x20 Description: current sub request is the 1st in the request (bit per vq)
#define PXP2_REG_RQ_CMG_VQ_LAST_SR 0x120744UL //ACCESS:R DataWidth:0x20 Description: current sub request is the last in the request (bit per vq)
#define PXP2_REG_RQ_GARB 0x120748UL //ACCESS:R DataWidth:0x20 Description: Status signals in pswrq_garb module
#define PXP2_REG_RQ_GARB_S1 0x12074cUL //ACCESS:R DataWidth:0x20 Description: Status signals in pswrq_garb_s1 module: bits 15:0 - i_rd_arbiter instance ; Bits 31:16 - i_wr_arbiter instance
#define PXP2_REG_RQ_GARB_S1_BW_RD_STS 0x120750UL //ACCESS:R DataWidth:0x1c Description: bandwidth status for rd arbiter in s1
#define PXP2_REG_RQ_GARB_S1_BW_WR_STS 0x120754UL //ACCESS:R DataWidth:0xc Description: bandwidth status for wr arbiter in s1
#define PXP2_REG_RQ_CMG_GARB_HOQ_RDWR_N 0x120758UL //ACCESS:R DataWidth:0x20 Description: bit per VQ
#define PXP2_REG_RQ_CMG_GARB_HOQ_STS 0x12075cUL //ACCESS:R DataWidth:0x20 Description: bit per VQ
#define PXP2_REG_RQ_GARB_CTRL 0x120760UL //ACCESS:R DataWidth:0x20 Description: Status signals in pswrq_garb_ctrl module:
#define PXP2_REG_RQ_GARB_SBMT 0x120764UL //ACCESS:R DataWidth:0x20 Description: Status signals in pswrq_garb_sbmt module: {3b0 ; rd_is_pending ; 3b0 ; rd_p_th_ok ; 3b0 ; pending_rd_arr_en ; 3b0 ; rd_gnt_disable ; 3b0 ; blk_mbs2_th_n_ok ; 2b0 ; rd_gnt_cnt[1:0] ; pswrd_pswrq_blk_cnt[7:0]}
#define PXP2_REG_RQ_PSWRD_PSWRQ_BLK_PER_VQ 0x120768UL //ACCESS:R DataWidth:0x1d Description: Available blocks in pswrd reader buffer (per vq)
#define PXP2_REG_RD_TM_65 0x12076cUL //ACCESS:RW DataWidth:0x8 Multi Field Register
#define PXP2_RD_TM_65_REG_RD_BLK_FREE_LIST_TM (0x3<<0)
#define PXP2_RD_TM_65_REG_RD_BLK_FREE_LIST_TM_SIZE 0
#define PXP2_RD_TM_65_REG_RD_NEXT_BLK_PTR_TM (0x3<<2)
#define PXP2_RD_TM_65_REG_RD_NEXT_BLK_PTR_TM_SIZE 2
#define PXP2_RD_TM_65_REG_RD_SR_MEMC_TM (0x3<<4)
#define PXP2_RD_TM_65_REG_RD_SR_MEMC_TM_SIZE 4
#define PXP2_RD_TM_65_REG_RD_COMP_CTX_TM (0x3<<6)
#define PXP2_RD_TM_65_REG_RD_COMP_CTX_TM_SIZE 6
#define PXP2_REG_RD_MASK_ERROR_TO_CLIENTS 0x120770UL //ACCESS:RW DataWidth:0xc Description: Debug only: '1' indicates that error indication is masked towards the corresponding client.
#define PXP2_REG_RD_CONF11 0x120774UL //ACCESS:RW DataWidth:0x12 Multi Field Register
#define PXP2_RD_CONF11_REG_RD_ERROR_PATTERN (0xffff<<0)
#define PXP2_RD_CONF11_REG_RD_ERROR_PATTERN_SIZE 0
#define PXP2_RD_CONF11_REG_RD_OVERRIDE_DATA_WHEN_ERROR (0x1<<16)
#define PXP2_RD_CONF11_REG_RD_OVERRIDE_DATA_WHEN_ERROR_SIZE 16
#define PXP2_RD_CONF11_REG_RD_OVERRIDE_LAST_CYCLE_ONLY (0x1<<17)
#define PXP2_RD_CONF11_REG_RD_OVERRIDE_LAST_CYCLE_ONLY_SIZE 17
#define PXP2_REG_RD_CPL_ERR_DETAILS 0x120778UL //ACCESS:R DataWidth:0x1d Description: Details of first request with error on receive side: [15:0] - Echo ID. [28:16] - sub-request length plus start_offset_2_0 minus 1.
#define PXP2_REG_RD_CPL_ERR_DETAILS2 0x12077cUL //ACCESS:R DataWidth:0xa Description: Details of first request with error on receive side: [4:0] - VQ ID. [8:5] - client ID. [9] - valid - indicates if there was a completion error since the last time this register was read.
#define PXP2_REG_RQ_ATC_USDM_FLAGS 0x120780UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_USDMDP_FLAGS 0x120784UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_TSDM_FLAGS 0x120788UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_XSDM_FLAGS 0x12078cUL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_DMAE_FLAGS 0x120790UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_CDUWR_FLAGS 0x120794UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_CDURD_FLAGS 0x120798UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_PBF_FLAGS 0x12079cUL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_QM_FLAGS 0x1207a0UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_TM_FLAGS 0x1207a4UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_SRC_FLAGS 0x1207a8UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_DBG_FLAGS 0x1207acUL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_HC_FLAGS 0x1207b0UL //ACCESS:RW DataWidth:0x4 Description: ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
#define PXP2_REG_RQ_ATC_VQ_ENABLE 0x1207b4UL //ACCESS:RW DataWidth:0x20 Description: ATC VQ enable bits. When set - SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). When reset - all SR-s from the VQ will NOT go through the ATC. b0 - VQ0; b1 - VQ1; b30 - VQ30; b31 - reserved (should be filled with zeroes).
#define PXP2_REG_RQ_CLOSE_GATE_WR_CLIENT_EN 0x1207b8UL //ACCESS:RW DataWidth:0xc Description: BW counter wr clients that are enabled during close the gates flow (bit per wr vq). In E2 no clients operate during close the gates
#define PXP2_REG_RQ_ATC_INTERNAL_ATS_ENABLE_ALL 0x1207bcUL //ACCESS:R DataWidth:0x10 Description: Concatenated values of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b14 - PF7; b15 - VF7;
#define PXP2_REG_RQ_ATC_VQ_GO_TRANSLATED 0x1207c0UL //ACCESS:RW DataWidth:0x20 Description: DEBUG ONLY. bit per VQ. go translated set means that SR of the matched VQ will be always sent to the GLUE with the at_valid=1 indication (see atc_code in PSWRQ-PGLUE interface for more details). In that case the address will be delivered by the chip (and not by the ATC). This mode will be used mainly for debug and the other configurations must make sure that ATC will never be used for that VQ while the go_translated bit for that VQ is set. when reset means that the at_valid indication will be determined according to the ATC.
#define PXP2_REG_RQ_ATC_GLOBAL_ENABLE 0x1207c4UL //ACCESS:RW DataWidth:0x1 Description: Global ATC enable bit. when reset all ATC logic is disabled within the PSWRQ. The value of this register must be the same as RD_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.
#define PXP2_REG_RQ_L2P_VF_ERR_VQ_ID 0x1207c8UL //ACCESS:RC DataWidth:0x5 Description: The VQ id of the request with rq_l2p_vf_err interrupt
#define PXP2_REG_RD_ATC_GLOBAL_ENABLE 0x1207ccUL //ACCESS:RW DataWidth:0x1 Description: Global ATC enable bit. When reset all ATC logic is disabled within the PSWRD. 'ATC entry ID' interface from PSWRQ is ignored and 'ATC RCPL Done' interface to ATC is not generated. The value of this register must be the same as PSWRQ_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.
#define PXP2_REG_RD_ATC_ENTRY_ID_TM 0x1207d4UL //ACCESS:RW DataWidth:0x2 Description: TM bits of ATC entry ID memory - unused in E3.
#define PXP2_REG_RQ_TREQ_FIFO_FILL_LVL 0x1207fcUL //ACCESS:R DataWidth:0x6 Description: The fill level of the TREQ fifo
#define PXP2_REG_RQ_ICPL_FIFO_FILL_LVL 0x120910UL //ACCESS:R DataWidth:0x3 Description: The fill level of the ICPL fifo
#define PXP2_REG_RQ_ATC_TREQ_FIFO_TM 0x120914UL //ACCESS:RW DataWidth:0x2 Description: NOT USED
#define PXP2_REG_RQ_ASSERT_IF_ILT_FAIL 0x120918UL //ACCESS:RW DataWidth:0x1 Description: when set - assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail due to overflow on vah_plus_1st signal (Cont00041628). If reset - interrupt will not assert
#define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092cUL //ACCESS:RW DataWidth:0x4 Description: Determines alignment of read SRs when a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B aligned. 4 - 512B aligned.
#define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930UL //ACCESS:RW DataWidth:0x1 Description: when set the new alignment method (E2) will be applied; when reset the original alignment method (E1 E1H) will be applied
#define PXP2_REG_WR_HP_FORCE_DEASSERT_E2 0x120934UL //ACCESS:RW DataWidth:0x2 Description: has_payload forced de-assertion after grant from PSWRQ. 0 - as in B0; 1 - forced to 2 cycles de-assertion after grant. Bit[0] - all clients but USDM-DP; bit[1] - USDM-DP client.
#define PXP2_REG_RQ_HOQ_RAM_RD_EN 0x120938UL //ACCESS:RW DataWidth:0x1 Description: FOR DBG: enable reading from the hoq ram; when set hoq rbc read is enabled; when reset hoq rbc read is disabled (i.e. rq_hoq_ram_rd_req will not have any affect)
#define PXP2_REG_RD_CONTINUE_SERVING_PBF 0x12095cUL //ACCESS:RW DataWidth:0x1 Description: This register defines the delivery port behavior when finishing delivering a request to the PBF and the data for the next request is already in the Tetris buffer. 0 - The delivery port continues delivering the next PBF request only if the second delivery port is idle. This is the behavior in E1 E1H and E2. 1 - The delivery port always continues delivering the next PBF request. This is more efficient since about 11 arbitration cycles are not wasted.
#define PXP2_REG_RD_TM1_E3 0x120960UL //ACCESS:RW DataWidth:0x1e Multi Field Register
#define PXP2_RD_TM1_E3_REG_RD_TETRIS4_TMA (0x1f<<0)
#define PXP2_RD_TM1_E3_REG_RD_TETRIS4_TMA_SIZE 0
#define PXP2_RD_TM1_E3_REG_RD_TETRIS4_TMB (0x1f<<5)
#define PXP2_RD_TM1_E3_REG_RD_TETRIS4_TMB_SIZE 5
#define PXP2_RD_TM1_E3_REG_RD_TETRIS5_TMA (0x1f<<10)
#define PXP2_RD_TM1_E3_REG_RD_TETRIS5_TMA_SIZE 10
#define PXP2_RD_TM1_E3_REG_RD_TETRIS5_TMB (0x1f<<15)
#define PXP2_RD_TM1_E3_REG_RD_TETRIS5_TMB_SIZE 15
#define PXP2_RD_TM1_E3_REG_RD_TETRIS6_TMA (0x1f<<20)
#define PXP2_RD_TM1_E3_REG_RD_TETRIS6_TMA_SIZE 20
#define PXP2_RD_TM1_E3_REG_RD_TETRIS6_TMB (0x1f<<25)
#define PXP2_RD_TM1_E3_REG_RD_TETRIS6_TMB_SIZE 25
#define PXP2_REG_RD_TM2_E3 0x120964UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define PXP2_RD_TM2_E3_REG_RD_TETRIS7_TMA (0x1f<<0)
#define PXP2_RD_TM2_E3_REG_RD_TETRIS7_TMA_SIZE 0
#define PXP2_RD_TM2_E3_REG_RD_TETRIS7_TMB (0x1f<<5)
#define PXP2_RD_TM2_E3_REG_RD_TETRIS7_TMB_SIZE 5
#define PXP2_REG_PSWWR_USDMDP_TM 0x120968UL //ACCESS:RW DataWidth:0x14 Multi Field Register
#define PXP2_PSWWR_USDMDP_TM_REG_WR_USDMDP_FIFO2_TMA (0x1f<<0)
#define PXP2_PSWWR_USDMDP_TM_REG_WR_USDMDP_FIFO2_TMA_SIZE 0
#define PXP2_PSWWR_USDMDP_TM_REG_WR_USDMDP_FIFO2_TMB (0x1f<<5)
#define PXP2_PSWWR_USDMDP_TM_REG_WR_USDMDP_FIFO2_TMB_SIZE 5
#define PXP2_PSWWR_USDMDP_TM_REG_WR_USDMDP_FIFO3_TMA (0x1f<<10)
#define PXP2_PSWWR_USDMDP_TM_REG_WR_USDMDP_FIFO3_TMA_SIZE 10
#define PXP2_PSWWR_USDMDP_TM_REG_WR_USDMDP_FIFO3_TMB (0x1f<<15)
#define PXP2_PSWWR_USDMDP_TM_REG_WR_USDMDP_FIFO3_TMB_SIZE 15
#define PXP2_REG_RQ_SR_CNT_WINDOW_MODE 0x1209a4UL //ACCESS:RW DataWidth:0x1 Description: Counting window mode. 0 - manual window: counting is manually being initiated & stopped by the user through GRC. 1 - configured window: counting occurs according to configured window size.
#define PXP2_REG_RQ_SR_CNT_WINDOW_SIZE 0x1209a8UL //ACCESS:RW DataWidth:0x20 Description: Determines the size of the counting window. Valid when working in predefined window mode (i.e. Sr_cnt_window_mode = 1). Granularity of sr_cnt_clk_tickxclk_pci cycles.
#define PXP2_REG_RQ_SR_CNT_START_MODE 0x1209b8UL //ACCESS:RW DataWidth:0x1 Description: Determines the trigger for start counting (for both SR counters & global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start counting upon first PBF/USDM-DP SR that is sent to the PGLUE.
#define PXP2_REG_RQ_SR_CNT_ENABLE 0x1209bcUL //ACCESS:RW DataWidth:0x1 Description: Enables the SR counting mechanism.
#define PXP2_REG_RQ_SR_CNT_CLK_TICK 0x1209c0UL //ACCESS:RW DataWidth:0x3 Description: The number of clk_pci ticks minus 1 between each increment of the global window counter (i.e. 0 is for 1 clk_pci cycle; 1 is for 2 clk_pci cycles; 7 is for 8 clk_pci cycles)
#define PXP2_REG_PGL_ADDR_88_F0 0x120534UL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: GRC address for configuration access to PCIE config address 0x88. any write to this PCIE address will cause a GRC write access to the address that's in t this register
#define PXP2_REG_PGL_ADDR_88_F0_SIZE 1
#define PXP2_REG_PGL_ADDR_8C_F0 0x120538UL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: GRC address for configuration access to PCIE config address 0x8c. any write to this PCIE address will cause a GRC write access to the address that's in t this register
#define PXP2_REG_PGL_ADDR_8C_F0_SIZE 1
#define PXP2_REG_PGL_ADDR_90_F0 0x12053cUL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: GRC address for configuration access to PCIE config address 0x90. any write to this PCIE address will cause a GRC write access to the address that's in t this register
#define PXP2_REG_PGL_ADDR_90_F0_SIZE 1
#define PXP2_REG_PGL_ADDR_94_F0 0x120540UL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: GRC address for configuration access to PCIE config address 0x94. any write to this PCIE address will cause a GRC write access to the address that's in t this register
#define PXP2_REG_PGL_ADDR_94_F0_SIZE 1
#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061cUL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: first memory address base for cdu in ILT
#define PXP2_REG_RQ_CDU_FIRST_ILT_SIZE 1
#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: last memory address base for cdu in ILT
#define PXP2_REG_RQ_CDU_LAST_ILT_SIZE 1
#define PXP2_REG_RQ_CSDM_FIRST_ILT 0x120624UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: first memory address base for csdm in ILT
#define PXP2_REG_RQ_CSDM_FIRST_ILT_SIZE 1
#define PXP2_REG_RQ_CSDM_LAST_ILT 0x120628UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: last memory address base for csdm in ILT
#define PXP2_REG_RQ_CSDM_LAST_ILT_SIZE 1
#define PXP2_REG_RQ_DBG_FIRST_ILT 0x12062cUL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: first memory address base for dbg in ILT
#define PXP2_REG_RQ_DBG_FIRST_ILT_SIZE 1
#define PXP2_REG_RQ_DBG_LAST_ILT 0x120630UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: last memory address base for dbg in ILT
#define PXP2_REG_RQ_DBG_LAST_ILT_SIZE 1
#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: first memory address base for qm in ILT
#define PXP2_REG_RQ_QM_FIRST_ILT_SIZE 1
#define PXP2_REG_RQ_QM_LAST_ILT 0x120638UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: last memory address base for qm in ILT
#define PXP2_REG_RQ_QM_LAST_ILT_SIZE 1
#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063cUL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: first memory address base for src in ILT
#define PXP2_REG_RQ_SRC_FIRST_ILT_SIZE 1
#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: last memory address base for src in ILT
#define PXP2_REG_RQ_SRC_LAST_ILT_SIZE 1
#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: first memory address base for tm in ILT
#define PXP2_REG_RQ_TM_FIRST_ILT_SIZE 1
#define PXP2_REG_RQ_TM_LAST_ILT 0x120648UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: last memory address base for tm in ILT
#define PXP2_REG_RQ_TM_LAST_ILT_SIZE 1
#define PXP2_REG_RQ_TSDM_FIRST_ILT 0x12064cUL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: first memory address base for tsdm in ILT
#define PXP2_REG_RQ_TSDM_FIRST_ILT_SIZE 1
#define PXP2_REG_RQ_TSDM_LAST_ILT 0x120650UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: last memory address base for tsdm in ILT
#define PXP2_REG_RQ_TSDM_LAST_ILT_SIZE 1
#define PXP2_REG_RQ_USDM_FIRST_ILT 0x120654UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: first memory address base for usdm in ILT
#define PXP2_REG_RQ_USDM_FIRST_ILT_SIZE 1
#define PXP2_REG_RQ_USDM_LAST_ILT 0x120658UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: last memory address base for usdm in ILT
#define PXP2_REG_RQ_USDM_LAST_ILT_SIZE 1
#define PXP2_REG_RQ_USDMDP_FIRST_ILT 0x12065cUL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: first memory address base for usdmdp in ILT
#define PXP2_REG_RQ_USDMDP_FIRST_ILT_SIZE 1
#define PXP2_REG_RQ_USDMDP_LAST_ILT 0x120660UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: last memory address base for usdmdp in ILT
#define PXP2_REG_RQ_USDMDP_LAST_ILT_SIZE 1
#define PXP2_REG_RQ_XSDM_FIRST_ILT 0x120664UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: first memory address base for xsdm in ILT
#define PXP2_REG_RQ_XSDM_FIRST_ILT_SIZE 1
#define PXP2_REG_RQ_XSDM_LAST_ILT 0x120668UL //ACCESS:RW DataWidth:0xc SPLIT:8 Description: last memory address base for xsdm in ILT
#define PXP2_REG_RQ_XSDM_LAST_ILT_SIZE 1
#define PXP2_REG_RD_CPL_ERR_DETAILS_CLR 0x1207d0UL //ACCESS:W DataWidth:0x1 Description: Writing to this register clears rd_cpl_err_details and rd_cpl_err_details2 and enables logging new error details
#define PXP2_REG_RD_CPL_ERR_DETAILS_CLR_SIZE 1
#define PXP2_REG_RQ_ATC_INTERNAL_ATS_ENABLE 0x1207d8UL //ACCESS:RW DataWidth:0x2 SPLIT:8 Description: ATC enable values per PF as follows: b0 - PF enable; b1 - VF enable; PF enable bit is relevant when VF_Valid (in the request) bit is 0; VF enable bit is relevant when VF_Valid bit is 0.
#define PXP2_REG_RQ_ATC_INTERNAL_ATS_ENABLE_SIZE 1
#define PXP2_REG_PGL_EXP_ROM0 0x120800UL //ACCESS:RW DataWidth:0x20 Description: first dword data of expansion rom request. When this register is written a completion is sent to the pcie core. When the expansion rom request contains more than one dword this register should be written last. Writing to this register when there is not pending expansion rom request should not be done!
#define PXP2_REG_PGL_EXP_ROM0_SIZE 1
#define PXP2_REG_PGL_EXP_ROM1 0x120804UL //ACCESS:RW DataWidth:0x20 Description: second dword data of expansion rom request.
#define PXP2_REG_PGL_EXP_ROM1_SIZE 1
#define PXP2_REG_PGL_EXP_ROM2 0x120808UL //ACCESS:RW DataWidth:0x20 Description: third dword data of expansion rom request. this register is special. reading from it provides a vector outstanding read requests. if a bit is zero it means that a read request on the corresponding tag did not finish yet (not all completions have arrived for it)
#define PXP2_REG_PGL_EXP_ROM2_SIZE 1
#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080cUL //ACCESS:R DataWidth:0x5 Description: Number of entries in the ufifo;This fifo has l2p completions
#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY_SIZE 1
#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 0 in pswrq memory
#define PXP2_REG_RQ_VQ0_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ0_MAX_ENTRY_CNT 0x120814UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 0
#define PXP2_REG_RQ_VQ0_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 10 in pswrq memory
#define PXP2_REG_RQ_VQ10_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ10_MAX_ENTRY_CNT 0x12081cUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 10
#define PXP2_REG_RQ_VQ10_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 11 in pswrq memory
#define PXP2_REG_RQ_VQ11_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ11_MAX_ENTRY_CNT 0x120824UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 11
#define PXP2_REG_RQ_VQ11_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 12 in pswrq memory
#define PXP2_REG_RQ_VQ12_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ12_MAX_ENTRY_CNT 0x12082cUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 12
#define PXP2_REG_RQ_VQ12_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 13 in pswrq memory
#define PXP2_REG_RQ_VQ13_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ13_MAX_ENTRY_CNT 0x120834UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 13
#define PXP2_REG_RQ_VQ13_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 14 in pswrq memory
#define PXP2_REG_RQ_VQ14_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ14_MAX_ENTRY_CNT 0x12083cUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 14
#define PXP2_REG_RQ_VQ14_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 15 in pswrq memory
#define PXP2_REG_RQ_VQ15_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ15_MAX_ENTRY_CNT 0x120844UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 15
#define PXP2_REG_RQ_VQ15_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 16 in pswrq memory
#define PXP2_REG_RQ_VQ16_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ16_MAX_ENTRY_CNT 0x12084cUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 16
#define PXP2_REG_RQ_VQ16_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 17 in pswrq memory
#define PXP2_REG_RQ_VQ17_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ17_MAX_ENTRY_CNT 0x120854UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 17
#define PXP2_REG_RQ_VQ17_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 18 in pswrq memory
#define PXP2_REG_RQ_VQ18_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ18_MAX_ENTRY_CNT 0x12085cUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 18
#define PXP2_REG_RQ_VQ18_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 19 in pswrq memory
#define PXP2_REG_RQ_VQ19_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ19_MAX_ENTRY_CNT 0x120864UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 19
#define PXP2_REG_RQ_VQ19_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 1 in pswrq memory
#define PXP2_REG_RQ_VQ1_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ1_MAX_ENTRY_CNT 0x12086cUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 1
#define PXP2_REG_RQ_VQ1_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 20 in pswrq memory
#define PXP2_REG_RQ_VQ20_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ20_MAX_ENTRY_CNT 0x120874UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 20
#define PXP2_REG_RQ_VQ20_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 21 in pswrq memory
#define PXP2_REG_RQ_VQ21_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ21_MAX_ENTRY_CNT 0x12087cUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 21
#define PXP2_REG_RQ_VQ21_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 22 in pswrq memory
#define PXP2_REG_RQ_VQ22_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ22_MAX_ENTRY_CNT 0x120884UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 22
#define PXP2_REG_RQ_VQ22_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 23 in pswrq memory
#define PXP2_REG_RQ_VQ23_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ23_MAX_ENTRY_CNT 0x12088cUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 23
#define PXP2_REG_RQ_VQ23_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 24 in pswrq memory
#define PXP2_REG_RQ_VQ24_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ24_MAX_ENTRY_CNT 0x120894UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 24
#define PXP2_REG_RQ_VQ24_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 25 in pswrq memory
#define PXP2_REG_RQ_VQ25_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ25_MAX_ENTRY_CNT 0x12089cUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 25
#define PXP2_REG_RQ_VQ25_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 26 in pswrq memory
#define PXP2_REG_RQ_VQ26_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ26_MAX_ENTRY_CNT 0x1208a4UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 26
#define PXP2_REG_RQ_VQ26_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 27 in pswrq memory
#define PXP2_REG_RQ_VQ27_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ27_MAX_ENTRY_CNT 0x1208acUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 27
#define PXP2_REG_RQ_VQ27_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 28 in pswrq memory
#define PXP2_REG_RQ_VQ28_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ28_MAX_ENTRY_CNT 0x1208b4UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 28
#define PXP2_REG_RQ_VQ28_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 29 in pswrq memory
#define PXP2_REG_RQ_VQ29_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ29_MAX_ENTRY_CNT 0x1208bcUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 29
#define PXP2_REG_RQ_VQ29_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 2 in pswrq memory
#define PXP2_REG_RQ_VQ2_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ2_MAX_ENTRY_CNT 0x1208c4UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 2
#define PXP2_REG_RQ_VQ2_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 30 in pswrq memory
#define PXP2_REG_RQ_VQ30_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ30_MAX_ENTRY_CNT 0x1208ccUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 30
#define PXP2_REG_RQ_VQ30_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 31 in pswrq memory
#define PXP2_REG_RQ_VQ31_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ31_MAX_ENTRY_CNT 0x1208d4UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 31
#define PXP2_REG_RQ_VQ31_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 3 in pswrq memory
#define PXP2_REG_RQ_VQ3_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ3_MAX_ENTRY_CNT 0x1208dcUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 3
#define PXP2_REG_RQ_VQ3_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 4 in pswrq memory
#define PXP2_REG_RQ_VQ4_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ4_MAX_ENTRY_CNT 0x1208e4UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 4
#define PXP2_REG_RQ_VQ4_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 5 in pswrq memory
#define PXP2_REG_RQ_VQ5_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ5_MAX_ENTRY_CNT 0x1208ecUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 5
#define PXP2_REG_RQ_VQ5_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 6 in pswrq memory
#define PXP2_REG_RQ_VQ6_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ6_MAX_ENTRY_CNT 0x1208f4UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 6
#define PXP2_REG_RQ_VQ6_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 7 in pswrq memory
#define PXP2_REG_RQ_VQ7_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ7_MAX_ENTRY_CNT 0x1208fcUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 7
#define PXP2_REG_RQ_VQ7_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 8 in pswrq memory
#define PXP2_REG_RQ_VQ8_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ8_MAX_ENTRY_CNT 0x120904UL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 8
#define PXP2_REG_RQ_VQ8_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908UL //ACCESS:R DataWidth:0x8 Description: Number of entries occupied by vq 9 in pswrq memory
#define PXP2_REG_RQ_VQ9_ENTRY_CNT_SIZE 1
#define PXP2_REG_RQ_VQ9_MAX_ENTRY_CNT 0x12090cUL //ACCESS:R DataWidth:0x8 Description: Maximum Number of entries occupied by vq 9
#define PXP2_REG_RQ_VQ9_MAX_ENTRY_CNT_SIZE 1
#define PXP2_REG_DBG_OUT_DATA_LSB 0x12091cUL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that goes to the DBG block.
#define PXP2_REG_DBG_OUT_DATA_LSB_SIZE 1
#define PXP2_REG_DBG_OUT_DATA_MSB 0x120920UL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that goes to the DBG block.
#define PXP2_REG_DBG_OUT_DATA_MSB_SIZE 1
#define PXP2_REG_DBG_OUT_FRAME 0x120924UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits that goes to the DBG block. Bit0 is the frame of data byte0; Bit1 is the frame of data byte1; Bit2 is the frame of data byte2; Bit3 is the frame of data byte4
#define PXP2_REG_DBG_OUT_FRAME_SIZE 1
#define PXP2_REG_DBG_OUT_VALID 0x120928UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits that goes to the DBG block. Bit0 validtes data byte0; Bit1 validates data byte1; Bit2 validates data byte2; Bit3 validates data byte4
#define PXP2_REG_DBG_OUT_VALID_SIZE 1
#define PXP2_REG_RQ_HOQ_RAM_RD_REQ 0x12093cUL //ACCESS:RW DataWidth:0x5 Description: FOR DBG: read request from the hoq ram; the write data represents the address which is the vqid; in order to read from the hoq ram the read enable register should be set as well (rq_hoq_ram_rd_en); upon read completion (rq_hoq_ram_rd_status =1) data_rd_0 data_rd_1 data_rd_2 and data_rd_3 are ready with the valid values
#define PXP2_REG_RQ_HOQ_RAM_RD_REQ_SIZE 1
#define PXP2_REG_RQ_HOQ_RAM_RD_STATUS 0x120940UL //ACCESS:R DataWidth:0x1 Description: FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 data_rd2 and data_rd_3); when reset - still waiting for hoq ram read request to be completed)
#define PXP2_REG_RQ_HOQ_RAM_RD_STATUS_SIZE 1
#define PXP2_REG_RQ_HOQ_RAM_DATA_RD_0 0x120944UL //ACCESS:R DataWidth:0x20 Description: FOR DBG: bits 15:0 length; bits 31:16 request id
#define PXP2_REG_RQ_HOQ_RAM_DATA_RD_0_SIZE 1
#define PXP2_REG_RQ_HOQ_RAM_DATA_RD_1 0x120948UL //ACCESS:R DataWidth:0x20 Description: FOR DBG: address (32 lsb)
#define PXP2_REG_RQ_HOQ_RAM_DATA_RD_1_SIZE 1
#define PXP2_REG_RQ_HOQ_RAM_DATA_RD_2 0x12094cUL //ACCESS:R DataWidth:0x20 Description: FOR DBG: address (32 msb)
#define PXP2_REG_RQ_HOQ_RAM_DATA_RD_2_SIZE 1
#define PXP2_REG_RQ_HOQ_RAM_DATA_RD_3 0x120950UL //ACCESS:R DataWidth:0x20 Description: FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 client id; bit 6 done type; bit 7 resevred; bit 10:8 pfid; bit 11 vf_valid; bit 17:12 vfid; bits 20:18 atc flags; bits 31:21 reserved
#define PXP2_REG_RQ_HOQ_RAM_DATA_RD_3_SIZE 1
#define PXP2_REG_RQ_SR_CNT_WR_CNT 0x12096cUL //ACCESS:R DataWidth:0x20 Description: The total number of WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
#define PXP2_REG_RQ_SR_CNT_WR_CNT_SIZE 1
#define PXP2_REG_RQ_SR_CNT_RD_CNT 0x120970UL //ACCESS:R DataWidth:0x20 Description: The total number of RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
#define PXP2_REG_RQ_SR_CNT_RD_CNT_SIZE 1
#define PXP2_REG_RQ_SR_CNT_PBF_CNT 0x120974UL //ACCESS:R DataWidth:0x20 Description: The number of PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
#define PXP2_REG_RQ_SR_CNT_PBF_CNT_SIZE 1
#define PXP2_REG_RQ_SR_CNT_USDMDP_CNT 0x120978UL //ACCESS:R DataWidth:0x20 Description: The number of USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
#define PXP2_REG_RQ_SR_CNT_USDMDP_CNT_SIZE 1
#define PXP2_REG_RQ_SR_CNT_TREQ_CNT 0x12097cUL //ACCESS:R DataWidth:0x20 Description: The number of TREQ SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
#define PXP2_REG_RQ_SR_CNT_TREQ_CNT_SIZE 1
#define PXP2_REG_RQ_SR_CNT_ICPL_CNT 0x120980UL //ACCESS:R DataWidth:0x20 Description: The number of ICPL SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
#define PXP2_REG_RQ_SR_CNT_ICPL_CNT_SIZE 1
#define PXP2_REG_RQ_SR_CNT_WR_BYTE_LSB 0x120984UL //ACCESS:R DataWidth:0x20 Description: The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value
#define PXP2_REG_RQ_SR_CNT_WR_BYTE_LSB_SIZE 1
#define PXP2_REG_RQ_SR_CNT_WR_BYTE_MSB 0x120988UL //ACCESS:R DataWidth:0x9 Description: The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value
#define PXP2_REG_RQ_SR_CNT_WR_BYTE_MSB_SIZE 1
#define PXP2_REG_RQ_SR_CNT_RD_BYTE_LSB 0x12098cUL //ACCESS:R DataWidth:0x20 Description: The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value
#define PXP2_REG_RQ_SR_CNT_RD_BYTE_LSB_SIZE 1
#define PXP2_REG_RQ_SR_CNT_RD_BYTE_MSB 0x120990UL //ACCESS:R DataWidth:0xc Description: The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value
#define PXP2_REG_RQ_SR_CNT_RD_BYTE_MSB_SIZE 1
#define PXP2_REG_RQ_SR_CNT_PBF_BYTE_LSB 0x120994UL //ACCESS:R DataWidth:0x20 Description: The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value
#define PXP2_REG_RQ_SR_CNT_PBF_BYTE_LSB_SIZE 1
#define PXP2_REG_RQ_SR_CNT_PBF_BYTE_MSB 0x120998UL //ACCESS:R DataWidth:0xc Description: The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value
#define PXP2_REG_RQ_SR_CNT_PBF_BYTE_MSB_SIZE 1
#define PXP2_REG_RQ_SR_CNT_USDMDP_BYTE_LSB 0x12099cUL //ACCESS:R DataWidth:0x20 Description: The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value
#define PXP2_REG_RQ_SR_CNT_USDMDP_BYTE_LSB_SIZE 1
#define PXP2_REG_RQ_SR_CNT_USDMDP_BYTE_MSB 0x1209a0UL //ACCESS:R DataWidth:0x9 Description: The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value
#define PXP2_REG_RQ_SR_CNT_USDMDP_BYTE_MSB_SIZE 1
#define PXP2_REG_RQ_SR_CNT_WINDOW_VALUE 0x1209acUL //ACCESS:R DataWidth:0x20 Description: Global window counter for the current value of the recorded window. Represents the number of sr_cnt_clk_tickxclk_pci cycles from the beginning of counting. NOTE: beginning of counting is determined according to Sr_cnt_start_mode
#define PXP2_REG_RQ_SR_CNT_WINDOW_VALUE_SIZE 1
#define PXP2_REG_RQ_SR_CNT_MANUAL_CMD 0x1209b0UL //ACCESS:W DataWidth:0x1 Description: Write Only register. The manual window command sent by the user. Valid when working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - stop counting. 1 - start counting.
#define PXP2_REG_RQ_SR_CNT_MANUAL_CMD_SIZE 1
#define PXP2_REG_RQ_SR_CNT_RST 0x1209b4UL //ACCESS:W DataWidth:0x1 Description: Write Only register. RBC write command to this reg (any value) will reset the SR counters & the global window counter. In addition it'll move the Sr_cnt_status to idle state.
#define PXP2_REG_RQ_SR_CNT_RST_SIZE 1
#define PXP2_REG_RQ_SR_CNT_STATUS 0x1209c4UL //ACCESS:R DataWidth:0x2 Description: The status of the SR count mechanism: 0 - idle: ready to start new counting. 1 - ongoing: counting is currently ongoing. 2 - done: counting is completed. SR counters & global window counter are valid.
#define PXP2_REG_RQ_SR_CNT_STATUS_SIZE 1
#define PXP2_REG_RQ_LAST_RD_SR_LOG_0 0x1209c8UL //ACCESS:R DataWidth:0x20 Description: SR address - 32 lsb
#define PXP2_REG_RQ_LAST_RD_SR_LOG_0_SIZE 1
#define PXP2_REG_RQ_LAST_RD_SR_LOG_1 0x1209ccUL //ACCESS:R DataWidth:0x20 Description: SR address - 32 msb
#define PXP2_REG_RQ_LAST_RD_SR_LOG_1_SIZE 1
#define PXP2_REG_RQ_LAST_RD_SR_LOG_2 0x1209d0UL //ACCESS:R DataWidth:0x20 Description: b15-0: reqid; b28-16: SR length; b29 - reserved; b31-30: attributes
#define PXP2_REG_RQ_LAST_RD_SR_LOG_2_SIZE 1
#define PXP2_REG_RQ_LAST_RD_SR_LOG_3 0x1209d4UL //ACCESS:R DataWidth:0x20 Description: b2-0: PFID; b3: vf_valid; b9-b4: VFID; b10: first SR; b11: last SR; b15-12: client id; b20-16: vq; b22-21: atc code; b29-23: srid; b31-30: endianity
#define PXP2_REG_RQ_LAST_RD_SR_LOG_3_SIZE 1
#define PXP2_REG_RQ_LAST_RD_SR_LOG_4 0x1209d8UL //ACCESS:R DataWidth:0x5 Description: treq otb entry
#define PXP2_REG_RQ_LAST_RD_SR_LOG_4_SIZE 1
#define PXP2_REG_RQ_LAST_WR_SR_LOG_0 0x1209dcUL //ACCESS:R DataWidth:0x20 Description: SR address - 32 lsb
#define PXP2_REG_RQ_LAST_WR_SR_LOG_0_SIZE 1
#define PXP2_REG_RQ_LAST_WR_SR_LOG_1 0x1209e0UL //ACCESS:R DataWidth:0x20 Description: SR address - 32 msb
#define PXP2_REG_RQ_LAST_WR_SR_LOG_1_SIZE 1
#define PXP2_REG_RQ_LAST_WR_SR_LOG_2 0x1209e4UL //ACCESS:R DataWidth:0x20 Description: b15-0: reqid; b28-16: SR length; b29 - reserved; b31-30: attributes
#define PXP2_REG_RQ_LAST_WR_SR_LOG_2_SIZE 1
#define PXP2_REG_RQ_LAST_WR_SR_LOG_3 0x1209e8UL //ACCESS:R DataWidth:0x20 Description: b2-0: PFID; b3: vf_valid; b9-b4: VFID; b10: first SR; b11: last SR; b15-12: client id; b20-16: vq; b22-21: atc code; b27-23: start offset; b28: usdm err; b29: wdone type; b31-30: endianity
#define PXP2_REG_RQ_LAST_WR_SR_LOG_3_SIZE 1
#define PXP2_REG_RQ_LAST_WR_SR_LOG_4 0x1209ecUL //ACCESS:R DataWidth:0x5 Description: icpl itag index
#define PXP2_REG_RQ_LAST_WR_SR_LOG_4_SIZE 1
#define PXP2_REG_RD_FIRST_SR_NODES 0x120b00UL //ACCESS:WB_R DataWidth:0x1c Description: Debug only and read only: Each entry provides the first sub request ID in 4 VQs. SR ID of 0x7f is NULL and means there is no sub request in this VQ in PSWRD. The reset value is the one expected in idle check except for the Timers VQ (VQ3). E2 note: due to a bug (CQ44496) in the implementation only the first out of the 8 addresses (for VQs 0 through 3) is accessible.
#define PXP2_REG_RD_FIRST_SR_NODES_SIZE 8
#define PXP2_REG_RQ_ONCHIP_AT 0x122000UL //ACCESS:WB DataWidth:0x35 Description: Onchip address table
#define PXP2_REG_RQ_ONCHIP_AT_SIZE 2048
#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000UL //ACCESS:WB DataWidth:0x35 Description: Onchip address table - B0
#define PXP2_REG_RQ_ONCHIP_AT_B0_SIZE 6144
#define PXP2_REG_PGL_ADDR_88_F1 0x120544UL //ACCESS:R DataWidth:0x20 Description: GRC address for configuration access to PCIE config address 0x88. any write to this PCIE address will cause a GRC write access to the address that's in t this register
#define PXP2_REG_PGL_ADDR_88_F1_SIZE 1
#define PXP2_REG_PGL_ADDR_8C_F1 0x120548UL //ACCESS:R DataWidth:0x20 Description: GRC address for configuration access to PCIE config address 0x8c. any write to this PCIE address will cause a GRC write access to the address that's in t this register
#define PXP2_REG_PGL_ADDR_8C_F1_SIZE 1
#define PXP2_REG_PGL_ADDR_90_F1 0x12054cUL //ACCESS:R DataWidth:0x20 Description: GRC address for configuration access to PCIE config address 0x90. any write to this PCIE address will cause a GRC write access to the address that's in t this register
#define PXP2_REG_PGL_ADDR_90_F1_SIZE 1
#define PXP2_REG_PGL_ADDR_94_F1 0x120550UL //ACCESS:R DataWidth:0x20 Description: GRC address for configuration access to PCIE config address 0x94. any write to this PCIE address will cause a GRC write access to the address that's in t this register
#define PXP2_REG_PGL_ADDR_94_F1_SIZE 1
#define PXP2_REG_WR_CDU_TM 0x1206a4UL //ACCESS:R DataWidth:0x4 Description: Bits [1:0] are for fifo 0;Bits [3:2] are for fifo 1
#define PXP2_REG_WR_CDU_TM_SIZE 1
#define PXP2_REG_RQ_OFFCHIP_AT 0x120a00UL //ACCESS:R DataWidth:0x34 Description: NOT USED
#define PXP2_REG_RQ_OFFCHIP_AT_SIZE 64
#define PXP2_REG_PXP2_UNUSED_EMPTY_0 0x1207dcUL //ACCESS:R DataWidth:0x20 Unused empty space
#define PXP2_REG_PXP2_UNUSED_EMPTY_0_SIZE 8
#define PXP2_REG_PXP2_UNUSED_EMPTY_1 0x120954UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PXP2_REG_PXP2_UNUSED_EMPTY_1_SIZE 2
#define PXP2_REG_PXP2_UNUSED_EMPTY_2 0x1209f0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PXP2_REG_PXP2_UNUSED_EMPTY_2_SIZE 4
#define PXP2_REG_PXP2_UNUSED_EMPTY_3 0x120b20UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PXP2_REG_PXP2_UNUSED_EMPTY_3_SIZE 1336
#define PXP2_REG_PXP2_UNUSED_EMPTY_4 0x124000UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PXP2_REG_PXP2_UNUSED_EMPTY_4_SIZE 4096
#define PXP_REG_HST_DISABLE_INPUTS 0x103000UL //ACCESS:RW DataWidth:0x1 Description: debug only: When '1'; inputs to the PSWHST block in clk domain are ignored
#define PXP_REG_HST_ARB_IS_IDLE 0x103004UL //ACCESS:R DataWidth:0x1 Description: debug only: Indication if PSWHST arbiter is idle
#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008UL //ACCESS:R DataWidth:0x8 Description: debug only: A bit mask for all PSWHST arbiter clients. '1' means this client is waiting for the arbiter.
#define PXP_REG_HST_USDM_SWAP_MODE 0x10300cUL //ACCESS:RW DataWidth:0x2 Description: USDM byte swapping mode configuration for host read and write requests
#define PXP_REG_HST_CSDM_SWAP_MODE 0x103010UL //ACCESS:RW DataWidth:0x2 Description: CSDM byte swapping mode configuration for host read and write requests
#define PXP_REG_HST_XSDM_SWAP_MODE 0x103014UL //ACCESS:RW DataWidth:0x2 Description: XSDM byte swapping mode configuration for host read and write requests
#define PXP_REG_HST_TSDM_SWAP_MODE 0x103018UL //ACCESS:RW DataWidth:0x2 Description: TSDM byte swapping mode configuration for host read and write requests
#define PXP_REG_HST_HC_SWAP_MODE 0x10301cUL //ACCESS:RW DataWidth:0x2 Description: HC byte swapping mode configuration for host read and write requests
#define PXP_REG_HST_GRC_SWAP_MODE 0x103020UL //ACCESS:RW DataWidth:0x2 Description: GRC byte swapping mode configuration for host read and write requests
#define PXP_REG_HST_DQ_SWAP_MODE 0x103024UL //ACCESS:RW DataWidth:0x2 Description: DORQ byte swapping mode configuration for host read and write requests
#define PXP_REG_WR_USDM_FULL_TH 0x103028UL //ACCESS:RW DataWidth:0x5 Description: if number of entries in the usdm fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_CSDM_FULL_TH 0x10302cUL //ACCESS:RW DataWidth:0x5 Description: if number of entries in the csdm fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_XSDM_FULL_TH 0x103030UL //ACCESS:RW DataWidth:0x5 Description: if number of entries in the xsdm fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_TSDM_FULL_TH 0x103034UL //ACCESS:RW DataWidth:0x4 Description: if number of entries in the tsdm fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_QM_FULL_TH 0x103038UL //ACCESS:RW DataWidth:0x3 Description: if number of entries in the qm fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_TM_FULL_TH 0x10303cUL //ACCESS:RW DataWidth:0x5 Description: if number of entries in the tm fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_SRC_FULL_TH 0x103040UL //ACCESS:RW DataWidth:0x4 Description: if number of entries in the src fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_DBG_FULL_TH 0x103044UL //ACCESS:RW DataWidth:0x5 Description: if number of entries in the dbg fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_HC_FULL_TH 0x103048UL //ACCESS:RW DataWidth:0x5 Description: if number of entries in the hc fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_DMAE_FULL_TH 0x10304cUL //ACCESS:RW DataWidth:0x4 Description: if number of entries in the dmae input fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_CDU_FULL_TH 0x103050UL //ACCESS:RW DataWidth:0x4 Description: if number of entries in the cdu input fifo is bigger than this number than full will be asserted
#define PXP_REG_WR_USDMDP_FULL_TH 0x103054UL //ACCESS:RW DataWidth:0x4 Description: if number of entries in the usdmdp input fifo is bigger than this number than full will be asserted
#define PXP_REG_DBGSYN_STATUS 0x103058UL //ACCESS:R DataWidth:0x5 Description: debug only: Number of used entries in debug bus sync FIFO
#define PXP_REG_DBG_SELECT 0x10305cUL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PXP to the DBG block) - for selecting a line to output to the DBG block.
#define PXP_REG_DBG_BYTE_ENABLE 0x103060UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from PXP to the DBG block) - for enabling bytes in the selected line (after the select and before the shift)
#define PXP_REG_DBG_SHIFT 0x103064UL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from PXP to the DBG block) - for circular right shifting of the selected line (after the enabling)
#define PXP_REG_PXP_INT_STS_0 0x103068UL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define PXP_PXP_INT_STS_0_REG_RD_POP_ERROR (0x1<<1)
#define PXP_PXP_INT_STS_0_REG_RD_POP_ERROR_SIZE 1
#define PXP_PXP_INT_STS_0_REG_RD_POP_PBF_ERROR (0x1<<2)
#define PXP_PXP_INT_STS_0_REG_RD_POP_PBF_ERROR_SIZE 2
#define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO1_ERR (0x1<<3)
#define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO1_ERR_SIZE 3
#define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO2_ERR (0x1<<4)
#define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO2_ERR_SIZE 4
#define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO3_ERR (0x1<<5)
#define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO3_ERR_SIZE 5
#define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO4_ERR (0x1<<6)
#define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO4_ERR_SIZE 6
#define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO5_ERR (0x1<<7)
#define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO5_ERR_SIZE 7
#define PXP_PXP_INT_STS_0_REG_HST_HDR_SYNC_FIFO_ERR (0x1<<8)
#define PXP_PXP_INT_STS_0_REG_HST_HDR_SYNC_FIFO_ERR_SIZE 8
#define PXP_PXP_INT_STS_0_REG_HST_DATA_SYNC_FIFO_ERR (0x1<<9)
#define PXP_PXP_INT_STS_0_REG_HST_DATA_SYNC_FIFO_ERR_SIZE 9
#define PXP_PXP_INT_STS_0_REG_HST_CPL_SYNC_FIFO_ERR (0x1<<10)
#define PXP_PXP_INT_STS_0_REG_HST_CPL_SYNC_FIFO_ERR_SIZE 10
#define PXP_PXP_INT_STS_0_REG_RQ_PBF_FIFO_OVERFLOW (0x1<<11)
#define PXP_PXP_INT_STS_0_REG_RQ_PBF_FIFO_OVERFLOW_SIZE 11
#define PXP_PXP_INT_STS_0_REG_RQ_SRC_FIFO_OVERFLOW (0x1<<12)
#define PXP_PXP_INT_STS_0_REG_RQ_SRC_FIFO_OVERFLOW_SIZE 12
#define PXP_PXP_INT_STS_0_REG_RQ_QM_FIFO_OVERFLOW (0x1<<13)
#define PXP_PXP_INT_STS_0_REG_RQ_QM_FIFO_OVERFLOW_SIZE 13
#define PXP_PXP_INT_STS_0_REG_RQ_TM_FIFO_OVERFLOW (0x1<<14)
#define PXP_PXP_INT_STS_0_REG_RQ_TM_FIFO_OVERFLOW_SIZE 14
#define PXP_PXP_INT_STS_0_REG_RQ_USDM_FIFO_OVERFLOW (0x1<<15)
#define PXP_PXP_INT_STS_0_REG_RQ_USDM_FIFO_OVERFLOW_SIZE 15
#define PXP_PXP_INT_STS_0_REG_RQ_USDMDP_FIFO_OVERFLOW (0x1<<16)
#define PXP_PXP_INT_STS_0_REG_RQ_USDMDP_FIFO_OVERFLOW_SIZE 16
#define PXP_PXP_INT_STS_0_REG_RQ_XSDM_FIFO_OVERFLOW (0x1<<17)
#define PXP_PXP_INT_STS_0_REG_RQ_XSDM_FIFO_OVERFLOW_SIZE 17
#define PXP_PXP_INT_STS_0_REG_RQ_TSDM_FIFO_OVERFLOW (0x1<<18)
#define PXP_PXP_INT_STS_0_REG_RQ_TSDM_FIFO_OVERFLOW_SIZE 18
#define PXP_PXP_INT_STS_0_REG_RQ_CSDM_FIFO_OVERFLOW (0x1<<19)
#define PXP_PXP_INT_STS_0_REG_RQ_CSDM_FIFO_OVERFLOW_SIZE 19
#define PXP_PXP_INT_STS_0_REG_RQ_CDUWR_FIFO_OVERFLOW (0x1<<20)
#define PXP_PXP_INT_STS_0_REG_RQ_CDUWR_FIFO_OVERFLOW_SIZE 20
#define PXP_PXP_INT_STS_0_REG_RQ_CDURD_FIFO_OVERFLOW (0x1<<21)
#define PXP_PXP_INT_STS_0_REG_RQ_CDURD_FIFO_OVERFLOW_SIZE 21
#define PXP_PXP_INT_STS_0_REG_RQ_DMAE_FIFO_OVERFLOW (0x1<<22)
#define PXP_PXP_INT_STS_0_REG_RQ_DMAE_FIFO_OVERFLOW_SIZE 22
#define PXP_PXP_INT_STS_0_REG_RQ_HC_FIFO_OVERFLOW (0x1<<23)
#define PXP_PXP_INT_STS_0_REG_RQ_HC_FIFO_OVERFLOW_SIZE 23
#define PXP_PXP_INT_STS_0_REG_RQ_DBG_FIFO_OVERFLOW (0x1<<24)
#define PXP_PXP_INT_STS_0_REG_RQ_DBG_FIFO_OVERFLOW_SIZE 24
#define PXP_PXP_INT_STS_0_REG_WR_SRC_FIFO_OVERFLOW (0x1<<25)
#define PXP_PXP_INT_STS_0_REG_WR_SRC_FIFO_OVERFLOW_SIZE 25
#define PXP_PXP_INT_STS_0_REG_WR_QM_FIFO_OVERFLOW (0x1<<26)
#define PXP_PXP_INT_STS_0_REG_WR_QM_FIFO_OVERFLOW_SIZE 26
#define PXP_PXP_INT_STS_0_REG_WR_TM_FIFO_OVERFLOW (0x1<<27)
#define PXP_PXP_INT_STS_0_REG_WR_TM_FIFO_OVERFLOW_SIZE 27
#define PXP_PXP_INT_STS_0_REG_WR_USDM_FIFO_OVERFLOW (0x1<<28)
#define PXP_PXP_INT_STS_0_REG_WR_USDM_FIFO_OVERFLOW_SIZE 28
#define PXP_PXP_INT_STS_0_REG_WR_USDMDP_FIFO_OVERFLOW (0x1<<29)
#define PXP_PXP_INT_STS_0_REG_WR_USDMDP_FIFO_OVERFLOW_SIZE 29
#define PXP_PXP_INT_STS_0_REG_WR_XSDM_FIFO_OVERFLOW (0x1<<30)
#define PXP_PXP_INT_STS_0_REG_WR_XSDM_FIFO_OVERFLOW_SIZE 30
#define PXP_PXP_INT_STS_0_REG_WR_TSDM_FIFO_OVERFLOW (0x1<<31)
#define PXP_PXP_INT_STS_0_REG_WR_TSDM_FIFO_OVERFLOW_SIZE 31
#define PXP_REG_PXP_INT_STS_CLR_0 0x10306cUL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define PXP_PXP_INT_STS_CLR_0_REG_RD_POP_ERROR (0x1<<1)
#define PXP_PXP_INT_STS_CLR_0_REG_RD_POP_ERROR_SIZE 1
#define PXP_PXP_INT_STS_CLR_0_REG_RD_POP_PBF_ERROR (0x1<<2)
#define PXP_PXP_INT_STS_CLR_0_REG_RD_POP_PBF_ERROR_SIZE 2
#define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO1_ERR (0x1<<3)
#define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO1_ERR_SIZE 3
#define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO2_ERR (0x1<<4)
#define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO2_ERR_SIZE 4
#define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO3_ERR (0x1<<5)
#define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO3_ERR_SIZE 5
#define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO4_ERR (0x1<<6)
#define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO4_ERR_SIZE 6
#define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO5_ERR (0x1<<7)
#define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO5_ERR_SIZE 7
#define PXP_PXP_INT_STS_CLR_0_REG_HST_HDR_SYNC_FIFO_ERR (0x1<<8)
#define PXP_PXP_INT_STS_CLR_0_REG_HST_HDR_SYNC_FIFO_ERR_SIZE 8
#define PXP_PXP_INT_STS_CLR_0_REG_HST_DATA_SYNC_FIFO_ERR (0x1<<9)
#define PXP_PXP_INT_STS_CLR_0_REG_HST_DATA_SYNC_FIFO_ERR_SIZE 9
#define PXP_PXP_INT_STS_CLR_0_REG_HST_CPL_SYNC_FIFO_ERR (0x1<<10)
#define PXP_PXP_INT_STS_CLR_0_REG_HST_CPL_SYNC_FIFO_ERR_SIZE 10
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_PBF_FIFO_OVERFLOW (0x1<<11)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_PBF_FIFO_OVERFLOW_SIZE 11
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_SRC_FIFO_OVERFLOW (0x1<<12)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_SRC_FIFO_OVERFLOW_SIZE 12
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_QM_FIFO_OVERFLOW (0x1<<13)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_QM_FIFO_OVERFLOW_SIZE 13
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_TM_FIFO_OVERFLOW (0x1<<14)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_TM_FIFO_OVERFLOW_SIZE 14
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_USDM_FIFO_OVERFLOW (0x1<<15)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_USDM_FIFO_OVERFLOW_SIZE 15
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_USDMDP_FIFO_OVERFLOW (0x1<<16)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_USDMDP_FIFO_OVERFLOW_SIZE 16
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_XSDM_FIFO_OVERFLOW (0x1<<17)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_XSDM_FIFO_OVERFLOW_SIZE 17
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_TSDM_FIFO_OVERFLOW (0x1<<18)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_TSDM_FIFO_OVERFLOW_SIZE 18
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_CSDM_FIFO_OVERFLOW (0x1<<19)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_CSDM_FIFO_OVERFLOW_SIZE 19
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_CDUWR_FIFO_OVERFLOW (0x1<<20)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_CDUWR_FIFO_OVERFLOW_SIZE 20
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_CDURD_FIFO_OVERFLOW (0x1<<21)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_CDURD_FIFO_OVERFLOW_SIZE 21
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_DMAE_FIFO_OVERFLOW (0x1<<22)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_DMAE_FIFO_OVERFLOW_SIZE 22
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_HC_FIFO_OVERFLOW (0x1<<23)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_HC_FIFO_OVERFLOW_SIZE 23
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_DBG_FIFO_OVERFLOW (0x1<<24)
#define PXP_PXP_INT_STS_CLR_0_REG_RQ_DBG_FIFO_OVERFLOW_SIZE 24
#define PXP_PXP_INT_STS_CLR_0_REG_WR_SRC_FIFO_OVERFLOW (0x1<<25)
#define PXP_PXP_INT_STS_CLR_0_REG_WR_SRC_FIFO_OVERFLOW_SIZE 25
#define PXP_PXP_INT_STS_CLR_0_REG_WR_QM_FIFO_OVERFLOW (0x1<<26)
#define PXP_PXP_INT_STS_CLR_0_REG_WR_QM_FIFO_OVERFLOW_SIZE 26
#define PXP_PXP_INT_STS_CLR_0_REG_WR_TM_FIFO_OVERFLOW (0x1<<27)
#define PXP_PXP_INT_STS_CLR_0_REG_WR_TM_FIFO_OVERFLOW_SIZE 27
#define PXP_PXP_INT_STS_CLR_0_REG_WR_USDM_FIFO_OVERFLOW (0x1<<28)
#define PXP_PXP_INT_STS_CLR_0_REG_WR_USDM_FIFO_OVERFLOW_SIZE 28
#define PXP_PXP_INT_STS_CLR_0_REG_WR_USDMDP_FIFO_OVERFLOW (0x1<<29)
#define PXP_PXP_INT_STS_CLR_0_REG_WR_USDMDP_FIFO_OVERFLOW_SIZE 29
#define PXP_PXP_INT_STS_CLR_0_REG_WR_XSDM_FIFO_OVERFLOW (0x1<<30)
#define PXP_PXP_INT_STS_CLR_0_REG_WR_XSDM_FIFO_OVERFLOW_SIZE 30
#define PXP_PXP_INT_STS_CLR_0_REG_WR_TSDM_FIFO_OVERFLOW (0x1<<31)
#define PXP_PXP_INT_STS_CLR_0_REG_WR_TSDM_FIFO_OVERFLOW_SIZE 31
#define PXP_REG_PXP_INT_STS_WR_0 0x103070UL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define PXP_PXP_INT_STS_WR_0_REG_RD_POP_ERROR (0x1<<1)
#define PXP_PXP_INT_STS_WR_0_REG_RD_POP_ERROR_SIZE 1
#define PXP_PXP_INT_STS_WR_0_REG_RD_POP_PBF_ERROR (0x1<<2)
#define PXP_PXP_INT_STS_WR_0_REG_RD_POP_PBF_ERROR_SIZE 2
#define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO1_ERR (0x1<<3)
#define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO1_ERR_SIZE 3
#define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO2_ERR (0x1<<4)
#define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO2_ERR_SIZE 4
#define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO3_ERR (0x1<<5)
#define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO3_ERR_SIZE 5
#define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO4_ERR (0x1<<6)
#define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO4_ERR_SIZE 6
#define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO5_ERR (0x1<<7)
#define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO5_ERR_SIZE 7
#define PXP_PXP_INT_STS_WR_0_REG_HST_HDR_SYNC_FIFO_ERR (0x1<<8)
#define PXP_PXP_INT_STS_WR_0_REG_HST_HDR_SYNC_FIFO_ERR_SIZE 8
#define PXP_PXP_INT_STS_WR_0_REG_HST_DATA_SYNC_FIFO_ERR (0x1<<9)
#define PXP_PXP_INT_STS_WR_0_REG_HST_DATA_SYNC_FIFO_ERR_SIZE 9
#define PXP_PXP_INT_STS_WR_0_REG_HST_CPL_SYNC_FIFO_ERR (0x1<<10)
#define PXP_PXP_INT_STS_WR_0_REG_HST_CPL_SYNC_FIFO_ERR_SIZE 10
#define PXP_PXP_INT_STS_WR_0_REG_RQ_PBF_FIFO_OVERFLOW (0x1<<11)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_PBF_FIFO_OVERFLOW_SIZE 11
#define PXP_PXP_INT_STS_WR_0_REG_RQ_SRC_FIFO_OVERFLOW (0x1<<12)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_SRC_FIFO_OVERFLOW_SIZE 12
#define PXP_PXP_INT_STS_WR_0_REG_RQ_QM_FIFO_OVERFLOW (0x1<<13)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_QM_FIFO_OVERFLOW_SIZE 13
#define PXP_PXP_INT_STS_WR_0_REG_RQ_TM_FIFO_OVERFLOW (0x1<<14)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_TM_FIFO_OVERFLOW_SIZE 14
#define PXP_PXP_INT_STS_WR_0_REG_RQ_USDM_FIFO_OVERFLOW (0x1<<15)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_USDM_FIFO_OVERFLOW_SIZE 15
#define PXP_PXP_INT_STS_WR_0_REG_RQ_USDMDP_FIFO_OVERFLOW (0x1<<16)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_USDMDP_FIFO_OVERFLOW_SIZE 16
#define PXP_PXP_INT_STS_WR_0_REG_RQ_XSDM_FIFO_OVERFLOW (0x1<<17)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_XSDM_FIFO_OVERFLOW_SIZE 17
#define PXP_PXP_INT_STS_WR_0_REG_RQ_TSDM_FIFO_OVERFLOW (0x1<<18)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_TSDM_FIFO_OVERFLOW_SIZE 18
#define PXP_PXP_INT_STS_WR_0_REG_RQ_CSDM_FIFO_OVERFLOW (0x1<<19)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_CSDM_FIFO_OVERFLOW_SIZE 19
#define PXP_PXP_INT_STS_WR_0_REG_RQ_CDUWR_FIFO_OVERFLOW (0x1<<20)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_CDUWR_FIFO_OVERFLOW_SIZE 20
#define PXP_PXP_INT_STS_WR_0_REG_RQ_CDURD_FIFO_OVERFLOW (0x1<<21)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_CDURD_FIFO_OVERFLOW_SIZE 21
#define PXP_PXP_INT_STS_WR_0_REG_RQ_DMAE_FIFO_OVERFLOW (0x1<<22)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_DMAE_FIFO_OVERFLOW_SIZE 22
#define PXP_PXP_INT_STS_WR_0_REG_RQ_HC_FIFO_OVERFLOW (0x1<<23)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_HC_FIFO_OVERFLOW_SIZE 23
#define PXP_PXP_INT_STS_WR_0_REG_RQ_DBG_FIFO_OVERFLOW (0x1<<24)
#define PXP_PXP_INT_STS_WR_0_REG_RQ_DBG_FIFO_OVERFLOW_SIZE 24
#define PXP_PXP_INT_STS_WR_0_REG_WR_SRC_FIFO_OVERFLOW (0x1<<25)
#define PXP_PXP_INT_STS_WR_0_REG_WR_SRC_FIFO_OVERFLOW_SIZE 25
#define PXP_PXP_INT_STS_WR_0_REG_WR_QM_FIFO_OVERFLOW (0x1<<26)
#define PXP_PXP_INT_STS_WR_0_REG_WR_QM_FIFO_OVERFLOW_SIZE 26
#define PXP_PXP_INT_STS_WR_0_REG_WR_TM_FIFO_OVERFLOW (0x1<<27)
#define PXP_PXP_INT_STS_WR_0_REG_WR_TM_FIFO_OVERFLOW_SIZE 27
#define PXP_PXP_INT_STS_WR_0_REG_WR_USDM_FIFO_OVERFLOW (0x1<<28)
#define PXP_PXP_INT_STS_WR_0_REG_WR_USDM_FIFO_OVERFLOW_SIZE 28
#define PXP_PXP_INT_STS_WR_0_REG_WR_USDMDP_FIFO_OVERFLOW (0x1<<29)
#define PXP_PXP_INT_STS_WR_0_REG_WR_USDMDP_FIFO_OVERFLOW_SIZE 29
#define PXP_PXP_INT_STS_WR_0_REG_WR_XSDM_FIFO_OVERFLOW (0x1<<30)
#define PXP_PXP_INT_STS_WR_0_REG_WR_XSDM_FIFO_OVERFLOW_SIZE 30
#define PXP_PXP_INT_STS_WR_0_REG_WR_TSDM_FIFO_OVERFLOW (0x1<<31)
#define PXP_PXP_INT_STS_WR_0_REG_WR_TSDM_FIFO_OVERFLOW_SIZE 31
#define PXP_REG_PXP_INT_MASK_0 0x103074UL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define PXP_PXP_INT_MASK_0_REG_RD_POP_ERROR (0x1<<1)
#define PXP_PXP_INT_MASK_0_REG_RD_POP_ERROR_SIZE 1
#define PXP_PXP_INT_MASK_0_REG_RD_POP_PBF_ERROR (0x1<<2)
#define PXP_PXP_INT_MASK_0_REG_RD_POP_PBF_ERROR_SIZE 2
#define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO1_ERR (0x1<<3)
#define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO1_ERR_SIZE 3
#define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO2_ERR (0x1<<4)
#define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO2_ERR_SIZE 4
#define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO3_ERR (0x1<<5)
#define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO3_ERR_SIZE 5
#define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO4_ERR (0x1<<6)
#define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO4_ERR_SIZE 6
#define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO5_ERR (0x1<<7)
#define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO5_ERR_SIZE 7
#define PXP_PXP_INT_MASK_0_REG_HST_HDR_SYNC_FIFO_ERR (0x1<<8)
#define PXP_PXP_INT_MASK_0_REG_HST_HDR_SYNC_FIFO_ERR_SIZE 8
#define PXP_PXP_INT_MASK_0_REG_HST_DATA_SYNC_FIFO_ERR (0x1<<9)
#define PXP_PXP_INT_MASK_0_REG_HST_DATA_SYNC_FIFO_ERR_SIZE 9
#define PXP_PXP_INT_MASK_0_REG_HST_CPL_SYNC_FIFO_ERR (0x1<<10)
#define PXP_PXP_INT_MASK_0_REG_HST_CPL_SYNC_FIFO_ERR_SIZE 10
#define PXP_PXP_INT_MASK_0_REG_RQ_PBF_FIFO_OVERFLOW (0x1<<11)
#define PXP_PXP_INT_MASK_0_REG_RQ_PBF_FIFO_OVERFLOW_SIZE 11
#define PXP_PXP_INT_MASK_0_REG_RQ_SRC_FIFO_OVERFLOW (0x1<<12)
#define PXP_PXP_INT_MASK_0_REG_RQ_SRC_FIFO_OVERFLOW_SIZE 12
#define PXP_PXP_INT_MASK_0_REG_RQ_QM_FIFO_OVERFLOW (0x1<<13)
#define PXP_PXP_INT_MASK_0_REG_RQ_QM_FIFO_OVERFLOW_SIZE 13
#define PXP_PXP_INT_MASK_0_REG_RQ_TM_FIFO_OVERFLOW (0x1<<14)
#define PXP_PXP_INT_MASK_0_REG_RQ_TM_FIFO_OVERFLOW_SIZE 14
#define PXP_PXP_INT_MASK_0_REG_RQ_USDM_FIFO_OVERFLOW (0x1<<15)
#define PXP_PXP_INT_MASK_0_REG_RQ_USDM_FIFO_OVERFLOW_SIZE 15
#define PXP_PXP_INT_MASK_0_REG_RQ_USDMDP_FIFO_OVERFLOW (0x1<<16)
#define PXP_PXP_INT_MASK_0_REG_RQ_USDMDP_FIFO_OVERFLOW_SIZE 16
#define PXP_PXP_INT_MASK_0_REG_RQ_XSDM_FIFO_OVERFLOW (0x1<<17)
#define PXP_PXP_INT_MASK_0_REG_RQ_XSDM_FIFO_OVERFLOW_SIZE 17
#define PXP_PXP_INT_MASK_0_REG_RQ_TSDM_FIFO_OVERFLOW (0x1<<18)
#define PXP_PXP_INT_MASK_0_REG_RQ_TSDM_FIFO_OVERFLOW_SIZE 18
#define PXP_PXP_INT_MASK_0_REG_RQ_CSDM_FIFO_OVERFLOW (0x1<<19)
#define PXP_PXP_INT_MASK_0_REG_RQ_CSDM_FIFO_OVERFLOW_SIZE 19
#define PXP_PXP_INT_MASK_0_REG_RQ_CDUWR_FIFO_OVERFLOW (0x1<<20)
#define PXP_PXP_INT_MASK_0_REG_RQ_CDUWR_FIFO_OVERFLOW_SIZE 20
#define PXP_PXP_INT_MASK_0_REG_RQ_CDURD_FIFO_OVERFLOW (0x1<<21)
#define PXP_PXP_INT_MASK_0_REG_RQ_CDURD_FIFO_OVERFLOW_SIZE 21
#define PXP_PXP_INT_MASK_0_REG_RQ_DMAE_FIFO_OVERFLOW (0x1<<22)
#define PXP_PXP_INT_MASK_0_REG_RQ_DMAE_FIFO_OVERFLOW_SIZE 22
#define PXP_PXP_INT_MASK_0_REG_RQ_HC_FIFO_OVERFLOW (0x1<<23)
#define PXP_PXP_INT_MASK_0_REG_RQ_HC_FIFO_OVERFLOW_SIZE 23
#define PXP_PXP_INT_MASK_0_REG_RQ_DBG_FIFO_OVERFLOW (0x1<<24)
#define PXP_PXP_INT_MASK_0_REG_RQ_DBG_FIFO_OVERFLOW_SIZE 24
#define PXP_PXP_INT_MASK_0_REG_WR_SRC_FIFO_OVERFLOW (0x1<<25)
#define PXP_PXP_INT_MASK_0_REG_WR_SRC_FIFO_OVERFLOW_SIZE 25
#define PXP_PXP_INT_MASK_0_REG_WR_QM_FIFO_OVERFLOW (0x1<<26)
#define PXP_PXP_INT_MASK_0_REG_WR_QM_FIFO_OVERFLOW_SIZE 26
#define PXP_PXP_INT_MASK_0_REG_WR_TM_FIFO_OVERFLOW (0x1<<27)
#define PXP_PXP_INT_MASK_0_REG_WR_TM_FIFO_OVERFLOW_SIZE 27
#define PXP_PXP_INT_MASK_0_REG_WR_USDM_FIFO_OVERFLOW (0x1<<28)
#define PXP_PXP_INT_MASK_0_REG_WR_USDM_FIFO_OVERFLOW_SIZE 28
#define PXP_PXP_INT_MASK_0_REG_WR_USDMDP_FIFO_OVERFLOW (0x1<<29)
#define PXP_PXP_INT_MASK_0_REG_WR_USDMDP_FIFO_OVERFLOW_SIZE 29
#define PXP_PXP_INT_MASK_0_REG_WR_XSDM_FIFO_OVERFLOW (0x1<<30)
#define PXP_PXP_INT_MASK_0_REG_WR_XSDM_FIFO_OVERFLOW_SIZE 30
#define PXP_PXP_INT_MASK_0_REG_WR_TSDM_FIFO_OVERFLOW (0x1<<31)
#define PXP_PXP_INT_MASK_0_REG_WR_TSDM_FIFO_OVERFLOW_SIZE 31
#define PXP_REG_PXP_INT_STS_1 0x103078UL //ACCESS:R DataWidth:0x8 Description: Interrupt register #1 read
#define PXP_PXP_INT_STS_1_REG_WR_CSDM_FIFO_OVERFLOW (0x1<<0)
#define PXP_PXP_INT_STS_1_REG_WR_CSDM_FIFO_OVERFLOW_SIZE 0
#define PXP_PXP_INT_STS_1_REG_WR_CDUWR_FIFO_OVERFLOW (0x1<<1)
#define PXP_PXP_INT_STS_1_REG_WR_CDUWR_FIFO_OVERFLOW_SIZE 1
#define PXP_PXP_INT_STS_1_REG_WR_DBG_FIFO_OVERFLOW (0x1<<2)
#define PXP_PXP_INT_STS_1_REG_WR_DBG_FIFO_OVERFLOW_SIZE 2
#define PXP_PXP_INT_STS_1_REG_WR_DMAE_FIFO_OVERFLOW (0x1<<3)
#define PXP_PXP_INT_STS_1_REG_WR_DMAE_FIFO_OVERFLOW_SIZE 3
#define PXP_PXP_INT_STS_1_REG_WR_HC_FIFO_OVERFLOW (0x1<<4)
#define PXP_PXP_INT_STS_1_REG_WR_HC_FIFO_OVERFLOW_SIZE 4
#define PXP_PXP_INT_STS_1_REG_HST_VF_DISABLED_ACCESS (0x1<<5)
#define PXP_PXP_INT_STS_1_REG_HST_VF_DISABLED_ACCESS_SIZE 5
#define PXP_PXP_INT_STS_1_REG_HST_INCORRECT_ACCESS (0x1<<6)
#define PXP_PXP_INT_STS_1_REG_HST_INCORRECT_ACCESS_SIZE 6
#define PXP_PXP_INT_STS_1_REG_HST_PERMISSION_VIOLATION (0x1<<7)
#define PXP_PXP_INT_STS_1_REG_HST_PERMISSION_VIOLATION_SIZE 7
#define PXP_REG_PXP_INT_STS_CLR_1 0x10307cUL //ACCESS:RC DataWidth:0x8 Description: Interrupt register #1 read clear
#define PXP_PXP_INT_STS_CLR_1_REG_WR_CSDM_FIFO_OVERFLOW (0x1<<0)
#define PXP_PXP_INT_STS_CLR_1_REG_WR_CSDM_FIFO_OVERFLOW_SIZE 0
#define PXP_PXP_INT_STS_CLR_1_REG_WR_CDUWR_FIFO_OVERFLOW (0x1<<1)
#define PXP_PXP_INT_STS_CLR_1_REG_WR_CDUWR_FIFO_OVERFLOW_SIZE 1
#define PXP_PXP_INT_STS_CLR_1_REG_WR_DBG_FIFO_OVERFLOW (0x1<<2)
#define PXP_PXP_INT_STS_CLR_1_REG_WR_DBG_FIFO_OVERFLOW_SIZE 2
#define PXP_PXP_INT_STS_CLR_1_REG_WR_DMAE_FIFO_OVERFLOW (0x1<<3)
#define PXP_PXP_INT_STS_CLR_1_REG_WR_DMAE_FIFO_OVERFLOW_SIZE 3
#define PXP_PXP_INT_STS_CLR_1_REG_WR_HC_FIFO_OVERFLOW (0x1<<4)
#define PXP_PXP_INT_STS_CLR_1_REG_WR_HC_FIFO_OVERFLOW_SIZE 4
#define PXP_PXP_INT_STS_CLR_1_REG_HST_VF_DISABLED_ACCESS (0x1<<5)
#define PXP_PXP_INT_STS_CLR_1_REG_HST_VF_DISABLED_ACCESS_SIZE 5
#define PXP_PXP_INT_STS_CLR_1_REG_HST_INCORRECT_ACCESS (0x1<<6)
#define PXP_PXP_INT_STS_CLR_1_REG_HST_INCORRECT_ACCESS_SIZE 6
#define PXP_PXP_INT_STS_CLR_1_REG_HST_PERMISSION_VIOLATION (0x1<<7)
#define PXP_PXP_INT_STS_CLR_1_REG_HST_PERMISSION_VIOLATION_SIZE 7
#define PXP_REG_PXP_INT_STS_WR_1 0x103080UL //ACCESS:WR DataWidth:0x8 Description: Interrupt register #1 bit set or clear
#define PXP_PXP_INT_STS_WR_1_REG_WR_CSDM_FIFO_OVERFLOW (0x1<<0)
#define PXP_PXP_INT_STS_WR_1_REG_WR_CSDM_FIFO_OVERFLOW_SIZE 0
#define PXP_PXP_INT_STS_WR_1_REG_WR_CDUWR_FIFO_OVERFLOW (0x1<<1)
#define PXP_PXP_INT_STS_WR_1_REG_WR_CDUWR_FIFO_OVERFLOW_SIZE 1
#define PXP_PXP_INT_STS_WR_1_REG_WR_DBG_FIFO_OVERFLOW (0x1<<2)
#define PXP_PXP_INT_STS_WR_1_REG_WR_DBG_FIFO_OVERFLOW_SIZE 2
#define PXP_PXP_INT_STS_WR_1_REG_WR_DMAE_FIFO_OVERFLOW (0x1<<3)
#define PXP_PXP_INT_STS_WR_1_REG_WR_DMAE_FIFO_OVERFLOW_SIZE 3
#define PXP_PXP_INT_STS_WR_1_REG_WR_HC_FIFO_OVERFLOW (0x1<<4)
#define PXP_PXP_INT_STS_WR_1_REG_WR_HC_FIFO_OVERFLOW_SIZE 4
#define PXP_PXP_INT_STS_WR_1_REG_HST_VF_DISABLED_ACCESS (0x1<<5)
#define PXP_PXP_INT_STS_WR_1_REG_HST_VF_DISABLED_ACCESS_SIZE 5
#define PXP_PXP_INT_STS_WR_1_REG_HST_INCORRECT_ACCESS (0x1<<6)
#define PXP_PXP_INT_STS_WR_1_REG_HST_INCORRECT_ACCESS_SIZE 6
#define PXP_PXP_INT_STS_WR_1_REG_HST_PERMISSION_VIOLATION (0x1<<7)
#define PXP_PXP_INT_STS_WR_1_REG_HST_PERMISSION_VIOLATION_SIZE 7
#define PXP_REG_PXP_INT_MASK_1 0x103084UL //ACCESS:RW DataWidth:0x8 Description: Interrupt mask register #1 read/write
#define PXP_PXP_INT_MASK_1_REG_WR_CSDM_FIFO_OVERFLOW (0x1<<0)
#define PXP_PXP_INT_MASK_1_REG_WR_CSDM_FIFO_OVERFLOW_SIZE 0
#define PXP_PXP_INT_MASK_1_REG_WR_CDUWR_FIFO_OVERFLOW (0x1<<1)
#define PXP_PXP_INT_MASK_1_REG_WR_CDUWR_FIFO_OVERFLOW_SIZE 1
#define PXP_PXP_INT_MASK_1_REG_WR_DBG_FIFO_OVERFLOW (0x1<<2)
#define PXP_PXP_INT_MASK_1_REG_WR_DBG_FIFO_OVERFLOW_SIZE 2
#define PXP_PXP_INT_MASK_1_REG_WR_DMAE_FIFO_OVERFLOW (0x1<<3)
#define PXP_PXP_INT_MASK_1_REG_WR_DMAE_FIFO_OVERFLOW_SIZE 3
#define PXP_PXP_INT_MASK_1_REG_WR_HC_FIFO_OVERFLOW (0x1<<4)
#define PXP_PXP_INT_MASK_1_REG_WR_HC_FIFO_OVERFLOW_SIZE 4
#define PXP_PXP_INT_MASK_1_REG_HST_VF_DISABLED_ACCESS (0x1<<5)
#define PXP_PXP_INT_MASK_1_REG_HST_VF_DISABLED_ACCESS_SIZE 5
#define PXP_PXP_INT_MASK_1_REG_HST_INCORRECT_ACCESS (0x1<<6)
#define PXP_PXP_INT_MASK_1_REG_HST_INCORRECT_ACCESS_SIZE 6
#define PXP_PXP_INT_MASK_1_REG_HST_PERMISSION_VIOLATION (0x1<<7)
#define PXP_PXP_INT_MASK_1_REG_HST_PERMISSION_VIOLATION_SIZE 7
#define PXP_REG_PXP_PRTY_STS 0x103088UL //ACCESS:R DataWidth:0x1b Description: Parity register #0 read
#define PXP_PXP_PRTY_STS_REG_PARITY (0x1<<0)
#define PXP_PXP_PRTY_STS_REG_PARITY_SIZE 0
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO0 (0x1<<1)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO0_SIZE 1
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO1 (0x1<<2)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO1_SIZE 2
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO2 (0x1<<3)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO2_SIZE 3
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO3 (0x1<<4)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO3_SIZE 4
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO4 (0x1<<5)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO4_SIZE 5
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO5 (0x1<<6)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO5_SIZE 6
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO6 (0x1<<7)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO6_SIZE 7
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO7 (0x1<<8)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO7_SIZE 8
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO8 (0x1<<9)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO8_SIZE 9
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO9 (0x1<<10)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO9_SIZE 10
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO10 (0x1<<11)
#define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO10_SIZE 11
#define PXP_PXP_PRTY_STS_REG_HST_HDR_SYNC_FIFO (0x1<<12)
#define PXP_PXP_PRTY_STS_REG_HST_HDR_SYNC_FIFO_SIZE 12
#define PXP_PXP_PRTY_STS_REG_HST_DATA_SYNC_FIFO1 (0x1<<13)
#define PXP_PXP_PRTY_STS_REG_HST_DATA_SYNC_FIFO1_SIZE 13
#define PXP_PXP_PRTY_STS_REG_HST_DATA_SYNC_FIFO2 (0x1<<14)
#define PXP_PXP_PRTY_STS_REG_HST_DATA_SYNC_FIFO2_SIZE 14
#define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO1 (0x1<<15)
#define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO1_SIZE 15
#define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO2 (0x1<<16)
#define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO2_SIZE 16
#define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO3 (0x1<<17)
#define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO3_SIZE 17
#define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO4 (0x1<<18)
#define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO4_SIZE 18
#define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO5 (0x1<<19)
#define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO5_SIZE 19
#define PXP_PXP_PRTY_STS_REG_HST_INBND_INT_MEM1 (0x1<<20)
#define PXP_PXP_PRTY_STS_REG_HST_INBND_INT_MEM1_SIZE 20
#define PXP_PXP_PRTY_STS_REG_HST_INBND_INT_MEM2 (0x1<<21)
#define PXP_PXP_PRTY_STS_REG_HST_INBND_INT_MEM2_SIZE 21
#define PXP_PXP_PRTY_STS_REG_HST_INBND_INT_MEM3 (0x1<<22)
#define PXP_PXP_PRTY_STS_REG_HST_INBND_INT_MEM3_SIZE 22
#define PXP_PXP_PRTY_STS_REG_RQ_WDONE_FIFO_PRTY (0x1<<23)
#define PXP_PXP_PRTY_STS_REG_RQ_WDONE_FIFO_PRTY_SIZE 23
#define PXP_PXP_PRTY_STS_REG_RQ_PHY_FIFO_PRTY (0x1<<24)
#define PXP_PXP_PRTY_STS_REG_RQ_PHY_FIFO_PRTY_SIZE 24
#define PXP_PXP_PRTY_STS_REG_DBGSYN_FIFO (0x1<<25)
#define PXP_PXP_PRTY_STS_REG_DBGSYN_FIFO_SIZE 25
#define PXP_PXP_PRTY_STS_REG_PERM_TABLE (0x1<<26)
#define PXP_PXP_PRTY_STS_REG_PERM_TABLE_SIZE 26
#define PXP_REG_PXP_PRTY_STS_CLR 0x10308cUL //ACCESS:RC DataWidth:0x1b Description: Parity register #0 read clear
#define PXP_PXP_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define PXP_PXP_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO0 (0x1<<1)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO0_SIZE 1
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO1 (0x1<<2)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO1_SIZE 2
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO2 (0x1<<3)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO2_SIZE 3
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO3 (0x1<<4)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO3_SIZE 4
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO4 (0x1<<5)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO4_SIZE 5
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO5 (0x1<<6)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO5_SIZE 6
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO6 (0x1<<7)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO6_SIZE 7
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO7 (0x1<<8)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO7_SIZE 8
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO8 (0x1<<9)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO8_SIZE 9
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO9 (0x1<<10)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO9_SIZE 10
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO10 (0x1<<11)
#define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO10_SIZE 11
#define PXP_PXP_PRTY_STS_CLR_REG_HST_HDR_SYNC_FIFO (0x1<<12)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_HDR_SYNC_FIFO_SIZE 12
#define PXP_PXP_PRTY_STS_CLR_REG_HST_DATA_SYNC_FIFO1 (0x1<<13)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_DATA_SYNC_FIFO1_SIZE 13
#define PXP_PXP_PRTY_STS_CLR_REG_HST_DATA_SYNC_FIFO2 (0x1<<14)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_DATA_SYNC_FIFO2_SIZE 14
#define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO1 (0x1<<15)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO1_SIZE 15
#define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO2 (0x1<<16)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO2_SIZE 16
#define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO3 (0x1<<17)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO3_SIZE 17
#define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO4 (0x1<<18)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO4_SIZE 18
#define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO5 (0x1<<19)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO5_SIZE 19
#define PXP_PXP_PRTY_STS_CLR_REG_HST_INBND_INT_MEM1 (0x1<<20)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_INBND_INT_MEM1_SIZE 20
#define PXP_PXP_PRTY_STS_CLR_REG_HST_INBND_INT_MEM2 (0x1<<21)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_INBND_INT_MEM2_SIZE 21
#define PXP_PXP_PRTY_STS_CLR_REG_HST_INBND_INT_MEM3 (0x1<<22)
#define PXP_PXP_PRTY_STS_CLR_REG_HST_INBND_INT_MEM3_SIZE 22
#define PXP_PXP_PRTY_STS_CLR_REG_RQ_WDONE_FIFO_PRTY (0x1<<23)
#define PXP_PXP_PRTY_STS_CLR_REG_RQ_WDONE_FIFO_PRTY_SIZE 23
#define PXP_PXP_PRTY_STS_CLR_REG_RQ_PHY_FIFO_PRTY (0x1<<24)
#define PXP_PXP_PRTY_STS_CLR_REG_RQ_PHY_FIFO_PRTY_SIZE 24
#define PXP_PXP_PRTY_STS_CLR_REG_DBGSYN_FIFO (0x1<<25)
#define PXP_PXP_PRTY_STS_CLR_REG_DBGSYN_FIFO_SIZE 25
#define PXP_PXP_PRTY_STS_CLR_REG_PERM_TABLE (0x1<<26)
#define PXP_PXP_PRTY_STS_CLR_REG_PERM_TABLE_SIZE 26
#define PXP_REG_PXP_PRTY_STS_WR 0x103090UL //ACCESS:WR DataWidth:0x1b Description: Parity register #0 bit set or clear
#define PXP_PXP_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define PXP_PXP_PRTY_STS_WR_REG_PARITY_SIZE 0
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO0 (0x1<<1)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO0_SIZE 1
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO1 (0x1<<2)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO1_SIZE 2
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO2 (0x1<<3)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO2_SIZE 3
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO3 (0x1<<4)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO3_SIZE 4
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO4 (0x1<<5)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO4_SIZE 5
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO5 (0x1<<6)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO5_SIZE 6
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO6 (0x1<<7)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO6_SIZE 7
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO7 (0x1<<8)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO7_SIZE 8
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO8 (0x1<<9)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO8_SIZE 9
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO9 (0x1<<10)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO9_SIZE 10
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO10 (0x1<<11)
#define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO10_SIZE 11
#define PXP_PXP_PRTY_STS_WR_REG_HST_HDR_SYNC_FIFO (0x1<<12)
#define PXP_PXP_PRTY_STS_WR_REG_HST_HDR_SYNC_FIFO_SIZE 12
#define PXP_PXP_PRTY_STS_WR_REG_HST_DATA_SYNC_FIFO1 (0x1<<13)
#define PXP_PXP_PRTY_STS_WR_REG_HST_DATA_SYNC_FIFO1_SIZE 13
#define PXP_PXP_PRTY_STS_WR_REG_HST_DATA_SYNC_FIFO2 (0x1<<14)
#define PXP_PXP_PRTY_STS_WR_REG_HST_DATA_SYNC_FIFO2_SIZE 14
#define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO1 (0x1<<15)
#define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO1_SIZE 15
#define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO2 (0x1<<16)
#define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO2_SIZE 16
#define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO3 (0x1<<17)
#define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO3_SIZE 17
#define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO4 (0x1<<18)
#define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO4_SIZE 18
#define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO5 (0x1<<19)
#define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO5_SIZE 19
#define PXP_PXP_PRTY_STS_WR_REG_HST_INBND_INT_MEM1 (0x1<<20)
#define PXP_PXP_PRTY_STS_WR_REG_HST_INBND_INT_MEM1_SIZE 20
#define PXP_PXP_PRTY_STS_WR_REG_HST_INBND_INT_MEM2 (0x1<<21)
#define PXP_PXP_PRTY_STS_WR_REG_HST_INBND_INT_MEM2_SIZE 21
#define PXP_PXP_PRTY_STS_WR_REG_HST_INBND_INT_MEM3 (0x1<<22)
#define PXP_PXP_PRTY_STS_WR_REG_HST_INBND_INT_MEM3_SIZE 22
#define PXP_PXP_PRTY_STS_WR_REG_RQ_WDONE_FIFO_PRTY (0x1<<23)
#define PXP_PXP_PRTY_STS_WR_REG_RQ_WDONE_FIFO_PRTY_SIZE 23
#define PXP_PXP_PRTY_STS_WR_REG_RQ_PHY_FIFO_PRTY (0x1<<24)
#define PXP_PXP_PRTY_STS_WR_REG_RQ_PHY_FIFO_PRTY_SIZE 24
#define PXP_PXP_PRTY_STS_WR_REG_DBGSYN_FIFO (0x1<<25)
#define PXP_PXP_PRTY_STS_WR_REG_DBGSYN_FIFO_SIZE 25
#define PXP_PXP_PRTY_STS_WR_REG_PERM_TABLE (0x1<<26)
#define PXP_PXP_PRTY_STS_WR_REG_PERM_TABLE_SIZE 26
#define PXP_REG_PXP_PRTY_MASK 0x103094UL //ACCESS:RW DataWidth:0x1b Description: Parity mask register #0 read/write
#define PXP_PXP_PRTY_MASK_REG_PARITY (0x1<<0)
#define PXP_PXP_PRTY_MASK_REG_PARITY_SIZE 0
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO0 (0x1<<1)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO0_SIZE 1
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO1 (0x1<<2)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO1_SIZE 2
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO2 (0x1<<3)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO2_SIZE 3
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO3 (0x1<<4)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO3_SIZE 4
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO4 (0x1<<5)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO4_SIZE 5
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO5 (0x1<<6)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO5_SIZE 6
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO6 (0x1<<7)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO6_SIZE 7
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO7 (0x1<<8)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO7_SIZE 8
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO8 (0x1<<9)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO8_SIZE 9
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO9 (0x1<<10)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO9_SIZE 10
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO10 (0x1<<11)
#define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO10_SIZE 11
#define PXP_PXP_PRTY_MASK_REG_HST_HDR_SYNC_FIFO (0x1<<12)
#define PXP_PXP_PRTY_MASK_REG_HST_HDR_SYNC_FIFO_SIZE 12
#define PXP_PXP_PRTY_MASK_REG_HST_DATA_SYNC_FIFO1 (0x1<<13)
#define PXP_PXP_PRTY_MASK_REG_HST_DATA_SYNC_FIFO1_SIZE 13
#define PXP_PXP_PRTY_MASK_REG_HST_DATA_SYNC_FIFO2 (0x1<<14)
#define PXP_PXP_PRTY_MASK_REG_HST_DATA_SYNC_FIFO2_SIZE 14
#define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO1 (0x1<<15)
#define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO1_SIZE 15
#define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO2 (0x1<<16)
#define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO2_SIZE 16
#define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO3 (0x1<<17)
#define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO3_SIZE 17
#define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO4 (0x1<<18)
#define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO4_SIZE 18
#define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO5 (0x1<<19)
#define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO5_SIZE 19
#define PXP_PXP_PRTY_MASK_REG_HST_INBND_INT_MEM1 (0x1<<20)
#define PXP_PXP_PRTY_MASK_REG_HST_INBND_INT_MEM1_SIZE 20
#define PXP_PXP_PRTY_MASK_REG_HST_INBND_INT_MEM2 (0x1<<21)
#define PXP_PXP_PRTY_MASK_REG_HST_INBND_INT_MEM2_SIZE 21
#define PXP_PXP_PRTY_MASK_REG_HST_INBND_INT_MEM3 (0x1<<22)
#define PXP_PXP_PRTY_MASK_REG_HST_INBND_INT_MEM3_SIZE 22
#define PXP_PXP_PRTY_MASK_REG_RQ_WDONE_FIFO_PRTY (0x1<<23)
#define PXP_PXP_PRTY_MASK_REG_RQ_WDONE_FIFO_PRTY_SIZE 23
#define PXP_PXP_PRTY_MASK_REG_RQ_PHY_FIFO_PRTY (0x1<<24)
#define PXP_PXP_PRTY_MASK_REG_RQ_PHY_FIFO_PRTY_SIZE 24
#define PXP_PXP_PRTY_MASK_REG_DBGSYN_FIFO (0x1<<25)
#define PXP_PXP_PRTY_MASK_REG_DBGSYN_FIFO_SIZE 25
#define PXP_PXP_PRTY_MASK_REG_PERM_TABLE (0x1<<26)
#define PXP_PXP_PRTY_MASK_REG_PERM_TABLE_SIZE 26
#define PXP_REG_HST_HOST_STRICT_PRIORITY 0x103098UL //ACCESS:RW DataWidth:0x1 Description: When 1; host requests have strict priority on internal write requests; as in A0. When 0; arbiter alternately chooses host requests and internal write requests.
#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309cUL //ACCESS:R DataWidth:0x6 Description: debug only: A bit mask for all PSWHST internal write clients. '1' means this PSWHST is discarding inputs from this client. Each bit should update accoring to 'hst_discard_internal_writes' register when the state machine is idle.
#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0UL //ACCESS:R DataWidth:0x1 Description: debug only: '1' means this PSWHST is discarding doorbells. This bit should update accoring to 'hst_discard_doorbells' register when the state machine is idle
#define PXP_REG_HST_HDR_MEM_TM 0x1030acUL //ACCESS:RW DataWidth:0x2 Description: TM bits of hst_hdr_mem memory
#define PXP_REG_PXP_ECO_RSRV 0x1030b0UL //ACCESS:RW DataWidth:0xc Multi Field Register
#define PXP_PXP_ECO_RSRV_REG_RQ_ECO_RESERVED (0x3f<<0)
#define PXP_PXP_ECO_RSRV_REG_RQ_ECO_RESERVED_SIZE 0
#define PXP_PXP_ECO_RSRV_REG_WR_ECO_RESERVED (0x3f<<6)
#define PXP_PXP_ECO_RSRV_REG_WR_ECO_RESERVED_SIZE 6
#define PXP_REG_HST_VF_DISABLED_ERROR_DATA 0x1030b8UL //ACCESS:R DataWidth:0xf Description: The FID of the first access to a disabled VF; the format is [14:12] - pfid; [11:6] - vfid; [5] - vf_valid; [4:1] - client (0 USDM; 1 CSDM; 2 XSDM; 3 TSDM; 4 HC; 5 GRC; 6 DQ; 7 RESERVED SPACE; 8 ATC); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register
#define PXP_REG_HST_VF_DISABLED_ERROR_VALID 0x1030bcUL //ACCESS:R DataWidth:0x1 Description: 1 - An error request is logged and wasn't handled yet. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1)
#define PXP_REG_HST_VF_DISABLED_ERROR_ADDRESS 0x1030c0UL //ACCESS:R DataWidth:0x20 Description: The address of the first access to a disabled VF.
#define PXP_REG_HST_SDM_MAX_LENGTH 0x1030c4UL //ACCESS:RW DataWidth:0x6 Description: Maximum write transaction data in DWs that is sent to SDMs and IGU. Write requests with bigger length are discarded in PSWHST.
#define PXP_REG_HST_INCORRECT_ACCESS_DATA 0x1030c8UL //ACCESS:R DataWidth:0x1f Description: The data of the first incorrect access. the format is: [30:23] - length; [22:15] - byte enable; [14:12] - pfid; [11:6] - vfid; [5] - vf_valid; [4:1] - client (0 USDM; 1 CSDM; 2 XSDM; 3 TSDM; 4 HC; 5 GRC; 6 DQ; 7 RESERVED SPACE; 8 ATC); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register
#define PXP_REG_HST_INCORRECT_ACCESS_VALID 0x1030ccUL //ACCESS:R DataWidth:0x1 Description: 1 - An incorrect access is logged. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1)
#define PXP_REG_HST_INCORRECT_ACCESS_ADDRESS 0x1030d0UL //ACCESS:R DataWidth:0x20 Description: The address of the first incorrect access (length and alignement combination).
#define PXP_REG_HST_ZONE_PERM_TABLE_INIT 0x1030d8UL //ACCESS:RW DataWidth:0x1 Description: Start the Init sequence for the zone permission table
#define PXP_REG_HST_ZONE_PERM_TABLE_INIT_DONE 0x1030dcUL //ACCESS:RC DataWidth:0x1 Description: Done indication for the permission table's init sequence
#define PXP_REG_HST_PER_VIOLATION_VALID 0x1030e0UL //ACCESS:R DataWidth:0x1 Description: 1- permission violation data is logged. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1)
#define PXP_REG_HST_PER_VIOLATION_DATA 0x1030e4UL //ACCESS:R DataWidth:0xe Description: Log of the permission violation: {QID[7:0];VFID[5:0]}
#define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4UL //ACCESS:RW DataWidth:0x1 Description: When 1; doorbells are discarded and not passed to doorbell queue block. Should be used for close the gates.
#define PXP_REG_HST_DISCARD_DOORBELLS_SIZE 1
#define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8UL //ACCESS:RW DataWidth:0x1 Description: When 1; new internal writes arriving to the block are discarded. Should be used for close the gates.
#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_SIZE 1
#define PXP_REG_DBG_OUT_DATA_LSB 0x1030e8UL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that goes to the DBG block.
#define PXP_REG_DBG_OUT_DATA_LSB_SIZE 1
#define PXP_REG_DBG_OUT_DATA_MSB 0x1030ecUL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that goes to the DBG block.
#define PXP_REG_DBG_OUT_DATA_MSB_SIZE 1
#define PXP_REG_DBG_OUT_FRAME 0x1030f0UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits that goes to the DBG block. Bit0 is the frame of data byte0; Bit1 is the frame of data byte1; Bit2 is the frame of data byte2; Bit3 is the frame of data byte4
#define PXP_REG_DBG_OUT_FRAME_SIZE 1
#define PXP_REG_DBG_OUT_VALID 0x1030f4UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits that goes to the DBG block. Bit0 validtes data byte0; Bit1 validates data byte1; Bit2 validates data byte2; Bit3 validates data byte4
#define PXP_REG_DBG_OUT_VALID_SIZE 1
#define PXP_REG_HST_ZONE_PERMISSION_TABLE 0x103400UL //ACCESS:RW DataWidth:0x7 Description: Indirect access to the permission table. The fields are : {Valid; VFID[5:0]}
#define PXP_REG_HST_ZONE_PERMISSION_TABLE_SIZE 136
#define PXP_REG_HST_INBOUND_INT 0x103800UL //ACCESS:WB DataWidth:0xa0 Description: Used for initialization of the inbound interrupts memory
#define PXP_REG_HST_INBOUND_INT_SIZE 512
#define PXP_REG_HST_PORT4MODE_EN 0x1030b4UL //ACCESS:R DataWidth:0x1 Description: 4 Port mode enable bit
#define PXP_REG_HST_PORT4MODE_EN_SIZE 1
#define PXP_REG_PXP_UNUSED_EMPTY_0 0x1030d4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PXP_REG_PXP_UNUSED_EMPTY_0_SIZE 1
#define PXP_REG_PXP_UNUSED_EMPTY_1 0x1030f8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define PXP_REG_PXP_UNUSED_EMPTY_1_SIZE 194
#define QM_REG_XQM_WRC_FIFOLVL 0x168000UL //ACCESS:R DataWidth:0x6 Description: Keep the fill level of the fifo from write client 1
#define QM_REG_XQM_WRC_EN 0x168004UL //ACCESS:RW DataWidth:0x1 Description: Enable the write client 1
#define QM_REG_UQM_WRC_FIFOLVL 0x168008UL //ACCESS:R DataWidth:0x6 Description: Keep the fill level of the fifo from write client 2
#define QM_REG_UQM_WRC_EN 0x16800cUL //ACCESS:RW DataWidth:0x1 Description: Enable the write client 2
#define QM_REG_TQM_WRC_FIFOLVL 0x168010UL //ACCESS:R DataWidth:0x6 Description: Keep the fill level of the fifo from write client 3
#define QM_REG_TQM_WRC_EN 0x168014UL //ACCESS:RW DataWidth:0x1 Description: Enable the write client 3
#define QM_REG_CQM_WRC_FIFOLVL 0x168018UL //ACCESS:R DataWidth:0x6 Description: Keep the fill level of the fifo from write client 4
#define QM_REG_CQM_WRC_EN 0x16801cUL //ACCESS:RW DataWidth:0x1 Description: Enable the write client 4
#define QM_REG_CONNNUM_0 0x168020UL //ACCESS:RW DataWidth:0x14 Description: The number of connections divided by 16 which dictates the size of each queue which belongs to even function number.
#define QM_REG_CONNNUM_1 0x168024UL //ACCESS:RW DataWidth:0x14 Description: The number of connections divided by 16 which dictates the size of each queue which belongs to odd function number.
#define QM_REG_QSTATUS_LOW 0x168028UL //ACCESS:R DataWidth:0x20 Description: Current queues in pipeline: Queues from 0 to 31
#define QM_REG_QSTATUS_HIGH 0x16802cUL //ACCESS:R DataWidth:0x20 Description: Current queues in pipeline: Queues from 32 to 63
#define QM_REG_CTXREG_0 0x168030UL //ACCESS:RW DataWidth:0x8 Description: The context regions sent in the CFC load request
#define QM_REG_CTXREG_1 0x168034UL //ACCESS:RW DataWidth:0x8 Description: The context regions sent in the CFC load request
#define QM_REG_CTXREG_2 0x168038UL //ACCESS:RW DataWidth:0x8 Description: The context regions sent in the CFC load request
#define QM_REG_CTXREG_3 0x16803cUL //ACCESS:RW DataWidth:0x8 Description: The context regions sent in the CFC load request
#define QM_REG_ACTCTRINITVAL_0 0x168040UL //ACCESS:RW DataWidth:0x4 Description: The activity counter initial increment value sent in the load request
#define QM_REG_ACTCTRINITVAL_1 0x168044UL //ACCESS:RW DataWidth:0x4 Description: The activity counter initial increment value sent in the load request
#define QM_REG_ACTCTRINITVAL_2 0x168048UL //ACCESS:RW DataWidth:0x4 Description: The activity counter initial increment value sent in the load request
#define QM_REG_ACTCTRINITVAL_3 0x16804cUL //ACCESS:RW DataWidth:0x4 Description: The activity counter initial increment value sent in the load request
#define QM_REG_PCIREQQID 0x168050UL //ACCESS:RW DataWidth:0x5 Description: The virtual Queue ID used in the PCI request
#define QM_REG_PCIREQAT 0x168054UL //ACCESS:RW DataWidth:0x2 Description: The PCI attributes field used in the PCI request.
#define QM_REG_OVFQNUM 0x168058UL //ACCESS:RC DataWidth:0x6 Description: the Q were the qverflow occurs
#define QM_REG_OVFERROR 0x16805cUL //ACCESS:RC DataWidth:0x1 Description: A flag to indicate that overflow error occurred in one of the queues.
#define QM_REG_VOQINITCREDIT_0 0x168060UL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_1 0x168064UL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_2 0x168068UL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_3 0x16806cUL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_4 0x168070UL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_5 0x168074UL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_6 0x168078UL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_7 0x16807cUL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_8 0x168080UL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_9 0x168084UL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_10 0x168088UL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQINITCREDIT_11 0x16808cUL //ACCESS:RW DataWidth:0x10 Description: The init and maximum credit for each VoQ
#define QM_REG_VOQCREDITAFULLTHR 0x168090UL //ACCESS:RW DataWidth:0x10 Description: The credit value that if above the QM is considered almost full
#define QM_REG_BYTECREDITAFULLTHR 0x168094UL //ACCESS:RW DataWidth:0x11 Description: The byte credit value that if above the QM is considered almost full
#define QM_REG_AEMPTYTHR 0x168098UL //ACCESS:RW DataWidth:0x18 Description: Queue almost empty threshold
#define QM_REG_TASKCRDCOST_0 0x16809cUL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_1 0x1680a0UL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_2 0x1680a4UL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_3 0x1680a8UL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_4 0x1680acUL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_5 0x1680b0UL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_6 0x1680b4UL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_7 0x1680b8UL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_8 0x1680bcUL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_9 0x1680c0UL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_10 0x1680c4UL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_TASKCRDCOST_11 0x1680c8UL //ACCESS:RW DataWidth:0x8 Description: The credit cost per every task in the QM. A value per each VOQ
#define QM_REG_CMINITCRD_0 0x1680ccUL //ACCESS:RW DataWidth:0x4 Description: The initial credit for interface
#define QM_REG_CMINITCRD_1 0x1680d0UL //ACCESS:RW DataWidth:0x4 Description: The initial credit for interface
#define QM_REG_CMINITCRD_2 0x1680d4UL //ACCESS:RW DataWidth:0x4 Description: The initial credit for interface
#define QM_REG_CMINITCRD_3 0x1680d8UL //ACCESS:RW DataWidth:0x4 Description: The initial credit for interface
#define QM_REG_CMINITCRD_4 0x1680dcUL //ACCESS:RW DataWidth:0x4 Description: The initial credit for interface
#define QM_REG_CMINITCRD_5 0x1680e0UL //ACCESS:RW DataWidth:0x4 Description: The initial credit for interface
#define QM_REG_CMINITCRD_6 0x1680e4UL //ACCESS:RW DataWidth:0x4 Description: The initial credit for interface
#define QM_REG_CMINITCRD_7 0x1680e8UL //ACCESS:RW DataWidth:0x4 Description: The initial credit for interface
#define QM_REG_CMINTEN 0x1680ecUL //ACCESS:RW DataWidth:0x8 Description: A mask bit per CM interface. If this bit is 0 then this interface is masked
#define QM_REG_ENSEC 0x1680f0UL //ACCESS:RW DataWidth:0x4 Description: If cleared then the secondary interface will not be served by the RR arbiter
#define QM_REG_QVOQIDX_0 0x1680f4UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_1 0x1680f8UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_2 0x1680fcUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_3 0x168100UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_4 0x168104UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_5 0x168108UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_6 0x16810cUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_7 0x168110UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_8 0x168114UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_9 0x168118UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_10 0x16811cUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_11 0x168120UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_12 0x168124UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_13 0x168128UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_14 0x16812cUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_15 0x168130UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_16 0x168134UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_17 0x168138UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_18 0x16813cUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_19 0x168140UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_20 0x168144UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_21 0x168148UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_22 0x16814cUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_23 0x168150UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_24 0x168154UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_25 0x168158UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_26 0x16815cUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_27 0x168160UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_28 0x168164UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_29 0x168168UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_30 0x16816cUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_31 0x168170UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_32 0x168174UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_33 0x168178UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_34 0x16817cUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_35 0x168180UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_36 0x168184UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_37 0x168188UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_38 0x16818cUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_39 0x168190UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_40 0x168194UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_41 0x168198UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_42 0x16819cUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_43 0x1681a0UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_44 0x1681a4UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_45 0x1681a8UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_46 0x1681acUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_47 0x1681b0UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_48 0x1681b4UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_49 0x1681b8UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_50 0x1681bcUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_51 0x1681c0UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_52 0x1681c4UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_53 0x1681c8UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_54 0x1681ccUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_55 0x1681d0UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_56 0x1681d4UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_57 0x1681d8UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_58 0x1681dcUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_59 0x1681e0UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_60 0x1681e4UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_61 0x1681e8UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_62 0x1681ecUL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_QVOQIDX_63 0x1681f0UL //ACCESS:RW DataWidth:0x4 Description: Queue tied to VOQ
#define QM_REG_CMINTVOQMASK_0 0x1681f4UL //ACCESS:RW DataWidth:0xc Description: A bit vector which indicates which one of the queues are tied to interface 0
#define QM_REG_CMINTVOQMASK_1 0x1681f8UL //ACCESS:RW DataWidth:0xc Description: A bit vector which indicates which one of the queues are tied to interface 1
#define QM_REG_CMINTVOQMASK_2 0x1681fcUL //ACCESS:RW DataWidth:0xc Description: A bit vector which indicates which one of the queues are tied to interface 2
#define QM_REG_CMINTVOQMASK_3 0x168200UL //ACCESS:RW DataWidth:0xc Description: A bit vector which indicates which one of the queues are tied to interface 3
#define QM_REG_CMINTVOQMASK_4 0x168204UL //ACCESS:RW DataWidth:0xc Description: A bit vector which indicates which one of the queues are tied to interface 4
#define QM_REG_CMINTVOQMASK_5 0x168208UL //ACCESS:RW DataWidth:0xc Description: A bit vector which indicates which one of the queues are tied to interface 5
#define QM_REG_CMINTVOQMASK_6 0x16820cUL //ACCESS:RW DataWidth:0xc Description: A bit vector which indicates which one of the queues are tied to interface 6
#define QM_REG_CMINTVOQMASK_7 0x168210UL //ACCESS:RW DataWidth:0xc Description: A bit vector which indicates which one of the queues are tied to interface 7
#define QM_REG_HWAEMPTYMASK_MSB 0x168214UL //ACCESS:RW DataWidth:0x20 Description: A mask register to mask the Almost empty signals which will not be use for the almost empty indication to the HW block; queues 63:32
#define QM_REG_HWAEMPTYMASK_LSB 0x168218UL //ACCESS:RW DataWidth:0x20 Description: A mask register to mask the Almost empty signals which will not be use for the almost empty indication to the HW block; queues 31:0
#define QM_REG_ENBYTECRD_MSB 0x16821cUL //ACCESS:RW DataWidth:0x20 Description: A bit mask per each physical queue. If a bit is set then the physical queue uses the byte credit; queues 63-32
#define QM_REG_ENBYTECRD_LSB 0x168220UL //ACCESS:RW DataWidth:0x20 Description: A bit mask per each physical queue. If a bit is set then the physical queue uses the byte credit; queues 31-0
#define QM_REG_FUNCNUMSEL_MSB 0x16822cUL //ACCESS:RW DataWidth:0x20 Description: NA
#define QM_REG_FUNCNUMSEL_LSB 0x168230UL //ACCESS:RW DataWidth:0x20 Description: NA
#define QM_REG_BYTECRDCOST 0x168234UL //ACCESS:RW DataWidth:0x10 Description: The byte credit cost for each task. This value is for all byte credit counters
#define QM_REG_BYTECRDINITVAL 0x168238UL //ACCESS:RW DataWidth:0x11 Description: The initial byte credit value for all counters
#define QM_REG_ENBYPVOQMASK 0x16823cUL //ACCESS:RW DataWidth:0xc Description: The VOQ mask used to select the VOQs which needs to be full for bypass enable
#define QM_REG_VOQQMASK_0_LSB 0x168240UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_0_MSB 0x168244UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_1_LSB 0x168248UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_1_MSB 0x16824cUL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_2_LSB 0x168250UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_2_MSB 0x168254UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_3_LSB 0x168258UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_3_MSB 0x16825cUL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_4_LSB 0x168260UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_4_MSB 0x168264UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_5_LSB 0x168268UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_5_MSB 0x16826cUL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_6_LSB 0x168270UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_6_MSB 0x168274UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_7_LSB 0x168278UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_7_MSB 0x16827cUL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_8_LSB 0x168280UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_8_MSB 0x168284UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_9_LSB 0x168288UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_9_MSB 0x16828cUL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_10_LSB 0x168290UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_10_MSB 0x168294UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQQMASK_11_LSB 0x168298UL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 31-0
#define QM_REG_VOQQMASK_11_MSB 0x16829cUL //ACCESS:RW DataWidth:0x20 Description: The physical queue number associated with each VOQ; queues 63-32
#define QM_REG_VOQCREDIT_0 0x1682d0UL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_1 0x1682d4UL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_2 0x1682d8UL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_3 0x1682dcUL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_4 0x1682e0UL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_5 0x1682e4UL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_6 0x1682e8UL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_7 0x1682ecUL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_8 0x1682f0UL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_9 0x1682f4UL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_10 0x1682f8UL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_VOQCREDIT_11 0x1682fcUL //ACCESS:R DataWidth:0x11 Description: The credit value for each VOQ. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_QTASKCTR_0 0x168308UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_1 0x16830cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_2 0x168310UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_3 0x168314UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_4 0x168318UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_5 0x16831cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_6 0x168320UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_7 0x168324UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_8 0x168328UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_9 0x16832cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_10 0x168330UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_11 0x168334UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_12 0x168338UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_13 0x16833cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_14 0x168340UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_15 0x168344UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_16 0x168348UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_17 0x16834cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_18 0x168350UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_19 0x168354UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_20 0x168358UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_21 0x16835cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_22 0x168360UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_23 0x168364UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_24 0x168368UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_25 0x16836cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_26 0x168370UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_27 0x168374UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_28 0x168378UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_29 0x16837cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_30 0x168380UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_31 0x168384UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_32 0x168388UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_33 0x16838cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_34 0x168390UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_35 0x168394UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_36 0x168398UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_37 0x16839cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_38 0x1683a0UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_39 0x1683a4UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_40 0x1683a8UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_41 0x1683acUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_42 0x1683b0UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_43 0x1683b4UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_44 0x1683b8UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_45 0x1683bcUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_46 0x1683c0UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_47 0x1683c4UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_48 0x1683c8UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_49 0x1683ccUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_50 0x1683d0UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_51 0x1683d4UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_52 0x1683d8UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_53 0x1683dcUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_54 0x1683e0UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_55 0x1683e4UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_56 0x1683e8UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_57 0x1683ecUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_58 0x1683f0UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_59 0x1683f4UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_60 0x1683f8UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_61 0x1683fcUL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_62 0x168400UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_QTASKCTR_63 0x168404UL //ACCESS:R DataWidth:0x18 Description: The number of tasks queued for each queue; queues 63-0
#define QM_REG_VOQCRDERRREG 0x168408UL //ACCESS:RC DataWidth:0x20 Description: VOQ credit update error register; b3-b0: voq id (pbf error); b7-b4: voq id (storm increment error); b11-b8: voq id (storm decrement error); b12: pbf error valid; b13: storm increment error valid; b14: storm decrement error valid; b15: reserved; b27-b16: voq warning (warning=decremented below zero). mask bit per voq counter; b31-b28: reserved; NOTE: VOQ id-s represent HW VOQ id
#define QM_REG_QLEVELMHVAL 0x16840cUL //ACCESS:RC DataWidth:0x18 Description: The MAX hold value of the fill level of the physical queue
#define QM_REG_PAUSESTATE0 0x168410UL //ACCESS:R DataWidth:0x10 Description: Pause state for physical queues 15-0
#define QM_REG_PAUSESTATE1 0x168414UL //ACCESS:R DataWidth:0x10 Description: Pause state for physical queues 31-16
#define QM_REG_BIGRAMLOW_TM 0x168420UL //ACCESS:RW DataWidth:0x5 Description: TM Bits of bigram low memory; queues 63-0
#define QM_REG_BIGRAMHIGH_TM 0x168424UL //ACCESS:RW DataWidth:0x5 Description: TM Bits of bigram high memory; queues 63-0
#define QM_REG_SOFT_RESET 0x168428UL //ACCESS:RW DataWidth:0x1 Description: Initialization bit command
#define QM_REG_DBG_SELECT 0x16842cUL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for selecting a line to output to the DBG block.
#define QM_REG_DBG_BYTE_ENABLE 0x168430UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define QM_REG_DBG_SHIFT 0x168434UL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define QM_REG_QM_INT_STS 0x168438UL //ACCESS:R DataWidth:0xe Description: Interrupt register #0 read
#define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define QM_QM_INT_STS_REG_OVF_ERR (0x1<<1)
#define QM_QM_INT_STS_REG_OVF_ERR_SIZE 1
#define QM_QM_INT_STS_REG_PF_USG_CNT_0_ERR (0x1<<2)
#define QM_QM_INT_STS_REG_PF_USG_CNT_0_ERR_SIZE 2
#define QM_QM_INT_STS_REG_PF_USG_CNT_1_ERR (0x1<<3)
#define QM_QM_INT_STS_REG_PF_USG_CNT_1_ERR_SIZE 3
#define QM_QM_INT_STS_REG_PF_USG_CNT_2_ERR (0x1<<4)
#define QM_QM_INT_STS_REG_PF_USG_CNT_2_ERR_SIZE 4
#define QM_QM_INT_STS_REG_PF_USG_CNT_3_ERR (0x1<<5)
#define QM_QM_INT_STS_REG_PF_USG_CNT_3_ERR_SIZE 5
#define QM_QM_INT_STS_REG_PF_USG_CNT_4_ERR (0x1<<6)
#define QM_QM_INT_STS_REG_PF_USG_CNT_4_ERR_SIZE 6
#define QM_QM_INT_STS_REG_PF_USG_CNT_5_ERR (0x1<<7)
#define QM_QM_INT_STS_REG_PF_USG_CNT_5_ERR_SIZE 7
#define QM_QM_INT_STS_REG_PF_USG_CNT_6_ERR (0x1<<8)
#define QM_QM_INT_STS_REG_PF_USG_CNT_6_ERR_SIZE 8
#define QM_QM_INT_STS_REG_PF_USG_CNT_7_ERR (0x1<<9)
#define QM_QM_INT_STS_REG_PF_USG_CNT_7_ERR_SIZE 9
#define QM_QM_INT_STS_REG_VOQ_CRD_INC_ERR (0x1<<10)
#define QM_QM_INT_STS_REG_VOQ_CRD_INC_ERR_SIZE 10
#define QM_QM_INT_STS_REG_VOQ_CRD_DEC_ERR (0x1<<11)
#define QM_QM_INT_STS_REG_VOQ_CRD_DEC_ERR_SIZE 11
#define QM_QM_INT_STS_REG_BYTE_CRD_INC_ERR (0x1<<12)
#define QM_QM_INT_STS_REG_BYTE_CRD_INC_ERR_SIZE 12
#define QM_QM_INT_STS_REG_BYTE_CRD_DEC_ERR (0x1<<13)
#define QM_QM_INT_STS_REG_BYTE_CRD_DEC_ERR_SIZE 13
#define QM_REG_QM_INT_STS_CLR 0x16843cUL //ACCESS:RC DataWidth:0xe Description: Interrupt register #0 read clear
#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define QM_QM_INT_STS_CLR_REG_OVF_ERR (0x1<<1)
#define QM_QM_INT_STS_CLR_REG_OVF_ERR_SIZE 1
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_0_ERR (0x1<<2)
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_0_ERR_SIZE 2
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_1_ERR (0x1<<3)
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_1_ERR_SIZE 3
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_2_ERR (0x1<<4)
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_2_ERR_SIZE 4
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_3_ERR (0x1<<5)
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_3_ERR_SIZE 5
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_4_ERR (0x1<<6)
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_4_ERR_SIZE 6
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_5_ERR (0x1<<7)
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_5_ERR_SIZE 7
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_6_ERR (0x1<<8)
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_6_ERR_SIZE 8
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_7_ERR (0x1<<9)
#define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_7_ERR_SIZE 9
#define QM_QM_INT_STS_CLR_REG_VOQ_CRD_INC_ERR (0x1<<10)
#define QM_QM_INT_STS_CLR_REG_VOQ_CRD_INC_ERR_SIZE 10
#define QM_QM_INT_STS_CLR_REG_VOQ_CRD_DEC_ERR (0x1<<11)
#define QM_QM_INT_STS_CLR_REG_VOQ_CRD_DEC_ERR_SIZE 11
#define QM_QM_INT_STS_CLR_REG_BYTE_CRD_INC_ERR (0x1<<12)
#define QM_QM_INT_STS_CLR_REG_BYTE_CRD_INC_ERR_SIZE 12
#define QM_QM_INT_STS_CLR_REG_BYTE_CRD_DEC_ERR (0x1<<13)
#define QM_QM_INT_STS_CLR_REG_BYTE_CRD_DEC_ERR_SIZE 13
#define QM_REG_QM_INT_STS_WR 0x168440UL //ACCESS:WR DataWidth:0xe Description: Interrupt register #0 bit set or clear
#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define QM_QM_INT_STS_WR_REG_OVF_ERR (0x1<<1)
#define QM_QM_INT_STS_WR_REG_OVF_ERR_SIZE 1
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_0_ERR (0x1<<2)
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_0_ERR_SIZE 2
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_1_ERR (0x1<<3)
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_1_ERR_SIZE 3
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_2_ERR (0x1<<4)
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_2_ERR_SIZE 4
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_3_ERR (0x1<<5)
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_3_ERR_SIZE 5
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_4_ERR (0x1<<6)
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_4_ERR_SIZE 6
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_5_ERR (0x1<<7)
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_5_ERR_SIZE 7
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_6_ERR (0x1<<8)
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_6_ERR_SIZE 8
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_7_ERR (0x1<<9)
#define QM_QM_INT_STS_WR_REG_PF_USG_CNT_7_ERR_SIZE 9
#define QM_QM_INT_STS_WR_REG_VOQ_CRD_INC_ERR (0x1<<10)
#define QM_QM_INT_STS_WR_REG_VOQ_CRD_INC_ERR_SIZE 10
#define QM_QM_INT_STS_WR_REG_VOQ_CRD_DEC_ERR (0x1<<11)
#define QM_QM_INT_STS_WR_REG_VOQ_CRD_DEC_ERR_SIZE 11
#define QM_QM_INT_STS_WR_REG_BYTE_CRD_INC_ERR (0x1<<12)
#define QM_QM_INT_STS_WR_REG_BYTE_CRD_INC_ERR_SIZE 12
#define QM_QM_INT_STS_WR_REG_BYTE_CRD_DEC_ERR (0x1<<13)
#define QM_QM_INT_STS_WR_REG_BYTE_CRD_DEC_ERR_SIZE 13
#define QM_REG_QM_INT_MASK 0x168444UL //ACCESS:RW DataWidth:0xe Description: Interrupt mask register #0 read/write
#define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define QM_QM_INT_MASK_REG_OVF_ERR (0x1<<1)
#define QM_QM_INT_MASK_REG_OVF_ERR_SIZE 1
#define QM_QM_INT_MASK_REG_PF_USG_CNT_0_ERR (0x1<<2)
#define QM_QM_INT_MASK_REG_PF_USG_CNT_0_ERR_SIZE 2
#define QM_QM_INT_MASK_REG_PF_USG_CNT_1_ERR (0x1<<3)
#define QM_QM_INT_MASK_REG_PF_USG_CNT_1_ERR_SIZE 3
#define QM_QM_INT_MASK_REG_PF_USG_CNT_2_ERR (0x1<<4)
#define QM_QM_INT_MASK_REG_PF_USG_CNT_2_ERR_SIZE 4
#define QM_QM_INT_MASK_REG_PF_USG_CNT_3_ERR (0x1<<5)
#define QM_QM_INT_MASK_REG_PF_USG_CNT_3_ERR_SIZE 5
#define QM_QM_INT_MASK_REG_PF_USG_CNT_4_ERR (0x1<<6)
#define QM_QM_INT_MASK_REG_PF_USG_CNT_4_ERR_SIZE 6
#define QM_QM_INT_MASK_REG_PF_USG_CNT_5_ERR (0x1<<7)
#define QM_QM_INT_MASK_REG_PF_USG_CNT_5_ERR_SIZE 7
#define QM_QM_INT_MASK_REG_PF_USG_CNT_6_ERR (0x1<<8)
#define QM_QM_INT_MASK_REG_PF_USG_CNT_6_ERR_SIZE 8
#define QM_QM_INT_MASK_REG_PF_USG_CNT_7_ERR (0x1<<9)
#define QM_QM_INT_MASK_REG_PF_USG_CNT_7_ERR_SIZE 9
#define QM_QM_INT_MASK_REG_VOQ_CRD_INC_ERR (0x1<<10)
#define QM_QM_INT_MASK_REG_VOQ_CRD_INC_ERR_SIZE 10
#define QM_QM_INT_MASK_REG_VOQ_CRD_DEC_ERR (0x1<<11)
#define QM_QM_INT_MASK_REG_VOQ_CRD_DEC_ERR_SIZE 11
#define QM_QM_INT_MASK_REG_BYTE_CRD_INC_ERR (0x1<<12)
#define QM_QM_INT_MASK_REG_BYTE_CRD_INC_ERR_SIZE 12
#define QM_QM_INT_MASK_REG_BYTE_CRD_DEC_ERR (0x1<<13)
#define QM_QM_INT_MASK_REG_BYTE_CRD_DEC_ERR_SIZE 13
#define QM_REG_QM_PRTY_STS 0x168448UL //ACCESS:R DataWidth:0xc Description: Parity register #0 read
#define QM_QM_PRTY_STS_REG_PARITY (0x1<<0)
#define QM_QM_PRTY_STS_REG_PARITY_SIZE 0
#define QM_QM_PRTY_STS_REG_XCM_WRC_FIFO (0x1<<1)
#define QM_QM_PRTY_STS_REG_XCM_WRC_FIFO_SIZE 1
#define QM_QM_PRTY_STS_REG_UCM_WRC_FIFO (0x1<<2)
#define QM_QM_PRTY_STS_REG_UCM_WRC_FIFO_SIZE 2
#define QM_QM_PRTY_STS_REG_TCM_WRC_FIFO (0x1<<3)
#define QM_QM_PRTY_STS_REG_TCM_WRC_FIFO_SIZE 3
#define QM_QM_PRTY_STS_REG_CCM_WRC_FIFO (0x1<<4)
#define QM_QM_PRTY_STS_REG_CCM_WRC_FIFO_SIZE 4
#define QM_QM_PRTY_STS_REG_BIGRAMHIGH (0x1<<5)
#define QM_QM_PRTY_STS_REG_BIGRAMHIGH_SIZE 5
#define QM_QM_PRTY_STS_REG_BIGRAMLOW (0x1<<6)
#define QM_QM_PRTY_STS_REG_BIGRAMLOW_SIZE 6
#define QM_QM_PRTY_STS_REG_BASE_ADDRESS (0x1<<7)
#define QM_QM_PRTY_STS_REG_BASE_ADDRESS_SIZE 7
#define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
#define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8
#define QM_QM_PRTY_STS_REG_BIGRAMHIGH_EXT_A (0x1<<9)
#define QM_QM_PRTY_STS_REG_BIGRAMHIGH_EXT_A_SIZE 9
#define QM_QM_PRTY_STS_REG_BIGRAMLOW_EXT_A (0x1<<10)
#define QM_QM_PRTY_STS_REG_BIGRAMLOW_EXT_A_SIZE 10
#define QM_QM_PRTY_STS_REG_BASE_ADDRESS_EXT_A (0x1<<11)
#define QM_QM_PRTY_STS_REG_BASE_ADDRESS_EXT_A_SIZE 11
#define QM_REG_QM_PRTY_STS_CLR 0x16844cUL //ACCESS:RC DataWidth:0xc Description: Parity register #0 read clear
#define QM_QM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define QM_QM_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define QM_QM_PRTY_STS_CLR_REG_XCM_WRC_FIFO (0x1<<1)
#define QM_QM_PRTY_STS_CLR_REG_XCM_WRC_FIFO_SIZE 1
#define QM_QM_PRTY_STS_CLR_REG_UCM_WRC_FIFO (0x1<<2)
#define QM_QM_PRTY_STS_CLR_REG_UCM_WRC_FIFO_SIZE 2
#define QM_QM_PRTY_STS_CLR_REG_TCM_WRC_FIFO (0x1<<3)
#define QM_QM_PRTY_STS_CLR_REG_TCM_WRC_FIFO_SIZE 3
#define QM_QM_PRTY_STS_CLR_REG_CCM_WRC_FIFO (0x1<<4)
#define QM_QM_PRTY_STS_CLR_REG_CCM_WRC_FIFO_SIZE 4
#define QM_QM_PRTY_STS_CLR_REG_BIGRAMHIGH (0x1<<5)
#define QM_QM_PRTY_STS_CLR_REG_BIGRAMHIGH_SIZE 5
#define QM_QM_PRTY_STS_CLR_REG_BIGRAMLOW (0x1<<6)
#define QM_QM_PRTY_STS_CLR_REG_BIGRAMLOW_SIZE 6
#define QM_QM_PRTY_STS_CLR_REG_BASE_ADDRESS (0x1<<7)
#define QM_QM_PRTY_STS_CLR_REG_BASE_ADDRESS_SIZE 7
#define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
#define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8
#define QM_QM_PRTY_STS_CLR_REG_BIGRAMHIGH_EXT_A (0x1<<9)
#define QM_QM_PRTY_STS_CLR_REG_BIGRAMHIGH_EXT_A_SIZE 9
#define QM_QM_PRTY_STS_CLR_REG_BIGRAMLOW_EXT_A (0x1<<10)
#define QM_QM_PRTY_STS_CLR_REG_BIGRAMLOW_EXT_A_SIZE 10
#define QM_QM_PRTY_STS_CLR_REG_BASE_ADDRESS_EXT_A (0x1<<11)
#define QM_QM_PRTY_STS_CLR_REG_BASE_ADDRESS_EXT_A_SIZE 11
#define QM_REG_QM_PRTY_STS_WR 0x168450UL //ACCESS:WR DataWidth:0xc Description: Parity register #0 bit set or clear
#define QM_QM_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define QM_QM_PRTY_STS_WR_REG_PARITY_SIZE 0
#define QM_QM_PRTY_STS_WR_REG_XCM_WRC_FIFO (0x1<<1)
#define QM_QM_PRTY_STS_WR_REG_XCM_WRC_FIFO_SIZE 1
#define QM_QM_PRTY_STS_WR_REG_UCM_WRC_FIFO (0x1<<2)
#define QM_QM_PRTY_STS_WR_REG_UCM_WRC_FIFO_SIZE 2
#define QM_QM_PRTY_STS_WR_REG_TCM_WRC_FIFO (0x1<<3)
#define QM_QM_PRTY_STS_WR_REG_TCM_WRC_FIFO_SIZE 3
#define QM_QM_PRTY_STS_WR_REG_CCM_WRC_FIFO (0x1<<4)
#define QM_QM_PRTY_STS_WR_REG_CCM_WRC_FIFO_SIZE 4
#define QM_QM_PRTY_STS_WR_REG_BIGRAMHIGH (0x1<<5)
#define QM_QM_PRTY_STS_WR_REG_BIGRAMHIGH_SIZE 5
#define QM_QM_PRTY_STS_WR_REG_BIGRAMLOW (0x1<<6)
#define QM_QM_PRTY_STS_WR_REG_BIGRAMLOW_SIZE 6
#define QM_QM_PRTY_STS_WR_REG_BASE_ADDRESS (0x1<<7)
#define QM_QM_PRTY_STS_WR_REG_BASE_ADDRESS_SIZE 7
#define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
#define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8
#define QM_QM_PRTY_STS_WR_REG_BIGRAMHIGH_EXT_A (0x1<<9)
#define QM_QM_PRTY_STS_WR_REG_BIGRAMHIGH_EXT_A_SIZE 9
#define QM_QM_PRTY_STS_WR_REG_BIGRAMLOW_EXT_A (0x1<<10)
#define QM_QM_PRTY_STS_WR_REG_BIGRAMLOW_EXT_A_SIZE 10
#define QM_QM_PRTY_STS_WR_REG_BASE_ADDRESS_EXT_A (0x1<<11)
#define QM_QM_PRTY_STS_WR_REG_BASE_ADDRESS_EXT_A_SIZE 11
#define QM_REG_QM_PRTY_MASK 0x168454UL //ACCESS:RW DataWidth:0xc Description: Parity mask register #0 read/write
#define QM_QM_PRTY_MASK_REG_PARITY (0x1<<0)
#define QM_QM_PRTY_MASK_REG_PARITY_SIZE 0
#define QM_QM_PRTY_MASK_REG_XCM_WRC_FIFO (0x1<<1)
#define QM_QM_PRTY_MASK_REG_XCM_WRC_FIFO_SIZE 1
#define QM_QM_PRTY_MASK_REG_UCM_WRC_FIFO (0x1<<2)
#define QM_QM_PRTY_MASK_REG_UCM_WRC_FIFO_SIZE 2
#define QM_QM_PRTY_MASK_REG_TCM_WRC_FIFO (0x1<<3)
#define QM_QM_PRTY_MASK_REG_TCM_WRC_FIFO_SIZE 3
#define QM_QM_PRTY_MASK_REG_CCM_WRC_FIFO (0x1<<4)
#define QM_QM_PRTY_MASK_REG_CCM_WRC_FIFO_SIZE 4
#define QM_QM_PRTY_MASK_REG_BIGRAMHIGH (0x1<<5)
#define QM_QM_PRTY_MASK_REG_BIGRAMHIGH_SIZE 5
#define QM_QM_PRTY_MASK_REG_BIGRAMLOW (0x1<<6)
#define QM_QM_PRTY_MASK_REG_BIGRAMLOW_SIZE 6
#define QM_QM_PRTY_MASK_REG_BASE_ADDRESS (0x1<<7)
#define QM_QM_PRTY_MASK_REG_BASE_ADDRESS_SIZE 7
#define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
#define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8
#define QM_QM_PRTY_MASK_REG_BIGRAMHIGH_EXT_A (0x1<<9)
#define QM_QM_PRTY_MASK_REG_BIGRAMHIGH_EXT_A_SIZE 9
#define QM_QM_PRTY_MASK_REG_BIGRAMLOW_EXT_A (0x1<<10)
#define QM_QM_PRTY_MASK_REG_BIGRAMLOW_EXT_A_SIZE 10
#define QM_QM_PRTY_MASK_REG_BASE_ADDRESS_EXT_A (0x1<<11)
#define QM_QM_PRTY_MASK_REG_BASE_ADDRESS_EXT_A_SIZE 11
#define QM_REG_PAUSESTATE2 0x16e684UL //ACCESS:R DataWidth:0x10 Description: Pause state for physical queues 47-32
#define QM_REG_PAUSESTATE3 0x16e688UL //ACCESS:R DataWidth:0x10 Description: Pause state for physical queues 63-48
#define QM_REG_PQ2PCIFUNC_0 0x16e6bcUL //ACCESS:RW DataWidth:0x3 Description: pci function number of queues 15-0
#define QM_REG_PQ2PCIFUNC_1 0x16e6c0UL //ACCESS:RW DataWidth:0x3 Description: pci function number of queues 31-16
#define QM_REG_PQ2PCIFUNC_2 0x16e6c4UL //ACCESS:RW DataWidth:0x3 Description: pci function number of queues 47-32
#define QM_REG_PQ2PCIFUNC_3 0x16e6c8UL //ACCESS:RW DataWidth:0x3 Description: pci function number of queues 63-48
#define QM_REG_ECO_RESERVED 0x16e6e0UL //ACCESS:RW DataWidth:0x8 Description: eco reserved register
#define QM_REG_PCIREQATC 0x16e6e4UL //ACCESS:RW DataWidth:0x18 Description: The PCI ATC flags used in the PCI request. b2-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in page; b7: reserved (zero); b10-b8: rd middle bank in page; b11: reserved (zero); b14-b12: wr middle bank in page; b15: reserved (zero); b18-b16: rd last bank in page; b19: reserved (zero); b22-b20: wr last bank in page; b23: reserved (zero);
#define QM_REG_BYTECRD0 0x16e6fcUL //ACCESS:R DataWidth:0x12 Description: The credit value for byte credit 0. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_BYTECRD1 0x16e700UL //ACCESS:R DataWidth:0x12 Description: The credit value for byte credit 1. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_BYTECRD2 0x16e704UL //ACCESS:R DataWidth:0x12 Description: The credit value for byte credit 2. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_BYTECRDERRREG 0x16e708UL //ACCESS:RC DataWidth:0x20 Description: byte credit update error register; b2-b0: byte credit id (pbf error); b3 - reserved (zero filled); b6-b4: byte credit id (storm increment error); b7 - reserved (zero filled); b10-b8: byte credit id (storm decrement error); b11 - reserved (zero filled); b12: pbf error valid; b13: storm increment error valid; b14: storm decrement error valid; b15: reserved; b22-b16: byte credit warning (warning=decremented below zero). mask bit per voq counter; b31-b23: reserved; NOTE: VOQ id-s represent HW
#define QM_REG_PCI_RD_ERR_EN 0x16e788UL //ACCESS:RW DataWidth:0x1 Description: enable pci rd error usage. When set pci rd error indication coming from the pci will set the bank with error (within pci_rd_err reg). When reset pci_rd_reg will be always 0 (i.e. not affected by the error coming from the pci).
#define QM_REG_QMPAGESIZE 0x16e790UL //ACCESS:RW DataWidth:0x5 Description: The STU size; this should be configured according to the minimal STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M
#define QM_REG_PQ_MODE 0x16e794UL //ACCESS:RW DataWidth:0x1 Description: This register affects the way the QM looks on the interfaces that involve physical queue logic (push; pop; xsdm command; xcm bypass) and takes care of the required physical queue mapping logic. the QM will map IPQN[4:0] = EPQN[4:0]. In addition when set the QM will map IPQN[5]=EPQN[6]. when reset IPQN[5]=EPQN[5].
#define QM_REG_EEE_BYTE_CRD_EN 0x16e7a8UL //ACCESS:RW DataWidth:0x7 Description: when set eee idle state requires both the byte credit counter and voq counter to be full (i.e. equal to their init values). When reset only the voq counter needs to be full. Bit per byte credit counter as follows: bit0 - byte credit0; bit 1 - byte credit1; . . .; bit 6 - byte credit6;
#define QM_REG_BYTECRD3 0x16e7acUL //ACCESS:R DataWidth:0x12 Description: The credit value for byte credit 3. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_BYTECRD4 0x16e7b0UL //ACCESS:R DataWidth:0x12 Description: The credit value for byte credit 4. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_BYTECRD5 0x16e7b4UL //ACCESS:R DataWidth:0x12 Description: The credit value for byte credit 5. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_BYTECRD6 0x16e7b8UL //ACCESS:R DataWidth:0x12 Description: The credit value for byte credit 6. The value is 2s complement value (i.e. msb is used for the sign).
#define QM_REG_FWVOQ0TOHWVOQ 0x16e7bcUL //ACCESS:RW DataWidth:0x3 Description: Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of FW (virtual) VOQ0
#define QM_REG_FWVOQ1TOHWVOQ 0x16e7c0UL //ACCESS:RW DataWidth:0x3 Description: Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of FW (virtual) VOQ1
#define QM_REG_FWVOQ2TOHWVOQ 0x16e7c4UL //ACCESS:RW DataWidth:0x3 Description: Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of FW (virtual) VOQ2
#define QM_REG_FWVOQ3TOHWVOQ 0x16e7c8UL //ACCESS:RW DataWidth:0x3 Description: Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of FW (virtual) VOQ3
#define QM_REG_FWVOQ4TOHWVOQ 0x16e7ccUL //ACCESS:RW DataWidth:0x3 Description: Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of FW (virtual) VOQ4
#define QM_REG_FWVOQ5TOHWVOQ 0x16e7d0UL //ACCESS:RW DataWidth:0x3 Description: Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of FW (virtual) VOQ5
#define QM_REG_FWVOQ6TOHWVOQ 0x16e7d4UL //ACCESS:RW DataWidth:0x3 Description: Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of FW (virtual) VOQ6
#define QM_REG_FWVOQ7TOHWVOQ 0x16e7d8UL //ACCESS:RW DataWidth:0x3 Description: Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of FW (virtual) VOQ7
#define QM_REG_MHQNUMSEL 0x168800UL //ACCESS:RW DataWidth:0x6 Description: The physical queue number for the MAX hold queue fill level statistics
#define QM_REG_MHQNUMSEL_SIZE 1
#define QM_REG_OUTLDREQ 0x168804UL //ACCESS:RW DataWidth:0x4 Description: The number of outstanding request to CFC
#define QM_REG_OUTLDREQ_SIZE 1
#define QM_REG_UPDATECREDIT 0x168808UL //ACCESS:RW DataWidth:0x20 Description: Credit update command interface. NOTE: unlike the command from the XSDM (that updates credit based on the FW VOQ id) the RBC command will update credit based on HW VOQ id. Or in other words the VOQ id field represent HW VOQ id.
#define QM_REG_UPDATECREDIT_SIZE 1
#define QM_REG_WRRWEIGHTS_0 0x16880cUL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_0_SIZE 1
#define QM_REG_WRRWEIGHTS_1 0x168810UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_1_SIZE 1
#define QM_REG_WRRWEIGHTS_10 0x168814UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_10_SIZE 1
#define QM_REG_WRRWEIGHTS_11 0x168818UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_11_SIZE 1
#define QM_REG_WRRWEIGHTS_12 0x16881cUL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_12_SIZE 1
#define QM_REG_WRRWEIGHTS_13 0x168820UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_13_SIZE 1
#define QM_REG_WRRWEIGHTS_14 0x168824UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_14_SIZE 1
#define QM_REG_WRRWEIGHTS_15 0x168828UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_15_SIZE 1
#define QM_REG_WRRWEIGHTS_2 0x16882cUL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_2_SIZE 1
#define QM_REG_WRRWEIGHTS_3 0x168830UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_3_SIZE 1
#define QM_REG_WRRWEIGHTS_4 0x168834UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_4_SIZE 1
#define QM_REG_WRRWEIGHTS_5 0x168838UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_5_SIZE 1
#define QM_REG_WRRWEIGHTS_6 0x16883cUL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_6_SIZE 1
#define QM_REG_WRRWEIGHTS_7 0x168840UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_7_SIZE 1
#define QM_REG_WRRWEIGHTS_8 0x168844UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_8_SIZE 1
#define QM_REG_WRRWEIGHTS_9 0x168848UL //ACCESS:RW DataWidth:0x20 Description: Wrr weights. NOTE: weight update is allowed only to queues which are either empty or paused
#define QM_REG_WRRWEIGHTS_9_SIZE 1
#define QM_REG_BASEADDR 0x168900UL //ACCESS:RW DataWidth:0x20 Description: The base logical address (in bytes) of each physical queue. The index I represents the physical queue number. The 12 lsbs are ignore and considered zero so practically there are only 20 bits in this register; queues 63-0
#define QM_REG_BASEADDR_SIZE 64
#define QM_REG_PTRTBL 0x168a00UL //ACCESS:WB DataWidth:0x36 Description: Pointer Table Memory for queues 63-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank;
#define QM_REG_PTRTBL_SIZE 128
#define QM_REG_BIGRAMHIGH 0x16a000UL //ACCESS:RW DataWidth:0x1e Description: High part of BigRAM
#define QM_REG_BIGRAMHIGH_SIZE 1536
#define QM_REG_BIGRAMLOW 0x16c000UL //ACCESS:RW DataWidth:0x1e Description: Low part of BigRAM
#define QM_REG_BIGRAMLOW_SIZE 1536
#define QM_REG_PF_USG_CNT_0 0x16e040UL //ACCESS:R DataWidth:0x18 Description: The number of tasks stored in the QM for the PF. only even functions are valid in E2 (odd I registers will be hard wired to 0)
#define QM_REG_PF_USG_CNT_0_SIZE 1
#define QM_REG_PF_USG_CNT_1 0x16e044UL //ACCESS:R DataWidth:0x18 Description: The number of tasks stored in the QM for the PF. only even functions are valid in E2 (odd I registers will be hard wired to 0)
#define QM_REG_PF_USG_CNT_1_SIZE 1
#define QM_REG_PF_USG_CNT_2 0x16e048UL //ACCESS:R DataWidth:0x18 Description: The number of tasks stored in the QM for the PF. only even functions are valid in E2 (odd I registers will be hard wired to 0)
#define QM_REG_PF_USG_CNT_2_SIZE 1
#define QM_REG_PF_USG_CNT_3 0x16e04cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks stored in the QM for the PF. only even functions are valid in E2 (odd I registers will be hard wired to 0)
#define QM_REG_PF_USG_CNT_3_SIZE 1
#define QM_REG_PF_USG_CNT_4 0x16e050UL //ACCESS:R DataWidth:0x18 Description: The number of tasks stored in the QM for the PF. only even functions are valid in E2 (odd I registers will be hard wired to 0)
#define QM_REG_PF_USG_CNT_4_SIZE 1
#define QM_REG_PF_USG_CNT_5 0x16e054UL //ACCESS:R DataWidth:0x18 Description: The number of tasks stored in the QM for the PF. only even functions are valid in E2 (odd I registers will be hard wired to 0)
#define QM_REG_PF_USG_CNT_5_SIZE 1
#define QM_REG_PF_USG_CNT_6 0x16e058UL //ACCESS:R DataWidth:0x18 Description: The number of tasks stored in the QM for the PF. only even functions are valid in E2 (odd I registers will be hard wired to 0)
#define QM_REG_PF_USG_CNT_6_SIZE 1
#define QM_REG_PF_USG_CNT_7 0x16e05cUL //ACCESS:R DataWidth:0x18 Description: The number of tasks stored in the QM for the PF. only even functions are valid in E2 (odd I registers will be hard wired to 0)
#define QM_REG_PF_USG_CNT_7_SIZE 1
#define QM_REG_PF_EN 0x16e70cUL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: PF enable vector. Bit per PF. If set the PF is enabled
#define QM_REG_PF_EN_SIZE 1
#define QM_REG_PCI_RD_ERR_0 0x16e768UL //ACCESS:R DataWidth:0x20 Description: pci read error that indicates for each bank if the data in the bank has error. The bits allocation is as follows: bit0 - bank0 pq0; bit1 - bank1 pq0; bit2 - bank2 pq0; bit3 - reserved (should be written with 0); bit4 - bank0 pq1; bit5 - bank1 pq1; bit6 - bank2 pq1; bit7 - reserved (should be written with 0); etc. there are 8 registers - 8 physical queues exist in each register as follows: register 0 pq 7-0; register 1 pq 15-8; etc.
#define QM_REG_PCI_RD_ERR_0_SIZE 1
#define QM_REG_PCI_RD_ERR_1 0x16e76cUL //ACCESS:R DataWidth:0x20 Description: pci read error that indicates for each bank if the data in the bank has error. The bits allocation is as follows: bit0 - bank0 pq0; bit1 - bank1 pq0; bit2 - bank2 pq0; bit3 - reserved (should be written with 0); bit4 - bank0 pq1; bit5 - bank1 pq1; bit6 - bank2 pq1; bit7 - reserved (should be written with 0); etc. there are 8 registers - 8 physical queues exist in each register as follows: register 0 pq 7-0; register 1 pq 15-8; etc.
#define QM_REG_PCI_RD_ERR_1_SIZE 1
#define QM_REG_PCI_RD_ERR_2 0x16e770UL //ACCESS:R DataWidth:0x20 Description: pci read error that indicates for each bank if the data in the bank has error. The bits allocation is as follows: bit0 - bank0 pq0; bit1 - bank1 pq0; bit2 - bank2 pq0; bit3 - reserved (should be written with 0); bit4 - bank0 pq1; bit5 - bank1 pq1; bit6 - bank2 pq1; bit7 - reserved (should be written with 0); etc. there are 8 registers - 8 physical queues exist in each register as follows: register 0 pq 7-0; register 1 pq 15-8; etc.
#define QM_REG_PCI_RD_ERR_2_SIZE 1
#define QM_REG_PCI_RD_ERR_3 0x16e774UL //ACCESS:R DataWidth:0x20 Description: pci read error that indicates for each bank if the data in the bank has error. The bits allocation is as follows: bit0 - bank0 pq0; bit1 - bank1 pq0; bit2 - bank2 pq0; bit3 - reserved (should be written with 0); bit4 - bank0 pq1; bit5 - bank1 pq1; bit6 - bank2 pq1; bit7 - reserved (should be written with 0); etc. there are 8 registers - 8 physical queues exist in each register as follows: register 0 pq 7-0; register 1 pq 15-8; etc.
#define QM_REG_PCI_RD_ERR_3_SIZE 1
#define QM_REG_PCI_RD_ERR_4 0x16e778UL //ACCESS:R DataWidth:0x20 Description: pci read error that indicates for each bank if the data in the bank has error. The bits allocation is as follows: bit0 - bank0 pq0; bit1 - bank1 pq0; bit2 - bank2 pq0; bit3 - reserved (should be written with 0); bit4 - bank0 pq1; bit5 - bank1 pq1; bit6 - bank2 pq1; bit7 - reserved (should be written with 0); etc. there are 8 registers - 8 physical queues exist in each register as follows: register 0 pq 7-0; register 1 pq 15-8; etc.
#define QM_REG_PCI_RD_ERR_4_SIZE 1
#define QM_REG_PCI_RD_ERR_5 0x16e77cUL //ACCESS:R DataWidth:0x20 Description: pci read error that indicates for each bank if the data in the bank has error. The bits allocation is as follows: bit0 - bank0 pq0; bit1 - bank1 pq0; bit2 - bank2 pq0; bit3 - reserved (should be written with 0); bit4 - bank0 pq1; bit5 - bank1 pq1; bit6 - bank2 pq1; bit7 - reserved (should be written with 0); etc. there are 8 registers - 8 physical queues exist in each register as follows: register 0 pq 7-0; register 1 pq 15-8; etc.
#define QM_REG_PCI_RD_ERR_5_SIZE 1
#define QM_REG_PCI_RD_ERR_6 0x16e780UL //ACCESS:R DataWidth:0x20 Description: pci read error that indicates for each bank if the data in the bank has error. The bits allocation is as follows: bit0 - bank0 pq0; bit1 - bank1 pq0; bit2 - bank2 pq0; bit3 - reserved (should be written with 0); bit4 - bank0 pq1; bit5 - bank1 pq1; bit6 - bank2 pq1; bit7 - reserved (should be written with 0); etc. there are 8 registers - 8 physical queues exist in each register as follows: register 0 pq 7-0; register 1 pq 15-8; etc.
#define QM_REG_PCI_RD_ERR_6_SIZE 1
#define QM_REG_PCI_RD_ERR_7 0x16e784UL //ACCESS:R DataWidth:0x20 Description: pci read error that indicates for each bank if the data in the bank has error. The bits allocation is as follows: bit0 - bank0 pq0; bit1 - bank1 pq0; bit2 - bank2 pq0; bit3 - reserved (should be written with 0); bit4 - bank0 pq1; bit5 - bank1 pq1; bit6 - bank2 pq1; bit7 - reserved (should be written with 0); etc. there are 8 registers - 8 physical queues exist in each register as follows: register 0 pq 7-0; register 1 pq 15-8; etc.
#define QM_REG_PCI_RD_ERR_7_SIZE 1
#define QM_REG_PCI_RD_ERR_RST 0x16e78cUL //ACCESS:RW DataWidth:0x6 Description: WRITE ONLY command register. Command for reseting the pci error bits for the banks of the pq in the command. upon reset the pci_rd_err register should be updated accordingly with the new values.
#define QM_REG_PCI_RD_ERR_RST_SIZE 1
#define QM_REG_DBG_OUT_DATA_LSB 0x16e798UL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that goes to the DBG block.
#define QM_REG_DBG_OUT_DATA_LSB_SIZE 1
#define QM_REG_DBG_OUT_DATA_MSB 0x16e79cUL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that goes to the DBG block.
#define QM_REG_DBG_OUT_DATA_MSB_SIZE 1
#define QM_REG_DBG_OUT_FRAME 0x16e7a0UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits that goes to the DBG block. Bit0 is the frame of data byte0; Bit1 is the frame of data byte1; Bit2 is the frame of data byte2; Bit3 is the frame of data byte4
#define QM_REG_DBG_OUT_FRAME_SIZE 1
#define QM_REG_DBG_OUT_VALID 0x16e7a4UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits that goes to the DBG block. Bit0 validtes data byte0; Bit1 validates data byte1; Bit2 validates data byte2; Bit3 validates data byte4
#define QM_REG_DBG_OUT_VALID_SIZE 1
#define QM_REG_BYTECRDPORT_MSB 0x168224UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_BYTECRDPORT_MSB_SIZE 1
#define QM_REG_BYTECRDPORT_LSB 0x168228UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_BYTECRDPORT_LSB_SIZE 1
#define QM_REG_VOQPORT_0 0x1682a0UL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_0_SIZE 1
#define QM_REG_VOQPORT_1 0x1682a4UL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_1_SIZE 1
#define QM_REG_VOQPORT_2 0x1682a8UL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_2_SIZE 1
#define QM_REG_VOQPORT_3 0x1682acUL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_3_SIZE 1
#define QM_REG_VOQPORT_4 0x1682b0UL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_4_SIZE 1
#define QM_REG_VOQPORT_5 0x1682b4UL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_5_SIZE 1
#define QM_REG_VOQPORT_6 0x1682b8UL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_6_SIZE 1
#define QM_REG_VOQPORT_7 0x1682bcUL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_7_SIZE 1
#define QM_REG_VOQPORT_8 0x1682c0UL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_8_SIZE 1
#define QM_REG_VOQPORT_9 0x1682c4UL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_9_SIZE 1
#define QM_REG_VOQPORT_10 0x1682c8UL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_10_SIZE 1
#define QM_REG_VOQPORT_11 0x1682ccUL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_VOQPORT_11_SIZE 1
#define QM_REG_PORT0BYTECRD 0x168300UL //ACCESS:R DataWidth:0x10 Description: NOT USED
#define QM_REG_PORT0BYTECRD_SIZE 1
#define QM_REG_PORT1BYTECRD 0x168304UL //ACCESS:R DataWidth:0x10 Description: NOT USED
#define QM_REG_PORT1BYTECRD_SIZE 1
#define QM_REG_REMAINPAUSETM0 0x168418UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_REMAINPAUSETM0_SIZE 1
#define QM_REG_REMAINPAUSETM1 0x16841cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_REMAINPAUSETM1_SIZE 1
#define QM_REG_WRRWEIGHTS_16 0x16e000UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_16_SIZE 1
#define QM_REG_WRRWEIGHTS_17 0x16e004UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_17_SIZE 1
#define QM_REG_WRRWEIGHTS_18 0x16e008UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_18_SIZE 1
#define QM_REG_WRRWEIGHTS_19 0x16e00cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_19_SIZE 1
#define QM_REG_WRRWEIGHTS_20 0x16e010UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_20_SIZE 1
#define QM_REG_WRRWEIGHTS_21 0x16e014UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_21_SIZE 1
#define QM_REG_WRRWEIGHTS_22 0x16e018UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_22_SIZE 1
#define QM_REG_WRRWEIGHTS_23 0x16e01cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_23_SIZE 1
#define QM_REG_WRRWEIGHTS_24 0x16e020UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_24_SIZE 1
#define QM_REG_WRRWEIGHTS_25 0x16e024UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_25_SIZE 1
#define QM_REG_WRRWEIGHTS_26 0x16e028UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_26_SIZE 1
#define QM_REG_WRRWEIGHTS_27 0x16e02cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_27_SIZE 1
#define QM_REG_WRRWEIGHTS_28 0x16e030UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_28_SIZE 1
#define QM_REG_WRRWEIGHTS_29 0x16e034UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_29_SIZE 1
#define QM_REG_WRRWEIGHTS_30 0x16e038UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_30_SIZE 1
#define QM_REG_WRRWEIGHTS_31 0x16e03cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_WRRWEIGHTS_31_SIZE 1
#define QM_REG_BASEADDR_EXT_A 0x16e100UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_BASEADDR_EXT_A_SIZE 64
#define QM_REG_PTRTBL_EXT_A 0x16e200UL //ACCESS:R DataWidth:0x36 Description: NOT USED
#define QM_REG_PTRTBL_EXT_A_SIZE 128
#define QM_REG_BIGRAMSELUPPERQUEUES 0x16e400UL //ACCESS:R DataWidth:0x1 Description: NOT USED
#define QM_REG_BIGRAMSELUPPERQUEUES_SIZE 1
#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_QSTATUS_LOW_EXT_A_SIZE 1
#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_QSTATUS_HIGH_EXT_A_SIZE 1
#define QM_REG_QVOQIDX_64 0x16e40cUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_64_SIZE 1
#define QM_REG_QVOQIDX_65 0x16e410UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_65_SIZE 1
#define QM_REG_QVOQIDX_66 0x16e414UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_66_SIZE 1
#define QM_REG_QVOQIDX_67 0x16e418UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_67_SIZE 1
#define QM_REG_QVOQIDX_68 0x16e41cUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_68_SIZE 1
#define QM_REG_QVOQIDX_69 0x16e420UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_69_SIZE 1
#define QM_REG_QVOQIDX_70 0x16e424UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_70_SIZE 1
#define QM_REG_QVOQIDX_71 0x16e428UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_71_SIZE 1
#define QM_REG_QVOQIDX_72 0x16e42cUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_72_SIZE 1
#define QM_REG_QVOQIDX_73 0x16e430UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_73_SIZE 1
#define QM_REG_QVOQIDX_74 0x16e434UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_74_SIZE 1
#define QM_REG_QVOQIDX_75 0x16e438UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_75_SIZE 1
#define QM_REG_QVOQIDX_76 0x16e43cUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_76_SIZE 1
#define QM_REG_QVOQIDX_77 0x16e440UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_77_SIZE 1
#define QM_REG_QVOQIDX_78 0x16e444UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_78_SIZE 1
#define QM_REG_QVOQIDX_79 0x16e448UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_79_SIZE 1
#define QM_REG_QVOQIDX_80 0x16e44cUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_80_SIZE 1
#define QM_REG_QVOQIDX_81 0x16e450UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_81_SIZE 1
#define QM_REG_QVOQIDX_82 0x16e454UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_82_SIZE 1
#define QM_REG_QVOQIDX_83 0x16e458UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_83_SIZE 1
#define QM_REG_QVOQIDX_84 0x16e45cUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_84_SIZE 1
#define QM_REG_QVOQIDX_85 0x16e460UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_85_SIZE 1
#define QM_REG_QVOQIDX_86 0x16e464UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_86_SIZE 1
#define QM_REG_QVOQIDX_87 0x16e468UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_87_SIZE 1
#define QM_REG_QVOQIDX_88 0x16e46cUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_88_SIZE 1
#define QM_REG_QVOQIDX_89 0x16e470UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_89_SIZE 1
#define QM_REG_QVOQIDX_90 0x16e474UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_90_SIZE 1
#define QM_REG_QVOQIDX_91 0x16e478UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_91_SIZE 1
#define QM_REG_QVOQIDX_92 0x16e47cUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_92_SIZE 1
#define QM_REG_QVOQIDX_93 0x16e480UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_93_SIZE 1
#define QM_REG_QVOQIDX_94 0x16e484UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_94_SIZE 1
#define QM_REG_QVOQIDX_95 0x16e488UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_95_SIZE 1
#define QM_REG_QVOQIDX_96 0x16e48cUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_96_SIZE 1
#define QM_REG_QVOQIDX_97 0x16e490UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_97_SIZE 1
#define QM_REG_QVOQIDX_98 0x16e494UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_98_SIZE 1
#define QM_REG_QVOQIDX_99 0x16e498UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_99_SIZE 1
#define QM_REG_QVOQIDX_100 0x16e49cUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_100_SIZE 1
#define QM_REG_QVOQIDX_101 0x16e4a0UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_101_SIZE 1
#define QM_REG_QVOQIDX_102 0x16e4a4UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_102_SIZE 1
#define QM_REG_QVOQIDX_103 0x16e4a8UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_103_SIZE 1
#define QM_REG_QVOQIDX_104 0x16e4acUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_104_SIZE 1
#define QM_REG_QVOQIDX_105 0x16e4b0UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_105_SIZE 1
#define QM_REG_QVOQIDX_106 0x16e4b4UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_106_SIZE 1
#define QM_REG_QVOQIDX_107 0x16e4b8UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_107_SIZE 1
#define QM_REG_QVOQIDX_108 0x16e4bcUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_108_SIZE 1
#define QM_REG_QVOQIDX_109 0x16e4c0UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_109_SIZE 1
#define QM_REG_QVOQIDX_110 0x16e4c4UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_110_SIZE 1
#define QM_REG_QVOQIDX_111 0x16e4c8UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_111_SIZE 1
#define QM_REG_QVOQIDX_112 0x16e4ccUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_112_SIZE 1
#define QM_REG_QVOQIDX_113 0x16e4d0UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_113_SIZE 1
#define QM_REG_QVOQIDX_114 0x16e4d4UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_114_SIZE 1
#define QM_REG_QVOQIDX_115 0x16e4d8UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_115_SIZE 1
#define QM_REG_QVOQIDX_116 0x16e4dcUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_116_SIZE 1
#define QM_REG_QVOQIDX_117 0x16e4e0UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_117_SIZE 1
#define QM_REG_QVOQIDX_118 0x16e4e4UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_118_SIZE 1
#define QM_REG_QVOQIDX_119 0x16e4e8UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_119_SIZE 1
#define QM_REG_QVOQIDX_120 0x16e4ecUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_120_SIZE 1
#define QM_REG_QVOQIDX_121 0x16e4f0UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_121_SIZE 1
#define QM_REG_QVOQIDX_122 0x16e4f4UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_122_SIZE 1
#define QM_REG_QVOQIDX_123 0x16e4f8UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_123_SIZE 1
#define QM_REG_QVOQIDX_124 0x16e4fcUL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_124_SIZE 1
#define QM_REG_QVOQIDX_125 0x16e500UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_125_SIZE 1
#define QM_REG_QVOQIDX_126 0x16e504UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_126_SIZE 1
#define QM_REG_QVOQIDX_127 0x16e508UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_QVOQIDX_127_SIZE 1
#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_HWAEMPTYMASK_MSB_EXT_A_SIZE 1
#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_HWAEMPTYMASK_LSB_EXT_A_SIZE 1
#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_ENBYTECRD_MSB_EXT_A_SIZE 1
#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_ENBYTECRD_LSB_EXT_A_SIZE 1
#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_BYTECRDPORT_MSB_EXT_A_SIZE 1
#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_BYTECRDPORT_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_0_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_0_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_1_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_1_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_2_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_2_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_3_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_3_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_4_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_4_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_5_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_5_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_6_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_6_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_7_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_7_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_8_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_8_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_9_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_9_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_10_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_10_MSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57cUL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_11_LSB_EXT_A_SIZE 1
#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580UL //ACCESS:R DataWidth:0x20 Description: NOT USED
#define QM_REG_VOQQMASK_11_MSB_EXT_A_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_0 0x16e584UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_0_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_1 0x16e588UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_1_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_2 0x16e58cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_2_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_3 0x16e590UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_3_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_4 0x16e594UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_4_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_5 0x16e598UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_5_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_6 0x16e59cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_6_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_7 0x16e5a0UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_7_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_8 0x16e5a4UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_8_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_9 0x16e5a8UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_9_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_10 0x16e5acUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_10_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_11 0x16e5b0UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_11_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_12 0x16e5b4UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_12_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_13 0x16e5b8UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_13_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_14 0x16e5bcUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_14_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_15 0x16e5c0UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_15_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_16 0x16e5c4UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_16_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_17 0x16e5c8UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_17_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_18 0x16e5ccUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_18_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_19 0x16e5d0UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_19_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_20 0x16e5d4UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_20_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_21 0x16e5d8UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_21_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_22 0x16e5dcUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_22_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_23 0x16e5e0UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_23_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_24 0x16e5e4UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_24_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_25 0x16e5e8UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_25_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_26 0x16e5ecUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_26_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_27 0x16e5f0UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_27_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_28 0x16e5f4UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_28_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_29 0x16e5f8UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_29_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_30 0x16e5fcUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_30_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_31 0x16e600UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_31_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_32 0x16e604UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_32_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_33 0x16e608UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_33_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_34 0x16e60cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_34_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_35 0x16e610UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_35_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_36 0x16e614UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_36_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_37 0x16e618UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_37_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_38 0x16e61cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_38_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_39 0x16e620UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_39_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_40 0x16e624UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_40_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_41 0x16e628UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_41_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_42 0x16e62cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_42_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_43 0x16e630UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_43_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_44 0x16e634UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_44_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_45 0x16e638UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_45_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_46 0x16e63cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_46_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_47 0x16e640UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_47_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_48 0x16e644UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_48_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_49 0x16e648UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_49_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_50 0x16e64cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_50_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_51 0x16e650UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_51_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_52 0x16e654UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_52_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_53 0x16e658UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_53_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_54 0x16e65cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_54_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_55 0x16e660UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_55_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_56 0x16e664UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_56_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_57 0x16e668UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_57_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_58 0x16e66cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_58_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_59 0x16e670UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_59_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_60 0x16e674UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_60_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_61 0x16e678UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_61_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_62 0x16e67cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_62_SIZE 1
#define QM_REG_QTASKCTR_EXT_A_63 0x16e680UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_QTASKCTR_EXT_A_63_SIZE 1
#define QM_REG_PAUSESTATE4 0x16e68cUL //ACCESS:R DataWidth:0x10 Description: NOT USED
#define QM_REG_PAUSESTATE4_SIZE 1
#define QM_REG_PAUSESTATE5 0x16e690UL //ACCESS:R DataWidth:0x10 Description: NOT USED
#define QM_REG_PAUSESTATE5_SIZE 1
#define QM_REG_PAUSESTATE6 0x16e694UL //ACCESS:R DataWidth:0x10 Description: NOT USED
#define QM_REG_PAUSESTATE6_SIZE 1
#define QM_REG_PAUSESTATE7 0x16e698UL //ACCESS:R DataWidth:0x10 Description: NOT USED
#define QM_REG_PAUSESTATE7_SIZE 1
#define QM_REG_REMAINPAUSETM2 0x16e69cUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_REMAINPAUSETM2_SIZE 1
#define QM_REG_REMAINPAUSETM3 0x16e6a0UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_REMAINPAUSETM3_SIZE 1
#define QM_REG_REMAINPAUSETM4 0x16e6a4UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_REMAINPAUSETM4_SIZE 1
#define QM_REG_REMAINPAUSETM5 0x16e6a8UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_REMAINPAUSETM5_SIZE 1
#define QM_REG_REMAINPAUSETM6 0x16e6acUL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_REMAINPAUSETM6_SIZE 1
#define QM_REG_REMAINPAUSETM7 0x16e6b0UL //ACCESS:R DataWidth:0x18 Description: NOT USED
#define QM_REG_REMAINPAUSETM7_SIZE 1
#define QM_REG_BIGRAMLOW_EXT_A_TM 0x16e6b4UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_BIGRAMLOW_EXT_A_TM_SIZE 1
#define QM_REG_BIGRAMHIGH_EXT_A_TM 0x16e6b8UL //ACCESS:R DataWidth:0x4 Description: NOT USED
#define QM_REG_BIGRAMHIGH_EXT_A_TM_SIZE 1
#define QM_REG_PQ2PCIFUNC_4 0x16e6ccUL //ACCESS:R DataWidth:0x3 Description: NOT USED
#define QM_REG_PQ2PCIFUNC_4_SIZE 1
#define QM_REG_PQ2PCIFUNC_5 0x16e6d0UL //ACCESS:R DataWidth:0x3 Description: NOT USED
#define QM_REG_PQ2PCIFUNC_5_SIZE 1
#define QM_REG_PQ2PCIFUNC_6 0x16e6d4UL //ACCESS:R DataWidth:0x3 Description: NOT USED
#define QM_REG_PQ2PCIFUNC_6_SIZE 1
#define QM_REG_PQ2PCIFUNC_7 0x16e6d8UL //ACCESS:R DataWidth:0x3 Description: NOT USED
#define QM_REG_PQ2PCIFUNC_7_SIZE 1
#define QM_REG_WRBUFFER_TM 0x16e6dcUL //ACCESS:R DataWidth:0x2 Description: NOT USED
#define QM_REG_WRBUFFER_TM_SIZE 1
#define QM_REG_BYTECRDCMDQ_0 0x16e6e8UL //ACCESS:R DataWidth:0x20 Description: NOT USED - removed for E3 B0
#define QM_REG_BYTECRDCMDQ_0_SIZE 1
#define QM_REG_BYTECRDCMDQ_1 0x16e6ecUL //ACCESS:R DataWidth:0x20 Description: NOT USED - removed for E3 B0
#define QM_REG_BYTECRDCMDQ_1_SIZE 1
#define QM_REG_BYTECRDCMDQ_2 0x16e6f0UL //ACCESS:R DataWidth:0x20 Description: NOT USED - removed for E3 B0
#define QM_REG_BYTECRDCMDQ_2_SIZE 1
#define QM_REG_BYTECRDCMDQ_3 0x16e6f4UL //ACCESS:R DataWidth:0x20 Description: NOT USED - removed for E3 B0
#define QM_REG_BYTECRDCMDQ_3_SIZE 1
#define QM_REG_VOQCMDQ 0x16e6f8UL //ACCESS:R DataWidth:0x18 Description: NOT USED - removed for E3 B0
#define QM_REG_VOQCMDQ_SIZE 1
#define QM_REG_QM_UNUSED_EMPTY_0 0x168458UL //ACCESS:R DataWidth:0x20 Unused empty space
#define QM_REG_QM_UNUSED_EMPTY_0_SIZE 234
#define QM_REG_QM_UNUSED_EMPTY_1 0x16884cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define QM_REG_QM_UNUSED_EMPTY_1_SIZE 45
#define QM_REG_QM_UNUSED_EMPTY_2 0x168c00UL //ACCESS:R DataWidth:0x20 Unused empty space
#define QM_REG_QM_UNUSED_EMPTY_2_SIZE 1280
#define QM_REG_QM_UNUSED_EMPTY_3 0x16e060UL //ACCESS:R DataWidth:0x20 Unused empty space
#define QM_REG_QM_UNUSED_EMPTY_3_SIZE 40
#define QM_REG_QM_UNUSED_EMPTY_4 0x16e710UL //ACCESS:R DataWidth:0x20 Unused empty space
#define QM_REG_QM_UNUSED_EMPTY_4_SIZE 22
#define QM_REG_QM_UNUSED_EMPTY_5 0x16e7dcUL //ACCESS:R DataWidth:0x20 Unused empty space
#define QM_REG_QM_UNUSED_EMPTY_5_SIZE 1545
#define SEM_FAST_REG_ECO_RESERVED 0x18608UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO
#define SEM_FAST_REG_FILTER_ID 0x18f00UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define SEM_FAST_FILTER_ID_REG_FILTER_CID (0xffffff<<0)
#define SEM_FAST_FILTER_ID_REG_FILTER_CID_SIZE 0
#define SEM_FAST_FILTER_ID_REG_FILTER_EVENT_ID (0xff<<24)
#define SEM_FAST_FILTER_ID_REG_FILTER_EVENT_ID_SIZE 24
#define SEM_FAST_REG_FILTER_ENABLE 0x18f40UL //ACCESS:RW DataWidth:0x7 Multi Field Register
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_EN (0x3<<0)
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_EN_SIZE 0
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_CID_USE_RCRD (0x1<<2)
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_CID_USE_RCRD_SIZE 2
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_CID_EN (0x1<<3)
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_CID_EN_SIZE 3
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_EVNT_ID_EN (0x1<<4)
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_EVNT_ID_EN_SIZE 4
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_DRA_SRC (0x1<<5)
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_DRA_SRC_SIZE 5
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_DRA_SRC_EN (0x1<<6)
#define SEM_FAST_FILTER_ENABLE_REG_FILTER_DRA_SRC_EN_SIZE 6
#define SEM_FAST_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD 0x19040UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define SEM_FAST_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD 0x19044UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define SEM_FAST_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD 0x19048UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define SEM_FAST_REG_CPU_MBIST_MEMCTRL_0_STATUS_0 0x1904cUL //ACCESS:R DataWidth:0x11 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define SEM_FAST_REG_CPU_MBIST_MEMCTRL_1_STATUS_0 0x19050UL //ACCESS:R DataWidth:0x11 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define SEM_FAST_REG_CPU_MBIST_MEMCTRL_2_STATUS_0 0x19054UL //ACCESS:R DataWidth:0x11 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define SEM_FAST_REG_CPU_MBIST_MEMCTRL_3_STATUS_0 0x19058UL //ACCESS:R DataWidth:0x11 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define SEM_FAST_REG_CPU_MBIST_MEMCTRL_3_CNTRL_CMD 0x1905cUL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define SEM_FAST_REG_CPU_MBIST_MEMCTRL_4_STATUS_0 0x19060UL //ACCESS:R DataWidth:0x11 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define SEM_FAST_REG_CPU_MBIST_MEMCTRL_4_CNTRL_CMD 0x19064UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define SEM_FAST_REG_PWRWDOG_E40_PWRDN 0x19080UL //ACCESS:RW DataWidth:0x1 Description: Power watchdog power down. 1 - power down; 0 - power up.Global register. Reset on POR.
#define SEM_FAST_REG_PWRWDOG_E40_CGFG 0x19084UL //ACCESS:RW DataWidth:0x8 Description: Power watchdog configuration. Adjustment of integer delay cgfg[7:4] and fractional delay cgfg[3:0]; valid range [0:191]. Global register. Reset on POR.
#define SEM_FAST_REG_PWRWDOG_E40_RSEL 0x19088UL //ACCESS:RW DataWidth:0x3 Description: Power watchdog selection of delay setting of ring delay element; recommended setting is 3b100 for longest ring delay; 3b010 will shorten the ring by one inverter+inverting mux; 3b001 will shorten the ring by two inverter+inverting mux cells;Global register. Reset on POR.
#define SEM_FAST_REG_PWRWDOG_E40_CLEARCFG 0x1908cUL //ACCESS:RW DataWidth:0x3 Description: Power watchdog selection of delay chain for the reset pulse; recommended setting is 3b100 for longest pulse; 3b010 will shorten the reset pulse by one inverter+inverting mux delay; 3b001 will shorten the reset pulse by two inverter+inverting mux delays; set clearcfg more or equal than rsel to ensure the ring gets flushed from the previous cycle; reducing the reset pulse length is needed to reach the highest possible operating frequencies.Global register. Reset on POR.
#define SEM_FAST_REG_PWRWDOG_E40_START 0x19090UL //ACCESS:RW DataWidth:0x6 Description: Power watchdog. Sets the number of trips through the ring delay element to start+1; range for start is [-1:31].Global register. Reset on POR.
#define SEM_FAST_REG_PWRWDOG_E40_ACCU_RUN 0x19094UL //ACCESS:RW DataWidth:0x1 Description: Power watchdog. When 0 all registers and states are of power watchdog accu sub-module are reset. Global register. Reset on POR.
#define SEM_FAST_REG_PWRWDOG_E40_ACCU_SKIP 0x19098UL //ACCESS:RW DataWidth:0x2 Description: Power watchdog. Allows to decimate the good signal to measure for beats. Global register. Reset on POR.
#define SEM_FAST_REG_PWRWDOG_E40_ACCU_SKIP_START 0x1909cUL //ACCESS:RW DataWidth:0x2 Description: Power watchdog. Start value of skip counter. Global register. Reset on POR.
#define SEM_FAST_REG_PWRWDOG_E40_DATA 0x190a0UL //ACCESS:R DataWidth:0xa Description: Power watchdog data.Global register. Reset on POR.
#define SEM_FAST_REG_PWRWDOG_E40_DONE 0x190a4UL //ACCESS:R DataWidth:0x1 Description: Power watchdog done. Global register. Reset on POR.
#define SEM_FAST_REG_SEM_FAST_PRTY_MASK 0x1ffe0UL //ACCESS:RW DataWidth:0x1 Description: Parity mask register #0 read/write
#define SEM_FAST_SEM_FAST_PRTY_MASK_REG_PARITY (0x1<<0)
#define SEM_FAST_SEM_FAST_PRTY_MASK_REG_PARITY_SIZE 0
#define SEM_FAST_REG_SEM_FAST_PRTY_STS_WR 0x1ffe4UL //ACCESS:WR DataWidth:0x1 Description: Parity register #0 bit set or clear
#define SEM_FAST_SEM_FAST_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define SEM_FAST_SEM_FAST_PRTY_STS_WR_REG_PARITY_SIZE 0
#define SEM_FAST_REG_SEM_FAST_PRTY_STS_CLR 0x1ffe8UL //ACCESS:RC DataWidth:0x1 Description: Parity register #0 read clear
#define SEM_FAST_SEM_FAST_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define SEM_FAST_SEM_FAST_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define SEM_FAST_REG_SEM_FAST_PRTY_STS 0x1ffecUL //ACCESS:R DataWidth:0x1 Description: Parity register #0 read
#define SEM_FAST_SEM_FAST_PRTY_STS_REG_PARITY (0x1<<0)
#define SEM_FAST_SEM_FAST_PRTY_STS_REG_PARITY_SIZE 0
#define SEM_FAST_REG_SEM_FAST_INT_MASK 0x1fff0UL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define SEM_FAST_REG_SEM_FAST_INT_STS_WR 0x1fff4UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define SEM_FAST_REG_SEM_FAST_INT_STS_CLR 0x1fff8UL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define SEM_FAST_REG_SEM_FAST_INT_STS 0x1fffcUL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define SEM_FAST_REG_INT_RAM0 0UL //ACCESS:RW DataWidth:0x20 Description: Internal RAM0 (if bit lsb of addr =0 => write to bits[31:0; otherway to [63:32)
#define SEM_FAST_REG_INT_RAM0_SIZE 16384
#define SEM_FAST_REG_CAM_MASK_LSB 0x10000UL //ACCESS:RW DataWidth:0x20 Description: cam_mask [31:0] only for search command
#define SEM_FAST_REG_CAM_MASK_LSB_SIZE 1
#define SEM_FAST_REG_CAM_MASK_MIDDLE 0x10040UL //ACCESS:RW DataWidth:0x1c Description: cam mask [59:32] middle bits only for cam_wdth=80 bit for search) when cam width is 80 bit; for cam width = 52 bit is not used
#define SEM_FAST_REG_CAM_MASK_MIDDLE_SIZE 1
#define SEM_FAST_REG_CAM_MASK_MSB 0x10400UL //ACCESS:RW DataWidth:0x14 Description: cam_mask [51:32] only for search command for cam width =52; or cam_mask [79:60] only for search command for cam width =81
#define SEM_FAST_REG_CAM_MASK_MSB_SIZE 1
#define SEM_FAST_REG_CAM_VALUE_LSB 0x10800UL //ACCESS:RW DataWidth:0x20 Description: cam_value [31:0]; only for search; add; invalidate commands
#define SEM_FAST_REG_CAM_VALUE_LSB_SIZE 1
#define SEM_FAST_REG_CAM_VALUE_MIDDLE 0x10840UL //ACCESS:RW DataWidth:0x1c Description: cam_value [59:32] only for search; add; invalidate commands when cam width is 80 bit; for cam width = 52 bit is not used
#define SEM_FAST_REG_CAM_VALUE_MIDDLE_SIZE 1
#define SEM_FAST_REG_CAM_VALUE_MSB 0x10c00UL //ACCESS:W DataWidth:0x20 Description: write or read to this offset will execute CAM command:b19:0-cam_value[51:32]; b29:20-offset only for search command; b30=1-add;0-invalidate; b31=1-search; 0-write
#define SEM_FAST_REG_CAM_VALUE_MSB_SIZE 256
#define SEM_FAST_REG_CAM_RD_DATA_MSB 0x11000UL //ACCESS:R DataWidth:0x14 Description: Read data from CAM: b20- validity; b[19:0] - cam_read_data[51:32] when cam width is 52 bit; or b20- validity; b[19:0] - cam_read_data[79:60] when cam width is 80 bit
#define SEM_FAST_REG_CAM_RD_DATA_MSB_SIZE 1
#define SEM_FAST_REG_CAM_RD_DATA_MIDDLE 0x11040UL //ACCESS:R DataWidth:0x1c Description: Read data from CAM : b59:32 -cam read data only when cam width = 80 bit; it is not used for cam width = 52 bit
#define SEM_FAST_REG_CAM_RD_DATA_MIDDLE_SIZE 1
#define SEM_FAST_REG_CAM_SEARCH 0x11400UL //ACCESS:R DataWidth:0xa Description: cam search result: b8:0-search result; b9-match
#define SEM_FAST_REG_CAM_SEARCH_SIZE 1
#define SEM_FAST_REG_CAM_MODE 0x11440UL //ACCESS:RW DataWidth:0x1 Description: Cam mode - 0: cam width =52 bit; 1=cam width=80 bit
#define SEM_FAST_REG_CAM_MODE_SIZE 1
#define SEM_FAST_REG_CAM_PRTY_EN 0x11480UL //ACCESS:RW DataWidth:0x1 Description: Cam parity enable - 0: cam read mechanism for parity check is disabled; 1- enabled
#define SEM_FAST_REG_CAM_PRTY_EN_SIZE 1
#define SEM_FAST_REG_CAM_MATCH_VECTOR 0x114c0UL //ACCESS:R DataWidth:0x20 Description: cam match vector 128 bit
#define SEM_FAST_REG_CAM_MATCH_VECTOR_SIZE 1
#define SEM_FAST_REG_PAS_REG_SET0 0x11800UL //ACCESS:R DataWidth:0x20 Description: passive register set0. If address lsb=0=>read from bits 31:0; otherway from bits 63:32. Used only for debugging. STORm must get waitp in time of reading this memory.
#define SEM_FAST_REG_PAS_REG_SET0_SIZE 56
#define SEM_FAST_REG_PAS_REG_SET1 0x11c00UL //ACCESS:R DataWidth:0x20 Description: passive register set1. If address lsb=0=>read from bits 31:0; otherway from bits 63:32. Used only for debugging. STORm must get waitp in time of reading this memory.
#define SEM_FAST_REG_PAS_REG_SET1_SIZE 56
#define SEM_FAST_REG_ACTIVE_REG_SET 0x12000UL //ACCESS:R DataWidth:0x1 Description: active register set of STORM. If 1 then passive register set 0 is active; other way passive register set 1 is active.
#define SEM_FAST_REG_ACTIVE_REG_SET_SIZE 1
#define SEM_FAST_REG_INT_RAM1 0x12400UL //ACCESS:RW DataWidth:0x20 Description: Internal RAM1 (if bit lsb of addr =0 => write to bits[31:0; otherway to [63:32)
#define SEM_FAST_REG_INT_RAM1_SIZE 5632
#define SEM_FAST_REG_FOC0_INIT_CREDIT 0x18000UL //ACCESS:RW DataWidth:0x8 Description: Init credit counter for FOC0.
#define SEM_FAST_REG_FOC0_INIT_CREDIT_SIZE 1
#define SEM_FAST_REG_FOC1_INIT_CREDIT 0x18040UL //ACCESS:RW DataWidth:0x8 Description: Init credit counter for FOC1.
#define SEM_FAST_REG_FOC1_INIT_CREDIT_SIZE 1
#define SEM_FAST_REG_FOC2_INIT_CREDIT 0x18080UL //ACCESS:RW DataWidth:0x8 Description: Init credit counter for FOC2.
#define SEM_FAST_REG_FOC2_INIT_CREDIT_SIZE 1
#define SEM_FAST_REG_FOC3_INIT_CREDIT 0x180c0UL //ACCESS:RW DataWidth:0x8 Description: Init credit counter for FOC3.
#define SEM_FAST_REG_FOC3_INIT_CREDIT_SIZE 1
#define SEM_FAST_REG_SYNC_DRA_RD_ALM_FULL 0x18100UL //ACCESS:RW DataWidth:0x5 Description: Almost full for DRA_RD SYNC FIFO
#define SEM_FAST_REG_SYNC_DRA_RD_ALM_FULL_SIZE 1
#define SEM_FAST_REG_SYNC_RAM_RD_ALM_FULL 0x18140UL //ACCESS:RW DataWidth:0x5 Description: Almost full for RAM_RD SYNC FIFO
#define SEM_FAST_REG_SYNC_RAM_RD_ALM_FULL_SIZE 1
#define SEM_FAST_REG_SYNC_EXT_STORE_ALM_FULL 0x18180UL //ACCESS:RW DataWidth:0x6 Description: Almost full for EXT_STORE SYNC FIFO
#define SEM_FAST_REG_SYNC_EXT_STORE_ALM_FULL_SIZE 1
#define SEM_FAST_REG_MAX_HANDLER_CYCLES 0x181c0UL //ACCESS:RW DataWidth:0x10 Description: maximal number of cycles when STORM is idle. After this number interrupt will be sent.
#define SEM_FAST_REG_MAX_HANDLER_CYCLES_SIZE 1
#define SEM_FAST_REG_IDLE_CYCLES 0x18200UL //ACCESS:R DataWidth:0x20 Description: STATISTICS - number of idle cycles of STORM
#define SEM_FAST_REG_IDLE_CYCLES_SIZE 1
#define SEM_FAST_REG_STORE_HALT_CYCLES 0x18240UL //ACCESS:R DataWidth:0x20 Description: STATISTICS - number of cycles when STORM is idle because of waitp from EXT_STORE FIFO
#define SEM_FAST_REG_STORE_HALT_CYCLES_SIZE 1
#define SEM_FAST_REG_FIN_HALT_CYCLES 0x18280UL //ACCESS:R DataWidth:0x20 Description: STATISTICS - number of cycles when STORM is idle because of waitp from FIN FIFO
#define SEM_FAST_REG_FIN_HALT_CYCLES_SIZE 1
#define SEM_FAST_REG_PARTIAL_HALT_CYCLES 0x182c0UL //ACCESS:R DataWidth:0x20 Description: STATISTICS - number of cycles when STORM is idle because of waitp from partial FIN
#define SEM_FAST_REG_PARTIAL_HALT_CYCLES_SIZE 1
#define SEM_FAST_REG_RT_CLK_TICK1 0x18300UL //ACCESS:RW DataWidth:0x18 Description: Tick for real time counter1
#define SEM_FAST_REG_RT_CLK_TICK1_SIZE 1
#define SEM_FAST_REG_RT_CLK_TICK2 0x18340UL //ACCESS:RW DataWidth:0x18 Description: Tick for real time counter2
#define SEM_FAST_REG_RT_CLK_TICK2_SIZE 1
#define SEM_FAST_REG_RT_CLK_TICK3 0x18380UL //ACCESS:RW DataWidth:0x18 Description: Tick for real time counter3
#define SEM_FAST_REG_RT_CLK_TICK3_SIZE 1
#define SEM_FAST_REG_RT_CLK_TICK4 0x183c0UL //ACCESS:RW DataWidth:0x18 Description: Tick for real time counter4
#define SEM_FAST_REG_RT_CLK_TICK4_SIZE 1
#define SEM_FAST_REG_REAL_TIME_CNT1 0x18400UL //ACCESS:R DataWidth:0x20 Description: real_time_cnt1 - reset value is changed next clock after reset
#define SEM_FAST_REG_REAL_TIME_CNT1_SIZE 1
#define SEM_FAST_REG_REAL_TIME_CNT2 0x18440UL //ACCESS:R DataWidth:0x20 Description: real_time_cnt2 - reset value is changed next clock after reset
#define SEM_FAST_REG_REAL_TIME_CNT2_SIZE 1
#define SEM_FAST_REG_REAL_TIME_CNT3 0x18480UL //ACCESS:R DataWidth:0x20 Description: real_time_cnt3 - reset value is changed next clock after reset
#define SEM_FAST_REG_REAL_TIME_CNT3_SIZE 1
#define SEM_FAST_REG_REAL_TIME_CNT4 0x184c0UL //ACCESS:R DataWidth:0x20 Description: real_time_cnt4 - reset value is changed next clock after reset
#define SEM_FAST_REG_REAL_TIME_CNT4_SIZE 1
#define SEM_FAST_REG_FOC_WITHOUT_CREDIT 0x18500UL //ACCESS:R DataWidth:0x16 Description: Status of FIN command: if message can to send with not enough credit: fin[21];foc0[20];foc1[19];foc2[18];foc3[17];pas[16];highest_rp[15:10;lowest_rp[9:4];foc3_rdy[3];foc2_rdy[2];foc1_rdy[1];foc0_rdy[0]
#define SEM_FAST_REG_FOC_WITHOUT_CREDIT_SIZE 1
#define SEM_FAST_REG_PC_BREAKPOINT 0x18540UL //ACCESS:RW DataWidth:0xf Description: PC breakpoint: address of PRAM. If STORM will read from this address. It will get waitp. It is active when ~breakpoint_waitp_disable = 1
#define SEM_FAST_REG_PC_BREAKPOINT_SIZE 1
#define SEM_FAST_REG_DBG_ALM_FULL 0x18580UL //ACCESS:RW DataWidth:0x7 Description: Almost full for DBG SYNC FIFO
#define SEM_FAST_REG_DBG_ALM_FULL_SIZE 1
#define SEM_FAST_REG_STORM_RF0_TM0 0x185c0UL //ACCESS:RW DataWidth:0x4 Description: TM for STORM_RF0 instaqnce 0
#define SEM_FAST_REG_STORM_RF0_TM0_SIZE 1
#define SEM_FAST_REG_STORM_RF0_TM1 0x185c4UL //ACCESS:RW DataWidth:0x4 Description: TM for STORM_RF0 instance 1
#define SEM_FAST_REG_STORM_RF0_TM1_SIZE 1
#define SEM_FAST_REG_STORM_RF1_TM0 0x185c8UL //ACCESS:RW DataWidth:0x4 Description: TM for STORM_RF1 instaqnce 0
#define SEM_FAST_REG_STORM_RF1_TM0_SIZE 1
#define SEM_FAST_REG_STORM_RF1_TM1 0x185ccUL //ACCESS:RW DataWidth:0x4 Description: TM for STORM_RF1 instance 1
#define SEM_FAST_REG_STORM_RF1_TM1_SIZE 1
#define SEM_FAST_REG_RAM0_RD_TM 0x185d0UL //ACCESS:RW DataWidth:0x8 Description: TM for RAM0_RD SYNC FIFO
#define SEM_FAST_REG_RAM0_RD_TM_SIZE 1
#define SEM_FAST_REG_RAM1_RD_TM 0x185d4UL //ACCESS:RW DataWidth:0x2 Description: TM for RAM1_RD SYNC FIFO
#define SEM_FAST_REG_RAM1_RD_TM_SIZE 1
#define SEM_FAST_REG_RAM0_WR_TM 0x185d8UL //ACCESS:RW DataWidth:0x8 Description: TM for RAM0_WR SYNC FIFO
#define SEM_FAST_REG_RAM0_WR_TM_SIZE 1
#define SEM_FAST_REG_RAM1_WR_TM 0x185dcUL //ACCESS:RW DataWidth:0x2 Description: TM for RAM1_WR SYNC FIFO
#define SEM_FAST_REG_RAM1_WR_TM_SIZE 1
#define SEM_FAST_REG_EXT_STORE_TM 0x185e0UL //ACCESS:RW DataWidth:0x8 Description: TM for EXT_STORE SYNC FIFO
#define SEM_FAST_REG_EXT_STORE_TM_SIZE 1
#define SEM_FAST_REG_DBG_LSB_TM 0x185e4UL //ACCESS:RW DataWidth:0x8 Description: TM for DBG_LSB SYNC FIFO
#define SEM_FAST_REG_DBG_LSB_TM_SIZE 1
#define SEM_FAST_REG_DBG_MSB_TM 0x185e8UL //ACCESS:RW DataWidth:0x8 Description: TM for DBG_MSB SYNC FIFO
#define SEM_FAST_REG_DBG_MSB_TM_SIZE 1
#define SEM_FAST_REG_DRA_WR_LSB_TM 0x185ecUL //ACCESS:RW DataWidth:0x8 Description: TM for DRA_WR_LSB SYNC FIFO
#define SEM_FAST_REG_DRA_WR_LSB_TM_SIZE 1
#define SEM_FAST_REG_DRA_WR_MSB_TM 0x185f0UL //ACCESS:RW DataWidth:0x8 Description: TM for DRA_WR_MSB SYNC FIFO
#define SEM_FAST_REG_DRA_WR_MSB_TM_SIZE 1
#define SEM_FAST_REG_INT_TABLE_TM 0x185f4UL //ACCESS:RW DataWidth:0x8 Description: TM for NT_TABLE SYNC FIFO
#define SEM_FAST_REG_INT_TABLE_TM_SIZE 1
#define SEM_FAST_REG_FIN_FIFO_TM 0x185f8UL //ACCESS:RW DataWidth:0x8 Description: TM for FIN SYNC FIFO
#define SEM_FAST_REG_FIN_FIFO_TM_SIZE 1
#define SEM_FAST_REG_DRA_RD_LSB_TM 0x185fcUL //ACCESS:RW DataWidth:0x8 Description: TM for DRA_RD_LSB SYNC FIFO
#define SEM_FAST_REG_DRA_RD_LSB_TM_SIZE 1
#define SEM_FAST_REG_DRA_RD_MSB_TM 0x18600UL //ACCESS:RW DataWidth:0x8 Description: TM for DRA_RD_MSB SYNC FIFO
#define SEM_FAST_REG_DRA_RD_MSB_TM_SIZE 1
#define SEM_FAST_REG_RAM1_TM 0x18604UL //ACCESS:RW DataWidth:0x5 Description: TM for INT_RAM1
#define SEM_FAST_REG_RAM1_TM_SIZE 1
#define SEM_FAST_REG_ERROR_RST 0x18800UL //ACCESS:W DataWidth:0x1 Description: reset to error interrupt
#define SEM_FAST_REG_ERROR_RST_SIZE 1
#define SEM_FAST_REG_PARITY_RST 0x18840UL //ACCESS:W DataWidth:0x1 Description: reset to parity interrupt
#define SEM_FAST_REG_PARITY_RST_SIZE 1
#define SEM_FAST_REG_RAM0_EXT_DISABLE 0x18880UL //ACCESS:RW DataWidth:0x1 Description: disable for SDM write to int_ram0
#define SEM_FAST_REG_RAM0_EXT_DISABLE_SIZE 1
#define SEM_FAST_REG_RAM1_EXT_DISABLE 0x188c0UL //ACCESS:RW DataWidth:0x1 Description: disable for SDM write to int_ram1
#define SEM_FAST_REG_RAM1_EXT_DISABLE_SIZE 1
#define SEM_FAST_REG_FULL 0x18900UL //ACCESS:R DataWidth:0x12 Description: Full data spelling : {vfc_out_fifo_full; cam_inp_msb_full; ext_load_rdy; sync_dbg_full; rd_fin_full; wr_data_full; inter_full; sync_wr_pop_full; sync_rd_push_full; sync_fin_full; cam_inp_lsb_full ; cam_inp_msb_full; cam_out_full; sync_ram0_rd_full; sync_ram1_rd_full; sync_ram0_wr_full; sync_ram1_wr_full; sync_ext_store_full}
#define SEM_FAST_REG_FULL_SIZE 1
#define SEM_FAST_REG_EMPTY 0x18940UL //ACCESS:R DataWidth:0x11 Description: Empty data spelling;{vfc_out_fifo_empty; cam_inp_msb2_empty; sync_dbg_empty; rd_fin_empty; wr_data_empty; inter_empty; sync_wr_pop_empty; sync_rd_push_empty; sync_fin_empty; cam_inp_lsb_empty; cam_inp_msb_empty; cam_out_empty; sync_ram0_rd_empty; sync_ram1_rd_empty; sync_ram0_wr_empty; sync_ram1_wr_empty; sync_ext_store_empty}
#define SEM_FAST_REG_EMPTY_SIZE 1
#define SEM_FAST_REG_ALM_FULL 0x18980UL //ACCESS:R DataWidth:0x3 Description: alm_full data spelling; {ram0_alm_full; ram1_alm_full; ext_alm_full}
#define SEM_FAST_REG_ALM_FULL_SIZE 1
#define SEM_FAST_REG_STATE_MACHINE 0x189c0UL //ACCESS:R DataWidth:0x6 Description: state machine bus spelling [vfc_ou_fifo_counter[11:8]; 2'b0; int_state[5:4]; 1'b0; wr_state[2:0}]
#define SEM_FAST_REG_STATE_MACHINE_SIZE 1
#define SEM_FAST_REG_PRAM_LAST_ADDR 0x18a00UL //ACCESS:R DataWidth:0x1e Description: last read address from STORM to pram {add_p_out_high; 2'b0; add_p_out_low}
#define SEM_FAST_REG_PRAM_LAST_ADDR_SIZE 1
#define SEM_FAST_REG_RBC_CAM_CLK_DIV 0x18a40UL //ACCESS:RW DataWidth:0x3 Description: cam clock divider : (may be equal to 2; 4; or 8 only)
#define SEM_FAST_REG_RBC_CAM_CLK_DIV_SIZE 1
#define SEM_FAST_REG_WAITP 0x18a80UL //ACCESS:RW DataWidth:0x1 Description: waitp to STORM(b0=1-set; b0=0-reset)
#define SEM_FAST_REG_WAITP_SIZE 1
#define SEM_FAST_REG_DEBUG_ACTIVE 0x18ac0UL //ACCESS:RW DataWidth:0x1 Description: debug active register. If set then output to debug FIFO is open
#define SEM_FAST_REG_DEBUG_ACTIVE_SIZE 1
#define SEM_FAST_REG_DEBUG_MODE 0x18b00UL //ACCESS:RW DataWidth:0x3 Description: debug mode (0-store to 0x7000; 1-pram_addr; 2-foc ready; 3-(b[31int; b[30:16-int_add;b[15-dra_rd; b[14-dra_rd_set; b[13:8-dra_rd_addr; b[7dra_wr; b[6dra_wr_set; b[5:0dra_wr_addr); 4- (dmem_wr[17; dmem_rd[16; dmem_add[15:0); 5-(int_rbc_cur_state[5:4; 1'b0; wr_rbc_cur_state[2:0); 6-recording handlers. This register is not applicable when ~debug_active =0
#define SEM_FAST_REG_DEBUG_MODE_SIZE 1
#define SEM_FAST_REG_INT_WAITP_DISABLE 0x18b40UL //ACCESS:RW DataWidth:0x1 Description: disable waitp by STORM to itself. If this register equal to 1then STORE from microcode to address 0x6015 is disabled.
#define SEM_FAST_REG_INT_WAITP_DISABLE_SIZE 1
#define SEM_FAST_REG_EXT_WAITP_DISABLE 0x18b80UL //ACCESS:RW DataWidth:0x1 Description: disable waitp from other 3 STORM
#define SEM_FAST_REG_EXT_WAITP_DISABLE_SIZE 1
#define SEM_FAST_REG_BREAKPOINT_WAITP_DISABLE 0x18bc0UL //ACCESS:RW DataWidth:0x1 Description: disable waitp by address is equal to the PcBreakpoint
#define SEM_FAST_REG_BREAKPOINT_WAITP_DISABLE_SIZE 1
#define SEM_FAST_REG_DBG_WAITP_DISABLE 0x18c00UL //ACCESS:RW DataWidth:0x1 Description: disable waitp by full debug fifo for debug mode 0
#define SEM_FAST_REG_DBG_WAITP_DISABLE_SIZE 1
#define SEM_FAST_REG_DBG_MODE3_SRC_DISABLE 0x18c40UL //ACCESS:RW DataWidth:0x3 Description: Disable register for each output of ~debug_mode=3 : b0-dra_wr disable; b1-dra_rd disable; b2-int disable
#define SEM_FAST_REG_DBG_MODE3_SRC_DISABLE_SIZE 1
#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE 0x18c80UL //ACCESS:RW DataWidth:0x2 Description: Disable register for each output of ~debug_mode=4 : b0-dmem_wr disable; b1-dmem_rd disable
#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_SIZE 1
#define SEM_FAST_REG_CAM_BIST_EN 0x18cc0UL //ACCESS:RW DataWidth:0x1 Description: Bist enable bit for Cam
#define SEM_FAST_REG_CAM_BIST_EN_SIZE 1
#define SEM_FAST_REG_CAM_BIST_DBG_SEL 0x18cc4UL //ACCESS:RW DataWidth:0x8 Description: This registers selects the type of data present on bist_status bus
#define SEM_FAST_REG_CAM_BIST_DBG_SEL_SIZE 1
#define SEM_FAST_REG_CAM_BIST_DONE 0x18d00UL //ACCESS:R DataWidth:0x1 Description: Bist done bit from CAM
#define SEM_FAST_REG_CAM_BIST_DONE_SIZE 1
#define SEM_FAST_REG_CAM_BIST_GO 0x18d40UL //ACCESS:R DataWidth:0x1 Description: Bist go bit from CAM
#define SEM_FAST_REG_CAM_BIST_GO_SIZE 1
#define SEM_FAST_REG_CAM_S2_STATUS 0x18d80UL //ACCESS:R DataWidth:0x20 Description: S2 status from CAM
#define SEM_FAST_REG_CAM_S2_STATUS_SIZE 1
#define SEM_FAST_REG_CAM_S3_STATUS 0x18dc0UL //ACCESS:R DataWidth:0x20 Description: S3 status from CAM
#define SEM_FAST_REG_CAM_S3_STATUS_SIZE 1
#define SEM_FAST_REG_CAM_S5_STATUS 0x18e00UL //ACCESS:R DataWidth:0x20 Description: S5 status from CAM
#define SEM_FAST_REG_CAM_S5_STATUS_SIZE 1
#define SEM_FAST_REG_CAM_S6_STATUS 0x18e40UL //ACCESS:R DataWidth:0x20 Description: S6 status from CAM
#define SEM_FAST_REG_CAM_S6_STATUS_SIZE 1
#define SEM_FAST_REG_CAM_S8_STATUS 0x18e80UL //ACCESS:R DataWidth:0x20 Description: S8 status from CAM
#define SEM_FAST_REG_CAM_S8_STATUS_SIZE 1
#define SEM_FAST_REG_CAM_BIST_STATUS 0x18e84UL //ACCESS:R DataWidth:0x20 Description: Bist status from CAM
#define SEM_FAST_REG_CAM_BIST_STATUS_SIZE 1
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x18ec0UL //ACCESS:RW DataWidth:0x7 Description: Disable register for each output of ~debug_mode=6 : b0-dra_in disable; b1-fin disable; b2-load disable;b3-pram disable;b4-ext storedisable; b5-other store disable; ; b6-vfc store disable)
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE_SIZE 1
#define SEM_FAST_REG_DBG_HALT_CYCLES 0x18f80UL //ACCESS:R DataWidth:0x20 Description: STATISTICS - number of cycles when STORM is idle because of waitp from debug block (recorded handlers or waitp mode)
#define SEM_FAST_REG_DBG_HALT_CYCLES_SIZE 1
#define SEM_FAST_REG_EVENT_ID_MASK 0x18fc0UL //ACCESS:RW DataWidth:0x8 Description: mask for event id. 1- specified bit is ignored; 0 - specified bit is checked
#define SEM_FAST_REG_EVENT_ID_MASK_SIZE 1
#define SEM_FAST_REG_VFC_DATA_WR 0x18fc4UL //ACCESS:W DataWidth:0x20 Description: Command data for VFC. VFC will accumulate all writing to this register till will be done write to vfc_wr_addr
#define SEM_FAST_REG_VFC_DATA_WR_SIZE 1
#define SEM_FAST_REG_VFC_ADDR 0x18fc8UL //ACCESS:W DataWidth:0xc Description: Command address for VFC. Write to it should be done when all command data was already written to vfc_data_wr register
#define SEM_FAST_REG_VFC_ADDR_SIZE 1
#define SEM_FAST_REG_VFC_DATA_RD 0x18fccUL //ACCESS:R DataWidth:0x20 Description: Read data from VFC
#define SEM_FAST_REG_VFC_DATA_RD_SIZE 1
#define SEM_FAST_REG_VFC_STATUS 0x18fd0UL //ACCESS:R DataWidth:0x3 Description: B0 - response is ready. It is set when response cycle of 32 bit is ready from VFC block. It is reset when read is done from vfc_data_rd register; B1 - vfc is busy. It is set when was done write to vfc_addr register. It is reset when last from VFC was received. B2 - sending command is on going. It will be set when was done write to vfc_data_wr register. It will be reset when it was done write to vfc_addr register. New command may be sent from RBC when all 3 bits of this register is reset.
#define SEM_FAST_REG_VFC_STATUS_SIZE 1
#define SEM_FAST_REG_GPRE0 0x18fd4UL //ACCESS:R DataWidth:0x8 Description: GPRE0 bits {2'b0; message is ready in passive register file; dra_wr path is not empty; vfc ready;ext_load_rdy; cam ready; dra-empty; thread_err}
#define SEM_FAST_REG_GPRE0_SIZE 1
#define SEM_FAST_REG_IDLE_CNT0 0x18fd8UL //ACCESS:R DataWidth:0x20 Description: Statistics - number of STORM idle cycles when whole SEM block is empty - no sleeping threads and no messages from FIC
#define SEM_FAST_REG_IDLE_CNT0_SIZE 1
#define SEM_FAST_REG_IDLE_CNT1 0x18fdcUL //ACCESS:R DataWidth:0x20 Description: Statistics - number of STORM idle cycles when all threads are sleeping
#define SEM_FAST_REG_IDLE_CNT1_SIZE 1
#define SEM_FAST_REG_IDLE_CNT2 0x18fe0UL //ACCESS:R DataWidth:0x20 Description: Statistics - number of STORM idle cycles when dra write is slower but not because of missed credits from foc interfaces
#define SEM_FAST_REG_IDLE_CNT2_SIZE 1
#define SEM_FAST_REG_IDLE_CNT3 0x18fe4UL //ACCESS:R DataWidth:0x20 Description: Statistics - number of STORM idle cycles when dra write is slower because of missed credits from foc interfaces
#define SEM_FAST_REG_IDLE_CNT3_SIZE 1
#define SEM_FAST_REG_IDLE_CNT4 0x18fe8UL //ACCESS:R DataWidth:0x20 Description: Statistics - number of STORM idle cycles when at least one thread is allocated
#define SEM_FAST_REG_IDLE_CNT4_SIZE 1
#define SEM_FAST_REG_MAX_THREAD_NUM 0x18fecUL //ACCESS:RW DataWidth:0x6 Description: Statistics - number of STORM idle cycles when dra write is slower because of missed credits from foc interfaces
#define SEM_FAST_REG_MAX_THREAD_NUM_SIZE 1
#define SEM_FAST_REG_GPRE 0x19000UL //ACCESS:R DataWidth:0x20 Description: 16 GPRE registers from STORM
#define SEM_FAST_REG_GPRE_SIZE 1
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_0 0x10004UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_0_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_1 0x10044UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_1_SIZE 239
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_2 0x10404UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_2_SIZE 255
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_3 0x10804UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_3_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_4 0x10844UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_4_SIZE 239
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_5 0x11004UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_5_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_6 0x11044UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_6_SIZE 239
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_7 0x11404UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_7_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_8 0x11444UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_8_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_9 0x11484UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_9_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_10 0x114c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_10_SIZE 207
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_11 0x11804UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_11_SIZE 255
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_12 0x11c04UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_12_SIZE 255
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_13 0x12004UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_13_SIZE 255
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_14 0x12800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_14_SIZE 5632
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_15 0x18004UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_15_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_16 0x18044UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_16_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_17 0x18084UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_17_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_18 0x180c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_18_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_19 0x18104UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_19_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_20 0x18144UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_20_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_21 0x18184UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_21_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_22 0x181c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_22_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_23 0x18204UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_23_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_24 0x18244UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_24_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_25 0x18284UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_25_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_26 0x182c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_26_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_27 0x18304UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_27_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_28 0x18344UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_28_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_29 0x18384UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_29_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_30 0x183c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_30_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_31 0x18404UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_31_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_32 0x18444UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_32_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_33 0x18484UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_33_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_34 0x184c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_34_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_35 0x18504UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_35_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_36 0x18544UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_36_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_37 0x18584UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_37_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_38 0x1860cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_38_SIZE 125
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_39 0x18804UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_39_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_40 0x18844UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_40_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_41 0x18884UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_41_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_42 0x188c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_42_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_43 0x18904UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_43_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_44 0x18944UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_44_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_45 0x18984UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_45_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_46 0x189c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_46_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_47 0x18a04UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_47_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_48 0x18a44UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_48_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_49 0x18a84UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_49_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_50 0x18ac4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_50_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_51 0x18b04UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_51_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_52 0x18b44UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_52_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_53 0x18b84UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_53_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_54 0x18bc4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_54_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_55 0x18c04UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_55_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_56 0x18c44UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_56_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_57 0x18c84UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_57_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_58 0x18cc8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_58_SIZE 14
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_59 0x18d04UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_59_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_60 0x18d44UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_60_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_61 0x18d84UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_61_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_62 0x18dc4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_62_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_63 0x18e04UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_63_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_64 0x18e44UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_64_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_65 0x18e88UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_65_SIZE 14
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_66 0x18ec4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_66_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_67 0x18f04UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_67_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_68 0x18f44UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_68_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_69 0x18f84UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_69_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_70 0x18ff0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_70_SIZE 4
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_71 0x19004UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_71_SIZE 15
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_72 0x19068UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_72_SIZE 6
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_73 0x190a8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SEM_FAST_REG_SEM_FAST_UNUSED_EMPTY_73_SIZE 7118
#define SRC_REG_KEYRSS0_0 0x40408UL //ACCESS:RW DataWidth:0x20 Register KeyRss0: 1 out of 10 Description: Key for parser RSS hash function - port 0.
#define SRC_REG_KEYRSS0_1 0x4040cUL //ACCESS:RW DataWidth:0x20 Register KeyRss0: 2 out of 10 Description: Key for parser RSS hash function - port 0.
#define SRC_REG_KEYRSS0_2 0x40410UL //ACCESS:RW DataWidth:0x20 Register KeyRss0: 3 out of 10 Description: Key for parser RSS hash function - port 0.
#define SRC_REG_KEYRSS0_3 0x40414UL //ACCESS:RW DataWidth:0x20 Register KeyRss0: 4 out of 10 Description: Key for parser RSS hash function - port 0.
#define SRC_REG_KEYRSS0_4 0x40418UL //ACCESS:RW DataWidth:0x20 Register KeyRss0: 5 out of 10 Description: Key for parser RSS hash function - port 0.
#define SRC_REG_KEYRSS0_5 0x4041cUL //ACCESS:RW DataWidth:0x20 Register KeyRss0: 6 out of 10 Description: Key for parser RSS hash function - port 0.
#define SRC_REG_KEYRSS0_6 0x40420UL //ACCESS:RW DataWidth:0x20 Register KeyRss0: 7 out of 10 Description: Key for parser RSS hash function - port 0.
#define SRC_REG_KEYRSS0_7 0x40424UL //ACCESS:RW DataWidth:0x20 Register KeyRss0: 8 out of 10 Description: Key for parser RSS hash function - port 0.
#define SRC_REG_KEYRSS0_8 0x40428UL //ACCESS:RW DataWidth:0x20 Register KeyRss0: 9 out of 10 Description: Key for parser RSS hash function - port 0.
#define SRC_REG_KEYRSS0_9 0x4042cUL //ACCESS:RW DataWidth:0x20 Register KeyRss0: 10 out of 10 Description: Key for parser RSS hash function - port 0.
#define SRC_REG_KEYRSS1_0 0x40430UL //ACCESS:RW DataWidth:0x20 Register KeyRss1: 1 out of 10 Description: Key for parser RSS hash function - port 1.
#define SRC_REG_KEYRSS1_1 0x40434UL //ACCESS:RW DataWidth:0x20 Register KeyRss1: 2 out of 10 Description: Key for parser RSS hash function - port 1.
#define SRC_REG_KEYRSS1_2 0x40438UL //ACCESS:RW DataWidth:0x20 Register KeyRss1: 3 out of 10 Description: Key for parser RSS hash function - port 1.
#define SRC_REG_KEYRSS1_3 0x4043cUL //ACCESS:RW DataWidth:0x20 Register KeyRss1: 4 out of 10 Description: Key for parser RSS hash function - port 1.
#define SRC_REG_KEYRSS1_4 0x40440UL //ACCESS:RW DataWidth:0x20 Register KeyRss1: 5 out of 10 Description: Key for parser RSS hash function - port 1.
#define SRC_REG_KEYRSS1_5 0x40444UL //ACCESS:RW DataWidth:0x20 Register KeyRss1: 6 out of 10 Description: Key for parser RSS hash function - port 1.
#define SRC_REG_KEYRSS1_6 0x40448UL //ACCESS:RW DataWidth:0x20 Register KeyRss1: 7 out of 10 Description: Key for parser RSS hash function - port 1.
#define SRC_REG_KEYRSS1_7 0x4044cUL //ACCESS:RW DataWidth:0x20 Register KeyRss1: 8 out of 10 Description: Key for parser RSS hash function - port 1.
#define SRC_REG_KEYRSS1_8 0x40450UL //ACCESS:RW DataWidth:0x20 Register KeyRss1: 9 out of 10 Description: Key for parser RSS hash function - port 1.
#define SRC_REG_KEYRSS1_9 0x40454UL //ACCESS:RW DataWidth:0x20 Register KeyRss1: 10 out of 10 Description: Key for parser RSS hash function - port 1.
#define SRC_REG_KEYSEARCH_0 0x40458UL //ACCESS:RW DataWidth:0x20 Register KeySearch: 1 out of 10 Description: Key for searcher hash function - port 1.
#define SRC_REG_KEYSEARCH_1 0x4045cUL //ACCESS:RW DataWidth:0x20 Register KeySearch: 2 out of 10 Description: Key for searcher hash function - port 1.
#define SRC_REG_KEYSEARCH_2 0x40460UL //ACCESS:RW DataWidth:0x20 Register KeySearch: 3 out of 10 Description: Key for searcher hash function - port 1.
#define SRC_REG_KEYSEARCH_3 0x40464UL //ACCESS:RW DataWidth:0x20 Register KeySearch: 4 out of 10 Description: Key for searcher hash function - port 1.
#define SRC_REG_KEYSEARCH_4 0x40468UL //ACCESS:RW DataWidth:0x20 Register KeySearch: 5 out of 10 Description: Key for searcher hash function - port 1.
#define SRC_REG_KEYSEARCH_5 0x4046cUL //ACCESS:RW DataWidth:0x20 Register KeySearch: 6 out of 10 Description: Key for searcher hash function - port 1.
#define SRC_REG_KEYSEARCH_6 0x40470UL //ACCESS:RW DataWidth:0x20 Register KeySearch: 7 out of 10 Description: Key for searcher hash function - port 1.
#define SRC_REG_KEYSEARCH_7 0x40474UL //ACCESS:RW DataWidth:0x20 Register KeySearch: 8 out of 10 Description: Key for searcher hash function - port 1.
#define SRC_REG_KEYSEARCH_8 0x40478UL //ACCESS:RW DataWidth:0x20 Register KeySearch: 9 out of 10 Description: Key for searcher hash function - port 1.
#define SRC_REG_KEYSEARCH_9 0x4047cUL //ACCESS:RW DataWidth:0x20 Register KeySearch: 10 out of 10 Description: Key for searcher hash function - port 1.
#define SRC_REG_NUM_CONCURRENT_TASKS 0x40480UL //ACCESS:RW DataWidth:0x3 Description: NOT IMPLEMENTED (Number of concurrent tasks; Values can be 1-4.)
#define SRC_REG_ALLOWSHORTCUT 0x40494UL //ACCESS:RW DataWidth:0x1 Description: If set; same search shortcut is allowed.
#define SRC_REG_MAXNUMHOPS 0x40498UL //ACCESS:RW DataWidth:0x6 Description: The maximum allowed HOP to search.
#define SRC_REG_SOFT_RST 0x4049cUL //ACCESS:RW DataWidth:0x1 Description: Reset internal state machines.
#define SRC_REG_DBG_SELECT 0x404a0UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from SRC to the DBG block) - for selecting a line to output to the DBG block.
#define SRC_REG_DBG_BYTE_ENABLE 0x404a4UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from SRC to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define SRC_REG_DBG_SHIFT 0x404a8UL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from SRC to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define SRC_REG_SRC_INT_STS 0x404acUL //ACCESS:R DataWidth:0x3 Description: Interrupt register #0 read
#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define SRC_SRC_INT_STS_REG_MMURQ_FIFO_ERR (0x1<<1)
#define SRC_SRC_INT_STS_REG_MMURQ_FIFO_ERR_SIZE 1
#define SRC_SRC_INT_STS_REG_WR_FIFO_ERR (0x1<<2)
#define SRC_SRC_INT_STS_REG_WR_FIFO_ERR_SIZE 2
#define SRC_REG_SRC_INT_STS_CLR 0x404b0UL //ACCESS:RC DataWidth:0x3 Description: Interrupt register #0 read clear
#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define SRC_SRC_INT_STS_CLR_REG_MMURQ_FIFO_ERR (0x1<<1)
#define SRC_SRC_INT_STS_CLR_REG_MMURQ_FIFO_ERR_SIZE 1
#define SRC_SRC_INT_STS_CLR_REG_WR_FIFO_ERR (0x1<<2)
#define SRC_SRC_INT_STS_CLR_REG_WR_FIFO_ERR_SIZE 2
#define SRC_REG_SRC_INT_STS_WR 0x404b4UL //ACCESS:WR DataWidth:0x3 Description: Interrupt register #0 bit set or clear
#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define SRC_SRC_INT_STS_WR_REG_MMURQ_FIFO_ERR (0x1<<1)
#define SRC_SRC_INT_STS_WR_REG_MMURQ_FIFO_ERR_SIZE 1
#define SRC_SRC_INT_STS_WR_REG_WR_FIFO_ERR (0x1<<2)
#define SRC_SRC_INT_STS_WR_REG_WR_FIFO_ERR_SIZE 2
#define SRC_REG_SRC_INT_MASK 0x404b8UL //ACCESS:RW DataWidth:0x3 Description: Interrupt mask register #0 read/write
#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define SRC_SRC_INT_MASK_REG_MMURQ_FIFO_ERR (0x1<<1)
#define SRC_SRC_INT_MASK_REG_MMURQ_FIFO_ERR_SIZE 1
#define SRC_SRC_INT_MASK_REG_WR_FIFO_ERR (0x1<<2)
#define SRC_SRC_INT_MASK_REG_WR_FIFO_ERR_SIZE 2
#define SRC_REG_SRC_PRTY_STS 0x404bcUL //ACCESS:R DataWidth:0x3 Description: Parity register #0 read
#define SRC_SRC_PRTY_STS_REG_PARITY (0x1<<0)
#define SRC_SRC_PRTY_STS_REG_PARITY_SIZE 0
#define SRC_SRC_PRTY_STS_REG_MEM_RQ (0x1<<1)
#define SRC_SRC_PRTY_STS_REG_MEM_RQ_SIZE 1
#define SRC_SRC_PRTY_STS_REG_WDATA (0x1<<2)
#define SRC_SRC_PRTY_STS_REG_WDATA_SIZE 2
#define SRC_REG_SRC_PRTY_STS_CLR 0x404c0UL //ACCESS:RC DataWidth:0x3 Description: Parity register #0 read clear
#define SRC_SRC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define SRC_SRC_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define SRC_SRC_PRTY_STS_CLR_REG_MEM_RQ (0x1<<1)
#define SRC_SRC_PRTY_STS_CLR_REG_MEM_RQ_SIZE 1
#define SRC_SRC_PRTY_STS_CLR_REG_WDATA (0x1<<2)
#define SRC_SRC_PRTY_STS_CLR_REG_WDATA_SIZE 2
#define SRC_REG_SRC_PRTY_STS_WR 0x404c4UL //ACCESS:WR DataWidth:0x3 Description: Parity register #0 bit set or clear
#define SRC_SRC_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define SRC_SRC_PRTY_STS_WR_REG_PARITY_SIZE 0
#define SRC_SRC_PRTY_STS_WR_REG_MEM_RQ (0x1<<1)
#define SRC_SRC_PRTY_STS_WR_REG_MEM_RQ_SIZE 1
#define SRC_SRC_PRTY_STS_WR_REG_WDATA (0x1<<2)
#define SRC_SRC_PRTY_STS_WR_REG_WDATA_SIZE 2
#define SRC_REG_SRC_PRTY_MASK 0x404c8UL //ACCESS:RW DataWidth:0x3 Description: Parity mask register #0 read/write
#define SRC_SRC_PRTY_MASK_REG_PARITY (0x1<<0)
#define SRC_SRC_PRTY_MASK_REG_PARITY_SIZE 0
#define SRC_SRC_PRTY_MASK_REG_MEM_RQ (0x1<<1)
#define SRC_SRC_PRTY_MASK_REG_MEM_RQ_SIZE 1
#define SRC_SRC_PRTY_MASK_REG_WDATA (0x1<<2)
#define SRC_SRC_PRTY_MASK_REG_WDATA_SIZE 2
#define SRC_REG_E1HMF_ENABLE 0x404ccUL //ACCESS:RW DataWidth:0x1 Description: If clr the searcher is compatible to E1 A0 - support only two ports. If set the searcher support 8 functions.
#define SRC_REG_KEYRSS0_EXT5 0x404d0UL //ACCESS:RW DataWidth:0x8 Description: Key for parser RSS 5 tuple extantion hash - port 0.
#define SRC_REG_KEYRSS1_EXT5 0x404d4UL //ACCESS:RW DataWidth:0x8 Description: Key for parser RSS 5 tuple extantion hash - port 1.
#define SRC_REG_TM_RAM_36X66 0x40550UL //ACCESS:RW DataWidth:0x2 Description: tm bits for ram_36x66
#define SRC_REG_ECO_RESERVED 0x40554UL //ACCESS:RW DataWidth:0x8 Description: eco reserved
#define SRC_REG_ATCTBL1 0x40558UL //ACCESS:RW DataWidth:0x3 Description: Controls PXP Request ATC field when accessing Table 1 (logical addressing)
#define SRC_REG_ATCTBL2 0x4055cUL //ACCESS:RW DataWidth:0x3 Description: Controls PXP Request ATC field when accessing Table 2 (Physical addressing)
#define SRC_REG_KEYSEARCH_VLAN 0x40560UL //ACCESS:RW DataWidth:0xc Description: Key for searcher hash function vlan field
#define SRC_REG_VLAN_HASH_ENABLE 0x40564UL //ACCESS:RW DataWidth:0x1 Description: Enable for VLAN in Hash Address
#define SRC_REG_ALLOWEMPTYSHORTCUT 0x40610UL //ACCESS:RW DataWidth:0x1 Description: If set; search return no match on empty shortcut is allowed.
#define SRC_REG_VLAN_MATCH_DISABLE 0x40614UL //ACCESS:RW DataWidth:0x1 Description: Disable VLAN and VLAN Promiscuous Mode (vpf) matching logic
#define SRC_REG_NUMBER_HASH_BITS0 0x40400UL //ACCESS:RW DataWidth:0x5 SPLIT:4 Description: The number of hash bits used for the search (h); Values can be 8 to 24.
#define SRC_REG_NUMBER_HASH_BITS0_SIZE 1
#define SRC_REG_NUMBER_HASH_BITS1 0x40404UL //ACCESS:RW DataWidth:0x5 SPLIT:4 Description: The number of hash bits used for the search (h); Values can be 8 to 24.
#define SRC_REG_NUMBER_HASH_BITS1_SIZE 1
#define SRC_REG_NUMIPV4CONN0 0x40484UL //ACCESS:RW DataWidth:0x1a SPLIT:4 Description: Number of Ipv4 connections - port 0 (statistics).
#define SRC_REG_NUMIPV4CONN0_SIZE 1
#define SRC_REG_NUMIPV4CONN1 0x40488UL //ACCESS:RW DataWidth:0x1a SPLIT:4 Description: Number of Ipv4 connections (statistics) - port 1.
#define SRC_REG_NUMIPV4CONN1_SIZE 1
#define SRC_REG_NUMIPV6CONN0 0x4048cUL //ACCESS:RW DataWidth:0x1a SPLIT:4 Description: Number of Ipv6 connections (statistics) - port 0.
#define SRC_REG_NUMIPV6CONN0_SIZE 1
#define SRC_REG_NUMIPV6CONN1 0x40490UL //ACCESS:RW DataWidth:0x1a SPLIT:4 Description: Number of Ipv6 connections (statistics) - port 1.
#define SRC_REG_NUMIPV6CONN1_SIZE 1
#define SRC_REG_EMPTY_PF 0x404e0UL //ACCESS:RW DataWidth:0x20 SPLIT:8 Description: empty bit per bin 256 bins per PF
#define SRC_REG_EMPTY_PF_SIZE 8
#define SRC_REG_COUNTFREE0 0x40500UL //ACCESS:RW DataWidth:0x16 SPLIT:4 Description: Number of free element in the free list of T2 entries - port 0.
#define SRC_REG_COUNTFREE0_SIZE 1
#define SRC_REG_COUNTFREE1 0x40504UL //ACCESS:RW DataWidth:0x16 SPLIT:4 Description: Number of free element in the free list of T2 entries - port 1.
#define SRC_REG_COUNTFREE1_SIZE 1
#define SRC_REG_FIRSTFREE0 0x40510UL //ACCESS:WB DataWidth:0x40 SPLIT:4 Description: First free element in the free list of T2 entries - port 0.
#define SRC_REG_FIRSTFREE0_SIZE 2
#define SRC_REG_FIRSTFREE1 0x40520UL //ACCESS:WB DataWidth:0x40 SPLIT:4 Description: First free element in the free list of T2 entries - port 1.
#define SRC_REG_FIRSTFREE1_SIZE 2
#define SRC_REG_LASTFREE0 0x40530UL //ACCESS:WB DataWidth:0x40 SPLIT:4 Description: Last free element in the free list of T2 entries - port 0.
#define SRC_REG_LASTFREE0_SIZE 2
#define SRC_REG_LASTFREE1 0x40540UL //ACCESS:WB DataWidth:0x40 SPLIT:4 Description: Last free element in the free list of T2 entries - port 1.
#define SRC_REG_LASTFREE1_SIZE 2
#define SRC_REG_DBG_OUT_DATA_LSB 0x40568UL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from SRC to the DBG block) - The 32 lsb data that goes to the DBG block.
#define SRC_REG_DBG_OUT_DATA_LSB_SIZE 1
#define SRC_REG_DBG_OUT_DATA_MSB 0x4056cUL //ACCESS:R DataWidth:0x20 Description: Debug only: For dbgmux usage (debug data that goes from SRC to the DBG block) - The 32 msb data that goes to the DBG block.
#define SRC_REG_DBG_OUT_DATA_MSB_SIZE 1
#define SRC_REG_DBG_OUT_FRAME 0x40570UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from SRC to the DBG block) - The 4 frame bits that goes to the DBG block. Bit0 is the frame of data byte0; Bit1 is the frame of data byte1; Bit2 is the frame of data byte2; Bit3 is the frame of data byte4
#define SRC_REG_DBG_OUT_FRAME_SIZE 1
#define SRC_REG_DBG_OUT_VALID 0x40574UL //ACCESS:R DataWidth:0x4 Description: Debug only: For dbgmux usage (debug data that goes from SRC to the DBG block) - The 4 valid bits that goes to the DBG block. Bit0 validtes data byte0; Bit1 validates data byte1; Bit2 validates data byte2; Bit3 validates data byte4
#define SRC_REG_DBG_OUT_VALID_SIZE 1
#define SRC_REG_SRC_UNUSED_EMPTY_0 0x404d8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SRC_REG_SRC_UNUSED_EMPTY_0_SIZE 2
#define SRC_REG_SRC_UNUSED_EMPTY_1 0x40508UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SRC_REG_SRC_UNUSED_EMPTY_1_SIZE 2
#define SRC_REG_SRC_UNUSED_EMPTY_2 0x40578UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SRC_REG_SRC_UNUSED_EMPTY_2_SIZE 38
#define SRC_REG_SRC_UNUSED_EMPTY_3 0x40618UL //ACCESS:R DataWidth:0x20 Unused empty space
#define SRC_REG_SRC_UNUSED_EMPTY_3_SIZE 122
#define TCM_REG_INIT 0x50000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
#define TCM_REG_TCM_STORM0_IFEN 0x50004UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_TCM_STORM1_IFEN 0x50008UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_TCM_TQM_IFEN 0x5000cUL //ACCESS:RW DataWidth:0x1 Description: CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_STORM_TCM_IFEN 0x50010UL //ACCESS:RW DataWidth:0x1 Description: STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_TQM_TCM_IFEN 0x50014UL //ACCESS:RW DataWidth:0x1 Description: QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_TSDM_IFEN 0x50018UL //ACCESS:RW DataWidth:0x1 Description: Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_TM_TCM_IFEN 0x5001cUL //ACCESS:RW DataWidth:0x1 Description: Timers - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_PRS_IFEN 0x50020UL //ACCESS:RW DataWidth:0x1 Description: Input prs Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_PBF_IFEN 0x50024UL //ACCESS:RW DataWidth:0x1 Description: Input pbf Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_USEM_IFEN 0x50028UL //ACCESS:RW DataWidth:0x1 Description: Input usem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_CSEM_IFEN 0x5002cUL //ACCESS:RW DataWidth:0x1 Description: Input csem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_CDU_AG_WR_IFEN 0x50030UL //ACCESS:RW DataWidth:0x1 Description: CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_CDU_AG_RD_IFEN 0x50034UL //ACCESS:RW DataWidth:0x1 Description: CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_CDU_SM_WR_IFEN 0x50038UL //ACCESS:RW DataWidth:0x1 Description: CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_CDU_SM_RD_IFEN 0x5003cUL //ACCESS:RW DataWidth:0x1 Description: CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_TCM_CFC_IFEN 0x50040UL //ACCESS:RW DataWidth:0x1 Description: CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define TCM_REG_XX_MAX_LL_SZ 0x50044UL //ACCESS:RW DataWidth:0x6 Description: Maximum link list size (messages locked) per connection in the XX protection.
#define TCM_REG_XX_OVFL_EVNT_ID 0x50048UL //ACCESS:RW DataWidth:0x8 Description: The Event ID; sent to the STORM in case of XX overflow.
#define TCM_REG_XX_MAX_NUM 0x5004cUL //ACCESS:RW DataWidth:0x4 Description: The maximum number of connections in the XX protection.
#define TCM_REG_N_SM_CTX_LD_0 0x50050UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_1 0x50054UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_2 0x50058UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_3 0x5005cUL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_4 0x50060UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_5 0x50064UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_6 0x50068UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_7 0x5006cUL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_8 0x50070UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_9 0x50074UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_10 0x50078UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_11 0x5007cUL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_12 0x50080UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_13 0x50084UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_14 0x50088UL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_N_SM_CTX_LD_15 0x5008cUL //ACCESS:RW DataWidth:0x4 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define TCM_REG_TQM_TCM_HDR_P 0x50090UL //ACCESS:RW DataWidth:0x1c Description: The CM header value for QM request (primary).
#define TCM_REG_TQM_TCM_HDR_S 0x50094UL //ACCESS:RW DataWidth:0x1c Description: The CM header value for QM request (secondary).
#define TCM_REG_TM_TCM_HDR 0x50098UL //ACCESS:RW DataWidth:0x1c Description: The CM header for Timers expiration command.
#define TCM_REG_ERR_TCM_HDR 0x5009cUL //ACCESS:RW DataWidth:0x1c Description: The CM erroneous header for QM and Timers formatting.
#define TCM_REG_ERR_EVNT_ID 0x500a0UL //ACCESS:RW DataWidth:0x8 Description: The Event ID in case of ErrorFlg is set in the input message.
#define TCM_REG_EXPR_EVNT_ID 0x500a4UL //ACCESS:RW DataWidth:0x8 Description: The Event ID for Timers expiration.
#define TCM_REG_STOP_EVNT_ID 0x500a8UL //ACCESS:RW DataWidth:0x8 Description: The Event ID for Timers formatting in case of stop done.
#define TCM_REG_STORM_WEIGHT 0x500acUL //ACCESS:RW DataWidth:0x3 Description: The weight of the STORM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define TCM_REG_PRS_WEIGHT 0x500b0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input prs in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define TCM_REG_PBF_WEIGHT 0x500b4UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input pbf in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define TCM_REG_USEM_WEIGHT 0x500b8UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input usem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define TCM_REG_CSEM_WEIGHT 0x500bcUL //ACCESS:RW DataWidth:0x3 Description: The weight of the input csem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define TCM_REG_CP_WEIGHT 0x500c0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the CP input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define TCM_REG_TSDM_WEIGHT 0x500c4UL //ACCESS:RW DataWidth:0x3 Description: The weight of the SDM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define TCM_REG_TQM_P_WEIGHT 0x500c8UL //ACCESS:RW DataWidth:0x3 Description: The weight of the QM (primary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define TCM_REG_TQM_S_WEIGHT 0x500ccUL //ACCESS:RW DataWidth:0x3 Description: The weight of the QM (secondary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define TCM_REG_TM_WEIGHT 0x500d0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the Timers input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define TCM_REG_TCM_TQM_USE_Q 0x500d4UL //ACCESS:RW DataWidth:0x1 Description: If set the Q index; received from the QM is inserted to event ID.
#define TCM_REG_TCM_REG0_SZ 0x500d8UL //ACCESS:RW DataWidth:0x3 Description: The size of AG context region 0 in REG-pairs. Designates the MS REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). Is used to determine the number of the AG context REG-pairs written back; when the input message Reg1WbFlg isn't set.
#define TCM_REG_STOP_DONE_HDR 0x500dcUL //ACCESS:RW DataWidth:0x1c Description: The CM header for Timers expiration command; when Stop Done input bit is set.
#define TCM_REG_PM_RAM_TM 0x50100UL //ACCESS:RW DataWidth:0x5 Description: TM bits of pending message RAM.
#define TCM_REG_SM_CTX0_TM 0x50104UL //ACCESS:RW DataWidth:0x5 Description: TM bits of STORM context. LSB.
#define TCM_REG_AG_CTX0_TM 0x50108UL //ACCESS:RW DataWidth:0x5 Description: TM bits of AG context.
#define TCM_REG_AG_CTX1_TM 0x5010cUL //ACCESS:RW DataWidth:0x5 Description: TM bits of AG context.
#define TCM_REG_AG_CTX2_TM 0x50110UL //ACCESS:RW DataWidth:0x5 Description: TM bits of AG context.
#define TCM_REG_GR_ARB_TYPE 0x50114UL //ACCESS:RW DataWidth:0x1 Description: Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr; ~tcm_registers_gr_ld0_pr.gr_ld0_pr and ~tcm_registers_gr_ld1_pr.gr_ld1_pr.
#define TCM_REG_GR_AG_PR 0x50118UL //ACCESS:RW DataWidth:0x2 Description: AG channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel is the compliment of the other 3 groups.
#define TCM_REG_GR_LD0_PR 0x5011cUL //ACCESS:RW DataWidth:0x2 Description: Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel is the compliment of the other 3 groups.
#define TCM_REG_GR_LD1_PR 0x50120UL //ACCESS:RW DataWidth:0x2 Description: Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel is the compliment of the other 3 groups.
#define TCM_REG_WND_UPD_CNT_FLG_Q 0x50124UL //ACCESS:RW DataWidth:0x2 Description: Queue index for WndUpdCntFlg.
#define TCM_REG_TIMEOUT_CNT_FLG_Q 0x50128UL //ACCESS:RW DataWidth:0x2 Description: Queue index for TimeoutCntFlg.
#define TCM_REG_RXMIT_DEC_Q 0x5012cUL //ACCESS:RW DataWidth:0x2 Description: Queue index for RxmitSeqDec and SndNxtDec (Rxmit decision rules).
#define TCM_REG_AUX1_CNT_FLG_Q 0x50130UL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX2_CNT_FLG_Q 0x50134UL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX3_CNT_FLG_Q 0x50138UL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX4_CNT_FLG_Q 0x5013cUL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX5_CNT_FLG_Q 0x50140UL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX6_CNT_FLG_Q 0x50144UL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX7_CNT_FLG_Q 0x50148UL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX8_CNT_FLG_Q 0x5014cUL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX9_CNT_FLG_Q 0x50150UL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX10_CNT_FLG_Q 0x50154UL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX11_CNT_FLG_Q 0x50158UL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_AUX12_CNT_FLG_Q 0x5015cUL //ACCESS:RW DataWidth:0x2 Description: The queue index to register to per each counter flag.
#define TCM_REG_STORM_LENGTH_MIS 0x50160UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the STORM interface.
#define TCM_REG_TSDM_LENGTH_MIS 0x50164UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the SDM interface.
#define TCM_REG_PRS_LENGTH_MIS 0x50168UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the In#6 interface.
#define TCM_REG_PBF_LENGTH_MIS 0x5016cUL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the In#7 interface.
#define TCM_REG_USEM_LENGTH_MIS 0x50170UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the In#8 interface.
#define TCM_REG_CSEM_LENGTH_MIS 0x50174UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the In#9 interface.
#define TCM_REG_XX_FREE 0x50178UL //ACCESS:R DataWidth:0x6 Description: Use to read the value of XX protection Free counter.
#define TCM_REG_CAM_OCCUP 0x5017cUL //ACCESS:R DataWidth:0x4 Description: Used to read the value of the XX protection CAM occupancy counter.
#define TCM_REG_UNLOCK_MISS 0x50180UL //ACCESS:RC DataWidth:0x1 Description: Set when an error; indicating the LCID to be unlocked doesn't exist in LCID CAM; happens. Is reset on read.
#define TCM_REG_TQM_GLB_USE_CNTR 0x50184UL //ACCESS:R DataWidth:0x1a Description: Used to read the QM global usage counter - the counter of the balance between QM requests sent and received by the TCM.
#define TCM_REG_CP_BUF_EMPTY 0x50188UL //ACCESS:R DataWidth:0x1 Description: CP buffer is empty status.
#define TCM_REG_CP_BUF_STATUS 0x5018cUL //ACCESS:R DataWidth:0x5 Description: CP buffer status.
#define TCM_REG_XX_OVFL_CNTR 0x50190UL //ACCESS:ST DataWidth:0x10 Description: Counter of XX 0verflow occurencies.
#define TCM_REG_STORM_MSG_CNTR 0x50194UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the STORM input.
#define TCM_REG_TSDM_MSG_CNTR 0x50198UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input SDM.
#define TCM_REG_PRS_MSG_CNTR 0x5019cUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input prs.
#define TCM_REG_PBF_MSG_CNTR 0x501a0UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input pbf.
#define TCM_REG_USEM_MSG_CNTR 0x501a4UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input usem.
#define TCM_REG_CSEM_MSG_CNTR 0x501a8UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input csem.
#define TCM_REG_CP_MSG_CNTR 0x501acUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the CP input.
#define TCM_REG_TQM_P_MSG_CNTR 0x501b0UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the QM input (primary).
#define TCM_REG_TQM_S_MSG_CNTR 0x501b4UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the QM input (secondary).
#define TCM_REG_TM_MSG_CNTR 0x501b8UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the Timers input.
#define TCM_REG_STORM_OUT_CNTR 0x501bcUL //ACCESS:ST DataWidth:0x18 Description: Counter of the output messages at FIC0 and FIC1 interfaces.
#define TCM_REG_TQM_OUT_CNTR 0x501c0UL //ACCESS:ST DataWidth:0x18 Description: Counter of the output QM commands.
#define TCM_REG_DBG_SELECT 0x501c4UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from TCM to the DBG block) - for selecting a line to output to the DBG block.
#define TCM_REG_DBG_BYTE_ENABLE 0x501c8UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from TCM to the DBG block) - for enabling bytes in the selected line (after the select; before the shift).
#define TCM_REG_DBG_SHIFT 0x501ccUL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from TCM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define TCM_REG_TCM_INT_STS 0x501d0UL //ACCESS:R DataWidth:0xb Description: Interrupt register #0 read
#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define TCM_TCM_INT_STS_REG_XX_UQ_ERR (0x1<<1)
#define TCM_TCM_INT_STS_REG_XX_UQ_ERR_SIZE 1
#define TCM_TCM_INT_STS_REG_STORM_ERR (0x1<<2)
#define TCM_TCM_INT_STS_REG_STORM_ERR_SIZE 2
#define TCM_TCM_INT_STS_REG_TSDM_ERR (0x1<<3)
#define TCM_TCM_INT_STS_REG_TSDM_ERR_SIZE 3
#define TCM_TCM_INT_STS_REG_PRS_ERR (0x1<<4)
#define TCM_TCM_INT_STS_REG_PRS_ERR_SIZE 4
#define TCM_TCM_INT_STS_REG_PBF_ERR (0x1<<5)
#define TCM_TCM_INT_STS_REG_PBF_ERR_SIZE 5
#define TCM_TCM_INT_STS_REG_USEM_ERR (0x1<<6)
#define TCM_TCM_INT_STS_REG_USEM_ERR_SIZE 6
#define TCM_TCM_INT_STS_REG_CSEM_ERR (0x1<<7)
#define TCM_TCM_INT_STS_REG_CSEM_ERR_SIZE 7
#define TCM_TCM_INT_STS_REG_CP0_ERR (0x1<<8)
#define TCM_TCM_INT_STS_REG_CP0_ERR_SIZE 8
#define TCM_TCM_INT_STS_REG_CP1_ERR (0x1<<9)
#define TCM_TCM_INT_STS_REG_CP1_ERR_SIZE 9
#define TCM_TCM_INT_STS_REG_UM_ERR (0x1<<10)
#define TCM_TCM_INT_STS_REG_UM_ERR_SIZE 10
#define TCM_REG_TCM_INT_STS_CLR 0x501d4UL //ACCESS:RC DataWidth:0xb Description: Interrupt register #0 read clear
#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define TCM_TCM_INT_STS_CLR_REG_XX_UQ_ERR (0x1<<1)
#define TCM_TCM_INT_STS_CLR_REG_XX_UQ_ERR_SIZE 1
#define TCM_TCM_INT_STS_CLR_REG_STORM_ERR (0x1<<2)
#define TCM_TCM_INT_STS_CLR_REG_STORM_ERR_SIZE 2
#define TCM_TCM_INT_STS_CLR_REG_TSDM_ERR (0x1<<3)
#define TCM_TCM_INT_STS_CLR_REG_TSDM_ERR_SIZE 3
#define TCM_TCM_INT_STS_CLR_REG_PRS_ERR (0x1<<4)
#define TCM_TCM_INT_STS_CLR_REG_PRS_ERR_SIZE 4
#define TCM_TCM_INT_STS_CLR_REG_PBF_ERR (0x1<<5)
#define TCM_TCM_INT_STS_CLR_REG_PBF_ERR_SIZE 5
#define TCM_TCM_INT_STS_CLR_REG_USEM_ERR (0x1<<6)
#define TCM_TCM_INT_STS_CLR_REG_USEM_ERR_SIZE 6
#define TCM_TCM_INT_STS_CLR_REG_CSEM_ERR (0x1<<7)
#define TCM_TCM_INT_STS_CLR_REG_CSEM_ERR_SIZE 7
#define TCM_TCM_INT_STS_CLR_REG_CP0_ERR (0x1<<8)
#define TCM_TCM_INT_STS_CLR_REG_CP0_ERR_SIZE 8
#define TCM_TCM_INT_STS_CLR_REG_CP1_ERR (0x1<<9)
#define TCM_TCM_INT_STS_CLR_REG_CP1_ERR_SIZE 9
#define TCM_TCM_INT_STS_CLR_REG_UM_ERR (0x1<<10)
#define TCM_TCM_INT_STS_CLR_REG_UM_ERR_SIZE 10
#define TCM_REG_TCM_INT_STS_WR 0x501d8UL //ACCESS:WR DataWidth:0xb Description: Interrupt register #0 bit set or clear
#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define TCM_TCM_INT_STS_WR_REG_XX_UQ_ERR (0x1<<1)
#define TCM_TCM_INT_STS_WR_REG_XX_UQ_ERR_SIZE 1
#define TCM_TCM_INT_STS_WR_REG_STORM_ERR (0x1<<2)
#define TCM_TCM_INT_STS_WR_REG_STORM_ERR_SIZE 2
#define TCM_TCM_INT_STS_WR_REG_TSDM_ERR (0x1<<3)
#define TCM_TCM_INT_STS_WR_REG_TSDM_ERR_SIZE 3
#define TCM_TCM_INT_STS_WR_REG_PRS_ERR (0x1<<4)
#define TCM_TCM_INT_STS_WR_REG_PRS_ERR_SIZE 4
#define TCM_TCM_INT_STS_WR_REG_PBF_ERR (0x1<<5)
#define TCM_TCM_INT_STS_WR_REG_PBF_ERR_SIZE 5
#define TCM_TCM_INT_STS_WR_REG_USEM_ERR (0x1<<6)
#define TCM_TCM_INT_STS_WR_REG_USEM_ERR_SIZE 6
#define TCM_TCM_INT_STS_WR_REG_CSEM_ERR (0x1<<7)
#define TCM_TCM_INT_STS_WR_REG_CSEM_ERR_SIZE 7
#define TCM_TCM_INT_STS_WR_REG_CP0_ERR (0x1<<8)
#define TCM_TCM_INT_STS_WR_REG_CP0_ERR_SIZE 8
#define TCM_TCM_INT_STS_WR_REG_CP1_ERR (0x1<<9)
#define TCM_TCM_INT_STS_WR_REG_CP1_ERR_SIZE 9
#define TCM_TCM_INT_STS_WR_REG_UM_ERR (0x1<<10)
#define TCM_TCM_INT_STS_WR_REG_UM_ERR_SIZE 10
#define TCM_REG_TCM_INT_MASK 0x501dcUL //ACCESS:RW DataWidth:0xb Description: Interrupt mask register #0 read/write
#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define TCM_TCM_INT_MASK_REG_XX_UQ_ERR (0x1<<1)
#define TCM_TCM_INT_MASK_REG_XX_UQ_ERR_SIZE 1
#define TCM_TCM_INT_MASK_REG_STORM_ERR (0x1<<2)
#define TCM_TCM_INT_MASK_REG_STORM_ERR_SIZE 2
#define TCM_TCM_INT_MASK_REG_TSDM_ERR (0x1<<3)
#define TCM_TCM_INT_MASK_REG_TSDM_ERR_SIZE 3
#define TCM_TCM_INT_MASK_REG_PRS_ERR (0x1<<4)
#define TCM_TCM_INT_MASK_REG_PRS_ERR_SIZE 4
#define TCM_TCM_INT_MASK_REG_PBF_ERR (0x1<<5)
#define TCM_TCM_INT_MASK_REG_PBF_ERR_SIZE 5
#define TCM_TCM_INT_MASK_REG_USEM_ERR (0x1<<6)
#define TCM_TCM_INT_MASK_REG_USEM_ERR_SIZE 6
#define TCM_TCM_INT_MASK_REG_CSEM_ERR (0x1<<7)
#define TCM_TCM_INT_MASK_REG_CSEM_ERR_SIZE 7
#define TCM_TCM_INT_MASK_REG_CP0_ERR (0x1<<8)
#define TCM_TCM_INT_MASK_REG_CP0_ERR_SIZE 8
#define TCM_TCM_INT_MASK_REG_CP1_ERR (0x1<<9)
#define TCM_TCM_INT_MASK_REG_CP1_ERR_SIZE 9
#define TCM_TCM_INT_MASK_REG_UM_ERR (0x1<<10)
#define TCM_TCM_INT_MASK_REG_UM_ERR_SIZE 10
#define TCM_REG_TCM_PRTY_STS 0x501e0UL //ACCESS:R DataWidth:0x1b Description: Parity register #0 read
#define TCM_TCM_PRTY_STS_REG_PARITY (0x1<<0)
#define TCM_TCM_PRTY_STS_REG_PARITY_SIZE 0
#define TCM_TCM_PRTY_STS_REG_XT_PRTY (0x1<<1)
#define TCM_TCM_PRTY_STS_REG_XT_PRTY_SIZE 1
#define TCM_TCM_PRTY_STS_REG_DT_PRTY (0x1<<2)
#define TCM_TCM_PRTY_STS_REG_DT_PRTY_SIZE 2
#define TCM_TCM_PRTY_STS_REG_PM_PRTY0 (0x1<<3)
#define TCM_TCM_PRTY_STS_REG_PM_PRTY0_SIZE 3
#define TCM_TCM_PRTY_STS_REG_PM_PRTY1 (0x1<<4)
#define TCM_TCM_PRTY_STS_REG_PM_PRTY1_SIZE 4
#define TCM_TCM_PRTY_STS_REG_UQ_PRTY (0x1<<5)
#define TCM_TCM_PRTY_STS_REG_UQ_PRTY_SIZE 5
#define TCM_TCM_PRTY_STS_REG_AG_PRTY0 (0x1<<6)
#define TCM_TCM_PRTY_STS_REG_AG_PRTY0_SIZE 6
#define TCM_TCM_PRTY_STS_REG_AG_PRTY1 (0x1<<7)
#define TCM_TCM_PRTY_STS_REG_AG_PRTY1_SIZE 7
#define TCM_TCM_PRTY_STS_REG_AG_PRTY2 (0x1<<8)
#define TCM_TCM_PRTY_STS_REG_AG_PRTY2_SIZE 8
#define TCM_TCM_PRTY_STS_REG_AG_PRTY3 (0x1<<9)
#define TCM_TCM_PRTY_STS_REG_AG_PRTY3_SIZE 9
#define TCM_TCM_PRTY_STS_REG_AG_PRTY4 (0x1<<10)
#define TCM_TCM_PRTY_STS_REG_AG_PRTY4_SIZE 10
#define TCM_TCM_PRTY_STS_REG_AG_PRTY5 (0x1<<11)
#define TCM_TCM_PRTY_STS_REG_AG_PRTY5_SIZE 11
#define TCM_TCM_PRTY_STS_REG_AG_PRTY6 (0x1<<12)
#define TCM_TCM_PRTY_STS_REG_AG_PRTY6_SIZE 12
#define TCM_TCM_PRTY_STS_REG_AG_PRTY7 (0x1<<13)
#define TCM_TCM_PRTY_STS_REG_AG_PRTY7_SIZE 13
#define TCM_TCM_PRTY_STS_REG_SM_PRTY0 (0x1<<14)
#define TCM_TCM_PRTY_STS_REG_SM_PRTY0_SIZE 14
#define TCM_TCM_PRTY_STS_REG_SM_PRTY1 (0x1<<15)
#define TCM_TCM_PRTY_STS_REG_SM_PRTY1_SIZE 15
#define TCM_TCM_PRTY_STS_REG_SM_PRTY2 (0x1<<16)
#define TCM_TCM_PRTY_STS_REG_SM_PRTY2_SIZE 16
#define TCM_TCM_PRTY_STS_REG_SM_PRTY3 (0x1<<17)
#define TCM_TCM_PRTY_STS_REG_SM_PRTY3_SIZE 17
#define TCM_TCM_PRTY_STS_REG_STORM_PRTY (0x1<<18)
#define TCM_TCM_PRTY_STS_REG_STORM_PRTY_SIZE 18
#define TCM_TCM_PRTY_STS_REG_TSDM_PRTY (0x1<<19)
#define TCM_TCM_PRTY_STS_REG_TSDM_PRTY_SIZE 19
#define TCM_TCM_PRTY_STS_REG_PRS_PRTY (0x1<<20)
#define TCM_TCM_PRTY_STS_REG_PRS_PRTY_SIZE 20
#define TCM_TCM_PRTY_STS_REG_PBF_PRTY (0x1<<21)
#define TCM_TCM_PRTY_STS_REG_PBF_PRTY_SIZE 21
#define TCM_TCM_PRTY_STS_REG_USEM_PRTY (0x1<<22)
#define TCM_TCM_PRTY_STS_REG_USEM_PRTY_SIZE 22
#define TCM_TCM_PRTY_STS_REG_CSEM_PRTY (0x1<<23)
#define TCM_TCM_PRTY_STS_REG_CSEM_PRTY_SIZE 23
#define TCM_TCM_PRTY_STS_REG_CP0_PRTY (0x1<<24)
#define TCM_TCM_PRTY_STS_REG_CP0_PRTY_SIZE 24
#define TCM_TCM_PRTY_STS_REG_CP1_PRTY (0x1<<25)
#define TCM_TCM_PRTY_STS_REG_CP1_PRTY_SIZE 25
#define TCM_TCM_PRTY_STS_REG_UM_PRTY (0x1<<26)
#define TCM_TCM_PRTY_STS_REG_UM_PRTY_SIZE 26
#define TCM_REG_TCM_PRTY_STS_CLR 0x501e4UL //ACCESS:RC DataWidth:0x1b Description: Parity register #0 read clear
#define TCM_TCM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define TCM_TCM_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define TCM_TCM_PRTY_STS_CLR_REG_XT_PRTY (0x1<<1)
#define TCM_TCM_PRTY_STS_CLR_REG_XT_PRTY_SIZE 1
#define TCM_TCM_PRTY_STS_CLR_REG_DT_PRTY (0x1<<2)
#define TCM_TCM_PRTY_STS_CLR_REG_DT_PRTY_SIZE 2
#define TCM_TCM_PRTY_STS_CLR_REG_PM_PRTY0 (0x1<<3)
#define TCM_TCM_PRTY_STS_CLR_REG_PM_PRTY0_SIZE 3
#define TCM_TCM_PRTY_STS_CLR_REG_PM_PRTY1 (0x1<<4)
#define TCM_TCM_PRTY_STS_CLR_REG_PM_PRTY1_SIZE 4
#define TCM_TCM_PRTY_STS_CLR_REG_UQ_PRTY (0x1<<5)
#define TCM_TCM_PRTY_STS_CLR_REG_UQ_PRTY_SIZE 5
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY0 (0x1<<6)
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY0_SIZE 6
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY1 (0x1<<7)
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY1_SIZE 7
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY2 (0x1<<8)
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY2_SIZE 8
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY3 (0x1<<9)
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY3_SIZE 9
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY4 (0x1<<10)
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY4_SIZE 10
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY5 (0x1<<11)
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY5_SIZE 11
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY6 (0x1<<12)
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY6_SIZE 12
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY7 (0x1<<13)
#define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY7_SIZE 13
#define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY0 (0x1<<14)
#define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY0_SIZE 14
#define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY1 (0x1<<15)
#define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY1_SIZE 15
#define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY2 (0x1<<16)
#define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY2_SIZE 16
#define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY3 (0x1<<17)
#define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY3_SIZE 17
#define TCM_TCM_PRTY_STS_CLR_REG_STORM_PRTY (0x1<<18)
#define TCM_TCM_PRTY_STS_CLR_REG_STORM_PRTY_SIZE 18
#define TCM_TCM_PRTY_STS_CLR_REG_TSDM_PRTY (0x1<<19)
#define TCM_TCM_PRTY_STS_CLR_REG_TSDM_PRTY_SIZE 19
#define TCM_TCM_PRTY_STS_CLR_REG_PRS_PRTY (0x1<<20)
#define TCM_TCM_PRTY_STS_CLR_REG_PRS_PRTY_SIZE 20
#define TCM_TCM_PRTY_STS_CLR_REG_PBF_PRTY (0x1<<21)
#define TCM_TCM_PRTY_STS_CLR_REG_PBF_PRTY_SIZE 21
#define TCM_TCM_PRTY_STS_CLR_REG_USEM_PRTY (0x1<<22)
#define TCM_TCM_PRTY_STS_CLR_REG_USEM_PRTY_SIZE 22
#define TCM_TCM_PRTY_STS_CLR_REG_CSEM_PRTY (0x1<<23)
#define TCM_TCM_PRTY_STS_CLR_REG_CSEM_PRTY_SIZE 23
#define TCM_TCM_PRTY_STS_CLR_REG_CP0_PRTY (0x1<<24)
#define TCM_TCM_PRTY_STS_CLR_REG_CP0_PRTY_SIZE 24
#define TCM_TCM_PRTY_STS_CLR_REG_CP1_PRTY (0x1<<25)
#define TCM_TCM_PRTY_STS_CLR_REG_CP1_PRTY_SIZE 25
#define TCM_TCM_PRTY_STS_CLR_REG_UM_PRTY (0x1<<26)
#define TCM_TCM_PRTY_STS_CLR_REG_UM_PRTY_SIZE 26
#define TCM_REG_TCM_PRTY_STS_WR 0x501e8UL //ACCESS:WR DataWidth:0x1b Description: Parity register #0 bit set or clear
#define TCM_TCM_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define TCM_TCM_PRTY_STS_WR_REG_PARITY_SIZE 0
#define TCM_TCM_PRTY_STS_WR_REG_XT_PRTY (0x1<<1)
#define TCM_TCM_PRTY_STS_WR_REG_XT_PRTY_SIZE 1
#define TCM_TCM_PRTY_STS_WR_REG_DT_PRTY (0x1<<2)
#define TCM_TCM_PRTY_STS_WR_REG_DT_PRTY_SIZE 2
#define TCM_TCM_PRTY_STS_WR_REG_PM_PRTY0 (0x1<<3)
#define TCM_TCM_PRTY_STS_WR_REG_PM_PRTY0_SIZE 3
#define TCM_TCM_PRTY_STS_WR_REG_PM_PRTY1 (0x1<<4)
#define TCM_TCM_PRTY_STS_WR_REG_PM_PRTY1_SIZE 4
#define TCM_TCM_PRTY_STS_WR_REG_UQ_PRTY (0x1<<5)
#define TCM_TCM_PRTY_STS_WR_REG_UQ_PRTY_SIZE 5
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY0 (0x1<<6)
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY0_SIZE 6
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY1 (0x1<<7)
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY1_SIZE 7
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY2 (0x1<<8)
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY2_SIZE 8
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY3 (0x1<<9)
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY3_SIZE 9
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY4 (0x1<<10)
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY4_SIZE 10
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY5 (0x1<<11)
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY5_SIZE 11
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY6 (0x1<<12)
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY6_SIZE 12
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY7 (0x1<<13)
#define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY7_SIZE 13
#define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY0 (0x1<<14)
#define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY0_SIZE 14
#define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY1 (0x1<<15)
#define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY1_SIZE 15
#define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY2 (0x1<<16)
#define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY2_SIZE 16
#define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY3 (0x1<<17)
#define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY3_SIZE 17
#define TCM_TCM_PRTY_STS_WR_REG_STORM_PRTY (0x1<<18)
#define TCM_TCM_PRTY_STS_WR_REG_STORM_PRTY_SIZE 18
#define TCM_TCM_PRTY_STS_WR_REG_TSDM_PRTY (0x1<<19)
#define TCM_TCM_PRTY_STS_WR_REG_TSDM_PRTY_SIZE 19
#define TCM_TCM_PRTY_STS_WR_REG_PRS_PRTY (0x1<<20)
#define TCM_TCM_PRTY_STS_WR_REG_PRS_PRTY_SIZE 20
#define TCM_TCM_PRTY_STS_WR_REG_PBF_PRTY (0x1<<21)
#define TCM_TCM_PRTY_STS_WR_REG_PBF_PRTY_SIZE 21
#define TCM_TCM_PRTY_STS_WR_REG_USEM_PRTY (0x1<<22)
#define TCM_TCM_PRTY_STS_WR_REG_USEM_PRTY_SIZE 22
#define TCM_TCM_PRTY_STS_WR_REG_CSEM_PRTY (0x1<<23)
#define TCM_TCM_PRTY_STS_WR_REG_CSEM_PRTY_SIZE 23
#define TCM_TCM_PRTY_STS_WR_REG_CP0_PRTY (0x1<<24)
#define TCM_TCM_PRTY_STS_WR_REG_CP0_PRTY_SIZE 24
#define TCM_TCM_PRTY_STS_WR_REG_CP1_PRTY (0x1<<25)
#define TCM_TCM_PRTY_STS_WR_REG_CP1_PRTY_SIZE 25
#define TCM_TCM_PRTY_STS_WR_REG_UM_PRTY (0x1<<26)
#define TCM_TCM_PRTY_STS_WR_REG_UM_PRTY_SIZE 26
#define TCM_REG_TCM_PRTY_MASK 0x501ecUL //ACCESS:RW DataWidth:0x1b Description: Parity mask register #0 read/write
#define TCM_TCM_PRTY_MASK_REG_PARITY (0x1<<0)
#define TCM_TCM_PRTY_MASK_REG_PARITY_SIZE 0
#define TCM_TCM_PRTY_MASK_REG_XT_PRTY (0x1<<1)
#define TCM_TCM_PRTY_MASK_REG_XT_PRTY_SIZE 1
#define TCM_TCM_PRTY_MASK_REG_DT_PRTY (0x1<<2)
#define TCM_TCM_PRTY_MASK_REG_DT_PRTY_SIZE 2
#define TCM_TCM_PRTY_MASK_REG_PM_PRTY0 (0x1<<3)
#define TCM_TCM_PRTY_MASK_REG_PM_PRTY0_SIZE 3
#define TCM_TCM_PRTY_MASK_REG_PM_PRTY1 (0x1<<4)
#define TCM_TCM_PRTY_MASK_REG_PM_PRTY1_SIZE 4
#define TCM_TCM_PRTY_MASK_REG_UQ_PRTY (0x1<<5)
#define TCM_TCM_PRTY_MASK_REG_UQ_PRTY_SIZE 5
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY0 (0x1<<6)
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY0_SIZE 6
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY1 (0x1<<7)
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY1_SIZE 7
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY2 (0x1<<8)
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY2_SIZE 8
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY3 (0x1<<9)
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY3_SIZE 9
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY4 (0x1<<10)
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY4_SIZE 10
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY5 (0x1<<11)
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY5_SIZE 11
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY6 (0x1<<12)
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY6_SIZE 12
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY7 (0x1<<13)
#define TCM_TCM_PRTY_MASK_REG_AG_PRTY7_SIZE 13
#define TCM_TCM_PRTY_MASK_REG_SM_PRTY0 (0x1<<14)
#define TCM_TCM_PRTY_MASK_REG_SM_PRTY0_SIZE 14
#define TCM_TCM_PRTY_MASK_REG_SM_PRTY1 (0x1<<15)
#define TCM_TCM_PRTY_MASK_REG_SM_PRTY1_SIZE 15
#define TCM_TCM_PRTY_MASK_REG_SM_PRTY2 (0x1<<16)
#define TCM_TCM_PRTY_MASK_REG_SM_PRTY2_SIZE 16
#define TCM_TCM_PRTY_MASK_REG_SM_PRTY3 (0x1<<17)
#define TCM_TCM_PRTY_MASK_REG_SM_PRTY3_SIZE 17
#define TCM_TCM_PRTY_MASK_REG_STORM_PRTY (0x1<<18)
#define TCM_TCM_PRTY_MASK_REG_STORM_PRTY_SIZE 18
#define TCM_TCM_PRTY_MASK_REG_TSDM_PRTY (0x1<<19)
#define TCM_TCM_PRTY_MASK_REG_TSDM_PRTY_SIZE 19
#define TCM_TCM_PRTY_MASK_REG_PRS_PRTY (0x1<<20)
#define TCM_TCM_PRTY_MASK_REG_PRS_PRTY_SIZE 20
#define TCM_TCM_PRTY_MASK_REG_PBF_PRTY (0x1<<21)
#define TCM_TCM_PRTY_MASK_REG_PBF_PRTY_SIZE 21
#define TCM_TCM_PRTY_MASK_REG_USEM_PRTY (0x1<<22)
#define TCM_TCM_PRTY_MASK_REG_USEM_PRTY_SIZE 22
#define TCM_TCM_PRTY_MASK_REG_CSEM_PRTY (0x1<<23)
#define TCM_TCM_PRTY_MASK_REG_CSEM_PRTY_SIZE 23
#define TCM_TCM_PRTY_MASK_REG_CP0_PRTY (0x1<<24)
#define TCM_TCM_PRTY_MASK_REG_CP0_PRTY_SIZE 24
#define TCM_TCM_PRTY_MASK_REG_CP1_PRTY (0x1<<25)
#define TCM_TCM_PRTY_MASK_REG_CP1_PRTY_SIZE 25
#define TCM_TCM_PRTY_MASK_REG_UM_PRTY (0x1<<26)
#define TCM_TCM_PRTY_MASK_REG_UM_PRTY_SIZE 26
#define TCM_REG_SM_CTX1_TM 0x50300UL //ACCESS:RW DataWidth:0x5 Description: TM bits of STORM context. MSB.
#define TCM_REG_IS_UM_TM 0x50304UL //ACCESS:RW DataWidth:0x2 Description: TM bits of UM input stage buffer.
#define TCM_REG_IS_STORM_TM 0x50308UL //ACCESS:RW DataWidth:0x2 Description: TM bits of STORM input stage buffer.
#define TCM_REG_ECO_RESERVED 0x5030cUL //ACCESS:RW DataWidth:0x8 Description: chicken bits
#define TCM_REG_IS_PRS_TM 0x50310UL //ACCESS:RW DataWidth:0x2 Description: TM bits of Parser input stage buffer.
#define TCM_REG_IS_USEM_TM 0x50314UL //ACCESS:RW DataWidth:0x2 Description: TM bits of Parser input stage buffer.
#define TCM_REG_L1ST_PAGE_MODE 0x50318UL //ACCESS:RW DataWidth:0x1 Description: L1 Storm context page mode enable. If 0 - the whole context of 256 LCIDs is visible. Possible only in legacy mode; looking only into the old per-LCID addresses and not seeing the new per-LCID addresses. If 1- page mode; when looking into all per-LCID addresses is possible but for only one page of the whole context.
#define TCM_REG_L1ST_PAGE 0x5031cUL //ACCESS:RW DataWidth:0x8 Description: L1 Storm context page to access to. Browses between the windows; the size of which is defined by ~tcm_registers_l1st_page_size.l1st_page_size. In E2 TCM it browses between 2 windows each of which contains context for 256/2=128 LCIDs. Only bits from 7 down to log(~tcm_registers_l1st_page_size.l1st_page_size;2) are meaningful. Meaning for ~tcm_registers_l1st_page_size.l1st_page_size=8h80; when 8h00 - LCIDs from 0 to 127 are visible; when 8h80 - LCIDs from 128 to 255. The SW can write exact start LCID into the register and only its msb will be used to select the appropriate page.
#define TCM_REG_L1ST_PAGE_SIZE 0x50320UL //ACCESS:R DataWidth:0x8 Description: L1 Storm context page size (measured in number of LCIDs fitting into one page). Hard-wired one-hot value; the log(~tcm_registers_l1st_page_size.l1st_page_size;2) of which designates the size of the page in LCIDs. For TCM it is 8h80 meaning page size is 2^7=128 LCIDs.
#define TCM_REG_L1ST_CTX_SIZE 0x50324UL //ACCESS:R DataWidth:0x8 Description: L1 Storm per-LCID context size (measured in REGs).
#define TCM_REG_UM_FIC1_FORCE 0x50330UL //ACCESS:RW DataWidth:0x1 Description: 0-messages unlocked from Pending messages RAM go to the FIC for which they were designated in input message; 1-messages unlocked from Pending messages RAM are forced to FIC1 whether they were destined to FIC0 or FIC1 in original message.
#define TCM_REG_PHYS_QNUM0_0 0x500e0UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 0 per port index.
#define TCM_REG_PHYS_QNUM0_0_SIZE 1
#define TCM_REG_PHYS_QNUM0_1 0x500e4UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 0 per port index.
#define TCM_REG_PHYS_QNUM0_1_SIZE 1
#define TCM_REG_PHYS_QNUM1_0 0x500e8UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 1 per port index.
#define TCM_REG_PHYS_QNUM1_0_SIZE 1
#define TCM_REG_PHYS_QNUM1_1 0x500ecUL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 1 per port index.
#define TCM_REG_PHYS_QNUM1_1_SIZE 1
#define TCM_REG_PHYS_QNUM2_0 0x500f0UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 2 per port index.
#define TCM_REG_PHYS_QNUM2_0_SIZE 1
#define TCM_REG_PHYS_QNUM2_1 0x500f4UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 2 per port index.
#define TCM_REG_PHYS_QNUM2_1_SIZE 1
#define TCM_REG_PHYS_QNUM3_0 0x500f8UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 3 per port index.
#define TCM_REG_PHYS_QNUM3_0_SIZE 1
#define TCM_REG_PHYS_QNUM3_1 0x500fcUL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 3 per port index.
#define TCM_REG_PHYS_QNUM3_1_SIZE 1
#define TCM_REG_LCID_CAM_0 0x501f0UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define TCM_REG_LCID_CAM_0_SIZE 1
#define TCM_REG_LCID_CAM_1 0x501f4UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define TCM_REG_LCID_CAM_1_SIZE 1
#define TCM_REG_LCID_CAM_2 0x501f8UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define TCM_REG_LCID_CAM_2_SIZE 1
#define TCM_REG_LCID_CAM_3 0x501fcUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define TCM_REG_LCID_CAM_3_SIZE 1
#define TCM_REG_CAM_OCCUP_ST 0x50200UL //ACCESS:RW DataWidth:0x4 Description: CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry. In order to comply with the SW scripts the write by GRC is also available for debug purposes.
#define TCM_REG_CAM_OCCUP_ST_SIZE 1
#define TCM_REG_CFC_INIT_CRD 0x50204UL //ACCESS:RW DataWidth:0x4 Description: CFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 1 at start-up.
#define TCM_REG_CFC_INIT_CRD_SIZE 1
#define TCM_REG_CP_MSG 0x50208UL //ACCESS:W DataWidth:0x20 Description: Use to write a CP message. Write only register.
#define TCM_REG_CP_MSG_SIZE 1
#define TCM_REG_FIC0_INIT_CRD 0x5020cUL //ACCESS:RW DataWidth:0x8 Description: FIC0 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up.
#define TCM_REG_FIC0_INIT_CRD_SIZE 1
#define TCM_REG_FIC1_INIT_CRD 0x50210UL //ACCESS:RW DataWidth:0x8 Description: FIC1 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up.
#define TCM_REG_FIC1_INIT_CRD_SIZE 1
#define TCM_REG_GLB_CNT_STICKY 0x50214UL //ACCESS:RW DataWidth:0x1a Description: QM global usage counter maximum sticky value. In order to comply with the SW scripts the write by GRC is also available for debug purposes.
#define TCM_REG_GLB_CNT_STICKY_SIZE 1
#define TCM_REG_LL_SZ_STICKY 0x50218UL //ACCESS:RW DataWidth:0x6 Description: XX LL maximum value ever reached sticky value for any connection. The write to the register is performed by the XX internal circuitry. In order to comply with the SW scripts the write by GRC is also available for debug purposes.
#define TCM_REG_LL_SZ_STICKY_SIZE 1
#define TCM_REG_TQM_INIT_CRD 0x5021cUL //ACCESS:RW DataWidth:0x6 Description: QM output initial credit. Max credit available - 32.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 32 at start-up.
#define TCM_REG_TQM_INIT_CRD_SIZE 1
#define TCM_REG_XX_INIT_CRD 0x50220UL //ACCESS:RW DataWidth:0x6 Description: Initial value for the credit counter; responsible for fulfilling of the Input Stage XX protection buffer by the XX protection pending messages. Max credit available - 127.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 19 at start-up.
#define TCM_REG_XX_INIT_CRD_SIZE 1
#define TCM_REG_XX_MSG_NUM 0x50224UL //ACCESS:RW DataWidth:0x6 Description: The maximum number of pending messages; which may be stored in XX protection. ~tcm_registers_xx_free.xx_free is also written on write.
#define TCM_REG_XX_MSG_NUM_SIZE 1
#define TCM_REG_LCID_CAM_4 0x50228UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define TCM_REG_LCID_CAM_4_SIZE 1
#define TCM_REG_LCID_CAM_5 0x5022cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define TCM_REG_LCID_CAM_5_SIZE 1
#define TCM_REG_LCID_CAM_6 0x50230UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define TCM_REG_LCID_CAM_6_SIZE 1
#define TCM_REG_LCID_CAM_7 0x50234UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define TCM_REG_LCID_CAM_7_SIZE 1
#define TCM_REG_LCID_CAM_8 0x50238UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define TCM_REG_LCID_CAM_8_SIZE 1
#define TCM_REG_LCID_CAM_9 0x5023cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define TCM_REG_LCID_CAM_9_SIZE 1
#define TCM_REG_XX_TABLE 0x50240UL //ACCESS:RW DataWidth:0x10 Description: Indirect access to the XX table of the XX protection mechanism. The fields are:[4:0] - tail pointer; [10:5] - Link List size;[15:11] - header pointer.
#define TCM_REG_XX_TABLE_SIZE 10
#define TCM_REG_XX_DESCR_TABLE 0x50280UL //ACCESS:RW DataWidth:0x15 Description: Indirect access to the descriptor table of the XX protection mechanism. The fields are: [5:0] - length of the message;[15:6] - message pointer;[20:16] - next pointer.
#define TCM_REG_XX_DESCR_TABLE_SIZE 29
#define TCM_REG_XX_PEND_MSG 0x52000UL //ACCESS:RW DataWidth:0x20 Description: Debug only. Indirect access to the Pending messages RAM of the XX protection mechanism. Bit [0] designates the REG in the 2-REGs memory row. The bits [10:1] designate the row.
#define TCM_REG_XX_PEND_MSG_SIZE 1740
#define TCM_REG_AG_CTX 0x54000UL //ACCESS:RW DataWidth:0x20 Description: Indirect access to AG context with 32-bits granularity. The bits [11:8] of the address should be the offset within the accessed LCID context; the bits [7:0] are the accessed LCID.Example: to write to REG10 LCID100. The RBC address should be 12'ha64.
#define TCM_REG_AG_CTX_SIZE 3328
#define TCM_REG_STORM_CTX 0x58000UL //ACCESS:RW DataWidth:0x20 Description: Indirect access to STORM context with 32-bits granularity. In page mode the bits [12:7] of the address should be the offset within the accessed LCID context; the bits [6:0] are the accessed LCID[6:0]. In non-page mode the bits [12:8] of the address should be the offset within the accessed LCID context; the bits [7:0] are the accessed LCID.Example: to write to REG10 LCID100. The RBC address should be 13'ha64. The actual size of the memory is 9216.
#define TCM_REG_STORM_CTX_SIZE 8192
#define TCM_REG_TCM_UNUSED_EMPTY_0 0x50328UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TCM_REG_TCM_UNUSED_EMPTY_0_SIZE 2
#define TCM_REG_TCM_UNUSED_EMPTY_1 0x50334UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TCM_REG_TCM_UNUSED_EMPTY_1_SIZE 1843
#define TM_REG_EN_TIMERS 0x164000UL //ACCESS:RW DataWidth:0x1 Description: Enable for Timers state machines.
#define TM_REG_TIMER_SOFT_RST 0x164004UL //ACCESS:RW DataWidth:0x1 Description: Timer software reset - active high.
#define TM_REG_EN_CL0_INPUT 0x164008UL //ACCESS:RW DataWidth:0x1 Description: Enable client0 input.
#define TM_REG_EN_CL1_INPUT 0x16400cUL //ACCESS:RW DataWidth:0x1 Description: Enable client1 input.
#define TM_REG_EN_CL2_INPUT 0x164010UL //ACCESS:RW DataWidth:0x1 Description: Enable client2 input.
#define TM_REG_TIMER_TICK_SIZE 0x16401cUL //ACCESS:RW DataWidth:0x14 Description: The amount of hardware cycles for each timer tick.
#define TM_REG_CLIN_ARB_TYPE 0x164020UL //ACCESS:RW DataWidth:0x1 Description: Clin arbiter type 0=roundrobbin 1=priority.
#define TM_REG_CLIN_PRIOR0_CLIENT 0x164024UL //ACCESS:RW DataWidth:0x2 Description: Client in High priority client number.
#define TM_REG_CLIN_PRIOR1_CLIENT 0x164028UL //ACCESS:RW DataWidth:0x2 Description: Client in Medium priority client number.
#define TM_REG_CLIN_PRIOR2_CLIENT 0x16402cUL //ACCESS:RW DataWidth:0x2 Description: Client in Low priority client number.
#define TM_REG_CL0_CONT_REGION 0x164030UL //ACCESS:RW DataWidth:0x8 Description: Client0 context region.
#define TM_REG_CL1_CONT_REGION 0x164034UL //ACCESS:RW DataWidth:0x8 Description: Client1 context region.
#define TM_REG_CL2_CONT_REGION 0x164038UL //ACCESS:RW DataWidth:0x8 Description: Client2 context region.
#define TM_REG_LIN0_SCAN_TIME 0x16403cUL //ACCESS:RW DataWidth:0x18 Description: Linear0 array scan timeout.
#define TM_REG_LIN1_SCAN_TIME 0x164040UL //ACCESS:RW DataWidth:0x18 Description: Linear1 array scan timeout.
#define TM_REG_TM_CONTEXT_REGION 0x164044UL //ACCESS:RW DataWidth:0x8 Description: Timers Context region.
#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048UL //ACCESS:RW DataWidth:0x12 Description: Linear0 Max active cid (in banks of 32 entries).
#define TM_REG_LIN1_MAX_ACTIVE_CID 0x16404cUL //ACCESS:RW DataWidth:0x12 Description: Linear1 Max active cid (in banks of 32 entries).
#define TM_REG_LIN0_MIN_ACTIVE_CID 0x164050UL //ACCESS:RW DataWidth:0x12 Description: Linear0 Min active cid (in banks of 32 entries).
#define TM_REG_LIN1_MIN_ACTIVE_CID 0x164054UL //ACCESS:RW DataWidth:0x12 Description: Linear1 Min active cid (in banks of 32 entries).
#define TM_REG_PCI_NS_FLAG 0x164058UL //ACCESS:RW DataWidth:0x1 Description: NS flag for pci requests.
#define TM_REG_PCI_RO_FLAG 0x16405cUL //ACCESS:RW DataWidth:0x1 Description: RO flag for pci requests.
#define TM_REG_PCI_FLOW_ID 0x164060UL //ACCESS:RW DataWidth:0x5 Description: Pci flow ID.
#define TM_REG_FALSE_EXPIR_CLIENT 0x164064UL //ACCESS:RW DataWidth:0x2 Description: Client number for false expirations.
#define TM_REG_LIN0_LOGIC_ADD_MASK 0x164068UL //ACCESS:RW DataWidth:0x20 Description: Linear0 Address mask.
#define TM_REG_LIN1_LOGIC_ADD_MASK 0x16406cUL //ACCESS:RW DataWidth:0x20 Description: Linear1 Address mask.
#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070UL //ACCESS:RW DataWidth:0x6 Description: Linear timer set_clear fifo threshold.
#define TM_REG_LIN_EXP_FIFO_ALFULL_THR 0x164074UL //ACCESS:RW DataWidth:0x3 Description: Linear expiration fifo threshold.
#define TM_REG_LIN_EXTA_FIFO_ALFULL_THR 0x164078UL //ACCESS:RW DataWidth:0x4 Description: Linear exta fifo threshold.
#define TM_REG_EXP_CFCRES_FIFO_ALFULL_THR 0x16407cUL //ACCESS:RW DataWidth:0x5 Description: Expiration cfc result fifo threshold.
#define TM_REG_CFCREQ_AC_FIFO_ALFULL_THR 0x164080UL //ACCESS:RW DataWidth:0x4 Description: CFC Request - Act cnt fifo threshold.
#define TM_REG_CFCREQ_EXP_FIFO_ALFULL_THR 0x164084UL //ACCESS:RW DataWidth:0x4 Description: CFC req - expiration fifo threshold.
#define TM_REG_CFCREQ_CLOUT_FIFO_ALFULL_THR 0x164088UL //ACCESS:RW DataWidth:0x4 Description: CFC req - clout fifo threshold.
#define TM_REG_CLOUT_DIRECT_FIFO_ALFULL_THR 0x16408cUL //ACCESS:RW DataWidth:0x5 Description: Client Out - direct fifo threshold. FIFO is not used.
#define TM_REG_CLOUT_TYP4_FIFO_ALFULL_THR 0x164090UL //ACCESS:RW DataWidth:0x5 Description: Client Out type4 fifo threshold.
#define TM_REG_SET_ERR_FLAG 0x164094UL //ACCESS:RC DataWidth:0x1 Description: Set error flag from cmd handler.
#define TM_REG_CLEAR_ERR_FLAG 0x164098UL //ACCESS:RC DataWidth:0x1 Description: Clear error flag from cmd handler.
#define TM_REG_STOPALL_ERR_FLAG 0x16409cUL //ACCESS:RC DataWidth:0x1 Description: Stopall error flag from cmd handler.
#define TM_REG_LIN0_NUM_SCANS 0x1640a0UL //ACCESS:ST DataWidth:0x10 Description: Linear0 Number of scans counter.
#define TM_REG_LIN1_NUM_SCANS 0x1640a4UL //ACCESS:ST DataWidth:0x10 Description: Linear1 Number of scans counter.
#define TM_REG_CLIENT0_EXPIR_CNT 0x1640a8UL //ACCESS:ST DataWidth:0x18 Description: Client0 Expiration counter.
#define TM_REG_CLIENT1_EXPIR_CNT 0x1640acUL //ACCESS:ST DataWidth:0x18 Description: Client1 Expiration counter.
#define TM_REG_CLIENT2_EXPIR_CNT 0x1640b0UL //ACCESS:ST DataWidth:0x18 Description: Client2 Expiration counter.
#define TM_REG_CLIENT0_REWIND_CNT 0x1640b4UL //ACCESS:ST DataWidth:0x18 Description: Client0 Rewind counter.
#define TM_REG_CLIENT1_REWIND_CNT 0x1640b8UL //ACCESS:ST DataWidth:0x18 Description: Client1 Rewind counter.
#define TM_REG_CLIENT2_REWIND_CNT 0x1640bcUL //ACCESS:ST DataWidth:0x18 Description: Client2 Rewind counter.
#define TM_REG_CLIENT_ALL_REWIND_CNT 0x1640c0UL //ACCESS:ST DataWidth:0x18 Description: All clients rewind counter.
#define TM_REG_CLIENT_ALL_CLEAR_CNT 0x1640c4UL //ACCESS:ST DataWidth:0x18 Description: All clients clear counter.
#define TM_REG_CLIENT_ALL_SET_CNT 0x1640c8UL //ACCESS:ST DataWidth:0x18 Description: All clients set counter.
#define TM_REG_CLIENT_ALL_STOPALL_CNT 0x1640ccUL //ACCESS:ST DataWidth:0x18 Description: All clients stopall counter.
#define TM_REG_EN_REAL_TIME_CNT 0x1640d8UL //ACCESS:RW DataWidth:0x1 Description: Enable real time counter.
#define TM_REG_CFCREQ_ECHO_FIFO_ALFULL_THR 0x1640dcUL //ACCESS:RW DataWidth:0x5 Description: Cfcreq echo fifofull threshold.
#define TM_REG_TM_L1_TM 0x1640e0UL //ACCESS:RW DataWidth:0x8 Description: TM Bits of context ram0 Memory.
#define TM_REG_DBG_SELECT 0x1640e4UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from TM to the DBG block) - for selecting a line to output to the DBG block
#define TM_REG_DBG_BYTE_ENABLE 0x1640e8UL //ACCESS:RW DataWidth:0x8 Description: Debug only: For dbgmux usage (debug data that goes from TM to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define TM_REG_DBG_SHIFT 0x1640ecUL //ACCESS:RW DataWidth:0x3 Description: Debug only: For dbgmux usage (debug data that goes from TM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define TM_REG_TM_INT_STS 0x1640f0UL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
#define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define TM_REG_TM_INT_STS_CLR 0x1640f4UL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define TM_REG_TM_INT_STS_WR 0x1640f8UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define TM_REG_TM_INT_MASK 0x1640fcUL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
#define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define TM_REG_TM_PRTY_STS 0x164100UL //ACCESS:R DataWidth:0x7 Description: Parity register #0 read
#define TM_TM_PRTY_STS_REG_PARITY (0x1<<0)
#define TM_TM_PRTY_STS_REG_PARITY_SIZE 0
#define TM_TM_PRTY_STS_REG_TM_L1_0_PARITY (0x1<<1)
#define TM_TM_PRTY_STS_REG_TM_L1_0_PARITY_SIZE 1
#define TM_TM_PRTY_STS_REG_TM_L1_1_PARITY (0x1<<2)
#define TM_TM_PRTY_STS_REG_TM_L1_1_PARITY_SIZE 2
#define TM_TM_PRTY_STS_REG_TU_BANK0_PARITY (0x1<<3)
#define TM_TM_PRTY_STS_REG_TU_BANK0_PARITY_SIZE 3
#define TM_TM_PRTY_STS_REG_TU_BANK1_PARITY (0x1<<4)
#define TM_TM_PRTY_STS_REG_TU_BANK1_PARITY_SIZE 4
#define TM_TM_PRTY_STS_REG_TU_SETCLR0_PARITY (0x1<<5)
#define TM_TM_PRTY_STS_REG_TU_SETCLR0_PARITY_SIZE 5
#define TM_TM_PRTY_STS_REG_TU_SETCLR1_PARITY (0x1<<6)
#define TM_TM_PRTY_STS_REG_TU_SETCLR1_PARITY_SIZE 6
#define TM_REG_TM_PRTY_STS_CLR 0x164104UL //ACCESS:RC DataWidth:0x7 Description: Parity register #0 read clear
#define TM_TM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define TM_TM_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define TM_TM_PRTY_STS_CLR_REG_TM_L1_0_PARITY (0x1<<1)
#define TM_TM_PRTY_STS_CLR_REG_TM_L1_0_PARITY_SIZE 1
#define TM_TM_PRTY_STS_CLR_REG_TM_L1_1_PARITY (0x1<<2)
#define TM_TM_PRTY_STS_CLR_REG_TM_L1_1_PARITY_SIZE 2
#define TM_TM_PRTY_STS_CLR_REG_TU_BANK0_PARITY (0x1<<3)
#define TM_TM_PRTY_STS_CLR_REG_TU_BANK0_PARITY_SIZE 3
#define TM_TM_PRTY_STS_CLR_REG_TU_BANK1_PARITY (0x1<<4)
#define TM_TM_PRTY_STS_CLR_REG_TU_BANK1_PARITY_SIZE 4
#define TM_TM_PRTY_STS_CLR_REG_TU_SETCLR0_PARITY (0x1<<5)
#define TM_TM_PRTY_STS_CLR_REG_TU_SETCLR0_PARITY_SIZE 5
#define TM_TM_PRTY_STS_CLR_REG_TU_SETCLR1_PARITY (0x1<<6)
#define TM_TM_PRTY_STS_CLR_REG_TU_SETCLR1_PARITY_SIZE 6
#define TM_REG_TM_PRTY_STS_WR 0x164108UL //ACCESS:WR DataWidth:0x7 Description: Parity register #0 bit set or clear
#define TM_TM_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define TM_TM_PRTY_STS_WR_REG_PARITY_SIZE 0
#define TM_TM_PRTY_STS_WR_REG_TM_L1_0_PARITY (0x1<<1)
#define TM_TM_PRTY_STS_WR_REG_TM_L1_0_PARITY_SIZE 1
#define TM_TM_PRTY_STS_WR_REG_TM_L1_1_PARITY (0x1<<2)
#define TM_TM_PRTY_STS_WR_REG_TM_L1_1_PARITY_SIZE 2
#define TM_TM_PRTY_STS_WR_REG_TU_BANK0_PARITY (0x1<<3)
#define TM_TM_PRTY_STS_WR_REG_TU_BANK0_PARITY_SIZE 3
#define TM_TM_PRTY_STS_WR_REG_TU_BANK1_PARITY (0x1<<4)
#define TM_TM_PRTY_STS_WR_REG_TU_BANK1_PARITY_SIZE 4
#define TM_TM_PRTY_STS_WR_REG_TU_SETCLR0_PARITY (0x1<<5)
#define TM_TM_PRTY_STS_WR_REG_TU_SETCLR0_PARITY_SIZE 5
#define TM_TM_PRTY_STS_WR_REG_TU_SETCLR1_PARITY (0x1<<6)
#define TM_TM_PRTY_STS_WR_REG_TU_SETCLR1_PARITY_SIZE 6
#define TM_REG_TM_PRTY_MASK 0x16410cUL //ACCESS:RW DataWidth:0x7 Description: Parity mask register #0 read/write
#define TM_TM_PRTY_MASK_REG_PARITY (0x1<<0)
#define TM_TM_PRTY_MASK_REG_PARITY_SIZE 0
#define TM_TM_PRTY_MASK_REG_TM_L1_0_PARITY (0x1<<1)
#define TM_TM_PRTY_MASK_REG_TM_L1_0_PARITY_SIZE 1
#define TM_TM_PRTY_MASK_REG_TM_L1_1_PARITY (0x1<<2)
#define TM_TM_PRTY_MASK_REG_TM_L1_1_PARITY_SIZE 2
#define TM_TM_PRTY_MASK_REG_TU_BANK0_PARITY (0x1<<3)
#define TM_TM_PRTY_MASK_REG_TU_BANK0_PARITY_SIZE 3
#define TM_TM_PRTY_MASK_REG_TU_BANK1_PARITY (0x1<<4)
#define TM_TM_PRTY_MASK_REG_TU_BANK1_PARITY_SIZE 4
#define TM_TM_PRTY_MASK_REG_TU_SETCLR0_PARITY (0x1<<5)
#define TM_TM_PRTY_MASK_REG_TU_SETCLR0_PARITY_SIZE 5
#define TM_TM_PRTY_MASK_REG_TU_SETCLR1_PARITY (0x1<<6)
#define TM_TM_PRTY_MASK_REG_TU_SETCLR1_PARITY_SIZE 6
#define TM_REG_EN_PHY0_ADDR_CACHE 0x164110UL //ACCESS:RW DataWidth:0x1 Description: Enable physical addres caching Port0.
#define TM_REG_EN_PHY1_ADDR_CACHE 0x164114UL //ACCESS:RW DataWidth:0x1 Description: Enable physical addres caching Port1.
#define TM_REG_TM_L1_1_TM 0x164118UL //ACCESS:RW DataWidth:0x8 Description: TM Bits of context ram1 Memory.
#define TM_REG_ECO_RESERVED 0x16411cUL //ACCESS:RW DataWidth:0x8 Description: chicken bits
#define TM_REG_SETCLR0_TM 0x164120UL //ACCESS:RW DataWidth:0x2 Description: TM Bits of setclr fifo0
#define TM_REG_SETCLR1_TM 0x164124UL //ACCESS:RW DataWidth:0x2 Description: TM Bits of setclr fifo1
#define TM_REG_ATC_PAGE_SIZE 0x164130UL //ACCESS:RW DataWidth:0x3 Description: Page size for atc purposes (000->4KB 001->8KB 010->16KB 011->32KB 100->64KB 101->128KB 111:110->RESERVED); applies to all PFs; can set to min between STUs of all PFs.
#define TM_REG_ATC_PAGE_1ST_BNK_RD 0x164134UL //ACCESS:RW DataWidth:0x3 Description: ATC flag for reading first bank in a page; bit2: 0->low priority 1->high priority; bit[1:0]: 00->do nothing 01->search only 10->search & cache 11->search & release
#define TM_REG_ATC_PAGE_1ST_BNK_WR 0x164138UL //ACCESS:RW DataWidth:0x3 Description: ATC flag for writing first bank in a page; bit2: 0->low priority 1->high priority; bit[1:0]: 00->do nothing 01->search only 10->search & cache 11->search & release
#define TM_REG_ATC_PAGE_LAS_BNK_RD 0x16413cUL //ACCESS:RW DataWidth:0x3 Description: ATC flag for reading last bank in a page; bit2: 0->low priority 1->high priority; bit[1:0]: 00->do nothing 01->search only 10->search & cache 11->search & release
#define TM_REG_ATC_PAGE_LAS_BNK_WR 0x164140UL //ACCESS:RW DataWidth:0x3 Description: ATC flag for writing last bank in a page; bit2: 0->low priority 1->high priority; bit[1:0]: 00->do nothing 01->search only 10->search & cache 11->search & release
#define TM_REG_ATC_PAGE_MID_BNK_RD 0x164144UL //ACCESS:RW DataWidth:0x3 Description: ATC flag for reading middle banks in a page; bit2: 0->low priority 1->high priority; bit[1:0]: 00->do nothing 01->search only 10->search & cache 11->search & release
#define TM_REG_ATC_PAGE_MID_BNK_WR 0x164148UL //ACCESS:RW DataWidth:0x3 Description: ATC flag for writing middle banks in a page; bit2: 0->low priority 1->high priority; bit[1:0]: 00->do nothing 01->search only 10->search & cache 11->search & release
#define TM_REG_ATC_SET_CLR_WR 0x16414cUL //ACCESS:RW DataWidth:0x3 Description: ATC flag for writes from set or clear (new) commands; bit2: 0->low priority 1->high priority; bit[1:0]: 00->do nothing 01->search only 10->search & cache 11->search & release
#define TM_REG_AC_UPD_CHANGE_DIS 0x164150UL //ACCESS:RW DataWidth:0x1 Description: Disables ac updt change; ac updt change prevents cmd handler from pre-incr ac for expiration msg clients & incr ac as part of client out cfc load request
#define TM_REG_EN_LINEAR0_TIMER 0x164014UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable Linear Engine Port0; function 0.
#define TM_REG_EN_LINEAR0_TIMER_SIZE 1
#define TM_REG_EN_LINEAR1_TIMER 0x164018UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable Linear Engine Port1; function 0.
#define TM_REG_EN_LINEAR1_TIMER_SIZE 1
#define TM_REG_LIN0_SCAN_ON 0x1640d0UL //ACCESS:R DataWidth:0x1 SPLIT:4 Description: Scan-on sig from lin engine 0. Active during bank-rd; scan; bank-wr; expr cfc load.
#define TM_REG_LIN0_SCAN_ON_SIZE 1
#define TM_REG_LIN1_SCAN_ON 0x1640d4UL //ACCESS:R DataWidth:0x1 SPLIT:4 Description: Scan-on sig from lin engine 1. Active during bank-rd; scan; bank-wr; expr cfc load.
#define TM_REG_LIN1_SCAN_ON_SIZE 1
#define TM_REG_LIN0_VNIC_UC 0x164128UL //ACCESS:R DataWidth:0x9 SPLIT:4 Description: vnic usage counter value for port 0 accurate only after bank write response is received.
#define TM_REG_LIN0_VNIC_UC_SIZE 1
#define TM_REG_LIN1_VNIC_UC 0x16412cUL //ACCESS:R DataWidth:0x9 SPLIT:4 Description: vnic usage counter value for port 1 accurate only after bank write response is received.
#define TM_REG_LIN1_VNIC_UC_SIZE 1
#define TM_REG_CURRENT_TIME 0x164200UL //ACCESS:R DataWidth:0x1e Description: Current Time read from Command Handler counter.
#define TM_REG_CURRENT_TIME_SIZE 1
#define TM_REG_CFC_AC_CRDCNT_VAL 0x164208UL //ACCESS:RW DataWidth:0x4 Description: Load value for for cfc ac credit cnt.
#define TM_REG_CFC_AC_CRDCNT_VAL_SIZE 1
#define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210UL //ACCESS:RW DataWidth:0x4 Description: Load value for cfc cld credit cnt.
#define TM_REG_CFC_CLD_CRDCNT_VAL_SIZE 1
#define TM_REG_CFC_LOADREQ_MAX_NUM 0x164218UL //ACCESS:RW DataWidth:0x4 Description: CFC max number of outstanding load requests for clients context loading.
#define TM_REG_CFC_LOADREQ_MAX_NUM_SIZE 1
#define TM_REG_CLOUT_CRDCNT0_VAL 0x164220UL //ACCESS:RW DataWidth:0x4 Description: Load value for clout0 cred cnt.
#define TM_REG_CLOUT_CRDCNT0_VAL_SIZE 1
#define TM_REG_CLOUT_CRDCNT1_VAL 0x164228UL //ACCESS:RW DataWidth:0x4 Description: Load value for clout1 cred cnt.
#define TM_REG_CLOUT_CRDCNT1_VAL_SIZE 1
#define TM_REG_CLOUT_CRDCNT2_VAL 0x164230UL //ACCESS:RW DataWidth:0x4 Description: Load value for clout2 cred cnt.
#define TM_REG_CLOUT_CRDCNT2_VAL_SIZE 1
#define TM_REG_EXP_CRDCNT_VAL 0x164238UL //ACCESS:RW DataWidth:0x4 Description: Load value for expiration credit cnt. CFC max number of outstanding load requests for timers (expiration) context loading.
#define TM_REG_EXP_CRDCNT_VAL_SIZE 1
#define TM_REG_LIN0_LOGIC_ADDR 0x164240UL //ACCESS:RW DataWidth:0x20 Description: Linear0 logic address.
#define TM_REG_LIN0_LOGIC_ADDR_SIZE 1
#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248UL //ACCESS:RW DataWidth:0x1 Description: Linear0 physical address valid.
#define TM_REG_LIN0_PHY_ADDR_VALID_SIZE 1
#define TM_REG_LIN1_LOGIC_ADDR 0x164250UL //ACCESS:RW DataWidth:0x20 Description: Linear1 logic address.
#define TM_REG_LIN1_LOGIC_ADDR_SIZE 1
#define TM_REG_LIN1_PHY_ADDR_VALID 0x164258UL //ACCESS:RW DataWidth:0x1 Description: Linear1 physical address valid.
#define TM_REG_LIN1_PHY_ADDR_VALID_SIZE 1
#define TM_REG_PCIARB_CRDCNT_VAL 0x164260UL //ACCESS:RW DataWidth:0x2 Description: Load value for pci arbiter credit cnt.
#define TM_REG_PCIARB_CRDCNT_VAL_SIZE 1
#define TM_REG_LIN0_PHY_ADDR 0x164270UL //ACCESS:WB DataWidth:0x40 Description: Linear0 phy address.
#define TM_REG_LIN0_PHY_ADDR_SIZE 2
#define TM_REG_LIN1_PHY_ADDR 0x164280UL //ACCESS:WB DataWidth:0x40 Description: Linear1 phy address.
#define TM_REG_LIN1_PHY_ADDR_SIZE 2
#define TM_REG_CONTEXT_RAM0 0x164800UL //ACCESS:WB DataWidth:0x40 Description: Context ram0 wide bus read-write.
#define TM_REG_CONTEXT_RAM0_SIZE 512
#define TM_REG_CONTEXT_RAM1 0x165000UL //ACCESS:WB DataWidth:0x23 Description: Context ram1 wide bus read-write.
#define TM_REG_CONTEXT_RAM1_SIZE 512
#define TM_REG_TM_UNUSED_EMPTY_0 0x164154UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TM_REG_TM_UNUSED_EMPTY_0_SIZE 43
#define TM_REG_TM_UNUSED_EMPTY_1 0x164204UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TM_REG_TM_UNUSED_EMPTY_1_SIZE 1
#define TM_REG_TM_UNUSED_EMPTY_2 0x164268UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TM_REG_TM_UNUSED_EMPTY_2_SIZE 2
#define TM_REG_TM_UNUSED_EMPTY_3 0x164290UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TM_REG_TM_UNUSED_EMPTY_3_SIZE 348
#define TM_REG_TM_UNUSED_EMPTY_4 0x165800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TM_REG_TM_UNUSED_EMPTY_4_SIZE 512
#define TSDM_REG_TIMER_TICK 0x42000UL //ACCESS:RW DataWidth:0x20 Description: Tick for timer counter. Applicable only when ~tsdm_registers_timer_tick_enable.timer_tick_enable =1
#define TSDM_REG_TIMERS_TICK_ENABLE 0x42004UL //ACCESS:RW DataWidth:0x1 Description: Enable for tick counter.
#define TSDM_REG_CFC_RSP_START_ADDR 0x42008UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the cfc_rsp lcid
#define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200cUL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the completion counters.
#define TSDM_REG_Q_COUNTER_START_ADDR 0x42010UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for queue counters
#define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the packet end message
#define TSDM_REG_COUNTERS_WRAP 0x42018UL //ACCESS:RW DataWidth:0x1 Description: Indicates if the 204 statistics counters should stop counting when reaching an all-ones value or should wrap-around 0=stop counting 1=wrap-around.
#define TSDM_REG_CMP_COUNTER_MAX0 0x4201cUL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #0
#define TSDM_REG_CMP_COUNTER_MAX1 0x42020UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #1
#define TSDM_REG_CMP_COUNTER_MAX2 0x42024UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #2
#define TSDM_REG_CMP_COUNTER_MAX3 0x42028UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #3
#define TSDM_REG_BRB1_ALMOST_FULL 0x4202cUL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from BRB1 in DMA_RSP block
#define TSDM_REG_PXP_ALMOST_FULL 0x42030UL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from pxp in DMA_RSP block
#define TSDM_REG_PB_ALMOST_FULL 0x42034UL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from PB in DMA_RSP block
#define TSDM_REG_AGG_INT_EVENT_0 0x42038UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 0
#define TSDM_REG_AGG_INT_EVENT_1 0x4203cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 1
#define TSDM_REG_AGG_INT_EVENT_2 0x42040UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 2
#define TSDM_REG_AGG_INT_EVENT_3 0x42044UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 3
#define TSDM_REG_AGG_INT_EVENT_4 0x42048UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 4
#define TSDM_REG_AGG_INT_EVENT_5 0x4204cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 5
#define TSDM_REG_AGG_INT_EVENT_6 0x42050UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 6
#define TSDM_REG_AGG_INT_EVENT_7 0x42054UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 7
#define TSDM_REG_AGG_INT_EVENT_8 0x42058UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 8
#define TSDM_REG_AGG_INT_EVENT_9 0x4205cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 9
#define TSDM_REG_AGG_INT_EVENT_10 0x42060UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 10
#define TSDM_REG_AGG_INT_EVENT_11 0x42064UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 11
#define TSDM_REG_AGG_INT_EVENT_12 0x42068UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 12
#define TSDM_REG_AGG_INT_EVENT_13 0x4206cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 13
#define TSDM_REG_AGG_INT_EVENT_14 0x42070UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 14
#define TSDM_REG_AGG_INT_EVENT_15 0x42074UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 15
#define TSDM_REG_AGG_INT_EVENT_16 0x42078UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 16
#define TSDM_REG_AGG_INT_EVENT_17 0x4207cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 17
#define TSDM_REG_AGG_INT_EVENT_18 0x42080UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 18
#define TSDM_REG_AGG_INT_EVENT_19 0x42084UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 19
#define TSDM_REG_AGG_INT_EVENT_20 0x42088UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 20
#define TSDM_REG_AGG_INT_EVENT_21 0x4208cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 21
#define TSDM_REG_AGG_INT_EVENT_22 0x42090UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 22
#define TSDM_REG_AGG_INT_EVENT_23 0x42094UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 23
#define TSDM_REG_AGG_INT_EVENT_24 0x42098UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 24
#define TSDM_REG_AGG_INT_EVENT_25 0x4209cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 25
#define TSDM_REG_AGG_INT_EVENT_26 0x420a0UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 26
#define TSDM_REG_AGG_INT_EVENT_27 0x420a4UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 27
#define TSDM_REG_AGG_INT_EVENT_28 0x420a8UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 28
#define TSDM_REG_AGG_INT_EVENT_29 0x420acUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 29
#define TSDM_REG_AGG_INT_EVENT_30 0x420b0UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 30
#define TSDM_REG_AGG_INT_EVENT_31 0x420b4UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 31
#define TSDM_REG_AGG_INT_T_0 0x420b8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 0
#define TSDM_REG_AGG_INT_T_1 0x420bcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 1
#define TSDM_REG_AGG_INT_T_2 0x420c0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 2
#define TSDM_REG_AGG_INT_T_3 0x420c4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 3
#define TSDM_REG_AGG_INT_T_4 0x420c8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 4
#define TSDM_REG_AGG_INT_T_5 0x420ccUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 5
#define TSDM_REG_AGG_INT_T_6 0x420d0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 6
#define TSDM_REG_AGG_INT_T_7 0x420d4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 7
#define TSDM_REG_AGG_INT_T_8 0x420d8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 8
#define TSDM_REG_AGG_INT_T_9 0x420dcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 9
#define TSDM_REG_AGG_INT_T_10 0x420e0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 10
#define TSDM_REG_AGG_INT_T_11 0x420e4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 11
#define TSDM_REG_AGG_INT_T_12 0x420e8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 12
#define TSDM_REG_AGG_INT_T_13 0x420ecUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 13
#define TSDM_REG_AGG_INT_T_14 0x420f0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 14
#define TSDM_REG_AGG_INT_T_15 0x420f4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 15
#define TSDM_REG_AGG_INT_T_16 0x420f8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 16
#define TSDM_REG_AGG_INT_T_17 0x420fcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 17
#define TSDM_REG_AGG_INT_T_18 0x42100UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 18
#define TSDM_REG_AGG_INT_T_19 0x42104UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 19
#define TSDM_REG_AGG_INT_T_20 0x42108UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 20
#define TSDM_REG_AGG_INT_T_21 0x4210cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 21
#define TSDM_REG_AGG_INT_T_22 0x42110UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 22
#define TSDM_REG_AGG_INT_T_23 0x42114UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 23
#define TSDM_REG_AGG_INT_T_24 0x42118UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 24
#define TSDM_REG_AGG_INT_T_25 0x4211cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 25
#define TSDM_REG_AGG_INT_T_26 0x42120UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 26
#define TSDM_REG_AGG_INT_T_27 0x42124UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 27
#define TSDM_REG_AGG_INT_T_28 0x42128UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 28
#define TSDM_REG_AGG_INT_T_29 0x4212cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 29
#define TSDM_REG_AGG_INT_T_30 0x42130UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 30
#define TSDM_REG_AGG_INT_T_31 0x42134UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 31
#define TSDM_REG_AGG_INT_FIC_0 0x42138UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 0
#define TSDM_REG_AGG_INT_FIC_1 0x4213cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 1
#define TSDM_REG_AGG_INT_FIC_2 0x42140UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 2
#define TSDM_REG_AGG_INT_FIC_3 0x42144UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 3
#define TSDM_REG_AGG_INT_FIC_4 0x42148UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 4
#define TSDM_REG_AGG_INT_FIC_5 0x4214cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 5
#define TSDM_REG_AGG_INT_FIC_6 0x42150UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 6
#define TSDM_REG_AGG_INT_FIC_7 0x42154UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 7
#define TSDM_REG_AGG_INT_FIC_8 0x42158UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 8
#define TSDM_REG_AGG_INT_FIC_9 0x4215cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 9
#define TSDM_REG_AGG_INT_FIC_10 0x42160UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 10
#define TSDM_REG_AGG_INT_FIC_11 0x42164UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 11
#define TSDM_REG_AGG_INT_FIC_12 0x42168UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 12
#define TSDM_REG_AGG_INT_FIC_13 0x4216cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 13
#define TSDM_REG_AGG_INT_FIC_14 0x42170UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 14
#define TSDM_REG_AGG_INT_FIC_15 0x42174UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 15
#define TSDM_REG_AGG_INT_FIC_16 0x42178UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 16
#define TSDM_REG_AGG_INT_FIC_17 0x4217cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 17
#define TSDM_REG_AGG_INT_FIC_18 0x42180UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 18
#define TSDM_REG_AGG_INT_FIC_19 0x42184UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 19
#define TSDM_REG_AGG_INT_FIC_20 0x42188UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 20
#define TSDM_REG_AGG_INT_FIC_21 0x4218cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 21
#define TSDM_REG_AGG_INT_FIC_22 0x42190UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 22
#define TSDM_REG_AGG_INT_FIC_23 0x42194UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 23
#define TSDM_REG_AGG_INT_FIC_24 0x42198UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 24
#define TSDM_REG_AGG_INT_FIC_25 0x4219cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 25
#define TSDM_REG_AGG_INT_FIC_26 0x421a0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 26
#define TSDM_REG_AGG_INT_FIC_27 0x421a4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 27
#define TSDM_REG_AGG_INT_FIC_28 0x421a8UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 28
#define TSDM_REG_AGG_INT_FIC_29 0x421acUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 29
#define TSDM_REG_AGG_INT_FIC_30 0x421b0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 30
#define TSDM_REG_AGG_INT_FIC_31 0x421b4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 31
#define TSDM_REG_AGG_INT_MODE_0 0x421b8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_1 0x421bcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_2 0x421c0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_3 0x421c4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_4 0x421c8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_5 0x421ccUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_6 0x421d0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_7 0x421d4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_8 0x421d8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_9 0x421dcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_10 0x421e0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_11 0x421e4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_12 0x421e8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_13 0x421ecUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_14 0x421f0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_15 0x421f4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_16 0x421f8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (16) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_17 0x421fcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (17)
#define TSDM_REG_AGG_INT_MODE_18 0x42200UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_19 0x42204UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_20 0x42208UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_21 0x4220cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_22 0x42210UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_23 0x42214UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_24 0x42218UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_25 0x4221cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_26 0x42220UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_27 0x42224UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_28 0x42228UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_29 0x4222cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_30 0x42230UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_AGG_INT_MODE_31 0x42234UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define TSDM_REG_ENABLE_IN1 0x42238UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define TSDM_ENABLE_IN1_REG_EXT_STORE_IN_EN (0x1<<0)
#define TSDM_ENABLE_IN1_REG_EXT_STORE_IN_EN_SIZE 0
#define TSDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN (0x1<<1)
#define TSDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN_SIZE 1
#define TSDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN (0x1<<2)
#define TSDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN_SIZE 2
#define TSDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN (0x1<<3)
#define TSDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN_SIZE 3
#define TSDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN (0x1<<4)
#define TSDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN_SIZE 4
#define TSDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN (0x1<<5)
#define TSDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN_SIZE 5
#define TSDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN (0x1<<6)
#define TSDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN_SIZE 6
#define TSDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN (0x1<<7)
#define TSDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN_SIZE 7
#define TSDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN (0x1<<8)
#define TSDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN_SIZE 8
#define TSDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN (0x1<<9)
#define TSDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN_SIZE 9
#define TSDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN (0x1<<10)
#define TSDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN_SIZE 10
#define TSDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN (0x1<<11)
#define TSDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN_SIZE 11
#define TSDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN (0x1<<12)
#define TSDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN_SIZE 12
#define TSDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN (0x1<<13)
#define TSDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN_SIZE 13
#define TSDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN (0x1<<14)
#define TSDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN_SIZE 14
#define TSDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN (0x1<<15)
#define TSDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN_SIZE 15
#define TSDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN (0x1<<16)
#define TSDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN_SIZE 16
#define TSDM_ENABLE_IN1_REG_PB_DATA_IN_EN (0x1<<17)
#define TSDM_ENABLE_IN1_REG_PB_DATA_IN_EN_SIZE 17
#define TSDM_ENABLE_IN1_REG_PRS_MSG_IN_EN (0x1<<18)
#define TSDM_ENABLE_IN1_REG_PRS_MSG_IN_EN_SIZE 18
#define TSDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN (0x1<<19)
#define TSDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN_SIZE 19
#define TSDM_ENABLE_IN1_REG_PXP_REQ_IN_EN (0x1<<20)
#define TSDM_ENABLE_IN1_REG_PXP_REQ_IN_EN_SIZE 20
#define TSDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN (0x1<<21)
#define TSDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN_SIZE 21
#define TSDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN (0x1<<22)
#define TSDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN_SIZE 22
#define TSDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN (0x1<<23)
#define TSDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN_SIZE 23
#define TSDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN (0x1<<24)
#define TSDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN_SIZE 24
#define TSDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN (0x1<<25)
#define TSDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN_SIZE 25
#define TSDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN (0x1<<26)
#define TSDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN_SIZE 26
#define TSDM_REG_ENABLE_IN2 0x4223cUL //ACCESS:RW DataWidth:0x7 Multi Field Register
#define TSDM_ENABLE_IN2_REG_SDM_ACK_IN_EN (0x1<<0)
#define TSDM_ENABLE_IN2_REG_SDM_ACK_IN_EN_SIZE 0
#define TSDM_ENABLE_IN2_REG_CM_ACK_IN_EN (0x1<<1)
#define TSDM_ENABLE_IN2_REG_CM_ACK_IN_EN_SIZE 1
#define TSDM_ENABLE_IN2_REG_PB_STATUS_IN_EN (0x1<<2)
#define TSDM_ENABLE_IN2_REG_PB_STATUS_IN_EN_SIZE 2
#define TSDM_ENABLE_IN2_REG_PB_FULL_IN_EN (0x1<<3)
#define TSDM_ENABLE_IN2_REG_PB_FULL_IN_EN_SIZE 3
#define TSDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN (0x1<<4)
#define TSDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN_SIZE 4
#define TSDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN (0x1<<5)
#define TSDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN_SIZE 5
#define TSDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN (0x1<<6)
#define TSDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN_SIZE 6
#define TSDM_REG_ENABLE_OUT1 0x42240UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define TSDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN (0x1<<0)
#define TSDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN_SIZE 0
#define TSDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN (0x1<<1)
#define TSDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN_SIZE 1
#define TSDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN (0x1<<2)
#define TSDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN_SIZE 2
#define TSDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN (0x1<<3)
#define TSDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN_SIZE 3
#define TSDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN (0x1<<4)
#define TSDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN_SIZE 4
#define TSDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN (0x1<<5)
#define TSDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN_SIZE 5
#define TSDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN (0x1<<6)
#define TSDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN_SIZE 6
#define TSDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN (0x1<<7)
#define TSDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN_SIZE 7
#define TSDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN (0x1<<8)
#define TSDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN_SIZE 8
#define TSDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN (0x1<<9)
#define TSDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN_SIZE 9
#define TSDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN (0x1<<10)
#define TSDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN_SIZE 10
#define TSDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN (0x1<<11)
#define TSDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN_SIZE 11
#define TSDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN (0x1<<12)
#define TSDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN_SIZE 12
#define TSDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN (0x1<<13)
#define TSDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN_SIZE 13
#define TSDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN (0x1<<14)
#define TSDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN_SIZE 14
#define TSDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN (0x1<<15)
#define TSDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN_SIZE 15
#define TSDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN (0x1<<16)
#define TSDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN_SIZE 16
#define TSDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN (0x1<<17)
#define TSDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN_SIZE 17
#define TSDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN (0x1<<18)
#define TSDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN_SIZE 18
#define TSDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN (0x1<<19)
#define TSDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN_SIZE 19
#define TSDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN (0x1<<20)
#define TSDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN_SIZE 20
#define TSDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN (0x1<<21)
#define TSDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN_SIZE 21
#define TSDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN (0x1<<22)
#define TSDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN_SIZE 22
#define TSDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN (0x1<<23)
#define TSDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN_SIZE 23
#define TSDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN (0x1<<24)
#define TSDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN_SIZE 24
#define TSDM_ENABLE_OUT1_REG_PB_OUT_EN (0x1<<25)
#define TSDM_ENABLE_OUT1_REG_PB_OUT_EN_SIZE 25
#define TSDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN (0x1<<26)
#define TSDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN_SIZE 26
#define TSDM_REG_ENABLE_OUT2 0x42244UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define TSDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN (0x1<<0)
#define TSDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN_SIZE 0
#define TSDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN (0x1<<1)
#define TSDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN_SIZE 1
#define TSDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN (0x1<<2)
#define TSDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN_SIZE 2
#define TSDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN (0x1<<3)
#define TSDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN_SIZE 3
#define TSDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN (0x1<<4)
#define TSDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN_SIZE 4
#define TSDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN (0x1<<5)
#define TSDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN_SIZE 5
#define TSDM_REG_NUM_OF_Q0_CMD 0x42248UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 0
#define TSDM_REG_NUM_OF_Q1_CMD 0x4224cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 1
#define TSDM_REG_NUM_OF_Q3_CMD 0x42250UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 3
#define TSDM_REG_NUM_OF_Q4_CMD 0x42254UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 4
#define TSDM_REG_NUM_OF_Q5_CMD 0x42258UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 5
#define TSDM_REG_NUM_OF_Q6_CMD 0x4225cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 6
#define TSDM_REG_NUM_OF_Q7_CMD 0x42260UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 7
#define TSDM_REG_NUM_OF_Q8_CMD 0x42264UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 8
#define TSDM_REG_NUM_OF_Q9_CMD 0x42268UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 9
#define TSDM_REG_NUM_OF_Q10_CMD 0x4226cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 10
#define TSDM_REG_NUM_OF_Q11_CMD 0x42270UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 11
#define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274UL //ACCESS:ST DataWidth:0x20 Description: The number of packet end messages received from the parser
#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278UL //ACCESS:ST DataWidth:0x20 Description: The number of requests received from the pxp async if
#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227cUL //ACCESS:ST DataWidth:0x20 Description: The number of ACK after placement messages received
#define TSDM_REG_STATISTICS_TM 0x42280UL //ACCESS:RW DataWidth:0x5 Description: TM bits for statistics sram
#define TSDM_REG_DBG_SELECT 0x42284UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from TSDM to the DBG block) - for selecting a line to output to the DBG block
#define TSDM_REG_DBG_BYTE_ENABLE 0x42288UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from TSDM to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define TSDM_REG_DBG_SHIFT 0x4228cUL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from TSDM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define TSDM_REG_TSDM_INT_STS_0 0x42290UL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define TSDM_TSDM_INT_STS_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define TSDM_TSDM_INT_STS_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define TSDM_TSDM_INT_STS_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define TSDM_TSDM_INT_STS_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define TSDM_TSDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define TSDM_TSDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define TSDM_TSDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define TSDM_TSDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define TSDM_TSDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define TSDM_TSDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define TSDM_TSDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define TSDM_TSDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define TSDM_TSDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define TSDM_TSDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define TSDM_TSDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define TSDM_TSDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define TSDM_TSDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define TSDM_TSDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define TSDM_TSDM_INT_STS_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define TSDM_TSDM_INT_STS_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define TSDM_TSDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define TSDM_TSDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define TSDM_TSDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define TSDM_TSDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define TSDM_TSDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define TSDM_TSDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define TSDM_TSDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define TSDM_TSDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define TSDM_TSDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define TSDM_TSDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define TSDM_TSDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define TSDM_TSDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define TSDM_TSDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define TSDM_TSDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define TSDM_TSDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define TSDM_TSDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define TSDM_TSDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define TSDM_TSDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define TSDM_REG_TSDM_INT_STS_CLR_0 0x42294UL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define TSDM_TSDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define TSDM_TSDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define TSDM_TSDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define TSDM_TSDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define TSDM_TSDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define TSDM_TSDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define TSDM_TSDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define TSDM_TSDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define TSDM_TSDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define TSDM_TSDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define TSDM_TSDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define TSDM_TSDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define TSDM_TSDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define TSDM_REG_TSDM_INT_STS_WR_0 0x42298UL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define TSDM_TSDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define TSDM_TSDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define TSDM_TSDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define TSDM_TSDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define TSDM_TSDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define TSDM_TSDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define TSDM_TSDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define TSDM_TSDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define TSDM_TSDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define TSDM_TSDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define TSDM_TSDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define TSDM_TSDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define TSDM_TSDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define TSDM_TSDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define TSDM_TSDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define TSDM_TSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define TSDM_TSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define TSDM_TSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define TSDM_TSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define TSDM_TSDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define TSDM_TSDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define TSDM_REG_TSDM_INT_MASK_0 0x4229cUL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define TSDM_TSDM_INT_MASK_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define TSDM_TSDM_INT_MASK_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define TSDM_TSDM_INT_MASK_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define TSDM_TSDM_INT_MASK_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define TSDM_TSDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define TSDM_TSDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define TSDM_TSDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define TSDM_TSDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define TSDM_TSDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define TSDM_TSDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define TSDM_TSDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define TSDM_TSDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define TSDM_TSDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define TSDM_TSDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define TSDM_TSDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define TSDM_TSDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define TSDM_TSDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define TSDM_TSDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define TSDM_TSDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define TSDM_TSDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define TSDM_TSDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define TSDM_TSDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define TSDM_TSDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define TSDM_TSDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define TSDM_TSDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define TSDM_TSDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define TSDM_TSDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define TSDM_TSDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define TSDM_TSDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define TSDM_TSDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define TSDM_TSDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define TSDM_TSDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define TSDM_TSDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define TSDM_TSDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define TSDM_TSDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define TSDM_TSDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define TSDM_TSDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define TSDM_TSDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define TSDM_REG_TSDM_INT_STS_1 0x422a0UL //ACCESS:R DataWidth:0xe Description: Interrupt register #1 read
#define TSDM_TSDM_INT_STS_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define TSDM_TSDM_INT_STS_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define TSDM_TSDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define TSDM_TSDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define TSDM_TSDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define TSDM_TSDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define TSDM_TSDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define TSDM_TSDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define TSDM_TSDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define TSDM_TSDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define TSDM_TSDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define TSDM_TSDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define TSDM_TSDM_INT_STS_1_REG_CM_DELAY_ERROR (0x1<<6)
#define TSDM_TSDM_INT_STS_1_REG_CM_DELAY_ERROR_SIZE 6
#define TSDM_TSDM_INT_STS_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define TSDM_TSDM_INT_STS_1_REG_PXP_DELAY_ERROR_SIZE 7
#define TSDM_TSDM_INT_STS_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define TSDM_TSDM_INT_STS_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define TSDM_TSDM_INT_STS_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define TSDM_TSDM_INT_STS_1_REG_TIMER_PEND_ERROR_SIZE 9
#define TSDM_TSDM_INT_STS_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define TSDM_TSDM_INT_STS_1_REG_DORQ_DPM_ERROR_SIZE 10
#define TSDM_TSDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define TSDM_TSDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define TSDM_TSDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define TSDM_TSDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define TSDM_TSDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define TSDM_TSDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define TSDM_REG_TSDM_INT_STS_CLR_1 0x422a4UL //ACCESS:RC DataWidth:0xe Description: Interrupt register #1 read clear
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define TSDM_TSDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR (0x1<<6)
#define TSDM_TSDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR_SIZE 6
#define TSDM_TSDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define TSDM_TSDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR_SIZE 7
#define TSDM_TSDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define TSDM_TSDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define TSDM_TSDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define TSDM_TSDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR_SIZE 9
#define TSDM_TSDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define TSDM_TSDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR_SIZE 10
#define TSDM_TSDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define TSDM_TSDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define TSDM_TSDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define TSDM_TSDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define TSDM_TSDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define TSDM_TSDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define TSDM_REG_TSDM_INT_STS_WR_1 0x422a8UL //ACCESS:WR DataWidth:0xe Description: Interrupt register #1 bit set or clear
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define TSDM_TSDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define TSDM_TSDM_INT_STS_WR_1_REG_CM_DELAY_ERROR (0x1<<6)
#define TSDM_TSDM_INT_STS_WR_1_REG_CM_DELAY_ERROR_SIZE 6
#define TSDM_TSDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define TSDM_TSDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR_SIZE 7
#define TSDM_TSDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define TSDM_TSDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define TSDM_TSDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define TSDM_TSDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR_SIZE 9
#define TSDM_TSDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define TSDM_TSDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR_SIZE 10
#define TSDM_TSDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define TSDM_TSDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define TSDM_TSDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define TSDM_TSDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define TSDM_TSDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define TSDM_TSDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define TSDM_REG_TSDM_INT_MASK_1 0x422acUL //ACCESS:RW DataWidth:0xe Description: Interrupt mask register #1 read/write
#define TSDM_TSDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define TSDM_TSDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define TSDM_TSDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define TSDM_TSDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define TSDM_TSDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define TSDM_TSDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define TSDM_TSDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define TSDM_TSDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define TSDM_TSDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define TSDM_TSDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define TSDM_TSDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define TSDM_TSDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define TSDM_TSDM_INT_MASK_1_REG_CM_DELAY_ERROR (0x1<<6)
#define TSDM_TSDM_INT_MASK_1_REG_CM_DELAY_ERROR_SIZE 6
#define TSDM_TSDM_INT_MASK_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define TSDM_TSDM_INT_MASK_1_REG_PXP_DELAY_ERROR_SIZE 7
#define TSDM_TSDM_INT_MASK_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define TSDM_TSDM_INT_MASK_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define TSDM_TSDM_INT_MASK_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define TSDM_TSDM_INT_MASK_1_REG_TIMER_PEND_ERROR_SIZE 9
#define TSDM_TSDM_INT_MASK_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define TSDM_TSDM_INT_MASK_1_REG_DORQ_DPM_ERROR_SIZE 10
#define TSDM_TSDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define TSDM_TSDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define TSDM_TSDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define TSDM_TSDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define TSDM_TSDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define TSDM_TSDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define TSDM_REG_TSDM_PRTY_STS 0x422b0UL //ACCESS:R DataWidth:0xb Description: Parity register #0 read
#define TSDM_TSDM_PRTY_STS_REG_PARITY (0x1<<0)
#define TSDM_TSDM_PRTY_STS_REG_PARITY_SIZE 0
#define TSDM_TSDM_PRTY_STS_REG_TIMERS (0x1<<1)
#define TSDM_TSDM_PRTY_STS_REG_TIMERS_SIZE 1
#define TSDM_TSDM_PRTY_STS_REG_INP_QUEUE (0x1<<2)
#define TSDM_TSDM_PRTY_STS_REG_INP_QUEUE_SIZE 2
#define TSDM_TSDM_PRTY_STS_REG_ASYNC_RD_DATA (0x1<<3)
#define TSDM_TSDM_PRTY_STS_REG_ASYNC_RD_DATA_SIZE 3
#define TSDM_TSDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define TSDM_TSDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define TSDM_TSDM_PRTY_STS_REG_BRB1_DP_RD_DATA (0x1<<5)
#define TSDM_TSDM_PRTY_STS_REG_BRB1_DP_RD_DATA_SIZE 5
#define TSDM_TSDM_PRTY_STS_REG_PB_RD_DATA (0x1<<6)
#define TSDM_TSDM_PRTY_STS_REG_PB_RD_DATA_SIZE 6
#define TSDM_TSDM_PRTY_STS_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define TSDM_TSDM_PRTY_STS_REG_PXP_CTRL_RD_DATA_SIZE 7
#define TSDM_TSDM_PRTY_STS_REG_INT_RAM_RD_DATA (0x1<<8)
#define TSDM_TSDM_PRTY_STS_REG_INT_RAM_RD_DATA_SIZE 8
#define TSDM_TSDM_PRTY_STS_REG_STAT_RD_DATA (0x1<<9)
#define TSDM_TSDM_PRTY_STS_REG_STAT_RD_DATA_SIZE 9
#define TSDM_TSDM_PRTY_STS_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define TSDM_TSDM_PRTY_STS_REG_CM_QUEUE_RD_DATA_SIZE 10
#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4UL //ACCESS:RC DataWidth:0xb Description: Parity register #0 read clear
#define TSDM_TSDM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define TSDM_TSDM_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define TSDM_TSDM_PRTY_STS_CLR_REG_TIMERS (0x1<<1)
#define TSDM_TSDM_PRTY_STS_CLR_REG_TIMERS_SIZE 1
#define TSDM_TSDM_PRTY_STS_CLR_REG_INP_QUEUE (0x1<<2)
#define TSDM_TSDM_PRTY_STS_CLR_REG_INP_QUEUE_SIZE 2
#define TSDM_TSDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA (0x1<<3)
#define TSDM_TSDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA_SIZE 3
#define TSDM_TSDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define TSDM_TSDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define TSDM_TSDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA (0x1<<5)
#define TSDM_TSDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA_SIZE 5
#define TSDM_TSDM_PRTY_STS_CLR_REG_PB_RD_DATA (0x1<<6)
#define TSDM_TSDM_PRTY_STS_CLR_REG_PB_RD_DATA_SIZE 6
#define TSDM_TSDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define TSDM_TSDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA_SIZE 7
#define TSDM_TSDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA (0x1<<8)
#define TSDM_TSDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA_SIZE 8
#define TSDM_TSDM_PRTY_STS_CLR_REG_STAT_RD_DATA (0x1<<9)
#define TSDM_TSDM_PRTY_STS_CLR_REG_STAT_RD_DATA_SIZE 9
#define TSDM_TSDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define TSDM_TSDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA_SIZE 10
#define TSDM_REG_TSDM_PRTY_STS_WR 0x422b8UL //ACCESS:WR DataWidth:0xb Description: Parity register #0 bit set or clear
#define TSDM_TSDM_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define TSDM_TSDM_PRTY_STS_WR_REG_PARITY_SIZE 0
#define TSDM_TSDM_PRTY_STS_WR_REG_TIMERS (0x1<<1)
#define TSDM_TSDM_PRTY_STS_WR_REG_TIMERS_SIZE 1
#define TSDM_TSDM_PRTY_STS_WR_REG_INP_QUEUE (0x1<<2)
#define TSDM_TSDM_PRTY_STS_WR_REG_INP_QUEUE_SIZE 2
#define TSDM_TSDM_PRTY_STS_WR_REG_ASYNC_RD_DATA (0x1<<3)
#define TSDM_TSDM_PRTY_STS_WR_REG_ASYNC_RD_DATA_SIZE 3
#define TSDM_TSDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define TSDM_TSDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define TSDM_TSDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA (0x1<<5)
#define TSDM_TSDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA_SIZE 5
#define TSDM_TSDM_PRTY_STS_WR_REG_PB_RD_DATA (0x1<<6)
#define TSDM_TSDM_PRTY_STS_WR_REG_PB_RD_DATA_SIZE 6
#define TSDM_TSDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define TSDM_TSDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA_SIZE 7
#define TSDM_TSDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA (0x1<<8)
#define TSDM_TSDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA_SIZE 8
#define TSDM_TSDM_PRTY_STS_WR_REG_STAT_RD_DATA (0x1<<9)
#define TSDM_TSDM_PRTY_STS_WR_REG_STAT_RD_DATA_SIZE 9
#define TSDM_TSDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define TSDM_TSDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA_SIZE 10
#define TSDM_REG_TSDM_PRTY_MASK 0x422bcUL //ACCESS:RW DataWidth:0xb Description: Parity mask register #0 read/write
#define TSDM_TSDM_PRTY_MASK_REG_PARITY (0x1<<0)
#define TSDM_TSDM_PRTY_MASK_REG_PARITY_SIZE 0
#define TSDM_TSDM_PRTY_MASK_REG_TIMERS (0x1<<1)
#define TSDM_TSDM_PRTY_MASK_REG_TIMERS_SIZE 1
#define TSDM_TSDM_PRTY_MASK_REG_INP_QUEUE (0x1<<2)
#define TSDM_TSDM_PRTY_MASK_REG_INP_QUEUE_SIZE 2
#define TSDM_TSDM_PRTY_MASK_REG_ASYNC_RD_DATA (0x1<<3)
#define TSDM_TSDM_PRTY_MASK_REG_ASYNC_RD_DATA_SIZE 3
#define TSDM_TSDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define TSDM_TSDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define TSDM_TSDM_PRTY_MASK_REG_BRB1_DP_RD_DATA (0x1<<5)
#define TSDM_TSDM_PRTY_MASK_REG_BRB1_DP_RD_DATA_SIZE 5
#define TSDM_TSDM_PRTY_MASK_REG_PB_RD_DATA (0x1<<6)
#define TSDM_TSDM_PRTY_MASK_REG_PB_RD_DATA_SIZE 6
#define TSDM_TSDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define TSDM_TSDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA_SIZE 7
#define TSDM_TSDM_PRTY_MASK_REG_INT_RAM_RD_DATA (0x1<<8)
#define TSDM_TSDM_PRTY_MASK_REG_INT_RAM_RD_DATA_SIZE 8
#define TSDM_TSDM_PRTY_MASK_REG_STAT_RD_DATA (0x1<<9)
#define TSDM_TSDM_PRTY_MASK_REG_STAT_RD_DATA_SIZE 9
#define TSDM_TSDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define TSDM_TSDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA_SIZE 10
#define TSDM_REG_CMP_COUNTER_MAX4 0x422c0UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #4
#define TSDM_REG_CMP_COUNTER_MAX5 0x422c4UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #5
#define TSDM_REG_CMP_COUNTER_MAX6 0x422c8UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #6
#define TSDM_REG_CMP_COUNTER_MAX7 0x422ccUL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #7
#define TSDM_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD 0x422d4UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define TSDM_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD 0x422d8UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define TSDM_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD 0x422dcUL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define TSDM_REG_CPU_MBIST_MEMCTRL_0_STATUS_0 0x422e0UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits.
#define TSDM_REG_CPU_MBIST_MEMCTRL_1_STATUS_0 0x422e4UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits.
#define TSDM_REG_CPU_MBIST_MEMCTRL_2_STATUS_0 0x422e8UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits.
#define TSDM_REG_CM_QUEUE_TM 0x42640UL //ACCESS:RW DataWidth:0x8 Description: TM bits for cm queue
#define TSDM_REG_INP_QUEUE_TM 0x42644UL //ACCESS:RW DataWidth:0x8 Description: TM bits for inp queue
#define TSDM_REG_ECO_RESERVED 0x42648UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO
#define TSDM_REG_FIFOS_TM 0x4264cUL //ACCESS:RW DataWidth:0x4 Description: TM bits fifos: BRB1_CTRL[1:0]; Reserved[3:2];Reserved[5:4];PXP_CTRL[7:6]
#define TSDM_REG_TIMERS_TM 0x42650UL //ACCESS:RW DataWidth:0x2 Description: TM bits for timers sram
#define TSDM_REG_AGGREG_INTERRUPT_LSB 0x42400UL //ACCESS:R DataWidth:0x20 Description: lsb register of aggregated interrupt in sdm_cm block
#define TSDM_REG_AGGREG_INTERRUPT_LSB_SIZE 1
#define TSDM_REG_AGGREG_INTERRUPT_MSB 0x42404UL //ACCESS:R DataWidth:0x20 Description: msb register of aggregated interrupt in sdm_cm block
#define TSDM_REG_AGGREG_INTERRUPT_MSB_SIZE 1
#define TSDM_REG_ASYNC_HOST_EMPTY 0x42408UL //ACCESS:R DataWidth:0x1 Description: async fifo empty in sdm_async block
#define TSDM_REG_ASYNC_HOST_EMPTY_SIZE 1
#define TSDM_REG_ASYNC_HOST_FULL 0x4240cUL //ACCESS:R DataWidth:0x1 Description: async fifo full in sdm_async block
#define TSDM_REG_ASYNC_HOST_FULL_SIZE 1
#define TSDM_REG_CFC_LOAD_PEND_EMPTY 0x42410UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo empty in sdm_dma_dst block
#define TSDM_REG_CFC_LOAD_PEND_EMPTY_SIZE 1
#define TSDM_REG_CFC_LOAD_PEND_FULL 0x42414UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo full in sdm_cfc block
#define TSDM_REG_CFC_LOAD_PEND_FULL_SIZE 1
#define TSDM_REG_CFC_LOAD_RSP_EMPTY 0x42418UL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo empty in sdm_dma_dst block
#define TSDM_REG_CFC_LOAD_RSP_EMPTY_SIZE 1
#define TSDM_REG_CFC_LOAD_RSP_FULL 0x4241cUL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo full in sdm_cfcblock
#define TSDM_REG_CFC_LOAD_RSP_FULL_SIZE 1
#define TSDM_REG_CM_DELAY_EMPTY 0x42420UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo empty in sdm_dma_dst block
#define TSDM_REG_CM_DELAY_EMPTY_SIZE 1
#define TSDM_REG_CM_DELAY_FULL 0x42424UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo full in sdm_cm block
#define TSDM_REG_CM_DELAY_FULL_SIZE 1
#define TSDM_REG_CM_QUEUE_EMPTY 0x42428UL //ACCESS:R DataWidth:0x1 Description: cm queue fifo empty in sdm_dma_dst block
#define TSDM_REG_CM_QUEUE_EMPTY_SIZE 1
#define TSDM_REG_CM_QUEUE_FULL 0x4242cUL //ACCESS:R DataWidth:0x1 Description: cm queue fifo full in sdm_cm block
#define TSDM_REG_CM_QUEUE_FULL_SIZE 1
#define TSDM_REG_DELAY_FIFO_EMPTY 0x42430UL //ACCESS:R DataWidth:0x1 Description: delay FIFO empty in sdm_inp block
#define TSDM_REG_DELAY_FIFO_EMPTY_SIZE 1
#define TSDM_REG_DELAY_FIFO_FULL 0x42434UL //ACCESS:R DataWidth:0x1 Description: delay FIFO full in sdm_inp block
#define TSDM_REG_DELAY_FIFO_FULL_SIZE 1
#define TSDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY 0x42438UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo empty in sdm_dma_dst block
#define TSDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY_SIZE 1
#define TSDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL 0x4243cUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo full in sdm_dma_dst block
#define TSDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL_SIZE 1
#define TSDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY 0x42440UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo empty in sdm_dma_dst block
#define TSDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY_SIZE 1
#define TSDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL 0x42444UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo full in sdm_dma_dst block
#define TSDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL_SIZE 1
#define TSDM_REG_DST_INT_RAM_IF_FULL 0x42448UL //ACCESS:R DataWidth:0x1 Description: int_ram if full in sdm_dma_dst block
#define TSDM_REG_DST_INT_RAM_IF_FULL_SIZE 1
#define TSDM_REG_DST_INT_RAM_WAIT_EMPTY 0x4244cUL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo empty in sdm_dma_dst block
#define TSDM_REG_DST_INT_RAM_WAIT_EMPTY_SIZE 1
#define TSDM_REG_DST_INT_RAM_WAIT_FULL 0x42450UL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo full in sdm_dma_dst block
#define TSDM_REG_DST_INT_RAM_WAIT_FULL_SIZE 1
#define TSDM_REG_DST_NONE_PEND_EMPTY 0x42454UL //ACCESS:R DataWidth:0x1 Description: none pending fifo empty in sdm_dma_dst block
#define TSDM_REG_DST_NONE_PEND_EMPTY_SIZE 1
#define TSDM_REG_DST_NONE_PEND_FULL 0x42458UL //ACCESS:R DataWidth:0x1 Description: none pending fifo full in sdm_dma_dst block
#define TSDM_REG_DST_NONE_PEND_FULL_SIZE 1
#define TSDM_REG_DST_PAS_BUF_IF_FULL 0x4245cUL //ACCESS:R DataWidth:0x1 Description: pas_buf if full in sdm_dma_dst block
#define TSDM_REG_DST_PAS_BUF_IF_FULL_SIZE 1
#define TSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0x42460UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo empty in sdm_dma_dst block
#define TSDM_REG_DST_PAS_BUF_WAIT_EMPTY_SIZE 1
#define TSDM_REG_DST_PAS_BUF_WAIT_FULL 0x42464UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo full in sdm_dma_dst block
#define TSDM_REG_DST_PAS_BUF_WAIT_FULL_SIZE 1
#define TSDM_REG_DST_PB_IF_FULL 0x42468UL //ACCESS:R DataWidth:0x1 Description: pb if full in sdm_dma_dst block
#define TSDM_REG_DST_PB_IF_FULL_SIZE 1
#define TSDM_REG_DST_PB_IMMED_EMPTY 0x4246cUL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo empty in sdm_dma_dst block
#define TSDM_REG_DST_PB_IMMED_EMPTY_SIZE 1
#define TSDM_REG_DST_PB_IMMED_FULL 0x42470UL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo full in sdm_dma_dst block
#define TSDM_REG_DST_PB_IMMED_FULL_SIZE 1
#define TSDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY 0x42474UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo empty in sdm_dma_dst block
#define TSDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY_SIZE 1
#define TSDM_REG_DST_PXP_CTRL_DST_PEND_FULL 0x42478UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo full in sdm_dma_dst block
#define TSDM_REG_DST_PXP_CTRL_DST_PEND_FULL_SIZE 1
#define TSDM_REG_DST_PXP_CTRL_IF_FULL 0x4247cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl if full in sdm_dma_dst block
#define TSDM_REG_DST_PXP_CTRL_IF_FULL_SIZE 1
#define TSDM_REG_DST_PXP_CTRL_IMMED_EMPTY 0x42480UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo empty in sdm_dma_dst block
#define TSDM_REG_DST_PXP_CTRL_IMMED_EMPTY_SIZE 1
#define TSDM_REG_DST_PXP_CTRL_IMMED_FULL 0x42484UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo full in sdm_dma_dst block
#define TSDM_REG_DST_PXP_CTRL_IMMED_FULL_SIZE 1
#define TSDM_REG_DST_PXP_CTRL_LINK_EMPTY 0x42488UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list empty in sdm_dma_dst block
#define TSDM_REG_DST_PXP_CTRL_LINK_EMPTY_SIZE 1
#define TSDM_REG_DST_PXP_CTRL_LINK_FULL 0x4248cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list full in sdm_dma_dst block
#define TSDM_REG_DST_PXP_CTRL_LINK_FULL_SIZE 1
#define TSDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY 0x42490UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo empty in sdm_dma_dst block
#define TSDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY_SIZE 1
#define TSDM_REG_DST_PXP_CTRL_SRC_PEND_FULL 0x42494UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo full in sdm_dma_dst block
#define TSDM_REG_DST_PXP_CTRL_SRC_PEND_FULL_SIZE 1
#define TSDM_REG_DST_PXP_DP_DST_PEND_EMPTY 0x42498UL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo empty in sdm_dma_dst block
#define TSDM_REG_DST_PXP_DP_DST_PEND_EMPTY_SIZE 1
#define TSDM_REG_DST_PXP_DP_DST_PEND_FULL 0x4249cUL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo full in sdm_dma_dst block
#define TSDM_REG_DST_PXP_DP_DST_PEND_FULL_SIZE 1
#define TSDM_REG_DST_PXP_DP_IF_FULL 0x424a0UL //ACCESS:R DataWidth:0x1 Description: pxp_dp if full in sdm_dma_dst block
#define TSDM_REG_DST_PXP_DP_IF_FULL_SIZE 1
#define TSDM_REG_DST_PXP_DP_LINK_EMPTY 0x424a4UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list empty in sdm_dma_dst block
#define TSDM_REG_DST_PXP_DP_LINK_EMPTY_SIZE 1
#define TSDM_REG_DST_PXP_DP_LINK_FULL 0x424a8UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list full in sdm_dma_dst block
#define TSDM_REG_DST_PXP_DP_LINK_FULL_SIZE 1
#define TSDM_REG_INIT_CREDIT_CFC_ACDEC 0x424acUL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC activity counters interface without receiving any ACK
#define TSDM_REG_INIT_CREDIT_CFC_ACDEC_SIZE 1
#define TSDM_REG_INIT_CREDIT_CFC_ACINC 0x424b0UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC activity counters interface without receiving any ACK.
#define TSDM_REG_INIT_CREDIT_CFC_ACINC_SIZE 1
#define TSDM_REG_INIT_CREDIT_CFC_LOAD 0x424b4UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC load interface without receiving any ACK.
#define TSDM_REG_INIT_CREDIT_CFC_LOAD_SIZE 1
#define TSDM_REG_INIT_CREDIT_CM 0x424b8UL //ACCESS:RW DataWidth:0x4 Description: The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block
#define TSDM_REG_INIT_CREDIT_CM_SIZE 1
#define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bcUL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the pxp control interface without receiving any ACK.
#define TSDM_REG_INIT_CREDIT_PXP_CTRL_SIZE 1
#define TSDM_REG_INT_RAM_RR_REQ 0x424c0UL //ACCESS:R DataWidth:0x6 Description: round robin for int_ram arbiter: b0-pas_buf; b1-int_ram;b2-pxp_dp;b3-pxp_ctrl;b4-brb1_ctrl;b5-brb1_dp;
#define TSDM_REG_INT_RAM_RR_REQ_SIZE 1
#define TSDM_REG_OPERATION_GEN 0x424c4UL //ACCESS:W DataWidth:0x11 Description: Generate an operation after completion; bit-16 is AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and bits 4:0 are the T124Param[4:0]
#define TSDM_REG_OPERATION_GEN_SIZE 1
#define TSDM_REG_PB_FULL 0x424c8UL //ACCESS:R DataWidth:0x1 Description: UPB IF full in sdm_inp block
#define TSDM_REG_PB_FULL_SIZE 1
#define TSDM_REG_PBF_FULL 0x424ccUL //ACCESS:R DataWidth:0x1 Description: PBF if full in sdm_inp block
#define TSDM_REG_PBF_FULL_SIZE 1
#define TSDM_REG_PXP_DELAY_EMPTY 0x424d0UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo empty in sdm_dma_dst block
#define TSDM_REG_PXP_DELAY_EMPTY_SIZE 1
#define TSDM_REG_PXP_DELAY_FULL 0x424d4UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo full in sdm_cm block
#define TSDM_REG_PXP_DELAY_FULL_SIZE 1
#define TSDM_REG_QM_FULL 0x424d8UL //ACCESS:R DataWidth:0x1 Description: QM IF full in sdm_inp block
#define TSDM_REG_QM_FULL_SIZE 1
#define TSDM_REG_QUEUE_EMPTY 0x424dcUL //ACCESS:R DataWidth:0xc Description: Input queue fifo empty in sdm_inp block
#define TSDM_REG_QUEUE_EMPTY_SIZE 1
#define TSDM_REG_QUEUE_FULL 0x424e0UL //ACCESS:R DataWidth:0xc Description: Input queue fifo full in sdm_inp block
#define TSDM_REG_QUEUE_FULL_SIZE 1
#define TSDM_REG_RR_CNT_COUNTERS_STATUS 0x424e4UL //ACCESS:R DataWidth:0x15 Description: round robin for all completion counters
#define TSDM_REG_RR_CNT_COUNTERS_STATUS_SIZE 1
#define TSDM_REG_RR_COMPLETE_REQ 0x424e8UL //ACCESS:R DataWidth:0x7 Description: round robin for all completion requests in sdm_cm block: b0-async b1-nop;b2-pxp_int; b3-timers;b4-dma;b5-grc;b6-rbc
#define TSDM_REG_RR_COMPLETE_REQ_SIZE 1
#define TSDM_REG_RR_PTR_REQ 0x424ecUL //ACCESS:R DataWidth:0x7 Description: round robin for cm pointer: b0-async; b1-dma_dp; b2 - dma_ctrl; b3-cfc; b4-nop; b5-timers; b6-pxp_int
#define TSDM_REG_RR_PTR_REQ_SIZE 1
#define TSDM_REG_RSP_BRB1_CTRL_IF_FULL 0x424f0UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl if is full in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_CTRL_IF_FULL_SIZE 1
#define TSDM_REG_RSP_BRB1_CTRL_PEND_EMPTY 0x424f4UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo empty in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_CTRL_PEND_EMPTY_SIZE 1
#define TSDM_REG_RSP_BRB1_CTRL_PEND_FULL 0x424f8UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo full in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_CTRL_PEND_FULL_SIZE 1
#define TSDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY 0x424fcUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo empty in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY_SIZE 1
#define TSDM_REG_RSP_BRB1_CTRL_RDATA_FULL 0x42500UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo full in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_CTRL_RDATA_FULL_SIZE 1
#define TSDM_REG_RSP_BRB1_DP_DST_EMPTY 0x42504UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo empty in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_DP_DST_EMPTY_SIZE 1
#define TSDM_REG_RSP_BRB1_DP_DST_FULL 0x42508UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo full in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_DP_DST_FULL_SIZE 1
#define TSDM_REG_RSP_BRB1_DP_IF_FULL 0x4250cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp if is full in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_DP_IF_FULL_SIZE 1
#define TSDM_REG_RSP_BRB1_DP_PEND_EMPTY 0x42510UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo empty in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_DP_PEND_EMPTY_SIZE 1
#define TSDM_REG_RSP_BRB1_DP_PEND_FULL 0x42514UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo full in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_DP_PEND_FULL_SIZE 1
#define TSDM_REG_RSP_BRB1_DP_RDATA_EMPTY 0x42518UL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo empty in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_DP_RDATA_EMPTY_SIZE 1
#define TSDM_REG_RSP_BRB1_DP_RDATA_FULL 0x4251cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo full in sdm_dma_rsp block
#define TSDM_REG_RSP_BRB1_DP_RDATA_FULL_SIZE 1
#define TSDM_REG_RSP_INT_RAM_PEND_EMPTY 0x42520UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo empty in sdm_dma_rsp block
#define TSDM_REG_RSP_INT_RAM_PEND_EMPTY_SIZE 1
#define TSDM_REG_RSP_INT_RAM_PEND_FULL 0x42524UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo full in sdm_dma_rsp block
#define TSDM_REG_RSP_INT_RAM_PEND_FULL_SIZE 1
#define TSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0x42528UL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo empty in sdm_dma_rsp block
#define TSDM_REG_RSP_INT_RAM_RDATA_EMPTY_SIZE 1
#define TSDM_REG_RSP_INT_RAM_RDATA_FULL 0x4252cUL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo full in sdm_dma_rsp block
#define TSDM_REG_RSP_INT_RAM_RDATA_FULL_SIZE 1
#define TSDM_REG_RSP_PB_IF_FULL 0x42530UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
#define TSDM_REG_RSP_PB_IF_FULL_SIZE 1
#define TSDM_REG_RSP_PB_PEND_EMPTY 0x42534UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo empty in sdm_dma_rsp block
#define TSDM_REG_RSP_PB_PEND_EMPTY_SIZE 1
#define TSDM_REG_RSP_PB_PEND_FULL 0x42538UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo full in sdm_dma_rsp block
#define TSDM_REG_RSP_PB_PEND_FULL_SIZE 1
#define TSDM_REG_RSP_PB_RDATA_EMPTY 0x4253cUL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo empty in sdm_dma_rsp block
#define TSDM_REG_RSP_PB_RDATA_EMPTY_SIZE 1
#define TSDM_REG_RSP_PB_RDATA_FULL 0x42540UL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo full in sdm_dma_rsp block
#define TSDM_REG_RSP_PB_RDATA_FULL_SIZE 1
#define TSDM_REG_RSP_PXP_CTRL_IF_FULL 0x42544UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
#define TSDM_REG_RSP_PXP_CTRL_IF_FULL_SIZE 1
#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo empty in sdm_dma_rsp block
#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
#define TSDM_REG_RSP_PXP_CTRL_RDATA_FULL 0x4254cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo full in sdm_dma_rsp block
#define TSDM_REG_RSP_PXP_CTRL_RDATA_FULL_SIZE 1
#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550UL //ACCESS:R DataWidth:0x1 Description: parser fifo empty in sdm_sync block
#define TSDM_REG_SYNC_PARSER_EMPTY_SIZE 1
#define TSDM_REG_SYNC_PARSER_FULL 0x42554UL //ACCESS:R DataWidth:0x1 Description: parser fifo full in sdm_sync block
#define TSDM_REG_SYNC_PARSER_FULL_SIZE 1
#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558UL //ACCESS:R DataWidth:0x1 Description: parser serial fifo empty in sdm_sync block
#define TSDM_REG_SYNC_SYNC_EMPTY_SIZE 1
#define TSDM_REG_SYNC_SYNC_FULL 0x4255cUL //ACCESS:R DataWidth:0x1 Description: parser serial fifo full in sdm_sync block
#define TSDM_REG_SYNC_SYNC_FULL_SIZE 1
#define TSDM_REG_TIMERS_ADDR_EMPTY 0x42560UL //ACCESS:R DataWidth:0x1 Description: address FIFO empty in sdm_timers block
#define TSDM_REG_TIMERS_ADDR_EMPTY_SIZE 1
#define TSDM_REG_TIMERS_ADDR_FULL 0x42564UL //ACCESS:R DataWidth:0x1 Description: address FIFO full in sdm_timers block
#define TSDM_REG_TIMERS_ADDR_FULL_SIZE 1
#define TSDM_REG_TIMERS_PEND_EMPTY 0x42568UL //ACCESS:R DataWidth:0x1 Description: pending FIFO empty in sdm_timers block
#define TSDM_REG_TIMERS_PEND_EMPTY_SIZE 1
#define TSDM_REG_TIMERS_PEND_FULL 0x4256cUL //ACCESS:R DataWidth:0x1 Description: pending FIFO full in sdm_timers block
#define TSDM_REG_TIMERS_PEND_FULL_SIZE 1
#define TSDM_REG_TIMERS 0x42580UL //ACCESS:WB DataWidth:0x34 Description: Debug only. Timers memory.
#define TSDM_REG_TIMERS_SIZE 28
#define TSDM_REG_STATISTICS 0x42800UL //ACCESS:RW DataWidth:0x20 Description: Statistics memory. Each read from RBC resets the corresponding statistic counter
#define TSDM_REG_STATISTICS_SIZE 256
#define TSDM_REG_CM_QUEUE 0x43000UL //ACCESS:WB DataWidth:0x40 Description: Debug only. CM queue memory.
#define TSDM_REG_CM_QUEUE_SIZE 292
#define TSDM_REG_INP_QUEUE 0x43800UL //ACCESS:WB DataWidth:0x40 Description: Debug only. Input queue memory.
#define TSDM_REG_INP_QUEUE_SIZE 352
#define TSDM_REG_TSDM_UNUSED_EMPTY_0 0x422d0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSDM_REG_TSDM_UNUSED_EMPTY_0_SIZE 1
#define TSDM_REG_TSDM_UNUSED_EMPTY_1 0x422ecUL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSDM_REG_TSDM_UNUSED_EMPTY_1_SIZE 69
#define TSDM_REG_TSDM_UNUSED_EMPTY_2 0x42570UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSDM_REG_TSDM_UNUSED_EMPTY_2_SIZE 4
#define TSDM_REG_TSDM_UNUSED_EMPTY_3 0x42600UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSDM_REG_TSDM_UNUSED_EMPTY_3_SIZE 16
#define TSDM_REG_TSDM_UNUSED_EMPTY_4 0x42654UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSDM_REG_TSDM_UNUSED_EMPTY_4_SIZE 107
#define TSDM_REG_TSDM_UNUSED_EMPTY_5 0x42c00UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSDM_REG_TSDM_UNUSED_EMPTY_5_SIZE 256
#define TSEM_REG_MSG_NUM_FIC0 0x180000UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that entered through FIC0
#define TSEM_REG_MSG_NUM_FIC1 0x180004UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that entered through FIC1
#define TSEM_REG_MSG_NUM_FOC0 0x180008UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC0
#define TSEM_REG_MSG_NUM_FOC1 0x18000cUL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC1
#define TSEM_REG_MSG_NUM_FOC2 0x180010UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC2
#define TSEM_REG_MSG_NUM_FOC3 0x180014UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC3
#define TSEM_REG_THREAD_INTER_CNT_ENABLE 0x180018UL //ACCESS:RW DataWidth:0x1 Description: Enable for start count of counter ~tsem_registers_thread_inter_cnt.thread_inter_cnt
#define TSEM_REG_THREAD_INTER_CNT 0x18001cUL //ACCESS:RW DataWidth:0x10 Description: Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter. This register may be used only when ~tsem_registers_thread_inter_cnt_enable.thread_inter_cnt_enable =1
#define TSEM_REG_ARB_ELEMENT0 0x180020UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 0. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2
#define TSEM_REG_ARB_ELEMENT1 0x180024UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 1. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~tsem_registers_arb_element0.arb_element0
#define TSEM_REG_ARB_ELEMENT2 0x180028UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 2. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~tsem_registers_arb_element0.arb_element0 and ~tsem_registers_arb_element1.arb_element1
#define TSEM_REG_ARB_ELEMENT3 0x18002cUL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 3. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2.Could not be equal to register ~tsem_registers_arb_element0.arb_element0 and ~tsem_registers_arb_element1.arb_element1 and ~tsem_registers_arb_element2.arb_element2
#define TSEM_REG_ARB_ELEMENT4 0x180030UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 4. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~tsem_registers_arb_element0.arb_element0 and ~tsem_registers_arb_element1.arb_element1 and ~tsem_registers_arb_element2.arb_element2 and ~tsem_registers_arb_element3.arb_element3
#define TSEM_REG_ARB_CYCLE_SIZE 0x180034UL //ACCESS:RW DataWidth:0x5 Description: The number of time_slots in the arbitration cycle
#define TSEM_REG_TS_0_AS 0x180038UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 0
#define TSEM_REG_TS_1_AS 0x18003cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 1
#define TSEM_REG_TS_2_AS 0x180040UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 2
#define TSEM_REG_TS_3_AS 0x180044UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 3
#define TSEM_REG_TS_4_AS 0x180048UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 4
#define TSEM_REG_TS_5_AS 0x18004cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 5
#define TSEM_REG_TS_6_AS 0x180050UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 6
#define TSEM_REG_TS_7_AS 0x180054UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 7
#define TSEM_REG_TS_8_AS 0x180058UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 8
#define TSEM_REG_TS_9_AS 0x18005cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 9
#define TSEM_REG_TS_10_AS 0x180060UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 10
#define TSEM_REG_TS_11_AS 0x180064UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 11
#define TSEM_REG_TS_12_AS 0x180068UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 12
#define TSEM_REG_TS_13_AS 0x18006cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 13
#define TSEM_REG_TS_14_AS 0x180070UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 14
#define TSEM_REG_TS_15_AS 0x180074UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 15
#define TSEM_REG_TS_16_AS 0x180078UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 16
#define TSEM_REG_TS_17_AS 0x18007cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 17
#define TSEM_REG_TS_18_AS 0x180080UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 18
#define TSEM_REG_TS_19_AS 0x180084UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 19
#define TSEM_REG_FIC0_MIN_MSG_LINES 0x180088UL //ACCESS:RW DataWidth:0x6 Description: The minimum number of cycles in a message from FIC0 interfaces after which the message can be sent to the passive register_file. It must be always equal to 2; other way it may cause to deadlock in a chip.
#define TSEM_REG_FIC1_MIN_MSG_LINES 0x18008cUL //ACCESS:RW DataWidth:0x6 Description: The minimum number of cycles in a message from FIC1 interfaces after which the message can be sent to the passive register_file. It must be always equal to 2; other way it may cause to deadlock in a chip.
#define TSEM_REG_PASSIVE_ALM_FULL 0x180090UL //ACCESS:RW DataWidth:0x5 Description: The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted
#define TSEM_REG_SYNC_DRA_WR_ALM_FULL 0x180094UL //ACCESS:RW DataWidth:0x5 Description: Almost full for sync dra_wr fifo (data from DRA to STORM)
#define TSEM_REG_SYNC_RAM_WR_ALM_FULL 0x180098UL //ACCESS:RW DataWidth:0x6 Description: Almost full for sync ram_wr fifo (data from EXT_IF to STORM)
#define TSEM_REG_DBG_ALM_FULL 0x18009cUL //ACCESS:RW DataWidth:0x6 Description: Almost full for slow debug fifo
#define TSEM_REG_EXCEPTION_INT 0x1800a0UL //ACCESS:RW DataWidth:0xf Description: The PRAM address for the interrupt in a case the event ID is bigger then the INT table size. This register is always NA; because this feature is removed
#define TSEM_REG_ENABLE_IN 0x1800a4UL //ACCESS:RW DataWidth:0xf Multi Field Register
#define TSEM_ENABLE_IN_REG_FIC0_ENABLE_IN (0x1<<0)
#define TSEM_ENABLE_IN_REG_FIC0_ENABLE_IN_SIZE 0
#define TSEM_ENABLE_IN_REG_FIC1_ENABLE_IN (0x1<<1)
#define TSEM_ENABLE_IN_REG_FIC1_ENABLE_IN_SIZE 1
#define TSEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN (0x1<<2)
#define TSEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN_SIZE 2
#define TSEM_ENABLE_IN_REG_GENERAL_ENABLE_IN (0x1<<3)
#define TSEM_ENABLE_IN_REG_GENERAL_ENABLE_IN_SIZE 3
#define TSEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN (0x1<<4)
#define TSEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN_SIZE 4
#define TSEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN (0x1<<5)
#define TSEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN_SIZE 5
#define TSEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN (0x1<<6)
#define TSEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN_SIZE 6
#define TSEM_ENABLE_IN_REG_RAM0_ENABLE_IN (0x1<<7)
#define TSEM_ENABLE_IN_REG_RAM0_ENABLE_IN_SIZE 7
#define TSEM_ENABLE_IN_REG_RAM1_ENABLE_IN (0x1<<8)
#define TSEM_ENABLE_IN_REG_RAM1_ENABLE_IN_SIZE 8
#define TSEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN (0x1<<9)
#define TSEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN_SIZE 9
#define TSEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN (0x1<<10)
#define TSEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN_SIZE 10
#define TSEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN (0x1<<11)
#define TSEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN_SIZE 11
#define TSEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN (0x1<<12)
#define TSEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN_SIZE 12
#define TSEM_ENABLE_IN_REG_WAITP_ENABLE_IN (0x1<<13)
#define TSEM_ENABLE_IN_REG_WAITP_ENABLE_IN_SIZE 13
#define TSEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN (0x1<<14)
#define TSEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN_SIZE 14
#define TSEM_REG_ENABLE_OUT 0x1800a8UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define TSEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT (0x1<<0)
#define TSEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT_SIZE 0
#define TSEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT (0x1<<1)
#define TSEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT_SIZE 1
#define TSEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT (0x1<<2)
#define TSEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT_SIZE 2
#define TSEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT (0x1<<3)
#define TSEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT_SIZE 3
#define TSEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT (0x1<<4)
#define TSEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT_SIZE 4
#define TSEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT (0x1<<5)
#define TSEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT_SIZE 5
#define TSEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT (0x1<<6)
#define TSEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT_SIZE 6
#define TSEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT (0x1<<7)
#define TSEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT_SIZE 7
#define TSEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT (0x1<<8)
#define TSEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT_SIZE 8
#define TSEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT (0x1<<9)
#define TSEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT_SIZE 9
#define TSEM_REG_STORM0_H_TM 0x1800acUL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm0_h memory instance
#define TSEM_REG_STORM1_H_TM 0x1800b0UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm1_h memory instance
#define TSEM_REG_STORM0_L_TM 0x1800b4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm0_l memory instance
#define TSEM_REG_STORM1_L_TM 0x1800b8UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm1_l memory instance
#define TSEM_REG_CAM_TM 0x1800bcUL //ACCESS:RW DataWidth:0xe Description: TM bits for cam
#define TSEM_REG_RAM0_TM 0x1800c0UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory ram0_0
#define TSEM_REG_INT_TABLE_TM 0x1800c4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory int_table
#define TSEM_REG_CLEAR_WAITP 0x1800c8UL //ACCESS:RW DataWidth:0x1 Description: Write 1 to this register will disable waitp from this storm to other storms
#define TSEM_REG_SLOW_DBG_MODE 0x1800ccUL //ACCESS:RW DataWidth:0x3 Description: debug mode for slow debug bus. Applicable only when ~tsem_registers_slow_dbg_active.slow_dbg_active =1. If mode =0 thread number; pram address and DRA WR data selected; if mode =1 fin command and DRA RD ; if mode =2 pram address and thread number and fin command and released thread from STORM; if mode =3 STORE data to SDM
#define TSEM_REG_SLOW_DBG_ACTIVE 0x1800d0UL //ACCESS:RW DataWidth:0x1 Description: debug mode is active
#define TSEM_REG_DBG_MSG_SRC 0x1800d4UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~tsem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0only FIC-s output to debug bus; 1=both FIC-s and passive buffer.
#define TSEM_REG_DBG_MODE0_CFG 0x1800d8UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~tsem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0 all the message output to debug bus; 1=partial message.
#define TSEM_REG_DBG_MODE0_CFG_CYCLE 0x1800dcUL //ACCESS:RW DataWidth:0x5 Description: Applicable only when ~tsem_registers_dbg_mode0_cfg.dbg_mode0_cfg =1. If =1 the additional cycles to extract to the debug bus.
#define TSEM_REG_DBG_MODE1_CFG 0x1800e0UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~tsem_registers_slow_dbg_mode.slow_dbg_mode =1. If=0 output to debug bus without the data; 1=with the data.
#define TSEM_REG_DBG_EACH_CYLE 0x1800e4UL //ACCESS:RW DataWidth:0x1 Description: If=0 output every cycle full indication or thread status; 1= output only when there is a change.
#define TSEM_REG_DBG_SELECT 0x1800e8UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from USEMI to the DBG block) - for selecting a line to output to the DBG block
#define TSEM_REG_DBG_BYTE_ENABLE 0x1800ecUL //ACCESS:RW DataWidth:0x8 Description: Debug only.For dbgmux usage (debug data that goes from USEM to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define TSEM_REG_DBG_SHIFT 0x1800f0UL //ACCESS:RW DataWidth:0x3 Description: Debug only.For dbgmux usage (debug data that goes from USEM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define TSEM_REG_TSEM_INT_STS_0 0x1800f4UL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define TSEM_TSEM_INT_STS_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define TSEM_TSEM_INT_STS_0_REG_FIC0_LAST_ERROR_SIZE 1
#define TSEM_TSEM_INT_STS_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define TSEM_TSEM_INT_STS_0_REG_FIC1_LAST_ERROR_SIZE 2
#define TSEM_TSEM_INT_STS_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define TSEM_TSEM_INT_STS_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define TSEM_TSEM_INT_STS_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define TSEM_TSEM_INT_STS_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define TSEM_TSEM_INT_STS_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define TSEM_TSEM_INT_STS_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define TSEM_TSEM_INT_STS_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define TSEM_TSEM_INT_STS_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define TSEM_TSEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define TSEM_TSEM_INT_STS_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define TSEM_TSEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define TSEM_TSEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define TSEM_TSEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define TSEM_TSEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define TSEM_TSEM_INT_STS_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define TSEM_TSEM_INT_STS_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define TSEM_TSEM_INT_STS_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define TSEM_TSEM_INT_STS_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define TSEM_TSEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define TSEM_TSEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define TSEM_TSEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define TSEM_TSEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define TSEM_TSEM_INT_STS_0_REG_RD_EMPTY_CAM (0x1<<20)
#define TSEM_TSEM_INT_STS_0_REG_RD_EMPTY_CAM_SIZE 20
#define TSEM_TSEM_INT_STS_0_REG_WR_FULL_CAM (0x1<<21)
#define TSEM_TSEM_INT_STS_0_REG_WR_FULL_CAM_SIZE 21
#define TSEM_TSEM_INT_STS_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define TSEM_TSEM_INT_STS_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define TSEM_TSEM_INT_STS_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define TSEM_TSEM_INT_STS_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define TSEM_TSEM_INT_STS_0_REG_CAM_OUT_FIFO (0x1<<24)
#define TSEM_TSEM_INT_STS_0_REG_CAM_OUT_FIFO_SIZE 24
#define TSEM_TSEM_INT_STS_0_REG_FIN_FIFO (0x1<<25)
#define TSEM_TSEM_INT_STS_0_REG_FIN_FIFO_SIZE 25
#define TSEM_TSEM_INT_STS_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define TSEM_TSEM_INT_STS_0_REG_SET0_THREAD_ERROR_SIZE 26
#define TSEM_TSEM_INT_STS_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define TSEM_TSEM_INT_STS_0_REG_SET1_THREAD_ERROR_SIZE 27
#define TSEM_TSEM_INT_STS_0_REG_THREAD_OVERRUN (0x1<<28)
#define TSEM_TSEM_INT_STS_0_REG_THREAD_OVERRUN_SIZE 28
#define TSEM_TSEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define TSEM_TSEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define TSEM_TSEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define TSEM_TSEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define TSEM_REG_TSEM_INT_STS_CLR_0 0x1800f8UL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR_SIZE 1
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR_SIZE 2
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define TSEM_TSEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define TSEM_TSEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define TSEM_TSEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define TSEM_TSEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define TSEM_TSEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define TSEM_TSEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define TSEM_TSEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define TSEM_TSEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define TSEM_TSEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define TSEM_TSEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define TSEM_TSEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM (0x1<<20)
#define TSEM_TSEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM_SIZE 20
#define TSEM_TSEM_INT_STS_CLR_0_REG_WR_FULL_CAM (0x1<<21)
#define TSEM_TSEM_INT_STS_CLR_0_REG_WR_FULL_CAM_SIZE 21
#define TSEM_TSEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define TSEM_TSEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define TSEM_TSEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define TSEM_TSEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define TSEM_TSEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO (0x1<<24)
#define TSEM_TSEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO_SIZE 24
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIN_FIFO (0x1<<25)
#define TSEM_TSEM_INT_STS_CLR_0_REG_FIN_FIFO_SIZE 25
#define TSEM_TSEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR_SIZE 26
#define TSEM_TSEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR_SIZE 27
#define TSEM_TSEM_INT_STS_CLR_0_REG_THREAD_OVERRUN (0x1<<28)
#define TSEM_TSEM_INT_STS_CLR_0_REG_THREAD_OVERRUN_SIZE 28
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define TSEM_REG_TSEM_INT_STS_WR_0 0x1800fcUL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR_SIZE 1
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR_SIZE 2
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define TSEM_TSEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define TSEM_TSEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define TSEM_TSEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define TSEM_TSEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define TSEM_TSEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define TSEM_TSEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define TSEM_TSEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define TSEM_TSEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define TSEM_TSEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define TSEM_TSEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define TSEM_TSEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define TSEM_TSEM_INT_STS_WR_0_REG_RD_EMPTY_CAM (0x1<<20)
#define TSEM_TSEM_INT_STS_WR_0_REG_RD_EMPTY_CAM_SIZE 20
#define TSEM_TSEM_INT_STS_WR_0_REG_WR_FULL_CAM (0x1<<21)
#define TSEM_TSEM_INT_STS_WR_0_REG_WR_FULL_CAM_SIZE 21
#define TSEM_TSEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define TSEM_TSEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define TSEM_TSEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define TSEM_TSEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define TSEM_TSEM_INT_STS_WR_0_REG_CAM_OUT_FIFO (0x1<<24)
#define TSEM_TSEM_INT_STS_WR_0_REG_CAM_OUT_FIFO_SIZE 24
#define TSEM_TSEM_INT_STS_WR_0_REG_FIN_FIFO (0x1<<25)
#define TSEM_TSEM_INT_STS_WR_0_REG_FIN_FIFO_SIZE 25
#define TSEM_TSEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define TSEM_TSEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR_SIZE 26
#define TSEM_TSEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define TSEM_TSEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR_SIZE 27
#define TSEM_TSEM_INT_STS_WR_0_REG_THREAD_OVERRUN (0x1<<28)
#define TSEM_TSEM_INT_STS_WR_0_REG_THREAD_OVERRUN_SIZE 28
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define TSEM_REG_TSEM_INT_MASK_0 0x180100UL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define TSEM_TSEM_INT_MASK_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define TSEM_TSEM_INT_MASK_0_REG_FIC0_LAST_ERROR_SIZE 1
#define TSEM_TSEM_INT_MASK_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define TSEM_TSEM_INT_MASK_0_REG_FIC1_LAST_ERROR_SIZE 2
#define TSEM_TSEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define TSEM_TSEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define TSEM_TSEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define TSEM_TSEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define TSEM_TSEM_INT_MASK_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define TSEM_TSEM_INT_MASK_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define TSEM_TSEM_INT_MASK_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define TSEM_TSEM_INT_MASK_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define TSEM_TSEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define TSEM_TSEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define TSEM_TSEM_INT_MASK_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define TSEM_TSEM_INT_MASK_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define TSEM_TSEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define TSEM_TSEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define TSEM_TSEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define TSEM_TSEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define TSEM_TSEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define TSEM_TSEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define TSEM_TSEM_INT_MASK_0_REG_RD_EMPTY_CAM (0x1<<20)
#define TSEM_TSEM_INT_MASK_0_REG_RD_EMPTY_CAM_SIZE 20
#define TSEM_TSEM_INT_MASK_0_REG_WR_FULL_CAM (0x1<<21)
#define TSEM_TSEM_INT_MASK_0_REG_WR_FULL_CAM_SIZE 21
#define TSEM_TSEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define TSEM_TSEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define TSEM_TSEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define TSEM_TSEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define TSEM_TSEM_INT_MASK_0_REG_CAM_OUT_FIFO (0x1<<24)
#define TSEM_TSEM_INT_MASK_0_REG_CAM_OUT_FIFO_SIZE 24
#define TSEM_TSEM_INT_MASK_0_REG_FIN_FIFO (0x1<<25)
#define TSEM_TSEM_INT_MASK_0_REG_FIN_FIFO_SIZE 25
#define TSEM_TSEM_INT_MASK_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define TSEM_TSEM_INT_MASK_0_REG_SET0_THREAD_ERROR_SIZE 26
#define TSEM_TSEM_INT_MASK_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define TSEM_TSEM_INT_MASK_0_REG_SET1_THREAD_ERROR_SIZE 27
#define TSEM_TSEM_INT_MASK_0_REG_THREAD_OVERRUN (0x1<<28)
#define TSEM_TSEM_INT_MASK_0_REG_THREAD_OVERRUN_SIZE 28
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define TSEM_TSEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define TSEM_REG_TSEM_INT_STS_1 0x180104UL //ACCESS:R DataWidth:0xd Description: Interrupt register #1 read
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define TSEM_TSEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define TSEM_TSEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define TSEM_TSEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define TSEM_TSEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define TSEM_TSEM_INT_STS_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define TSEM_TSEM_INT_STS_1_REG_DBG_FIFO_ERROR_SIZE 9
#define TSEM_TSEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define TSEM_TSEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define TSEM_TSEM_INT_STS_1_REG_VFC_INTERRUPT (0x1<<11)
#define TSEM_TSEM_INT_STS_1_REG_VFC_INTERRUPT_SIZE 11
#define TSEM_TSEM_INT_STS_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
#define TSEM_TSEM_INT_STS_1_REG_VFC_OUT_FIFO_ERROR_SIZE 12
#define TSEM_REG_TSEM_INT_STS_CLR_1 0x180108UL //ACCESS:RC DataWidth:0xd Description: Interrupt register #1 read clear
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define TSEM_TSEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define TSEM_TSEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR_SIZE 9
#define TSEM_TSEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define TSEM_TSEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define TSEM_TSEM_INT_STS_CLR_1_REG_VFC_INTERRUPT (0x1<<11)
#define TSEM_TSEM_INT_STS_CLR_1_REG_VFC_INTERRUPT_SIZE 11
#define TSEM_TSEM_INT_STS_CLR_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
#define TSEM_TSEM_INT_STS_CLR_1_REG_VFC_OUT_FIFO_ERROR_SIZE 12
#define TSEM_REG_TSEM_INT_STS_WR_1 0x18010cUL //ACCESS:WR DataWidth:0xd Description: Interrupt register #1 bit set or clear
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define TSEM_TSEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define TSEM_TSEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR_SIZE 9
#define TSEM_TSEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define TSEM_TSEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define TSEM_TSEM_INT_STS_WR_1_REG_VFC_INTERRUPT (0x1<<11)
#define TSEM_TSEM_INT_STS_WR_1_REG_VFC_INTERRUPT_SIZE 11
#define TSEM_TSEM_INT_STS_WR_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
#define TSEM_TSEM_INT_STS_WR_1_REG_VFC_OUT_FIFO_ERROR_SIZE 12
#define TSEM_REG_TSEM_INT_MASK_1 0x180110UL //ACCESS:RW DataWidth:0xd Description: Interrupt mask register #1 read/write
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define TSEM_TSEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define TSEM_TSEM_INT_MASK_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define TSEM_TSEM_INT_MASK_1_REG_DBG_FIFO_ERROR_SIZE 9
#define TSEM_TSEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define TSEM_TSEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define TSEM_TSEM_INT_MASK_1_REG_VFC_INTERRUPT (0x1<<11)
#define TSEM_TSEM_INT_MASK_1_REG_VFC_INTERRUPT_SIZE 11
#define TSEM_TSEM_INT_MASK_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
#define TSEM_TSEM_INT_MASK_1_REG_VFC_OUT_FIFO_ERROR_SIZE 12
#define TSEM_REG_TSEM_PRTY_STS_0 0x180114UL //ACCESS:R DataWidth:0x20 Description: Parity register #0 read
#define TSEM_TSEM_PRTY_STS_0_REG_PARITY (0x1<<0)
#define TSEM_TSEM_PRTY_STS_0_REG_PARITY_SIZE 0
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define TSEM_TSEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define TSEM_TSEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define TSEM_TSEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define TSEM_TSEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define TSEM_TSEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define TSEM_TSEM_PRTY_STS_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define TSEM_TSEM_PRTY_STS_0_REG_PAS_FIFO_PARITY_SIZE 10
#define TSEM_TSEM_PRTY_STS_0_REG_PAS_PARITY0 (0x1<<11)
#define TSEM_TSEM_PRTY_STS_0_REG_PAS_PARITY0_SIZE 11
#define TSEM_TSEM_PRTY_STS_0_REG_PAS_PARITY1 (0x1<<12)
#define TSEM_TSEM_PRTY_STS_0_REG_PAS_PARITY1_SIZE 12
#define TSEM_TSEM_PRTY_STS_0_REG_INT_TABLE_PARITY (0x1<<13)
#define TSEM_TSEM_PRTY_STS_0_REG_INT_TABLE_PARITY_SIZE 13
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY0 (0x1<<14)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY0_SIZE 14
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY1 (0x1<<15)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY1_SIZE 15
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY2 (0x1<<16)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY2_SIZE 16
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY3 (0x1<<17)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY3_SIZE 17
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY4 (0x1<<18)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY4_SIZE 18
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY5 (0x1<<19)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY5_SIZE 19
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY6 (0x1<<20)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY6_SIZE 20
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY7 (0x1<<21)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY7_SIZE 21
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY0 (0x1<<22)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY0_SIZE 22
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY1 (0x1<<23)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY1_SIZE 23
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY2 (0x1<<24)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY2_SIZE 24
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY3 (0x1<<25)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY3_SIZE 25
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY4 (0x1<<26)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY4_SIZE 26
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY5 (0x1<<27)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY5_SIZE 27
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY6 (0x1<<28)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY6_SIZE 28
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY7 (0x1<<29)
#define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY7_SIZE 29
#define TSEM_TSEM_PRTY_STS_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define TSEM_TSEM_PRTY_STS_0_REG_PRAM_LOW_PARITY_SIZE 30
#define TSEM_TSEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define TSEM_TSEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118UL //ACCESS:RC DataWidth:0x20 Description: Parity register #0 read clear
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PARITY_SIZE 0
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY_SIZE 10
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PAS_PARITY0 (0x1<<11)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PAS_PARITY0_SIZE 11
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PAS_PARITY1 (0x1<<12)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PAS_PARITY1_SIZE 12
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY (0x1<<13)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY_SIZE 13
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0 (0x1<<14)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0_SIZE 14
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1 (0x1<<15)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1_SIZE 15
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2 (0x1<<16)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2_SIZE 16
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3 (0x1<<17)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3_SIZE 17
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4 (0x1<<18)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4_SIZE 18
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5 (0x1<<19)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5_SIZE 19
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6 (0x1<<20)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6_SIZE 20
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7 (0x1<<21)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7_SIZE 21
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0 (0x1<<22)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0_SIZE 22
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1 (0x1<<23)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1_SIZE 23
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2 (0x1<<24)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2_SIZE 24
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3 (0x1<<25)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3_SIZE 25
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4 (0x1<<26)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4_SIZE 26
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5 (0x1<<27)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5_SIZE 27
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6 (0x1<<28)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6_SIZE 28
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7 (0x1<<29)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7_SIZE 29
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY_SIZE 30
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define TSEM_TSEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define TSEM_REG_TSEM_PRTY_STS_WR_0 0x18011cUL //ACCESS:WR DataWidth:0x20 Description: Parity register #0 bit set or clear
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PARITY_SIZE 0
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define TSEM_TSEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define TSEM_TSEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY_SIZE 10
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PAS_PARITY0 (0x1<<11)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PAS_PARITY0_SIZE 11
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PAS_PARITY1 (0x1<<12)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PAS_PARITY1_SIZE 12
#define TSEM_TSEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY (0x1<<13)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY_SIZE 13
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY0 (0x1<<14)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY0_SIZE 14
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY1 (0x1<<15)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY1_SIZE 15
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY2 (0x1<<16)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY2_SIZE 16
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY3 (0x1<<17)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY3_SIZE 17
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY4 (0x1<<18)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY4_SIZE 18
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY5 (0x1<<19)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY5_SIZE 19
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY6 (0x1<<20)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY6_SIZE 20
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY7 (0x1<<21)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY7_SIZE 21
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY0 (0x1<<22)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY0_SIZE 22
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY1 (0x1<<23)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY1_SIZE 23
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY2 (0x1<<24)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY2_SIZE 24
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY3 (0x1<<25)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY3_SIZE 25
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY4 (0x1<<26)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY4_SIZE 26
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY5 (0x1<<27)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY5_SIZE 27
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY6 (0x1<<28)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY6_SIZE 28
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY7 (0x1<<29)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY7_SIZE 29
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY_SIZE 30
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define TSEM_TSEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120UL //ACCESS:RW DataWidth:0x20 Description: Parity mask register #0 read/write
#define TSEM_TSEM_PRTY_MASK_0_REG_PARITY (0x1<<0)
#define TSEM_TSEM_PRTY_MASK_0_REG_PARITY_SIZE 0
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define TSEM_TSEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define TSEM_TSEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define TSEM_TSEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define TSEM_TSEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define TSEM_TSEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define TSEM_TSEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY_SIZE 10
#define TSEM_TSEM_PRTY_MASK_0_REG_PAS_PARITY0 (0x1<<11)
#define TSEM_TSEM_PRTY_MASK_0_REG_PAS_PARITY0_SIZE 11
#define TSEM_TSEM_PRTY_MASK_0_REG_PAS_PARITY1 (0x1<<12)
#define TSEM_TSEM_PRTY_MASK_0_REG_PAS_PARITY1_SIZE 12
#define TSEM_TSEM_PRTY_MASK_0_REG_INT_TABLE_PARITY (0x1<<13)
#define TSEM_TSEM_PRTY_MASK_0_REG_INT_TABLE_PARITY_SIZE 13
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY0 (0x1<<14)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY0_SIZE 14
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY1 (0x1<<15)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY1_SIZE 15
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY2 (0x1<<16)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY2_SIZE 16
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY3 (0x1<<17)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY3_SIZE 17
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY4 (0x1<<18)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY4_SIZE 18
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY5 (0x1<<19)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY5_SIZE 19
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY6 (0x1<<20)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY6_SIZE 20
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY7 (0x1<<21)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY7_SIZE 21
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY0 (0x1<<22)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY0_SIZE 22
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY1 (0x1<<23)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY1_SIZE 23
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY2 (0x1<<24)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY2_SIZE 24
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY3 (0x1<<25)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY3_SIZE 25
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY4 (0x1<<26)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY4_SIZE 26
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY5 (0x1<<27)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY5_SIZE 27
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY6 (0x1<<28)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY6_SIZE 28
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY7 (0x1<<29)
#define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY7_SIZE 29
#define TSEM_TSEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define TSEM_TSEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY_SIZE 30
#define TSEM_TSEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define TSEM_TSEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define TSEM_REG_TSEM_PRTY_STS_1 0x180124UL //ACCESS:R DataWidth:0x6 Description: Parity register #1 read
#define TSEM_TSEM_PRTY_STS_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define TSEM_TSEM_PRTY_STS_1_REG_SYNC_DBG_PARITY_SIZE 0
#define TSEM_TSEM_PRTY_STS_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define TSEM_TSEM_PRTY_STS_1_REG_SLOW_DBG_PARITY_SIZE 1
#define TSEM_TSEM_PRTY_STS_1_REG_CAM_PARITY (0x1<<2)
#define TSEM_TSEM_PRTY_STS_1_REG_CAM_PARITY_SIZE 2
#define TSEM_TSEM_PRTY_STS_1_REG_STORM_RF0_PARITY (0x1<<3)
#define TSEM_TSEM_PRTY_STS_1_REG_STORM_RF0_PARITY_SIZE 3
#define TSEM_TSEM_PRTY_STS_1_REG_STORM_RF1_PARITY (0x1<<4)
#define TSEM_TSEM_PRTY_STS_1_REG_STORM_RF1_PARITY_SIZE 4
#define TSEM_TSEM_PRTY_STS_1_REG_VFC_PARITY (0x1<<5)
#define TSEM_TSEM_PRTY_STS_1_REG_VFC_PARITY_SIZE 5
#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128UL //ACCESS:RC DataWidth:0x6 Description: Parity register #1 read clear
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY_SIZE 0
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY_SIZE 1
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_CAM_PARITY (0x1<<2)
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_CAM_PARITY_SIZE 2
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY (0x1<<3)
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY_SIZE 3
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY (0x1<<4)
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY_SIZE 4
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_VFC_PARITY (0x1<<5)
#define TSEM_TSEM_PRTY_STS_CLR_1_REG_VFC_PARITY_SIZE 5
#define TSEM_REG_TSEM_PRTY_STS_WR_1 0x18012cUL //ACCESS:WR DataWidth:0x6 Description: Parity register #1 bit set or clear
#define TSEM_TSEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define TSEM_TSEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY_SIZE 0
#define TSEM_TSEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define TSEM_TSEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY_SIZE 1
#define TSEM_TSEM_PRTY_STS_WR_1_REG_CAM_PARITY (0x1<<2)
#define TSEM_TSEM_PRTY_STS_WR_1_REG_CAM_PARITY_SIZE 2
#define TSEM_TSEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY (0x1<<3)
#define TSEM_TSEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY_SIZE 3
#define TSEM_TSEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY (0x1<<4)
#define TSEM_TSEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY_SIZE 4
#define TSEM_TSEM_PRTY_STS_WR_1_REG_VFC_PARITY (0x1<<5)
#define TSEM_TSEM_PRTY_STS_WR_1_REG_VFC_PARITY_SIZE 5
#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130UL //ACCESS:RW DataWidth:0x6 Description: Parity mask register #1 read/write
#define TSEM_TSEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define TSEM_TSEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY_SIZE 0
#define TSEM_TSEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define TSEM_TSEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY_SIZE 1
#define TSEM_TSEM_PRTY_MASK_1_REG_CAM_PARITY (0x1<<2)
#define TSEM_TSEM_PRTY_MASK_1_REG_CAM_PARITY_SIZE 2
#define TSEM_TSEM_PRTY_MASK_1_REG_STORM_RF0_PARITY (0x1<<3)
#define TSEM_TSEM_PRTY_MASK_1_REG_STORM_RF0_PARITY_SIZE 3
#define TSEM_TSEM_PRTY_MASK_1_REG_STORM_RF1_PARITY (0x1<<4)
#define TSEM_TSEM_PRTY_MASK_1_REG_STORM_RF1_PARITY_SIZE 4
#define TSEM_TSEM_PRTY_MASK_1_REG_VFC_PARITY (0x1<<5)
#define TSEM_TSEM_PRTY_MASK_1_REG_VFC_PARITY_SIZE 5
#define TSEM_REG_RAM0_TM1 0x18013cUL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory ram0_1
#define TSEM_REG_RAM0_TM2 0x180140UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory ram0_2
#define TSEM_REG_PAS_BUF_LSB_TM 0x1803a0UL //ACCESS:RW DataWidth:0x5 Description: TM bits PAS_BUF LSB
#define TSEM_REG_PAS_BUF_MSB_TM 0x1803a4UL //ACCESS:RW DataWidth:0x5 Description: TM bits PAS_BUF MSB
#define TSEM_REG_ECO_RESERVED 0x1803a8UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO
#define TSEM_REG_FIFOS_TM 0x1803acUL //ACCESS:RW DataWidth:0xe Description: TM bits for FIC0_LSB [1:0]; FIC0_MSB[3:2]; FIC1_LSB[5:4]; FIC1_MSB[7:6]; DBG_LSB[9:8];DBG_MSB[11:10]; EXT_PAS[13:12]
#define TSEM_REG_PAS_BUF_LSB_TMB 0x1803b4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_lsb
#define TSEM_REG_PAS_BUF_MSB_TMB 0x1803b8UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_msb
#define TSEM_REG_ARBITER_REQUEST 0x180200UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2
#define TSEM_REG_ARBITER_REQUEST_SIZE 1
#define TSEM_REG_ARBITER_SELECT 0x180204UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2
#define TSEM_REG_ARBITER_SELECT_SIZE 1
#define TSEM_REG_ARBITER_SLOT 0x180208UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last slot
#define TSEM_REG_ARBITER_SLOT_SIZE 1
#define TSEM_REG_DBG_IF_FULL 0x18020cUL //ACCESS:R DataWidth:0x1 Description: DBG IF is full in sem_slow_ls_dbg
#define TSEM_REG_DBG_IF_FULL_SIZE 1
#define TSEM_REG_DRA_EMPTY 0x180210UL //ACCESS:R DataWidth:0x1 Description: This register is active when FIN FIO is empty and DRA RD FIFO is empty
#define TSEM_REG_DRA_EMPTY_SIZE 1
#define TSEM_REG_EXT_PAS_EMPTY 0x180214UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO empty in sem_slow
#define TSEM_REG_EXT_PAS_EMPTY_SIZE 1
#define TSEM_REG_EXT_PAS_FULL 0x180218UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO Full in sem_slow
#define TSEM_REG_EXT_PAS_FULL_SIZE 1
#define TSEM_REG_EXT_STORE_FREE_ENTRIES 0x18021cUL //ACCESS:R DataWidth:0x6 Description: Number of free entries in the external STORE sync FIFO.
#define TSEM_REG_EXT_STORE_FREE_ENTRIES_SIZE 1
#define TSEM_REG_EXT_STORE_IF_FULL 0x180220UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE IF is full in sem_slow_ls_ext
#define TSEM_REG_EXT_STORE_IF_FULL_SIZE 1
#define TSEM_REG_FIC0_DISABLE 0x180224UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC0 May be updated during run_time by the microcode
#define TSEM_REG_FIC0_DISABLE_SIZE 1
#define TSEM_REG_FIC0_EMPTY 0x180228UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
#define TSEM_REG_FIC0_EMPTY_SIZE 1
#define TSEM_REG_FIC0_FULL 0x18022cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
#define TSEM_REG_FIC0_FULL_SIZE 1
#define TSEM_REG_FIC0_LENGTH 0x180230UL //ACCESS:R DataWidth:0x8 Description: Length from FIC0. Active only with ~tsem_registers_fic0_length_error.fic0_length_error interrupt
#define TSEM_REG_FIC0_LENGTH_SIZE 1
#define TSEM_REG_FIC1_DISABLE 0x180234UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC1 May be updated during run_time by the microcode
#define TSEM_REG_FIC1_DISABLE_SIZE 1
#define TSEM_REG_FIC1_EMPTY 0x180238UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
#define TSEM_REG_FIC1_EMPTY_SIZE 1
#define TSEM_REG_FIC1_FULL 0x18023cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
#define TSEM_REG_FIC1_FULL_SIZE 1
#define TSEM_REG_FIC1_LENGTH 0x180240UL //ACCESS:R DataWidth:0x8 Description: Length from FIC1. Active only with ~tsem_registers_fic1_length_error.fic1_length_error interrupt
#define TSEM_REG_FIC1_LENGTH_SIZE 1
#define TSEM_REG_GPI_DATA 0x180244UL //ACCESS:R DataWidth:0x18 Description: GPI signals that are inputs to SEMI
#define TSEM_REG_GPI_DATA_SIZE 1
#define TSEM_REG_NUM_OF_THREADS 0x180248UL //ACCESS:R DataWidth:0x6 Description: The number of threads currently active
#define TSEM_REG_NUM_OF_THREADS_SIZE 1
#define TSEM_REG_PAS_DISABLE 0x18024cUL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from the passive buffer May be updated during run_time by the microcode
#define TSEM_REG_PAS_DISABLE_SIZE 1
#define TSEM_REG_PAS_IF_FULL 0x180250UL //ACCESS:R DataWidth:0x1 Description: Full from passive buffer asserted toward SDM
#define TSEM_REG_PAS_IF_FULL_SIZE 1
#define TSEM_REG_RAM0_IF_FULL 0x180254UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM0 IF is full in sem_slow_ls_ram
#define TSEM_REG_RAM0_IF_FULL_SIZE 1
#define TSEM_REG_RAM1_IF_FULL 0x180258UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM1 IF is full in sem_slow_ls_ram
#define TSEM_REG_RAM1_IF_FULL_SIZE 1
#define TSEM_REG_SET0_THREAD_EMPTY 0x18025cUL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is empty in sem_slow_dra_wr
#define TSEM_REG_SET0_THREAD_EMPTY_SIZE 1
#define TSEM_REG_SET0_THREAD_FULL 0x180260UL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is full in sem_slow_dra_wr
#define TSEM_REG_SET0_THREAD_FULL_SIZE 1
#define TSEM_REG_SET1_THREAD_EMPTY 0x180264UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is empty in sem_slow_dra_wr
#define TSEM_REG_SET1_THREAD_EMPTY_SIZE 1
#define TSEM_REG_SET1_THREAD_FULL 0x180268UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is full in sem_slow_dra_wr
#define TSEM_REG_SET1_THREAD_FULL_SIZE 1
#define TSEM_REG_SLEEP_THREADS_VALID 0x18026cUL //ACCESS:R DataWidth:0x14 Description: Valid sleeping threads indication have bit per thread
#define TSEM_REG_SLEEP_THREADS_VALID_SIZE 1
#define TSEM_REG_SLOW_DBG_ALM_EMPTY 0x180270UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg (31 entry inside fifo)
#define TSEM_REG_SLOW_DBG_ALM_EMPTY_SIZE 1
#define TSEM_REG_SLOW_DBG_ALM_FULL 0x180274UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg according to configuration
#define TSEM_REG_SLOW_DBG_ALM_FULL_SIZE 1
#define TSEM_REG_SLOW_DBG_EMPTY 0x180278UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is empty in sem_slow_ls_dbg
#define TSEM_REG_SLOW_DBG_EMPTY_SIZE 1
#define TSEM_REG_SLOW_DBG_FULL 0x18027cUL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is full in sem_slow_ls_dbg
#define TSEM_REG_SLOW_DBG_FULL_SIZE 1
#define TSEM_REG_SLOW_DRA_FIN_EMPTY 0x180280UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is empty in sem_slow_dra_sync
#define TSEM_REG_SLOW_DRA_FIN_EMPTY_SIZE 1
#define TSEM_REG_SLOW_DRA_FIN_FULL 0x180284UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is full in sem_slow_dra_sync (never may be active)
#define TSEM_REG_SLOW_DRA_FIN_FULL_SIZE 1
#define TSEM_REG_SLOW_DRA_INT_EMPTY 0x180288UL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is empty in sem_slow_dra_sync
#define TSEM_REG_SLOW_DRA_INT_EMPTY_SIZE 1
#define TSEM_REG_SLOW_DRA_INT_FULL 0x18028cUL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is full in sem_slow_dra_int
#define TSEM_REG_SLOW_DRA_INT_FULL_SIZE 1
#define TSEM_REG_SLOW_DRA_RD_EMPTY 0x180290UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is empty in sem_slow_dra_sync
#define TSEM_REG_SLOW_DRA_RD_EMPTY_SIZE 1
#define TSEM_REG_SLOW_DRA_RD_FULL 0x180294UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is full in sem_slow_dra_sync
#define TSEM_REG_SLOW_DRA_RD_FULL_SIZE 1
#define TSEM_REG_SLOW_DRA_WR_EMPTY 0x180298UL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is empty in sem_slow_dra_sync
#define TSEM_REG_SLOW_DRA_WR_EMPTY_SIZE 1
#define TSEM_REG_SLOW_DRA_WR_FULL 0x18029cUL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is full in sem_slow_dra_sync
#define TSEM_REG_SLOW_DRA_WR_FULL_SIZE 1
#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is empty in sem_slow_ls_ext
#define TSEM_REG_SLOW_EXT_STORE_EMPTY_SIZE 1
#define TSEM_REG_SLOW_EXT_STORE_FULL 0x1802a4UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is full in sem_slow_ls_ext
#define TSEM_REG_SLOW_EXT_STORE_FULL_SIZE 1
#define TSEM_REG_SLOW_RAM0_RD_EMPTY 0x1802a8UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is empty in sem_slow_ls_ext
#define TSEM_REG_SLOW_RAM0_RD_EMPTY_SIZE 1
#define TSEM_REG_SLOW_RAM0_RD_FULL 0x1802acUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is full in sem_slow_ls_ext
#define TSEM_REG_SLOW_RAM0_RD_FULL_SIZE 1
#define TSEM_REG_SLOW_RAM0_WR_ALM_FULL 0x1802b0UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
#define TSEM_REG_SLOW_RAM0_WR_ALM_FULL_SIZE 1
#define TSEM_REG_SLOW_RAM0_WR_EMPTY 0x1802b4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is empty in sem_slow_ls_ext
#define TSEM_REG_SLOW_RAM0_WR_EMPTY_SIZE 1
#define TSEM_REG_SLOW_RAM0_WR_FULL 0x1802b8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is full in sem_slow_ls_ext
#define TSEM_REG_SLOW_RAM0_WR_FULL_SIZE 1
#define TSEM_REG_SLOW_RAM1_RD_EMPTY 0x1802bcUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is empty in sem_slow_ls_ext
#define TSEM_REG_SLOW_RAM1_RD_EMPTY_SIZE 1
#define TSEM_REG_SLOW_RAM1_RD_FULL 0x1802c0UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is full in sem_slow_ls_ext
#define TSEM_REG_SLOW_RAM1_RD_FULL_SIZE 1
#define TSEM_REG_SLOW_RAM1_WR_ALM_FULL 0x1802c4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
#define TSEM_REG_SLOW_RAM1_WR_ALM_FULL_SIZE 1
#define TSEM_REG_SLOW_RAM1_WR_EMPTY 0x1802c8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is empty in sem_slow_ls_ext
#define TSEM_REG_SLOW_RAM1_WR_EMPTY_SIZE 1
#define TSEM_REG_SLOW_RAM1_WR_FULL 0x1802ccUL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is full in sem_slow_ls_ext
#define TSEM_REG_SLOW_RAM1_WR_FULL_SIZE 1
#define TSEM_REG_SYNC_DBG_EMPTY 0x1802d0UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is empty in sem_slow_ls_sync
#define TSEM_REG_SYNC_DBG_EMPTY_SIZE 1
#define TSEM_REG_SYNC_DBG_FULL 0x1802d4UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is full in sem_slow_ls_sync
#define TSEM_REG_SYNC_DBG_FULL_SIZE 1
#define TSEM_REG_THREAD_ERROR 0x1802d8UL //ACCESS:R DataWidth:0x14 Description: Thread error indication have bit per thread
#define TSEM_REG_THREAD_ERROR_SIZE 1
#define TSEM_REG_THREAD_OVERRUN_NUM 0x1802dcUL //ACCESS:R DataWidth:0x14 Description: Threads are sleeping in passive buffer more than ~tsem_registers_thread_inter_cnt.thread_inter_cnt number of cycles
#define TSEM_REG_THREAD_OVERRUN_NUM_SIZE 1
#define TSEM_REG_THREAD_RDY 0x1802e0UL //ACCESS:R DataWidth:0x14 Description: Thread ready indication have bit per thread
#define TSEM_REG_THREAD_RDY_SIZE 1
#define TSEM_REG_THREADS_LIST 0x1802e4UL //ACCESS:RW DataWidth:0x14 Description: List of free threads . There is a bit per thread.
#define TSEM_REG_THREADS_LIST_SIZE 1
#define TSEM_REG_WB_MSB 0x1802e8UL //ACCESS:R DataWidth:0x2 Description: Reset value of this register is right when was not read to ~tsem_registers_fic0_fifo.fic0_fifo or ~tsem_registers_fic1_fifo.fic1_fifo or ~tsem_registers_passive_buffer.passive_buffer. For read from ~tsem_registers_passive_buffer.passive_buffer :b0- parity0; b1 parity1. For read from ~tsem_registers_fic0_fifo.fic0_fifo and ~tsem_registers_fic1_fifo.fic1_fifo :b1=0 data from ~tsem_registers_fic0_fifo.fic0_fifo and ~tsem_registers_fic1_fifo.fic1_fifo is valid; b1 =1 ~tsem_registers_fic0_fifo.fic0_fifo and ~tsem_registers_fic1_fifo.fic1_fifo is empty and data from it must be equal to 0; b0 - parity from ~tsem_registers_fic0_fifo.fic0_fifo and ~tsem_registers_fic1_fifo.fic1_fifo
#define TSEM_REG_WB_MSB_SIZE 1
#define TSEM_REG_FIC0_FIFO 0x180300UL //ACCESS:WB_R DataWidth:0x80 Description: Debug only. FIC0_fifo: b[127:0] data; b128-parity;b129=1- fifo empty;b129=0-data is valid
#define TSEM_REG_FIC0_FIFO_SIZE 4
#define TSEM_REG_FIC1_FIFO 0x180320UL //ACCESS:WB_R DataWidth:0x80 Description: Debug only. FIC1_fifo read for debugging mode; b[127:0] data; b128-parity;
#define TSEM_REG_FIC1_FIFO_SIZE 4
#define TSEM_REG_FIN_COMMAND 0x180340UL //ACCESS:WB_R DataWidth:0x6d Description: last fin command that was read from fifo. Its spelling in ~tsem_registers_fin_fifo.fin_fifo register
#define TSEM_REG_FIN_COMMAND_SIZE 4
#define TSEM_REG_FIN_FIFO 0x180360UL //ACCESS:WB_R DataWidth:0x6d Description: Debug only. FIn FIFO. [5:0] start_rp_foc3; [11:6] start_rp_foc2; [17:12] start_rp_foc1; [23:18] start_rp_foc0; [29:24] end_rp_foc3; [35:30] end_rp_foc2; [41:36] end_rp_foc1; [47:42] end_rp_foc0; [53:48] lowest rp; [59:54] highest rp; [65:60] store start rp; [71:66] store end rp; [77:72] load start rp; [83:78] load end rp; [85:84] priority; [101:86] pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid
#define TSEM_REG_FIN_FIFO_SIZE 4
#define TSEM_REG_VFPF_ERR_NUM 0x180380UL //ACCESS:W DataWidth:0x7 Description: VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
#define TSEM_REG_VFPF_ERR_NUM_SIZE 1
#define TSEM_REG_VF_ERR_VECTOR_LSB 0x180388UL //ACCESS:R DataWidth:0x20 Description: VF/PF error bitmap vector [0-31]
#define TSEM_REG_VF_ERR_VECTOR_LSB_SIZE 1
#define TSEM_REG_VF_ERR_VECTOR_MSB 0x180390UL //ACCESS:R DataWidth:0x20 Description: VF/PF error bitmap vector [32-63]
#define TSEM_REG_VF_ERR_VECTOR_MSB_SIZE 1
#define TSEM_REG_PF_ERR_VECTOR 0x180398UL //ACCESS:R DataWidth:0x8 Description: VF/PF error bitmap vector [0-7]
#define TSEM_REG_PF_ERR_VECTOR_SIZE 1
#define TSEM_REG_THREAD_SET_NUM 0x1803b0UL //ACCESS:W DataWidth:0x5 Description: Thread ID. Write thread ID will set ready indication for this thread ID
#define TSEM_REG_THREAD_SET_NUM_SIZE 1
#define TSEM_REG_INT_TABLE 0x180400UL //ACCESS:RW DataWidth:0xf Description: Interrupt table Read and write access to it is not possible in the middle of the work
#define TSEM_REG_INT_TABLE_SIZE 256
#define TSEM_REG_PASSIVE_BUFFER 0x181000UL //ACCESS:WB DataWidth:0x80 Description: Debug only. Passive buffer memory
#define TSEM_REG_PASSIVE_BUFFER_SIZE 1024
#define TSEM_REG_PASSIVE_BUFFER_MSB 0x182000UL //ACCESS:WB DataWidth:0x80 Description: Debug only. Passive buffer memory MSB that starts from row 256 of passive buffer till row 639
#define TSEM_REG_PASSIVE_BUFFER_MSB_SIZE 1536
#define TSEM_REG_FAST_MEMORY 0x1a0000UL //ACCESS:RW DataWidth:0x20 Description: This address space contains all registers and memories that are placed in SEM_FAST block. The SEM_FAST registers are described in appendix B. In order to access the SEM_FAST registers the base address TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each SEM_FAST register offset.
#define TSEM_REG_FAST_MEMORY_SIZE 32768
#define TSEM_REG_PRAM 0x1c0000UL //ACCESS:WB DataWidth:0x2e Description: pram memory. B45 is parity; b[44:0] - data.
#define TSEM_REG_PRAM_SIZE 65536
#define TSEM_REG_TSEM_UNUSED_EMPTY_0 0x180134UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSEM_REG_TSEM_UNUSED_EMPTY_0_SIZE 2
#define TSEM_REG_TSEM_UNUSED_EMPTY_1 0x180144UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSEM_REG_TSEM_UNUSED_EMPTY_1_SIZE 47
#define TSEM_REG_TSEM_UNUSED_EMPTY_2 0x1802ecUL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSEM_REG_TSEM_UNUSED_EMPTY_2_SIZE 5
#define TSEM_REG_TSEM_UNUSED_EMPTY_3 0x180384UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSEM_REG_TSEM_UNUSED_EMPTY_3_SIZE 1
#define TSEM_REG_TSEM_UNUSED_EMPTY_4 0x18038cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSEM_REG_TSEM_UNUSED_EMPTY_4_SIZE 1
#define TSEM_REG_TSEM_UNUSED_EMPTY_5 0x180394UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSEM_REG_TSEM_UNUSED_EMPTY_5_SIZE 1
#define TSEM_REG_TSEM_UNUSED_EMPTY_6 0x18039cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSEM_REG_TSEM_UNUSED_EMPTY_6_SIZE 1
#define TSEM_REG_TSEM_UNUSED_EMPTY_7 0x1803bcUL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSEM_REG_TSEM_UNUSED_EMPTY_7_SIZE 17
#define TSEM_REG_TSEM_UNUSED_EMPTY_8 0x180800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSEM_REG_TSEM_UNUSED_EMPTY_8_SIZE 512
#define TSEM_REG_TSEM_UNUSED_EMPTY_9 0x184000UL //ACCESS:R DataWidth:0x20 Unused empty space
#define TSEM_REG_TSEM_UNUSED_EMPTY_9_SIZE 28672
#define UCM_REG_INIT 0xe0000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
#define UCM_REG_UCM_STORM0_IFEN 0xe0004UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_UCM_STORM1_IFEN 0xe0008UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_UCM_UQM_IFEN 0xe000cUL //ACCESS:RW DataWidth:0x1 Description: CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_STORM_UCM_IFEN 0xe0010UL //ACCESS:RW DataWidth:0x1 Description: STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_UQM_UCM_IFEN 0xe0014UL //ACCESS:RW DataWidth:0x1 Description: QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_USDM_IFEN 0xe0018UL //ACCESS:RW DataWidth:0x1 Description: Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_TM_UCM_IFEN 0xe001cUL //ACCESS:RW DataWidth:0x1 Description: Timers - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_UCM_TM_IFEN 0xe0020UL //ACCESS:RW DataWidth:0x1 Description: CM - Timers Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_TSEM_IFEN 0xe0024UL //ACCESS:RW DataWidth:0x1 Description: Input tsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_CSEM_IFEN 0xe0028UL //ACCESS:RW DataWidth:0x1 Description: Input csem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_XSEM_IFEN 0xe002cUL //ACCESS:RW DataWidth:0x1 Description: Input xsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_DORQ_IFEN 0xe0030UL //ACCESS:RW DataWidth:0x1 Description: Input dorq Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_CDU_AG_WR_IFEN 0xe0034UL //ACCESS:RW DataWidth:0x1 Description: CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_CDU_AG_RD_IFEN 0xe0038UL //ACCESS:RW DataWidth:0x1 Description: CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_CDU_SM_WR_IFEN 0xe003cUL //ACCESS:RW DataWidth:0x1 Description: CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_CDU_SM_RD_IFEN 0xe0040UL //ACCESS:RW DataWidth:0x1 Description: CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_UCM_CFC_IFEN 0xe0044UL //ACCESS:RW DataWidth:0x1 Description: CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define UCM_REG_XX_MAX_LL_SZ 0xe0048UL //ACCESS:RW DataWidth:0x6 Description: Maximum link list size (pending messages) per connection in the XX protection.
#define UCM_REG_XX_OVFL_EVNT_ID 0xe004cUL //ACCESS:RW DataWidth:0x8 Description: The Event ID; sent to the STORM in case of XX overflow.
#define UCM_REG_XX_MAX_NUM 0xe0050UL //ACCESS:RW DataWidth:0x5 Description: The maximum number of connections in the XX protection.
#define UCM_REG_N_SM_CTX_LD_0 0xe0054UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_1 0xe0058UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_2 0xe005cUL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_3 0xe0060UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_4 0xe0064UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_5 0xe0068UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_6 0xe006cUL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_7 0xe0070UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_8 0xe0074UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_9 0xe0078UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_10 0xe007cUL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_11 0xe0080UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_12 0xe0084UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_13 0xe0088UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_14 0xe008cUL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_N_SM_CTX_LD_15 0xe0090UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define UCM_REG_UQM_UCM_HDR_P 0xe0094UL //ACCESS:RW DataWidth:0x1c Description: The CM header value for QM request (primary).
#define UCM_REG_UQM_UCM_HDR_S 0xe0098UL //ACCESS:RW DataWidth:0x1c Description: The CM header value for QM request (secondary).
#define UCM_REG_TM_UCM_HDR 0xe009cUL //ACCESS:RW DataWidth:0x1c Description: The CM header for Timers expiration command.
#define UCM_REG_ERR_UCM_HDR 0xe00a0UL //ACCESS:RW DataWidth:0x1c Description: The CM erroneous header for QM and Timers formatting.
#define UCM_REG_ERR_EVNT_ID 0xe00a4UL //ACCESS:RW DataWidth:0x8 Description: The Event ID in case ErrorFlg input message bit is set.
#define UCM_REG_EXPR_EVNT_ID 0xe00a8UL //ACCESS:RW DataWidth:0x8 Description: The Event ID for Timers expiration.
#define UCM_REG_STOP_EVNT_ID 0xe00acUL //ACCESS:RW DataWidth:0x8 Description: The Event ID for Timers formatting in case of stop done.
#define UCM_REG_STORM_WEIGHT 0xe00b0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the STORM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define UCM_REG_TSEM_WEIGHT 0xe00b4UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input tsem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define UCM_REG_CSEM_WEIGHT 0xe00b8UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input csem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define UCM_REG_XSEM_WEIGHT 0xe00bcUL //ACCESS:RW DataWidth:0x3 Description: The weight of the input xsem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define UCM_REG_DORQ_WEIGHT 0xe00c0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input dorq in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define UCM_REG_CP_WEIGHT 0xe00c4UL //ACCESS:RW DataWidth:0x3 Description: The weight of the CP input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define UCM_REG_USDM_WEIGHT 0xe00c8UL //ACCESS:RW DataWidth:0x3 Description: The weight of the SDM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define UCM_REG_UQM_P_WEIGHT 0xe00ccUL //ACCESS:RW DataWidth:0x3 Description: The weight of the QM (primary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define UCM_REG_UQM_S_WEIGHT 0xe00d0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the QM (secondary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define UCM_REG_TM_WEIGHT 0xe00d4UL //ACCESS:RW DataWidth:0x3 Description: The weight of the Timers input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define UCM_REG_UCM_UQM_USE_Q 0xe00d8UL //ACCESS:RW DataWidth:0x1 Description: If set the Q index; received from the QM is inserted to event ID.
#define UCM_REG_UCM_REG0_SZ 0xe00dcUL //ACCESS:RW DataWidth:0x2 Description: The size of AG context region 0 in REG-pairs. Designates the MS REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). Is used to determine the number of the AG context REG-pairs written back; when the Reg1WbFlg isn't set.
#define UCM_REG_STOP_DONE_HDR 0xe00e0UL //ACCESS:RW DataWidth:0x1c Description: The CM header for Timers expiration command; when Stop Done input bit is set.
#define UCM_REG_INV_CFLG_Q 0xe00e4UL //ACCESS:RW DataWidth:0x2 Description: The queue index for invalidate counter flag decision.
#define UCM_REG_CMP_CFLG_Q 0xe00e8UL //ACCESS:RW DataWidth:0x2 Description: The queue index for comparison counter flag decision.
#define UCM_REG_TX_CFLG_Q 0xe00ecUL //ACCESS:RW DataWidth:0x2 Description: The queue index for tx counter flag decision.
#define UCM_REG_TIMER_CFLG_Q 0xe00f0UL //ACCESS:RW DataWidth:0x2 Description: The queue index for timer counter flag decision.
#define UCM_REG_AUX_CFLG1_Q 0xe00f4UL //ACCESS:RW DataWidth:0x2 Description: The queue index for auxillary counter flag 1 decision.
#define UCM_REG_AUX_CFLG2_Q 0xe00f8UL //ACCESS:RW DataWidth:0x2 Description: The queue index for auxillary counter flag 2 decision.
#define UCM_REG_AUX_CFLG3_Q 0xe00fcUL //ACCESS:RW DataWidth:0x2 Description: The queue index for auxillary counter flag 3 decision.
#define UCM_REG_AUX_CFLG4_Q 0xe0100UL //ACCESS:RW DataWidth:0x2 Description: The queue index for auxillary counter flag 4 decision.
#define UCM_REG_AGG_MISC4_Q 0xe0104UL //ACCESS:RW DataWidth:0x2 Description: The queue index for aggregative miscellaneous 4 decision.
#define UCM_REG_AGG_VAL3_Q 0xe0108UL //ACCESS:RW DataWidth:0x2 Description: The queue index for aggregative value 3 decision.
#define UCM_REG_AGG_VAL2_Q 0xe010cUL //ACCESS:RW DataWidth:0x2 Description: The queue index for aggregative value 2 decision.
#define UCM_REG_PM_RAM_TM 0xe0130UL //ACCESS:RW DataWidth:0x5 Description: TM bits of Pending messages RAM.
#define UCM_REG_SM_CTX0_TM 0xe0134UL //ACCESS:RW DataWidth:0x5 Description: TM bits of STORM context. LSB.
#define UCM_REG_SM_CTX1_TM 0xe0138UL //ACCESS:RW DataWidth:0x4 Description: TM bits of STORM context. LSB.
#define UCM_REG_AG_CTX0_TM 0xe013cUL //ACCESS:RW DataWidth:0x5 Description: TM bits of AG context.
#define UCM_REG_AG_CTX1_TM 0xe0140UL //ACCESS:RW DataWidth:0x5 Description: TM bits of AG context.
#define UCM_REG_GR_ARB_TYPE 0xe0144UL //ACCESS:RW DataWidth:0x1 Description: Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr; ~ucm_registers_gr_ld0_pr.gr_ld0_pr and ~ucm_registers_gr_ld1_pr.gr_ld1_pr.
#define UCM_REG_GR_AG_PR 0xe0148UL //ACCESS:RW DataWidth:0x2 Description: AG channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel group is compliment to the others.
#define UCM_REG_GR_LD0_PR 0xe014cUL //ACCESS:RW DataWidth:0x2 Description: Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel group is compliment to the others.
#define UCM_REG_GR_LD1_PR 0xe0150UL //ACCESS:RW DataWidth:0x2 Description: Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel group is compliment to the others.
#define UCM_REG_STORM_LENGTH_MIS 0xe0154UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the STORM interface is detected.
#define UCM_REG_USDM_LENGTH_MIS 0xe0158UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the SDM interface is detected.
#define UCM_REG_TSEM_LENGTH_MIS 0xe015cUL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the tsem interface is detected.
#define UCM_REG_CSEM_LENGTH_MIS 0xe0160UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the csem interface is detected.
#define UCM_REG_XSEM_LENGTH_MIS 0xe0164UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the xsem interface isdetected.
#define UCM_REG_DORQ_LENGTH_MIS 0xe0168UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the dorq interface is detected.
#define UCM_REG_XX_FREE 0xe016cUL //ACCESS:R DataWidth:0x6 Description: Use to read the XX protection Free counter.
#define UCM_REG_CAM_OCCUP 0xe0170UL //ACCESS:R DataWidth:0x5 Description: Used to read the XX protection CAM occupancy counter.
#define UCM_REG_UNLOCK_MISS 0xe0174UL //ACCESS:RC DataWidth:0x1 Description: Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM; is detected.
#define UCM_REG_UQM_GLB_USE_CNTR 0xe0178UL //ACCESS:R DataWidth:0x1a Description: QM global usage counter. Indicates the balance between QM requests sent and received by the UCM.
#define UCM_REG_CP_BUF_EMPTY 0xe017cUL //ACCESS:R DataWidth:0x1 Description: CP buffer is empty indication.
#define UCM_REG_CP_BUF_STATUS 0xe0180UL //ACCESS:R DataWidth:0x5 Description: CP buffer status.
#define UCM_REG_XX_OVFL_CNTR 0xe0184UL //ACCESS:ST DataWidth:0x10 Description: Counter of XX 0verflow occurencies.
#define UCM_REG_STORM_MSG_CNTR 0xe0188UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the STORM input.
#define UCM_REG_USDM_MSG_CNTR 0xe018cUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input SDM.
#define UCM_REG_TSEM_MSG_CNTR 0xe0190UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input tsem.
#define UCM_REG_CSEM_MSG_CNTR 0xe0194UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input csem.
#define UCM_REG_XSEM_MSG_CNTR 0xe0198UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input xsem.
#define UCM_REG_DORQ_MSG_CNTR 0xe019cUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input dorq.
#define UCM_REG_CP_MSG_CNTR 0xe01a0UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the CP input.
#define UCM_REG_UQM_P_MSG_CNTR 0xe01a4UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the QM input (primary).
#define UCM_REG_UQM_S_MSG_CNTR 0xe01a8UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the QM input (secondary).
#define UCM_REG_TM_MSG_CNTR 0xe01acUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the Timers input.
#define UCM_REG_STORM_OUT_CNTR 0xe01b0UL //ACCESS:ST DataWidth:0x18 Description: Counter of the output messages at FIC0 and FIC1 interfaces.
#define UCM_REG_UQM_OUT_CNTR 0xe01b4UL //ACCESS:ST DataWidth:0x18 Description: Counter of the output QM commands.
#define UCM_REG_TM_OUT_CNTR 0xe01b8UL //ACCESS:ST DataWidth:0x18 Description: Counter of the output Timers commands.
#define UCM_REG_DBG_SELECT 0xe01bcUL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from UCM to the DBG block) - for selecting a line to output to the DBG block.
#define UCM_REG_DBG_BYTE_ENABLE 0xe01c0UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from UCM to the DBG block) - for enabling bytes in the selected line (after the select; before the shift).
#define UCM_REG_DBG_SHIFT 0xe01c4UL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from UCM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define UCM_REG_UCM_INT_STS 0xe01c8UL //ACCESS:R DataWidth:0xb Description: Interrupt register #0 read
#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define UCM_UCM_INT_STS_REG_XX_UQ_ERR (0x1<<1)
#define UCM_UCM_INT_STS_REG_XX_UQ_ERR_SIZE 1
#define UCM_UCM_INT_STS_REG_STORM_ERR (0x1<<2)
#define UCM_UCM_INT_STS_REG_STORM_ERR_SIZE 2
#define UCM_UCM_INT_STS_REG_USDM_ERR (0x1<<3)
#define UCM_UCM_INT_STS_REG_USDM_ERR_SIZE 3
#define UCM_UCM_INT_STS_REG_TSEM_ERR (0x1<<4)
#define UCM_UCM_INT_STS_REG_TSEM_ERR_SIZE 4
#define UCM_UCM_INT_STS_REG_CSEM_ERR (0x1<<5)
#define UCM_UCM_INT_STS_REG_CSEM_ERR_SIZE 5
#define UCM_UCM_INT_STS_REG_XSEM_ERR (0x1<<6)
#define UCM_UCM_INT_STS_REG_XSEM_ERR_SIZE 6
#define UCM_UCM_INT_STS_REG_DORQ_ERR (0x1<<7)
#define UCM_UCM_INT_STS_REG_DORQ_ERR_SIZE 7
#define UCM_UCM_INT_STS_REG_CP0_ERR (0x1<<8)
#define UCM_UCM_INT_STS_REG_CP0_ERR_SIZE 8
#define UCM_UCM_INT_STS_REG_CP1_ERR (0x1<<9)
#define UCM_UCM_INT_STS_REG_CP1_ERR_SIZE 9
#define UCM_UCM_INT_STS_REG_UM_ERR (0x1<<10)
#define UCM_UCM_INT_STS_REG_UM_ERR_SIZE 10
#define UCM_REG_UCM_INT_STS_CLR 0xe01ccUL //ACCESS:RC DataWidth:0xb Description: Interrupt register #0 read clear
#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define UCM_UCM_INT_STS_CLR_REG_XX_UQ_ERR (0x1<<1)
#define UCM_UCM_INT_STS_CLR_REG_XX_UQ_ERR_SIZE 1
#define UCM_UCM_INT_STS_CLR_REG_STORM_ERR (0x1<<2)
#define UCM_UCM_INT_STS_CLR_REG_STORM_ERR_SIZE 2
#define UCM_UCM_INT_STS_CLR_REG_USDM_ERR (0x1<<3)
#define UCM_UCM_INT_STS_CLR_REG_USDM_ERR_SIZE 3
#define UCM_UCM_INT_STS_CLR_REG_TSEM_ERR (0x1<<4)
#define UCM_UCM_INT_STS_CLR_REG_TSEM_ERR_SIZE 4
#define UCM_UCM_INT_STS_CLR_REG_CSEM_ERR (0x1<<5)
#define UCM_UCM_INT_STS_CLR_REG_CSEM_ERR_SIZE 5
#define UCM_UCM_INT_STS_CLR_REG_XSEM_ERR (0x1<<6)
#define UCM_UCM_INT_STS_CLR_REG_XSEM_ERR_SIZE 6
#define UCM_UCM_INT_STS_CLR_REG_DORQ_ERR (0x1<<7)
#define UCM_UCM_INT_STS_CLR_REG_DORQ_ERR_SIZE 7
#define UCM_UCM_INT_STS_CLR_REG_CP0_ERR (0x1<<8)
#define UCM_UCM_INT_STS_CLR_REG_CP0_ERR_SIZE 8
#define UCM_UCM_INT_STS_CLR_REG_CP1_ERR (0x1<<9)
#define UCM_UCM_INT_STS_CLR_REG_CP1_ERR_SIZE 9
#define UCM_UCM_INT_STS_CLR_REG_UM_ERR (0x1<<10)
#define UCM_UCM_INT_STS_CLR_REG_UM_ERR_SIZE 10
#define UCM_REG_UCM_INT_STS_WR 0xe01d0UL //ACCESS:WR DataWidth:0xb Description: Interrupt register #0 bit set or clear
#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define UCM_UCM_INT_STS_WR_REG_XX_UQ_ERR (0x1<<1)
#define UCM_UCM_INT_STS_WR_REG_XX_UQ_ERR_SIZE 1
#define UCM_UCM_INT_STS_WR_REG_STORM_ERR (0x1<<2)
#define UCM_UCM_INT_STS_WR_REG_STORM_ERR_SIZE 2
#define UCM_UCM_INT_STS_WR_REG_USDM_ERR (0x1<<3)
#define UCM_UCM_INT_STS_WR_REG_USDM_ERR_SIZE 3
#define UCM_UCM_INT_STS_WR_REG_TSEM_ERR (0x1<<4)
#define UCM_UCM_INT_STS_WR_REG_TSEM_ERR_SIZE 4
#define UCM_UCM_INT_STS_WR_REG_CSEM_ERR (0x1<<5)
#define UCM_UCM_INT_STS_WR_REG_CSEM_ERR_SIZE 5
#define UCM_UCM_INT_STS_WR_REG_XSEM_ERR (0x1<<6)
#define UCM_UCM_INT_STS_WR_REG_XSEM_ERR_SIZE 6
#define UCM_UCM_INT_STS_WR_REG_DORQ_ERR (0x1<<7)
#define UCM_UCM_INT_STS_WR_REG_DORQ_ERR_SIZE 7
#define UCM_UCM_INT_STS_WR_REG_CP0_ERR (0x1<<8)
#define UCM_UCM_INT_STS_WR_REG_CP0_ERR_SIZE 8
#define UCM_UCM_INT_STS_WR_REG_CP1_ERR (0x1<<9)
#define UCM_UCM_INT_STS_WR_REG_CP1_ERR_SIZE 9
#define UCM_UCM_INT_STS_WR_REG_UM_ERR (0x1<<10)
#define UCM_UCM_INT_STS_WR_REG_UM_ERR_SIZE 10
#define UCM_REG_UCM_INT_MASK 0xe01d4UL //ACCESS:RW DataWidth:0xb Description: Interrupt mask register #0 read/write
#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define UCM_UCM_INT_MASK_REG_XX_UQ_ERR (0x1<<1)
#define UCM_UCM_INT_MASK_REG_XX_UQ_ERR_SIZE 1
#define UCM_UCM_INT_MASK_REG_STORM_ERR (0x1<<2)
#define UCM_UCM_INT_MASK_REG_STORM_ERR_SIZE 2
#define UCM_UCM_INT_MASK_REG_USDM_ERR (0x1<<3)
#define UCM_UCM_INT_MASK_REG_USDM_ERR_SIZE 3
#define UCM_UCM_INT_MASK_REG_TSEM_ERR (0x1<<4)
#define UCM_UCM_INT_MASK_REG_TSEM_ERR_SIZE 4
#define UCM_UCM_INT_MASK_REG_CSEM_ERR (0x1<<5)
#define UCM_UCM_INT_MASK_REG_CSEM_ERR_SIZE 5
#define UCM_UCM_INT_MASK_REG_XSEM_ERR (0x1<<6)
#define UCM_UCM_INT_MASK_REG_XSEM_ERR_SIZE 6
#define UCM_UCM_INT_MASK_REG_DORQ_ERR (0x1<<7)
#define UCM_UCM_INT_MASK_REG_DORQ_ERR_SIZE 7
#define UCM_UCM_INT_MASK_REG_CP0_ERR (0x1<<8)
#define UCM_UCM_INT_MASK_REG_CP0_ERR_SIZE 8
#define UCM_UCM_INT_MASK_REG_CP1_ERR (0x1<<9)
#define UCM_UCM_INT_MASK_REG_CP1_ERR_SIZE 9
#define UCM_UCM_INT_MASK_REG_UM_ERR (0x1<<10)
#define UCM_UCM_INT_MASK_REG_UM_ERR_SIZE 10
#define UCM_REG_UCM_PRTY_STS 0xe01d8UL //ACCESS:R DataWidth:0x1b Description: Parity register #0 read
#define UCM_UCM_PRTY_STS_REG_PARITY (0x1<<0)
#define UCM_UCM_PRTY_STS_REG_PARITY_SIZE 0
#define UCM_UCM_PRTY_STS_REG_XT_PRTY (0x1<<1)
#define UCM_UCM_PRTY_STS_REG_XT_PRTY_SIZE 1
#define UCM_UCM_PRTY_STS_REG_DT_PRTY (0x1<<2)
#define UCM_UCM_PRTY_STS_REG_DT_PRTY_SIZE 2
#define UCM_UCM_PRTY_STS_REG_PM_PRTY0 (0x1<<3)
#define UCM_UCM_PRTY_STS_REG_PM_PRTY0_SIZE 3
#define UCM_UCM_PRTY_STS_REG_PM_PRTY1 (0x1<<4)
#define UCM_UCM_PRTY_STS_REG_PM_PRTY1_SIZE 4
#define UCM_UCM_PRTY_STS_REG_UQ_PRTY (0x1<<5)
#define UCM_UCM_PRTY_STS_REG_UQ_PRTY_SIZE 5
#define UCM_UCM_PRTY_STS_REG_AG_PRTY0 (0x1<<6)
#define UCM_UCM_PRTY_STS_REG_AG_PRTY0_SIZE 6
#define UCM_UCM_PRTY_STS_REG_AG_PRTY1 (0x1<<7)
#define UCM_UCM_PRTY_STS_REG_AG_PRTY1_SIZE 7
#define UCM_UCM_PRTY_STS_REG_AG_PRTY2 (0x1<<8)
#define UCM_UCM_PRTY_STS_REG_AG_PRTY2_SIZE 8
#define UCM_UCM_PRTY_STS_REG_AG_PRTY3 (0x1<<9)
#define UCM_UCM_PRTY_STS_REG_AG_PRTY3_SIZE 9
#define UCM_UCM_PRTY_STS_REG_AG_PRTY4 (0x1<<10)
#define UCM_UCM_PRTY_STS_REG_AG_PRTY4_SIZE 10
#define UCM_UCM_PRTY_STS_REG_AG_PRTY5 (0x1<<11)
#define UCM_UCM_PRTY_STS_REG_AG_PRTY5_SIZE 11
#define UCM_UCM_PRTY_STS_REG_AG_PRTY6 (0x1<<12)
#define UCM_UCM_PRTY_STS_REG_AG_PRTY6_SIZE 12
#define UCM_UCM_PRTY_STS_REG_AG_PRTY7 (0x1<<13)
#define UCM_UCM_PRTY_STS_REG_AG_PRTY7_SIZE 13
#define UCM_UCM_PRTY_STS_REG_SM_PRTY0 (0x1<<14)
#define UCM_UCM_PRTY_STS_REG_SM_PRTY0_SIZE 14
#define UCM_UCM_PRTY_STS_REG_SM_PRTY1 (0x1<<15)
#define UCM_UCM_PRTY_STS_REG_SM_PRTY1_SIZE 15
#define UCM_UCM_PRTY_STS_REG_SM_PRTY2 (0x1<<16)
#define UCM_UCM_PRTY_STS_REG_SM_PRTY2_SIZE 16
#define UCM_UCM_PRTY_STS_REG_SM_PRTY3 (0x1<<17)
#define UCM_UCM_PRTY_STS_REG_SM_PRTY3_SIZE 17
#define UCM_UCM_PRTY_STS_REG_STORM_PRTY (0x1<<18)
#define UCM_UCM_PRTY_STS_REG_STORM_PRTY_SIZE 18
#define UCM_UCM_PRTY_STS_REG_USDM_PRTY (0x1<<19)
#define UCM_UCM_PRTY_STS_REG_USDM_PRTY_SIZE 19
#define UCM_UCM_PRTY_STS_REG_TSEM_PRTY (0x1<<20)
#define UCM_UCM_PRTY_STS_REG_TSEM_PRTY_SIZE 20
#define UCM_UCM_PRTY_STS_REG_CSEM_PRTY (0x1<<21)
#define UCM_UCM_PRTY_STS_REG_CSEM_PRTY_SIZE 21
#define UCM_UCM_PRTY_STS_REG_XSEM_PRTY (0x1<<22)
#define UCM_UCM_PRTY_STS_REG_XSEM_PRTY_SIZE 22
#define UCM_UCM_PRTY_STS_REG_DORQ_PRTY (0x1<<23)
#define UCM_UCM_PRTY_STS_REG_DORQ_PRTY_SIZE 23
#define UCM_UCM_PRTY_STS_REG_CP0_PRTY (0x1<<24)
#define UCM_UCM_PRTY_STS_REG_CP0_PRTY_SIZE 24
#define UCM_UCM_PRTY_STS_REG_CP1_PRTY (0x1<<25)
#define UCM_UCM_PRTY_STS_REG_CP1_PRTY_SIZE 25
#define UCM_UCM_PRTY_STS_REG_UM_PRTY (0x1<<26)
#define UCM_UCM_PRTY_STS_REG_UM_PRTY_SIZE 26
#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dcUL //ACCESS:RC DataWidth:0x1b Description: Parity register #0 read clear
#define UCM_UCM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define UCM_UCM_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define UCM_UCM_PRTY_STS_CLR_REG_XT_PRTY (0x1<<1)
#define UCM_UCM_PRTY_STS_CLR_REG_XT_PRTY_SIZE 1
#define UCM_UCM_PRTY_STS_CLR_REG_DT_PRTY (0x1<<2)
#define UCM_UCM_PRTY_STS_CLR_REG_DT_PRTY_SIZE 2
#define UCM_UCM_PRTY_STS_CLR_REG_PM_PRTY0 (0x1<<3)
#define UCM_UCM_PRTY_STS_CLR_REG_PM_PRTY0_SIZE 3
#define UCM_UCM_PRTY_STS_CLR_REG_PM_PRTY1 (0x1<<4)
#define UCM_UCM_PRTY_STS_CLR_REG_PM_PRTY1_SIZE 4
#define UCM_UCM_PRTY_STS_CLR_REG_UQ_PRTY (0x1<<5)
#define UCM_UCM_PRTY_STS_CLR_REG_UQ_PRTY_SIZE 5
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY0 (0x1<<6)
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY0_SIZE 6
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY1 (0x1<<7)
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY1_SIZE 7
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY2 (0x1<<8)
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY2_SIZE 8
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY3 (0x1<<9)
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY3_SIZE 9
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY4 (0x1<<10)
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY4_SIZE 10
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY5 (0x1<<11)
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY5_SIZE 11
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY6 (0x1<<12)
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY6_SIZE 12
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY7 (0x1<<13)
#define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY7_SIZE 13
#define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY0 (0x1<<14)
#define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY0_SIZE 14
#define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY1 (0x1<<15)
#define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY1_SIZE 15
#define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY2 (0x1<<16)
#define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY2_SIZE 16
#define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY3 (0x1<<17)
#define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY3_SIZE 17
#define UCM_UCM_PRTY_STS_CLR_REG_STORM_PRTY (0x1<<18)
#define UCM_UCM_PRTY_STS_CLR_REG_STORM_PRTY_SIZE 18
#define UCM_UCM_PRTY_STS_CLR_REG_USDM_PRTY (0x1<<19)
#define UCM_UCM_PRTY_STS_CLR_REG_USDM_PRTY_SIZE 19
#define UCM_UCM_PRTY_STS_CLR_REG_TSEM_PRTY (0x1<<20)
#define UCM_UCM_PRTY_STS_CLR_REG_TSEM_PRTY_SIZE 20
#define UCM_UCM_PRTY_STS_CLR_REG_CSEM_PRTY (0x1<<21)
#define UCM_UCM_PRTY_STS_CLR_REG_CSEM_PRTY_SIZE 21
#define UCM_UCM_PRTY_STS_CLR_REG_XSEM_PRTY (0x1<<22)
#define UCM_UCM_PRTY_STS_CLR_REG_XSEM_PRTY_SIZE 22
#define UCM_UCM_PRTY_STS_CLR_REG_DORQ_PRTY (0x1<<23)
#define UCM_UCM_PRTY_STS_CLR_REG_DORQ_PRTY_SIZE 23
#define UCM_UCM_PRTY_STS_CLR_REG_CP0_PRTY (0x1<<24)
#define UCM_UCM_PRTY_STS_CLR_REG_CP0_PRTY_SIZE 24
#define UCM_UCM_PRTY_STS_CLR_REG_CP1_PRTY (0x1<<25)
#define UCM_UCM_PRTY_STS_CLR_REG_CP1_PRTY_SIZE 25
#define UCM_UCM_PRTY_STS_CLR_REG_UM_PRTY (0x1<<26)
#define UCM_UCM_PRTY_STS_CLR_REG_UM_PRTY_SIZE 26
#define UCM_REG_UCM_PRTY_STS_WR 0xe01e0UL //ACCESS:WR DataWidth:0x1b Description: Parity register #0 bit set or clear
#define UCM_UCM_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define UCM_UCM_PRTY_STS_WR_REG_PARITY_SIZE 0
#define UCM_UCM_PRTY_STS_WR_REG_XT_PRTY (0x1<<1)
#define UCM_UCM_PRTY_STS_WR_REG_XT_PRTY_SIZE 1
#define UCM_UCM_PRTY_STS_WR_REG_DT_PRTY (0x1<<2)
#define UCM_UCM_PRTY_STS_WR_REG_DT_PRTY_SIZE 2
#define UCM_UCM_PRTY_STS_WR_REG_PM_PRTY0 (0x1<<3)
#define UCM_UCM_PRTY_STS_WR_REG_PM_PRTY0_SIZE 3
#define UCM_UCM_PRTY_STS_WR_REG_PM_PRTY1 (0x1<<4)
#define UCM_UCM_PRTY_STS_WR_REG_PM_PRTY1_SIZE 4
#define UCM_UCM_PRTY_STS_WR_REG_UQ_PRTY (0x1<<5)
#define UCM_UCM_PRTY_STS_WR_REG_UQ_PRTY_SIZE 5
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY0 (0x1<<6)
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY0_SIZE 6
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY1 (0x1<<7)
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY1_SIZE 7
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY2 (0x1<<8)
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY2_SIZE 8
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY3 (0x1<<9)
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY3_SIZE 9
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY4 (0x1<<10)
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY4_SIZE 10
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY5 (0x1<<11)
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY5_SIZE 11
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY6 (0x1<<12)
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY6_SIZE 12
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY7 (0x1<<13)
#define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY7_SIZE 13
#define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY0 (0x1<<14)
#define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY0_SIZE 14
#define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY1 (0x1<<15)
#define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY1_SIZE 15
#define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY2 (0x1<<16)
#define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY2_SIZE 16
#define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY3 (0x1<<17)
#define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY3_SIZE 17
#define UCM_UCM_PRTY_STS_WR_REG_STORM_PRTY (0x1<<18)
#define UCM_UCM_PRTY_STS_WR_REG_STORM_PRTY_SIZE 18
#define UCM_UCM_PRTY_STS_WR_REG_USDM_PRTY (0x1<<19)
#define UCM_UCM_PRTY_STS_WR_REG_USDM_PRTY_SIZE 19
#define UCM_UCM_PRTY_STS_WR_REG_TSEM_PRTY (0x1<<20)
#define UCM_UCM_PRTY_STS_WR_REG_TSEM_PRTY_SIZE 20
#define UCM_UCM_PRTY_STS_WR_REG_CSEM_PRTY (0x1<<21)
#define UCM_UCM_PRTY_STS_WR_REG_CSEM_PRTY_SIZE 21
#define UCM_UCM_PRTY_STS_WR_REG_XSEM_PRTY (0x1<<22)
#define UCM_UCM_PRTY_STS_WR_REG_XSEM_PRTY_SIZE 22
#define UCM_UCM_PRTY_STS_WR_REG_DORQ_PRTY (0x1<<23)
#define UCM_UCM_PRTY_STS_WR_REG_DORQ_PRTY_SIZE 23
#define UCM_UCM_PRTY_STS_WR_REG_CP0_PRTY (0x1<<24)
#define UCM_UCM_PRTY_STS_WR_REG_CP0_PRTY_SIZE 24
#define UCM_UCM_PRTY_STS_WR_REG_CP1_PRTY (0x1<<25)
#define UCM_UCM_PRTY_STS_WR_REG_CP1_PRTY_SIZE 25
#define UCM_UCM_PRTY_STS_WR_REG_UM_PRTY (0x1<<26)
#define UCM_UCM_PRTY_STS_WR_REG_UM_PRTY_SIZE 26
#define UCM_REG_UCM_PRTY_MASK 0xe01e4UL //ACCESS:RW DataWidth:0x1b Description: Parity mask register #0 read/write
#define UCM_UCM_PRTY_MASK_REG_PARITY (0x1<<0)
#define UCM_UCM_PRTY_MASK_REG_PARITY_SIZE 0
#define UCM_UCM_PRTY_MASK_REG_XT_PRTY (0x1<<1)
#define UCM_UCM_PRTY_MASK_REG_XT_PRTY_SIZE 1
#define UCM_UCM_PRTY_MASK_REG_DT_PRTY (0x1<<2)
#define UCM_UCM_PRTY_MASK_REG_DT_PRTY_SIZE 2
#define UCM_UCM_PRTY_MASK_REG_PM_PRTY0 (0x1<<3)
#define UCM_UCM_PRTY_MASK_REG_PM_PRTY0_SIZE 3
#define UCM_UCM_PRTY_MASK_REG_PM_PRTY1 (0x1<<4)
#define UCM_UCM_PRTY_MASK_REG_PM_PRTY1_SIZE 4
#define UCM_UCM_PRTY_MASK_REG_UQ_PRTY (0x1<<5)
#define UCM_UCM_PRTY_MASK_REG_UQ_PRTY_SIZE 5
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY0 (0x1<<6)
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY0_SIZE 6
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY1 (0x1<<7)
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY1_SIZE 7
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY2 (0x1<<8)
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY2_SIZE 8
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY3 (0x1<<9)
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY3_SIZE 9
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY4 (0x1<<10)
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY4_SIZE 10
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY5 (0x1<<11)
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY5_SIZE 11
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY6 (0x1<<12)
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY6_SIZE 12
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY7 (0x1<<13)
#define UCM_UCM_PRTY_MASK_REG_AG_PRTY7_SIZE 13
#define UCM_UCM_PRTY_MASK_REG_SM_PRTY0 (0x1<<14)
#define UCM_UCM_PRTY_MASK_REG_SM_PRTY0_SIZE 14
#define UCM_UCM_PRTY_MASK_REG_SM_PRTY1 (0x1<<15)
#define UCM_UCM_PRTY_MASK_REG_SM_PRTY1_SIZE 15
#define UCM_UCM_PRTY_MASK_REG_SM_PRTY2 (0x1<<16)
#define UCM_UCM_PRTY_MASK_REG_SM_PRTY2_SIZE 16
#define UCM_UCM_PRTY_MASK_REG_SM_PRTY3 (0x1<<17)
#define UCM_UCM_PRTY_MASK_REG_SM_PRTY3_SIZE 17
#define UCM_UCM_PRTY_MASK_REG_STORM_PRTY (0x1<<18)
#define UCM_UCM_PRTY_MASK_REG_STORM_PRTY_SIZE 18
#define UCM_UCM_PRTY_MASK_REG_USDM_PRTY (0x1<<19)
#define UCM_UCM_PRTY_MASK_REG_USDM_PRTY_SIZE 19
#define UCM_UCM_PRTY_MASK_REG_TSEM_PRTY (0x1<<20)
#define UCM_UCM_PRTY_MASK_REG_TSEM_PRTY_SIZE 20
#define UCM_UCM_PRTY_MASK_REG_CSEM_PRTY (0x1<<21)
#define UCM_UCM_PRTY_MASK_REG_CSEM_PRTY_SIZE 21
#define UCM_UCM_PRTY_MASK_REG_XSEM_PRTY (0x1<<22)
#define UCM_UCM_PRTY_MASK_REG_XSEM_PRTY_SIZE 22
#define UCM_UCM_PRTY_MASK_REG_DORQ_PRTY (0x1<<23)
#define UCM_UCM_PRTY_MASK_REG_DORQ_PRTY_SIZE 23
#define UCM_UCM_PRTY_MASK_REG_CP0_PRTY (0x1<<24)
#define UCM_UCM_PRTY_MASK_REG_CP0_PRTY_SIZE 24
#define UCM_UCM_PRTY_MASK_REG_CP1_PRTY (0x1<<25)
#define UCM_UCM_PRTY_MASK_REG_CP1_PRTY_SIZE 25
#define UCM_UCM_PRTY_MASK_REG_UM_PRTY (0x1<<26)
#define UCM_UCM_PRTY_MASK_REG_UM_PRTY_SIZE 26
#define UCM_REG_SM_CTX01_TM 0xe01e8UL //ACCESS:RW DataWidth:0x4 Description: TM bits of STORM context. MSB.
#define UCM_REG_SM_CTX11_TM 0xe01ecUL //ACCESS:RW DataWidth:0x4 Description: TM bits of STORM context. MSB.
#define UCM_REG_IS_UM_TM 0xe01f0UL //ACCESS:RW DataWidth:0x2 Description: TM bits of UM input stage buffer.
#define UCM_REG_IS_STORM_TM 0xe01f4UL //ACCESS:RW DataWidth:0x2 Description: TM bits of STORM input stage buffer.
#define UCM_REG_ECO_RESERVED 0xe01f8UL //ACCESS:RW DataWidth:0x8 Description: chicken bits
#define UCM_REG_IS_CSEM_TM 0xe01fcUL //ACCESS:RW DataWidth:0x2 Description: TM bits of Csem input stage buffer.
#define UCM_REG_IS_TSEM_TM 0xe0274UL //ACCESS:RW DataWidth:0x2 Description: TM bits of Csem input stage buffer.
#define UCM_REG_IS_XSEM_TM 0xe0278UL //ACCESS:RW DataWidth:0x2 Description: TM bits of Csem input stage buffer.
#define UCM_REG_UM_FIC1_FORCE 0xe0400UL //ACCESS:RW DataWidth:0x1 Description: 0-messages unlocked from Pending messages RAM go to the FIC for which they were designated in input message; 1-messages unlocked from Pending messages RAM are forced to FIC1 whether they were destined to FIC0 or FIC1 in original message.
#define UCM_REG_PHYS_QNUM0_0 0xe0110UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 0 per port index (CID[23])
#define UCM_REG_PHYS_QNUM0_0_SIZE 1
#define UCM_REG_PHYS_QNUM0_1 0xe0114UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 0 per port index (CID[23])
#define UCM_REG_PHYS_QNUM0_1_SIZE 1
#define UCM_REG_PHYS_QNUM1_0 0xe0118UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 1 per port index (CID[23])
#define UCM_REG_PHYS_QNUM1_0_SIZE 1
#define UCM_REG_PHYS_QNUM1_1 0xe011cUL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 1 per port index (CID[23])
#define UCM_REG_PHYS_QNUM1_1_SIZE 1
#define UCM_REG_PHYS_QNUM2_0 0xe0120UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 2 per port index (CID[23])
#define UCM_REG_PHYS_QNUM2_0_SIZE 1
#define UCM_REG_PHYS_QNUM2_1 0xe0124UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 2 per port index (CID[23])
#define UCM_REG_PHYS_QNUM2_1_SIZE 1
#define UCM_REG_PHYS_QNUM3_0 0xe0128UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 3 per port index (CID[23])
#define UCM_REG_PHYS_QNUM3_0_SIZE 1
#define UCM_REG_PHYS_QNUM3_1 0xe012cUL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 3 per port index (CID[23])
#define UCM_REG_PHYS_QNUM3_1_SIZE 1
#define UCM_REG_CAM_OCCUP_ST 0xe0200UL //ACCESS:RW DataWidth:0x5 Description: CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.
#define UCM_REG_CAM_OCCUP_ST_SIZE 1
#define UCM_REG_CFC_INIT_CRD 0xe0204UL //ACCESS:RW DataWidth:0x4 Description: CFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 1 at start-up.
#define UCM_REG_CFC_INIT_CRD_SIZE 1
#define UCM_REG_CP_MSG 0xe0208UL //ACCESS:W DataWidth:0x20 Description: Used to write the CP message.
#define UCM_REG_CP_MSG_SIZE 1
#define UCM_REG_FIC0_INIT_CRD 0xe020cUL //ACCESS:RW DataWidth:0x8 Description: FIC0 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up.
#define UCM_REG_FIC0_INIT_CRD_SIZE 1
#define UCM_REG_FIC1_INIT_CRD 0xe0210UL //ACCESS:RW DataWidth:0x8 Description: FIC1 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up.
#define UCM_REG_FIC1_INIT_CRD_SIZE 1
#define UCM_REG_GLB_CNT_STICKY 0xe0214UL //ACCESS:RW DataWidth:0x1a Description: QM global usage counter maximum sticky value.
#define UCM_REG_GLB_CNT_STICKY_SIZE 1
#define UCM_REG_LL_SZ_STICKY 0xe0218UL //ACCESS:RW DataWidth:0x6 Description: XX LL maximum value ever reached sticky value for any connection. The write to the register is performed by the XX internal circuitry.
#define UCM_REG_LL_SZ_STICKY_SIZE 1
#define UCM_REG_TM_INIT_CRD 0xe021cUL //ACCESS:RW DataWidth:0x4 Description: Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 4 at start-up.
#define UCM_REG_TM_INIT_CRD_SIZE 1
#define UCM_REG_UQM_INIT_CRD 0xe0220UL //ACCESS:RW DataWidth:0x6 Description: QM output initial credit. Max credit available - 32.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 32 at start-up.
#define UCM_REG_UQM_INIT_CRD_SIZE 1
#define UCM_REG_XX_INIT_CRD 0xe0224UL //ACCESS:RW DataWidth:0x6 Description: Initial value for the credit counter; responsible for fulfilling of the Input Stage XX protection buffer by the XX protection pending messages. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 12 at start-up.
#define UCM_REG_XX_INIT_CRD_SIZE 1
#define UCM_REG_XX_MSG_NUM 0xe0228UL //ACCESS:RW DataWidth:0x6 Description: The maximum number of pending messages; which may be stored in XX protection. ~ucm_registers_xx_free.xx_free is also written on write.
#define UCM_REG_XX_MSG_NUM_SIZE 1
#define UCM_REG_LCID_CAM_0 0xe022cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_0_SIZE 1
#define UCM_REG_LCID_CAM_1 0xe0230UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_1_SIZE 1
#define UCM_REG_LCID_CAM_2 0xe0234UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_2_SIZE 1
#define UCM_REG_LCID_CAM_3 0xe0238UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_3_SIZE 1
#define UCM_REG_LCID_CAM_4 0xe023cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_4_SIZE 1
#define UCM_REG_LCID_CAM_5 0xe0240UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_5_SIZE 1
#define UCM_REG_LCID_CAM_6 0xe0244UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_6_SIZE 1
#define UCM_REG_LCID_CAM_7 0xe0248UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_7_SIZE 1
#define UCM_REG_LCID_CAM_8 0xe024cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_8_SIZE 1
#define UCM_REG_LCID_CAM_9 0xe0250UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_9_SIZE 1
#define UCM_REG_LCID_CAM_10 0xe0254UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_10_SIZE 1
#define UCM_REG_LCID_CAM_11 0xe0258UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_11_SIZE 1
#define UCM_REG_LCID_CAM_12 0xe025cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_12_SIZE 1
#define UCM_REG_LCID_CAM_13 0xe0260UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_13_SIZE 1
#define UCM_REG_LCID_CAM_14 0xe0264UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_14_SIZE 1
#define UCM_REG_LCID_CAM_15 0xe0268UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_15_SIZE 1
#define UCM_REG_LCID_CAM_16 0xe026cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_16_SIZE 1
#define UCM_REG_LCID_CAM_17 0xe0270UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define UCM_REG_LCID_CAM_17_SIZE 1
#define UCM_REG_XX_DESCR_TABLE 0xe0280UL //ACCESS:RW DataWidth:0x14 Description: Indirect access to the descriptor table of the XX protection mechanism. The fields are:[5:0] - message length;[14:6] - message pointer;[19:15] - next pointer.
#define UCM_REG_XX_DESCR_TABLE_SIZE 27
#define UCM_REG_XX_TABLE 0xe0300UL //ACCESS:RW DataWidth:0x10 Description: Indirect access to the XX table of the XX protection mechanism. The fields are: [4:0] - tail pointer;[10:5] - Link List size;[15:11] - header pointer.
#define UCM_REG_XX_TABLE_SIZE 18
#define UCM_REG_XX_PEND_MSG 0xe1000UL //ACCESS:RW DataWidth:0x20 Description: Indirect access to the Pending messages RAM of the XX protection mechanism. Bit [0] stands for one of two REGs in the row; bits [9:1] stand for the row in the memory.
#define UCM_REG_XX_PEND_MSG_SIZE 756
#define UCM_REG_AG_CTX 0xe2000UL //ACCESS:RW DataWidth:0x20 Description: Indirect access to AG context with 32-bits granularity. The bits [10:8] of the address should be the offset within the accessed LCID context; the bits [7:0] are the accessed LCID.Example: to write to REG10 LCID100. The RBC address should be 12'ha64.
#define UCM_REG_AG_CTX_SIZE 2048
#define UCM_REG_STORM_CTX 0xf0000UL //ACCESS:RW DataWidth:0x20 Description: Indirect access to STORM context with 32-bits granularity. The bits [13:8] of the address should be the offset within the accessed LCID context; the bits [7:0] are the accessed LCID.Example: to write to REG10 LCID100. The RBC address should be 13'ha64.
#define UCM_REG_STORM_CTX_SIZE 16384
#define UCM_REG_UCM_UNUSED_EMPTY_0 0xe027cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define UCM_REG_UCM_UNUSED_EMPTY_0_SIZE 1
#define UCM_REG_UCM_UNUSED_EMPTY_1 0xe0380UL //ACCESS:R DataWidth:0x20 Unused empty space
#define UCM_REG_UCM_UNUSED_EMPTY_1_SIZE 32
#define UCM_REG_UCM_UNUSED_EMPTY_2 0xe0404UL //ACCESS:R DataWidth:0x20 Unused empty space
#define UCM_REG_UCM_UNUSED_EMPTY_2_SIZE 767
#define UCM_REG_UCM_UNUSED_EMPTY_3 0xe4000UL //ACCESS:R DataWidth:0x20 Unused empty space
#define UCM_REG_UCM_UNUSED_EMPTY_3_SIZE 12288
#define UMAC_REG_IPG_HD_BKP_CNTL 0x4UL //ACCESS:RW DataWidth:0x7 Multi Field Register
#define UMAC_IPG_HD_BKP_CNTL_REG_HD_FC_ENA (0x1<<0)
#define UMAC_IPG_HD_BKP_CNTL_REG_HD_FC_ENA_SIZE 0
#define UMAC_IPG_HD_BKP_CNTL_REG_HD_FC_BKOFF_OK (0x1<<1)
#define UMAC_IPG_HD_BKP_CNTL_REG_HD_FC_BKOFF_OK_SIZE 1
#define UMAC_IPG_HD_BKP_CNTL_REG_IPG_CONFIG_RX (0x1f<<2)
#define UMAC_IPG_HD_BKP_CNTL_REG_IPG_CONFIG_RX_SIZE 2
#define UMAC_REG_COMMAND_CONFIG 0x8UL //ACCESS:RW DataWidth:0x1f Multi Field Register
#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
#define UMAC_COMMAND_CONFIG_REG_TX_ENA_SIZE 0
#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
#define UMAC_COMMAND_CONFIG_REG_RX_ENA_SIZE 1
#define UMAC_COMMAND_CONFIG_REG_ETH_SPEED (0x3<<2)
#define UMAC_COMMAND_CONFIG_REG_ETH_SPEED_SIZE 2
#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN_SIZE 4
#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
#define UMAC_COMMAND_CONFIG_REG_PAD_EN_SIZE 5
#define UMAC_COMMAND_CONFIG_REG_CRC_FWD (0x1<<6)
#define UMAC_COMMAND_CONFIG_REG_CRC_FWD_SIZE 6
#define UMAC_COMMAND_CONFIG_REG_PAUSE_FWD (0x1<<7)
#define UMAC_COMMAND_CONFIG_REG_PAUSE_FWD_SIZE 7
#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8)
#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE_SIZE 8
#define UMAC_COMMAND_CONFIG_REG_TX_ADDR_INS (0x1<<9)
#define UMAC_COMMAND_CONFIG_REG_TX_ADDR_INS_SIZE 9
#define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10)
#define UMAC_COMMAND_CONFIG_REG_HD_ENA_SIZE 10
#define UMAC_COMMAND_CONFIG_REG_RX_LOW_LATENCY_EN (0x1<<11)
#define UMAC_COMMAND_CONFIG_REG_RX_LOW_LATENCY_EN_SIZE 11
#define UMAC_COMMAND_CONFIG_REG_OVERFLOW_EN (0x1<<12)
#define UMAC_COMMAND_CONFIG_REG_OVERFLOW_EN_SIZE 12
#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
#define UMAC_COMMAND_CONFIG_REG_SW_RESET_SIZE 13
#define UMAC_COMMAND_CONFIG_REG_FCS_CORRUPT_URUN_EN (0x1<<14)
#define UMAC_COMMAND_CONFIG_REG_FCS_CORRUPT_URUN_EN_SIZE 14
#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA_SIZE 15
#define UMAC_COMMAND_CONFIG_REG_MAC_LOOP_CON (0x1<<16)
#define UMAC_COMMAND_CONFIG_REG_MAC_LOOP_CON_SIZE 16
#define UMAC_COMMAND_CONFIG_REG_SW_OVERRIDE_TX (0x1<<17)
#define UMAC_COMMAND_CONFIG_REG_SW_OVERRIDE_TX_SIZE 17
#define UMAC_COMMAND_CONFIG_REG_SW_OVERRIDE_RX (0x1<<18)
#define UMAC_COMMAND_CONFIG_REG_SW_OVERRIDE_RX_SIZE 18
#define UMAC_COMMAND_CONFIG_REG_UNUSED_0 (0x3<<19)
#define UMAC_COMMAND_CONFIG_REG_UNUSED_0_SIZE 19
#define UMAC_COMMAND_CONFIG_REG_EN_INTERNAL_TX_CRS (0x1<<21)
#define UMAC_COMMAND_CONFIG_REG_EN_INTERNAL_TX_CRS_SIZE 21
#define UMAC_COMMAND_CONFIG_REG_ENA_EXT_CONFIG (0x1<<22)
#define UMAC_COMMAND_CONFIG_REG_ENA_EXT_CONFIG_SIZE 22
#define UMAC_COMMAND_CONFIG_REG_CNTL_FRM_ENA (0x1<<23)
#define UMAC_COMMAND_CONFIG_REG_CNTL_FRM_ENA_SIZE 23
#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK_SIZE 24
#define UMAC_COMMAND_CONFIG_REG_LINE_LOOPBACK (0x1<<25)
#define UMAC_COMMAND_CONFIG_REG_LINE_LOOPBACK_SIZE 25
#define UMAC_COMMAND_CONFIG_REG_RX_ERR_DISC (0x1<<26)
#define UMAC_COMMAND_CONFIG_REG_RX_ERR_DISC_SIZE 26
#define UMAC_COMMAND_CONFIG_REG_PRBL_ENA (0x1<<27)
#define UMAC_COMMAND_CONFIG_REG_PRBL_ENA_SIZE 27
#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28)
#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE_SIZE 28
#define UMAC_COMMAND_CONFIG_REG_UNUSED_1 (0x1<<29)
#define UMAC_COMMAND_CONFIG_REG_UNUSED_1_SIZE 29
#define UMAC_COMMAND_CONFIG_REG_RUNT_FILTER_DIS (0x1<<30)
#define UMAC_COMMAND_CONFIG_REG_RUNT_FILTER_DIS_SIZE 30
#define UMAC_REG_MAC_ADDR0 0xcUL //ACCESS:RW DataWidth:0x20 Description: Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers to bit 17 of the MAC address etc.
#define UMAC_REG_MAC_ADDR1 0x10UL //ACCESS:RW DataWidth:0x10 Description: Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved.
#define UMAC_REG_MAXFR 0x14UL //ACCESS:RW DataWidth:0xe Description: Defines a 14-Bit maximum frame length used by the MAC receive logic to check frames.
#define UMAC_REG_STAD2 0x18UL //ACCESS:RW DataWidth:0x10 Description: 16-Bit value; sets; in increment of 512 Ethernet bit times; the pause quanta used in each Pause Frame sent to the remote Ethernet device.
#define UMAC_REG_TX_TS_SEQ_ID 0x3cUL //ACCESS:RW DataWidth:0x11 Multi Field Register
#define UMAC_TX_TS_SEQ_ID_REG_TSTS_SEQ_ID (0xffff<<0)
#define UMAC_TX_TS_SEQ_ID_REG_TSTS_SEQ_ID_SIZE 0
#define UMAC_TX_TS_SEQ_ID_REG_TSTS_VALID (0x1<<16)
#define UMAC_TX_TS_SEQ_ID_REG_TSTS_VALID_SIZE 16
#define UMAC_REG_SFD_OFFSET 0x40UL //ACCESS:RW DataWidth:0x4 Description: Defines the length of the EFM preamble between 5 and 15 Bytes. When set to 0; 1; 2; 3 or 4; the Preamble EFM length is set to 5 Bytes.
#define UMAC_REG_MAC_MODE 0x44UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define UMAC_MAC_MODE_REG_MAC_SPEED (0x3<<0)
#define UMAC_MAC_MODE_REG_MAC_SPEED_SIZE 0
#define UMAC_MAC_MODE_REG_MAC_DUPLEX (0x1<<2)
#define UMAC_MAC_MODE_REG_MAC_DUPLEX_SIZE 2
#define UMAC_MAC_MODE_REG_MAC_RX_PAUSE (0x1<<3)
#define UMAC_MAC_MODE_REG_MAC_RX_PAUSE_SIZE 3
#define UMAC_MAC_MODE_REG_MAC_TX_PAUSE (0x1<<4)
#define UMAC_MAC_MODE_REG_MAC_TX_PAUSE_SIZE 4
#define UMAC_MAC_MODE_REG_LINK_STATUS (0x1<<5)
#define UMAC_MAC_MODE_REG_LINK_STATUS_SIZE 5
#define UMAC_REG_TAG_0 0x48UL //ACCESS:RW DataWidth:0x11 Multi Field Register
#define UMAC_TAG_0_REG_FRM_TAG_0 (0xffff<<0)
#define UMAC_TAG_0_REG_FRM_TAG_0_SIZE 0
#define UMAC_TAG_0_REG_CONFIG_OUTER_TPID_ENABLE (0x1<<16)
#define UMAC_TAG_0_REG_CONFIG_OUTER_TPID_ENABLE_SIZE 16
#define UMAC_REG_TAG_1 0x4cUL //ACCESS:RW DataWidth:0x11 Multi Field Register
#define UMAC_TAG_1_REG_FRM_TAG_1 (0xffff<<0)
#define UMAC_TAG_1_REG_FRM_TAG_1_SIZE 0
#define UMAC_TAG_1_REG_CONFIG_INNER_TPID_ENABLE (0x1<<16)
#define UMAC_TAG_1_REG_CONFIG_INNER_TPID_ENABLE_SIZE 16
#define UMAC_REG_RX_PAUSE_QUANTA_SCALE 0x50UL //ACCESS:RW DataWidth:0x12 Multi Field Register
#define UMAC_RX_PAUSE_QUANTA_SCALE_REG_SCALE_VALUE (0xffff<<0)
#define UMAC_RX_PAUSE_QUANTA_SCALE_REG_SCALE_VALUE_SIZE 0
#define UMAC_RX_PAUSE_QUANTA_SCALE_REG_SCALE_CONTROL (0x1<<16)
#define UMAC_RX_PAUSE_QUANTA_SCALE_REG_SCALE_CONTROL_SIZE 16
#define UMAC_RX_PAUSE_QUANTA_SCALE_REG_SCALE_FIX (0x1<<17)
#define UMAC_RX_PAUSE_QUANTA_SCALE_REG_SCALE_FIX_SIZE 17
#define UMAC_REG_TX_PREAMBLE 0x54UL //ACCESS:RW DataWidth:0x3 Description: Set the transmit preamble excluding SFD to be programmable from min of 2 bytes to the max allowable of 7 bytes; with granularity of 1 byte.
#define UMAC_REG_TX_IPG_LENGTH 0x5cUL //ACCESS:RW DataWidth:0x7 Description: Set the Transmit minimum IPG from 8 to 64 Byte-times. If a value below 8 or above 64 is programmed; the minimum IPG is set to 12 byte-times.
#define UMAC_REG_PFC_XOFF_TIMER 0x60UL //ACCESS:RW DataWidth:0x10 Description: Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
#define UMAC_REG_UMAC_EEE_CTRL 0x64UL //ACCESS:RW DataWidth:0x8 Multi Field Register
#define UMAC_UMAC_EEE_CTRL_REG_UNUSED_2 (0x7<<0)
#define UMAC_UMAC_EEE_CTRL_REG_UNUSED_2_SIZE 0
#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1<<3)
#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN_SIZE 3
#define UMAC_UMAC_EEE_CTRL_REG_RX_FIFO_CHECK (0x1<<4)
#define UMAC_UMAC_EEE_CTRL_REG_RX_FIFO_CHECK_SIZE 4
#define UMAC_UMAC_EEE_CTRL_REG_EEE_TXCLK_DIS (0x1<<5)
#define UMAC_UMAC_EEE_CTRL_REG_EEE_TXCLK_DIS_SIZE 5
#define UMAC_UMAC_EEE_CTRL_REG_DIS_EEE_10M (0x1<<6)
#define UMAC_UMAC_EEE_CTRL_REG_DIS_EEE_10M_SIZE 6
#define UMAC_UMAC_EEE_CTRL_REG_LP_IDLE_PREDICTION_MODE (0x1<<7)
#define UMAC_UMAC_EEE_CTRL_REG_LP_IDLE_PREDICTION_MODE_SIZE 7
#define UMAC_REG_EEE_LPI_TIMER 0x68UL //ACCESS:RW DataWidth:0x20 Description: This is the duration for which condition to move to LPI state must be satisfied; at the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second.
#define UMAC_REG_EEE_WAKE_TIMER 0x6cUL //ACCESS:RW DataWidth:0x10 Description: This is the duration for which MAC must wait to go back to ACTIVE state from LPI state when it receives packet for transmission. The decrement unit is 1 micro-second.
#define UMAC_REG_EEE_REF_COUNT 0x70UL //ACCESS:RW DataWidth:0x10 Description: This field controls clock divider used to generate ~1us reference pulses used by EEE timers. It specifies integer number of timer clock cycles contained within 1us. We may consider having 0.5us reference; as timeout values in 802.3az/D1.3 are not always integer number of 1us.
#define UMAC_REG_UMAC_TIMESTAMP_ADJUST 0x74UL //ACCESS:RW DataWidth:0xb Multi Field Register
#define UMAC_UMAC_TIMESTAMP_ADJUST_REG_ADJUST (0x1ff<<0)
#define UMAC_UMAC_TIMESTAMP_ADJUST_REG_ADJUST_SIZE 0
#define UMAC_UMAC_TIMESTAMP_ADJUST_REG_EN_1588 (0x1<<9)
#define UMAC_UMAC_TIMESTAMP_ADJUST_REG_EN_1588_SIZE 9
#define UMAC_UMAC_TIMESTAMP_ADJUST_REG_AUTO_ADJUST (0x1<<10)
#define UMAC_UMAC_TIMESTAMP_ADJUST_REG_AUTO_ADJUST_SIZE 10
#define UMAC_REG_RX_IPG_INVAL 0x78UL //ACCESS:RW DataWidth:0x1 Description: Debug status; set if MAC receives an IPG less than programmed RX IPG or less than four bytes. Sticky bit. Clears when SW writes 0 into the field or by sw_reset.
#define UMAC_REG_THRESHOLD_VALUE 0x7cUL //ACCESS:RW DataWidth:0x10 Description: If LPI_Prediction is enabled then this register defines the number of IDLEs to be received by the UniMAC before allowing LP_IDLE to be sent to Link Partner.
#define UMAC_REG_PFC_ETH_TYPE 0x300UL //ACCESS:RW DataWidth:0x10 Description: These 16 bits are for programmable ethertype in PFC. Since PFC is not standardized yet; the ethertype must be programmable to make sure that when it gets standardized; we can be standards compliant.
#define UMAC_REG_PFC_OPCODE 0x304UL //ACCESS:RW DataWidth:0x10 Description: These 16 bits are for opcode. Since PFC is not standardized yet; the opcode must be programmable to make sure that when it gets standardized; we can be standards compliant.
#define UMAC_REG_PFC_MACDA_0 0x308UL //ACCESS:RW DataWidth:0x20 Description: Lower 32 bits of programmable DA for PPP. Since PPP is not standardized yet; the DA must be programmable to make sure that when it gets standardized; we can be standards compliant.
#define UMAC_REG_PFC_MACDA_1 0x30cUL //ACCESS:RW DataWidth:0x10 Description: Upper 16 bits of programmable DA for PPP. Since PPP is not standardized yet; the DA must be programmable to make sure that when it gets standardized; we can be standards compliant.
#define UMAC_REG_MACSEC_PROG_TX_CRC 0x310UL //ACCESS:RW DataWidth:0x20 Description: The transmitted CRC can be corrupted by replacing the FCS of the transmitted frame by the FCS programmed in this register. This is enabled and controlled by MACSEC_CNTRL register.
#define UMAC_REG_MACSEC_CNTRL 0x314UL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define UMAC_MACSEC_CNTRL_REG_TX_LAUNCH_EN (0x1<<0)
#define UMAC_MACSEC_CNTRL_REG_TX_LAUNCH_EN_SIZE 0
#define UMAC_MACSEC_CNTRL_REG_TX_CRC_CORUPT_EN (0x1<<1)
#define UMAC_MACSEC_CNTRL_REG_TX_CRC_CORUPT_EN_SIZE 1
#define UMAC_MACSEC_CNTRL_REG_TX_CRC_PROGRAM (0x1<<2)
#define UMAC_MACSEC_CNTRL_REG_TX_CRC_PROGRAM_SIZE 2
#define UMAC_MACSEC_CNTRL_REG_DIS_PAUSE_DATA_VAR_IPG (0x1<<3)
#define UMAC_MACSEC_CNTRL_REG_DIS_PAUSE_DATA_VAR_IPG_SIZE 3
#define UMAC_REG_TS_STATUS_CNTRL 0x318UL //ACCESS:RW DataWidth:0x5 Multi Field Register
#define UMAC_TS_STATUS_CNTRL_REG_TX_TS_FIFO_FULL (0x1<<0)
#define UMAC_TS_STATUS_CNTRL_REG_TX_TS_FIFO_FULL_SIZE 0
#define UMAC_TS_STATUS_CNTRL_REG_TX_TS_FIFO_EMPTY (0x1<<1)
#define UMAC_TS_STATUS_CNTRL_REG_TX_TS_FIFO_EMPTY_SIZE 1
#define UMAC_TS_STATUS_CNTRL_REG_WORD_AVAIL (0x7<<2)
#define UMAC_TS_STATUS_CNTRL_REG_WORD_AVAIL_SIZE 2
#define UMAC_REG_TX_TS_DATA 0x31cUL //ACCESS:RW DataWidth:0x20 Description: Every read of this register will fetch out one timestamp value corresponding to the preceding seq_id read from the transmit FIFO. Every 49 bit; val_bit + seq_id + timestamp is read in two steps; i.e.; one read from 0x10f (val_bit + seq_id) followed by another read from 0x1c7 (timestamp). Timestamp read without a preceding seq_id read will fetch stale timestamp value.
#define UMAC_REG_PAUSE_CONTROL 0x330UL //ACCESS:RW DataWidth:0x12 Multi Field Register
#define UMAC_PAUSE_CONTROL_REG_VALUE (0x1ffff<<0)
#define UMAC_PAUSE_CONTROL_REG_VALUE_SIZE 0
#define UMAC_PAUSE_CONTROL_REG_ENABLE (0x1<<17)
#define UMAC_PAUSE_CONTROL_REG_ENABLE_SIZE 17
#define UMAC_REG_FLUSH 0x334UL //ACCESS:RW DataWidth:0x1 Description: Flush enable bit to drop out all packets in Tx FIFO without egressing any packets when set.
#define UMAC_REG_RXFIFO_STAT 0x338UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define UMAC_RXFIFO_STAT_REG_RXFIFO_UNDERRUN (0x1<<0)
#define UMAC_RXFIFO_STAT_REG_RXFIFO_UNDERRUN_SIZE 0
#define UMAC_RXFIFO_STAT_REG_RXFIFO_OVERRUN (0x1<<1)
#define UMAC_RXFIFO_STAT_REG_RXFIFO_OVERRUN_SIZE 1
#define UMAC_REG_TXFIFO_STAT 0x33cUL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define UMAC_TXFIFO_STAT_REG_TXFIFO_UNDERRUN (0x1<<0)
#define UMAC_TXFIFO_STAT_REG_TXFIFO_UNDERRUN_SIZE 0
#define UMAC_TXFIFO_STAT_REG_TXFIFO_OVERRUN (0x1<<1)
#define UMAC_TXFIFO_STAT_REG_TXFIFO_OVERRUN_SIZE 1
#define UMAC_REG_MAC_PFC_CTRL 0x340UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define UMAC_MAC_PFC_CTRL_REG_PFC_TX_ENBL (0x1<<0)
#define UMAC_MAC_PFC_CTRL_REG_PFC_TX_ENBL_SIZE 0
#define UMAC_MAC_PFC_CTRL_REG_PFC_RX_ENBL (0x1<<1)
#define UMAC_MAC_PFC_CTRL_REG_PFC_RX_ENBL_SIZE 1
#define UMAC_MAC_PFC_CTRL_REG_FORCE_PFC_XON (0x1<<2)
#define UMAC_MAC_PFC_CTRL_REG_FORCE_PFC_XON_SIZE 2
#define UMAC_MAC_PFC_CTRL_REG_UNUSED_3 (0x1<<3)
#define UMAC_MAC_PFC_CTRL_REG_UNUSED_3_SIZE 3
#define UMAC_MAC_PFC_CTRL_REG_RX_PASS_PFC_FRM (0x1<<4)
#define UMAC_MAC_PFC_CTRL_REG_RX_PASS_PFC_FRM_SIZE 4
#define UMAC_MAC_PFC_CTRL_REG_PFC_STATS_EN (0x1<<5)
#define UMAC_MAC_PFC_CTRL_REG_PFC_STATS_EN_SIZE 5
#define UMAC_REG_MAC_PFC_REFRESH_CTRL 0x344UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define UMAC_MAC_PFC_REFRESH_CTRL_REG_PFC_REFRESH_EN (0x1<<0)
#define UMAC_MAC_PFC_REFRESH_CTRL_REG_PFC_REFRESH_EN_SIZE 0
#define UMAC_MAC_PFC_REFRESH_CTRL_REG_UNUSED_4 (0x7fff<<1)
#define UMAC_MAC_PFC_REFRESH_CTRL_REG_UNUSED_4_SIZE 1
#define UMAC_MAC_PFC_REFRESH_CTRL_REG_PFC_REFRESH_TIMER (0xffff<<16)
#define UMAC_MAC_PFC_REFRESH_CTRL_REG_PFC_REFRESH_TIMER_SIZE 16
#define UMAC_REG_UMAC_UNUSED_EMPTY_0 0x1cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define UMAC_REG_UMAC_UNUSED_EMPTY_0_SIZE 8
#define UMAC_REG_UMAC_UNUSED_EMPTY_1 0x58UL //ACCESS:R DataWidth:0x20 Unused empty space
#define UMAC_REG_UMAC_UNUSED_EMPTY_1_SIZE 1
#define UMAC_REG_UMAC_UNUSED_EMPTY_2 0x80UL //ACCESS:R DataWidth:0x20 Unused empty space
#define UMAC_REG_UMAC_UNUSED_EMPTY_2_SIZE 160
#define UMAC_REG_UMAC_UNUSED_EMPTY_3 0x320UL //ACCESS:R DataWidth:0x20 Unused empty space
#define UMAC_REG_UMAC_UNUSED_EMPTY_3_SIZE 4
#define UMAC_REG_UMAC_UNUSED_EMPTY_4 0x348UL //ACCESS:R DataWidth:0x20 Unused empty space
#define UMAC_REG_UMAC_UNUSED_EMPTY_4_SIZE 46
#define USDM_REG_TIMER_TICK 0xc4000UL //ACCESS:RW DataWidth:0x20 Description: Tick for timer counter. Applicable only when ~usdm_registers_timer_tick_enable.timer_tick_enable =1
#define USDM_REG_TIMERS_TICK_ENABLE 0xc4004UL //ACCESS:RW DataWidth:0x1 Description: Enable for tick counter.
#define USDM_REG_CFC_RSP_START_ADDR 0xc4008UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the cfc_rsp lcid
#define USDM_REG_CMP_COUNTER_START_ADDR 0xc400cUL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the completion counters.
#define USDM_REG_Q_COUNTER_START_ADDR 0xc4010UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for queue counters
#define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the packet end message
#define USDM_REG_COUNTERS_WRAP 0xc4018UL //ACCESS:RW DataWidth:0x1 Description: Indicates if the 204 statistics counters should stop counting when reaching an all-ones value or should wrap-around 0=stop counting 1=wrap-around.
#define USDM_REG_CMP_COUNTER_MAX0 0xc401cUL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #0
#define USDM_REG_CMP_COUNTER_MAX1 0xc4020UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #1
#define USDM_REG_CMP_COUNTER_MAX2 0xc4024UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #2
#define USDM_REG_CMP_COUNTER_MAX3 0xc4028UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #3
#define USDM_REG_BRB1_ALMOST_FULL 0xc402cUL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from BRB1 in DMA_RSP block
#define USDM_REG_PXP_ALMOST_FULL 0xc4030UL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from pxp in DMA_RSP block
#define USDM_REG_PB_ALMOST_FULL 0xc4034UL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from PB in DMA_RSP block
#define USDM_REG_AGG_INT_EVENT_0 0xc4038UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 0
#define USDM_REG_AGG_INT_EVENT_1 0xc403cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 1
#define USDM_REG_AGG_INT_EVENT_2 0xc4040UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 2
#define USDM_REG_AGG_INT_EVENT_3 0xc4044UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 3
#define USDM_REG_AGG_INT_EVENT_4 0xc4048UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 4
#define USDM_REG_AGG_INT_EVENT_5 0xc404cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 5
#define USDM_REG_AGG_INT_EVENT_6 0xc4050UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 6
#define USDM_REG_AGG_INT_EVENT_7 0xc4054UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 7
#define USDM_REG_AGG_INT_EVENT_8 0xc4058UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 8
#define USDM_REG_AGG_INT_EVENT_9 0xc405cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 9
#define USDM_REG_AGG_INT_EVENT_10 0xc4060UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 10
#define USDM_REG_AGG_INT_EVENT_11 0xc4064UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 11
#define USDM_REG_AGG_INT_EVENT_12 0xc4068UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 12
#define USDM_REG_AGG_INT_EVENT_13 0xc406cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 13
#define USDM_REG_AGG_INT_EVENT_14 0xc4070UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 14
#define USDM_REG_AGG_INT_EVENT_15 0xc4074UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 15
#define USDM_REG_AGG_INT_EVENT_16 0xc4078UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 16
#define USDM_REG_AGG_INT_EVENT_17 0xc407cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 17
#define USDM_REG_AGG_INT_EVENT_18 0xc4080UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 18
#define USDM_REG_AGG_INT_EVENT_19 0xc4084UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 19
#define USDM_REG_AGG_INT_EVENT_20 0xc4088UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 20
#define USDM_REG_AGG_INT_EVENT_21 0xc408cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 21
#define USDM_REG_AGG_INT_EVENT_22 0xc4090UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 22
#define USDM_REG_AGG_INT_EVENT_23 0xc4094UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 23
#define USDM_REG_AGG_INT_EVENT_24 0xc4098UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 24
#define USDM_REG_AGG_INT_EVENT_25 0xc409cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 25
#define USDM_REG_AGG_INT_EVENT_26 0xc40a0UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 26
#define USDM_REG_AGG_INT_EVENT_27 0xc40a4UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 27
#define USDM_REG_AGG_INT_EVENT_28 0xc40a8UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 28
#define USDM_REG_AGG_INT_EVENT_29 0xc40acUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 29
#define USDM_REG_AGG_INT_EVENT_30 0xc40b0UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 30
#define USDM_REG_AGG_INT_EVENT_31 0xc40b4UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 31
#define USDM_REG_AGG_INT_T_0 0xc40b8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 0
#define USDM_REG_AGG_INT_T_1 0xc40bcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 1
#define USDM_REG_AGG_INT_T_2 0xc40c0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 2
#define USDM_REG_AGG_INT_T_3 0xc40c4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 3
#define USDM_REG_AGG_INT_T_4 0xc40c8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 4
#define USDM_REG_AGG_INT_T_5 0xc40ccUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 5
#define USDM_REG_AGG_INT_T_6 0xc40d0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 6
#define USDM_REG_AGG_INT_T_7 0xc40d4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 7
#define USDM_REG_AGG_INT_T_8 0xc40d8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 8
#define USDM_REG_AGG_INT_T_9 0xc40dcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 9
#define USDM_REG_AGG_INT_T_10 0xc40e0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 10
#define USDM_REG_AGG_INT_T_11 0xc40e4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 11
#define USDM_REG_AGG_INT_T_12 0xc40e8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 12
#define USDM_REG_AGG_INT_T_13 0xc40ecUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 13
#define USDM_REG_AGG_INT_T_14 0xc40f0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 14
#define USDM_REG_AGG_INT_T_15 0xc40f4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 15
#define USDM_REG_AGG_INT_T_16 0xc40f8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 16
#define USDM_REG_AGG_INT_T_17 0xc40fcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 17
#define USDM_REG_AGG_INT_T_18 0xc4100UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 18
#define USDM_REG_AGG_INT_T_19 0xc4104UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 19
#define USDM_REG_AGG_INT_T_20 0xc4108UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 20
#define USDM_REG_AGG_INT_T_21 0xc410cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 21
#define USDM_REG_AGG_INT_T_22 0xc4110UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 22
#define USDM_REG_AGG_INT_T_23 0xc4114UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 23
#define USDM_REG_AGG_INT_T_24 0xc4118UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 24
#define USDM_REG_AGG_INT_T_25 0xc411cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 25
#define USDM_REG_AGG_INT_T_26 0xc4120UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 26
#define USDM_REG_AGG_INT_T_27 0xc4124UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 27
#define USDM_REG_AGG_INT_T_28 0xc4128UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 28
#define USDM_REG_AGG_INT_T_29 0xc412cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 29
#define USDM_REG_AGG_INT_T_30 0xc4130UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 30
#define USDM_REG_AGG_INT_T_31 0xc4134UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 31
#define USDM_REG_AGG_INT_FIC_0 0xc4138UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 0
#define USDM_REG_AGG_INT_FIC_1 0xc413cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 1
#define USDM_REG_AGG_INT_FIC_2 0xc4140UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 2
#define USDM_REG_AGG_INT_FIC_3 0xc4144UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 3
#define USDM_REG_AGG_INT_FIC_4 0xc4148UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 4
#define USDM_REG_AGG_INT_FIC_5 0xc414cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 5
#define USDM_REG_AGG_INT_FIC_6 0xc4150UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 6
#define USDM_REG_AGG_INT_FIC_7 0xc4154UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 7
#define USDM_REG_AGG_INT_FIC_8 0xc4158UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 8
#define USDM_REG_AGG_INT_FIC_9 0xc415cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 9
#define USDM_REG_AGG_INT_FIC_10 0xc4160UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 10
#define USDM_REG_AGG_INT_FIC_11 0xc4164UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 11
#define USDM_REG_AGG_INT_FIC_12 0xc4168UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 12
#define USDM_REG_AGG_INT_FIC_13 0xc416cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 13
#define USDM_REG_AGG_INT_FIC_14 0xc4170UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 14
#define USDM_REG_AGG_INT_FIC_15 0xc4174UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 15
#define USDM_REG_AGG_INT_FIC_16 0xc4178UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 16
#define USDM_REG_AGG_INT_FIC_17 0xc417cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 17
#define USDM_REG_AGG_INT_FIC_18 0xc4180UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 18
#define USDM_REG_AGG_INT_FIC_19 0xc4184UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 19
#define USDM_REG_AGG_INT_FIC_20 0xc4188UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 20
#define USDM_REG_AGG_INT_FIC_21 0xc418cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 21
#define USDM_REG_AGG_INT_FIC_22 0xc4190UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 22
#define USDM_REG_AGG_INT_FIC_23 0xc4194UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 23
#define USDM_REG_AGG_INT_FIC_24 0xc4198UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 24
#define USDM_REG_AGG_INT_FIC_25 0xc419cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 25
#define USDM_REG_AGG_INT_FIC_26 0xc41a0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 26
#define USDM_REG_AGG_INT_FIC_27 0xc41a4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 27
#define USDM_REG_AGG_INT_FIC_28 0xc41a8UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 28
#define USDM_REG_AGG_INT_FIC_29 0xc41acUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 29
#define USDM_REG_AGG_INT_FIC_30 0xc41b0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 30
#define USDM_REG_AGG_INT_FIC_31 0xc41b4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 31
#define USDM_REG_AGG_INT_MODE_0 0xc41b8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_1 0xc41bcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_2 0xc41c0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_3 0xc41c4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_4 0xc41c8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_5 0xc41ccUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_6 0xc41d0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_7 0xc41d4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_8 0xc41d8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_9 0xc41dcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_10 0xc41e0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_11 0xc41e4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_12 0xc41e8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_13 0xc41ecUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_14 0xc41f0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_15 0xc41f4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_16 0xc41f8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (16) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_17 0xc41fcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (17)
#define USDM_REG_AGG_INT_MODE_18 0xc4200UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_19 0xc4204UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_20 0xc4208UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_21 0xc420cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_22 0xc4210UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_23 0xc4214UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_24 0xc4218UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_25 0xc421cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_26 0xc4220UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_27 0xc4224UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_28 0xc4228UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_29 0xc422cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_30 0xc4230UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_AGG_INT_MODE_31 0xc4234UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define USDM_REG_ENABLE_IN1 0xc4238UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define USDM_ENABLE_IN1_REG_EXT_STORE_IN_EN (0x1<<0)
#define USDM_ENABLE_IN1_REG_EXT_STORE_IN_EN_SIZE 0
#define USDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN (0x1<<1)
#define USDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN_SIZE 1
#define USDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN (0x1<<2)
#define USDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN_SIZE 2
#define USDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN (0x1<<3)
#define USDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN_SIZE 3
#define USDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN (0x1<<4)
#define USDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN_SIZE 4
#define USDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN (0x1<<5)
#define USDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN_SIZE 5
#define USDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN (0x1<<6)
#define USDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN_SIZE 6
#define USDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN (0x1<<7)
#define USDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN_SIZE 7
#define USDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN (0x1<<8)
#define USDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN_SIZE 8
#define USDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN (0x1<<9)
#define USDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN_SIZE 9
#define USDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN (0x1<<10)
#define USDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN_SIZE 10
#define USDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN (0x1<<11)
#define USDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN_SIZE 11
#define USDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN (0x1<<12)
#define USDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN_SIZE 12
#define USDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN (0x1<<13)
#define USDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN_SIZE 13
#define USDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN (0x1<<14)
#define USDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN_SIZE 14
#define USDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN (0x1<<15)
#define USDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN_SIZE 15
#define USDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN (0x1<<16)
#define USDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN_SIZE 16
#define USDM_ENABLE_IN1_REG_PB_DATA_IN_EN (0x1<<17)
#define USDM_ENABLE_IN1_REG_PB_DATA_IN_EN_SIZE 17
#define USDM_ENABLE_IN1_REG_PRS_MSG_IN_EN (0x1<<18)
#define USDM_ENABLE_IN1_REG_PRS_MSG_IN_EN_SIZE 18
#define USDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN (0x1<<19)
#define USDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN_SIZE 19
#define USDM_ENABLE_IN1_REG_PXP_REQ_IN_EN (0x1<<20)
#define USDM_ENABLE_IN1_REG_PXP_REQ_IN_EN_SIZE 20
#define USDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN (0x1<<21)
#define USDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN_SIZE 21
#define USDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN (0x1<<22)
#define USDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN_SIZE 22
#define USDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN (0x1<<23)
#define USDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN_SIZE 23
#define USDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN (0x1<<24)
#define USDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN_SIZE 24
#define USDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN (0x1<<25)
#define USDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN_SIZE 25
#define USDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN (0x1<<26)
#define USDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN_SIZE 26
#define USDM_REG_ENABLE_IN2 0xc423cUL //ACCESS:RW DataWidth:0x7 Multi Field Register
#define USDM_ENABLE_IN2_REG_SDM_ACK_IN_EN (0x1<<0)
#define USDM_ENABLE_IN2_REG_SDM_ACK_IN_EN_SIZE 0
#define USDM_ENABLE_IN2_REG_CM_ACK_IN_EN (0x1<<1)
#define USDM_ENABLE_IN2_REG_CM_ACK_IN_EN_SIZE 1
#define USDM_ENABLE_IN2_REG_PB_STATUS_IN_EN (0x1<<2)
#define USDM_ENABLE_IN2_REG_PB_STATUS_IN_EN_SIZE 2
#define USDM_ENABLE_IN2_REG_PB_FULL_IN_EN (0x1<<3)
#define USDM_ENABLE_IN2_REG_PB_FULL_IN_EN_SIZE 3
#define USDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN (0x1<<4)
#define USDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN_SIZE 4
#define USDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN (0x1<<5)
#define USDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN_SIZE 5
#define USDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN (0x1<<6)
#define USDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN_SIZE 6
#define USDM_REG_ENABLE_OUT1 0xc4240UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define USDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN (0x1<<0)
#define USDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN_SIZE 0
#define USDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN (0x1<<1)
#define USDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN_SIZE 1
#define USDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN (0x1<<2)
#define USDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN_SIZE 2
#define USDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN (0x1<<3)
#define USDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN_SIZE 3
#define USDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN (0x1<<4)
#define USDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN_SIZE 4
#define USDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN (0x1<<5)
#define USDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN_SIZE 5
#define USDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN (0x1<<6)
#define USDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN_SIZE 6
#define USDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN (0x1<<7)
#define USDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN_SIZE 7
#define USDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN (0x1<<8)
#define USDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN_SIZE 8
#define USDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN (0x1<<9)
#define USDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN_SIZE 9
#define USDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN (0x1<<10)
#define USDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN_SIZE 10
#define USDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN (0x1<<11)
#define USDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN_SIZE 11
#define USDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN (0x1<<12)
#define USDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN_SIZE 12
#define USDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN (0x1<<13)
#define USDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN_SIZE 13
#define USDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN (0x1<<14)
#define USDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN_SIZE 14
#define USDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN (0x1<<15)
#define USDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN_SIZE 15
#define USDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN (0x1<<16)
#define USDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN_SIZE 16
#define USDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN (0x1<<17)
#define USDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN_SIZE 17
#define USDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN (0x1<<18)
#define USDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN_SIZE 18
#define USDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN (0x1<<19)
#define USDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN_SIZE 19
#define USDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN (0x1<<20)
#define USDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN_SIZE 20
#define USDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN (0x1<<21)
#define USDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN_SIZE 21
#define USDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN (0x1<<22)
#define USDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN_SIZE 22
#define USDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN (0x1<<23)
#define USDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN_SIZE 23
#define USDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN (0x1<<24)
#define USDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN_SIZE 24
#define USDM_ENABLE_OUT1_REG_PB_OUT_EN (0x1<<25)
#define USDM_ENABLE_OUT1_REG_PB_OUT_EN_SIZE 25
#define USDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN (0x1<<26)
#define USDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN_SIZE 26
#define USDM_REG_ENABLE_OUT2 0xc4244UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define USDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN (0x1<<0)
#define USDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN_SIZE 0
#define USDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN (0x1<<1)
#define USDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN_SIZE 1
#define USDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN (0x1<<2)
#define USDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN_SIZE 2
#define USDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN (0x1<<3)
#define USDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN_SIZE 3
#define USDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN (0x1<<4)
#define USDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN_SIZE 4
#define USDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN (0x1<<5)
#define USDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN_SIZE 5
#define USDM_REG_NUM_OF_Q0_CMD 0xc4248UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 0
#define USDM_REG_NUM_OF_Q1_CMD 0xc424cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 1
#define USDM_REG_NUM_OF_Q2_CMD 0xc4250UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 2
#define USDM_REG_NUM_OF_Q3_CMD 0xc4254UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 3
#define USDM_REG_NUM_OF_Q4_CMD 0xc4258UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 4
#define USDM_REG_NUM_OF_Q5_CMD 0xc425cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 5
#define USDM_REG_NUM_OF_Q6_CMD 0xc4260UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 6
#define USDM_REG_NUM_OF_Q7_CMD 0xc4264UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 7
#define USDM_REG_NUM_OF_Q8_CMD 0xc4268UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 8
#define USDM_REG_NUM_OF_Q9_CMD 0xc426cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 9
#define USDM_REG_NUM_OF_Q10_CMD 0xc4270UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 10
#define USDM_REG_NUM_OF_Q11_CMD 0xc4274UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 11
#define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278UL //ACCESS:ST DataWidth:0x20 Description: The number of packet end messages received from the parser
#define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427cUL //ACCESS:ST DataWidth:0x20 Description: The number of requests received from the pxp async if
#define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280UL //ACCESS:ST DataWidth:0x20 Description: The number of ACK after placement messages received
#define USDM_REG_STATISTICS_TM 0xc4284UL //ACCESS:RW DataWidth:0x4 Description: TM bits for statistics sram
#define USDM_REG_DBG_SELECT 0xc4288UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from USDM to the DBG block) - for selecting a line to output to the DBG block
#define USDM_REG_DBG_BYTE_ENABLE 0xc428cUL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from USDM to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define USDM_REG_DBG_SHIFT 0xc4290UL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from USDM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define USDM_REG_USDM_INT_STS_0 0xc4294UL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define USDM_USDM_INT_STS_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define USDM_USDM_INT_STS_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define USDM_USDM_INT_STS_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define USDM_USDM_INT_STS_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define USDM_USDM_INT_STS_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define USDM_USDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define USDM_USDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define USDM_USDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define USDM_USDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define USDM_USDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define USDM_USDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define USDM_USDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define USDM_USDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define USDM_USDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define USDM_USDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define USDM_USDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define USDM_USDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define USDM_USDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define USDM_USDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define USDM_USDM_INT_STS_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define USDM_USDM_INT_STS_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define USDM_USDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define USDM_USDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define USDM_USDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define USDM_USDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define USDM_USDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define USDM_USDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define USDM_USDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define USDM_USDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define USDM_USDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define USDM_USDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define USDM_USDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define USDM_USDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define USDM_USDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define USDM_USDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define USDM_USDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define USDM_USDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define USDM_USDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define USDM_USDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define USDM_REG_USDM_INT_STS_CLR_0 0xc4298UL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define USDM_USDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define USDM_USDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define USDM_USDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define USDM_USDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define USDM_USDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define USDM_USDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define USDM_USDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define USDM_USDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define USDM_USDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define USDM_USDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define USDM_USDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define USDM_USDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define USDM_USDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define USDM_USDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define USDM_USDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define USDM_USDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define USDM_USDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define USDM_USDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define USDM_USDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define USDM_USDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define USDM_USDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define USDM_USDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define USDM_USDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define USDM_USDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define USDM_USDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define USDM_USDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define USDM_USDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define USDM_USDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define USDM_USDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define USDM_USDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define USDM_USDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define USDM_USDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define USDM_USDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define USDM_USDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define USDM_USDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define USDM_USDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define USDM_USDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define USDM_USDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define USDM_REG_USDM_INT_STS_WR_0 0xc429cUL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define USDM_USDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define USDM_USDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define USDM_USDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define USDM_USDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define USDM_USDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define USDM_USDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define USDM_USDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define USDM_USDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define USDM_USDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define USDM_USDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define USDM_USDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define USDM_USDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define USDM_USDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define USDM_USDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define USDM_USDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define USDM_USDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define USDM_USDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define USDM_USDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define USDM_USDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define USDM_USDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define USDM_USDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define USDM_USDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define USDM_USDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define USDM_USDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define USDM_USDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define USDM_USDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define USDM_USDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define USDM_USDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define USDM_USDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define USDM_USDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define USDM_USDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define USDM_USDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define USDM_USDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define USDM_USDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define USDM_USDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define USDM_USDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define USDM_USDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define USDM_USDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define USDM_REG_USDM_INT_MASK_0 0xc42a0UL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define USDM_USDM_INT_MASK_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define USDM_USDM_INT_MASK_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define USDM_USDM_INT_MASK_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define USDM_USDM_INT_MASK_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define USDM_USDM_INT_MASK_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define USDM_USDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define USDM_USDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define USDM_USDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define USDM_USDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define USDM_USDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define USDM_USDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define USDM_USDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define USDM_USDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define USDM_USDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define USDM_USDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define USDM_USDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define USDM_USDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define USDM_USDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define USDM_USDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define USDM_USDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define USDM_USDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define USDM_USDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define USDM_USDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define USDM_USDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define USDM_USDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define USDM_USDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define USDM_USDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define USDM_USDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define USDM_USDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define USDM_USDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define USDM_USDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define USDM_USDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define USDM_USDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define USDM_USDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define USDM_USDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define USDM_USDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define USDM_USDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define USDM_USDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define USDM_USDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define USDM_REG_USDM_INT_STS_1 0xc42a4UL //ACCESS:R DataWidth:0xe Description: Interrupt register #1 read
#define USDM_USDM_INT_STS_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define USDM_USDM_INT_STS_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define USDM_USDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define USDM_USDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define USDM_USDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define USDM_USDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define USDM_USDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define USDM_USDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define USDM_USDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define USDM_USDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define USDM_USDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define USDM_USDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define USDM_USDM_INT_STS_1_REG_CM_DELAY_ERROR (0x1<<6)
#define USDM_USDM_INT_STS_1_REG_CM_DELAY_ERROR_SIZE 6
#define USDM_USDM_INT_STS_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define USDM_USDM_INT_STS_1_REG_PXP_DELAY_ERROR_SIZE 7
#define USDM_USDM_INT_STS_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define USDM_USDM_INT_STS_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define USDM_USDM_INT_STS_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define USDM_USDM_INT_STS_1_REG_TIMER_PEND_ERROR_SIZE 9
#define USDM_USDM_INT_STS_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define USDM_USDM_INT_STS_1_REG_DORQ_DPM_ERROR_SIZE 10
#define USDM_USDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define USDM_USDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define USDM_USDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define USDM_USDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define USDM_USDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define USDM_USDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define USDM_REG_USDM_INT_STS_CLR_1 0xc42a8UL //ACCESS:RC DataWidth:0xe Description: Interrupt register #1 read clear
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define USDM_USDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define USDM_USDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR (0x1<<6)
#define USDM_USDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR_SIZE 6
#define USDM_USDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define USDM_USDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR_SIZE 7
#define USDM_USDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define USDM_USDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define USDM_USDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define USDM_USDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR_SIZE 9
#define USDM_USDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define USDM_USDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR_SIZE 10
#define USDM_USDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define USDM_USDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define USDM_USDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define USDM_USDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define USDM_USDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define USDM_USDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define USDM_REG_USDM_INT_STS_WR_1 0xc42acUL //ACCESS:WR DataWidth:0xe Description: Interrupt register #1 bit set or clear
#define USDM_USDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define USDM_USDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define USDM_USDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define USDM_USDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define USDM_USDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define USDM_USDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define USDM_USDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define USDM_USDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define USDM_USDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define USDM_USDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define USDM_USDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define USDM_USDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define USDM_USDM_INT_STS_WR_1_REG_CM_DELAY_ERROR (0x1<<6)
#define USDM_USDM_INT_STS_WR_1_REG_CM_DELAY_ERROR_SIZE 6
#define USDM_USDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define USDM_USDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR_SIZE 7
#define USDM_USDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define USDM_USDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define USDM_USDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define USDM_USDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR_SIZE 9
#define USDM_USDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define USDM_USDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR_SIZE 10
#define USDM_USDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define USDM_USDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define USDM_USDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define USDM_USDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define USDM_USDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define USDM_USDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define USDM_REG_USDM_INT_MASK_1 0xc42b0UL //ACCESS:RW DataWidth:0xe Description: Interrupt mask register #1 read/write
#define USDM_USDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define USDM_USDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define USDM_USDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define USDM_USDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define USDM_USDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define USDM_USDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define USDM_USDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define USDM_USDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define USDM_USDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define USDM_USDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define USDM_USDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define USDM_USDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define USDM_USDM_INT_MASK_1_REG_CM_DELAY_ERROR (0x1<<6)
#define USDM_USDM_INT_MASK_1_REG_CM_DELAY_ERROR_SIZE 6
#define USDM_USDM_INT_MASK_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define USDM_USDM_INT_MASK_1_REG_PXP_DELAY_ERROR_SIZE 7
#define USDM_USDM_INT_MASK_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define USDM_USDM_INT_MASK_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define USDM_USDM_INT_MASK_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define USDM_USDM_INT_MASK_1_REG_TIMER_PEND_ERROR_SIZE 9
#define USDM_USDM_INT_MASK_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define USDM_USDM_INT_MASK_1_REG_DORQ_DPM_ERROR_SIZE 10
#define USDM_USDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define USDM_USDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define USDM_USDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define USDM_USDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define USDM_USDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define USDM_USDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define USDM_REG_USDM_PRTY_STS 0xc42b4UL //ACCESS:R DataWidth:0xb Description: Parity register #0 read
#define USDM_USDM_PRTY_STS_REG_PARITY (0x1<<0)
#define USDM_USDM_PRTY_STS_REG_PARITY_SIZE 0
#define USDM_USDM_PRTY_STS_REG_TIMERS (0x1<<1)
#define USDM_USDM_PRTY_STS_REG_TIMERS_SIZE 1
#define USDM_USDM_PRTY_STS_REG_INP_QUEUE (0x1<<2)
#define USDM_USDM_PRTY_STS_REG_INP_QUEUE_SIZE 2
#define USDM_USDM_PRTY_STS_REG_ASYNC_RD_DATA (0x1<<3)
#define USDM_USDM_PRTY_STS_REG_ASYNC_RD_DATA_SIZE 3
#define USDM_USDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define USDM_USDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define USDM_USDM_PRTY_STS_REG_BRB1_DP_RD_DATA (0x1<<5)
#define USDM_USDM_PRTY_STS_REG_BRB1_DP_RD_DATA_SIZE 5
#define USDM_USDM_PRTY_STS_REG_PB_RD_DATA (0x1<<6)
#define USDM_USDM_PRTY_STS_REG_PB_RD_DATA_SIZE 6
#define USDM_USDM_PRTY_STS_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define USDM_USDM_PRTY_STS_REG_PXP_CTRL_RD_DATA_SIZE 7
#define USDM_USDM_PRTY_STS_REG_INT_RAM_RD_DATA (0x1<<8)
#define USDM_USDM_PRTY_STS_REG_INT_RAM_RD_DATA_SIZE 8
#define USDM_USDM_PRTY_STS_REG_STAT_RD_DATA (0x1<<9)
#define USDM_USDM_PRTY_STS_REG_STAT_RD_DATA_SIZE 9
#define USDM_USDM_PRTY_STS_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define USDM_USDM_PRTY_STS_REG_CM_QUEUE_RD_DATA_SIZE 10
#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8UL //ACCESS:RC DataWidth:0xb Description: Parity register #0 read clear
#define USDM_USDM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define USDM_USDM_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define USDM_USDM_PRTY_STS_CLR_REG_TIMERS (0x1<<1)
#define USDM_USDM_PRTY_STS_CLR_REG_TIMERS_SIZE 1
#define USDM_USDM_PRTY_STS_CLR_REG_INP_QUEUE (0x1<<2)
#define USDM_USDM_PRTY_STS_CLR_REG_INP_QUEUE_SIZE 2
#define USDM_USDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA (0x1<<3)
#define USDM_USDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA_SIZE 3
#define USDM_USDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define USDM_USDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define USDM_USDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA (0x1<<5)
#define USDM_USDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA_SIZE 5
#define USDM_USDM_PRTY_STS_CLR_REG_PB_RD_DATA (0x1<<6)
#define USDM_USDM_PRTY_STS_CLR_REG_PB_RD_DATA_SIZE 6
#define USDM_USDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define USDM_USDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA_SIZE 7
#define USDM_USDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA (0x1<<8)
#define USDM_USDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA_SIZE 8
#define USDM_USDM_PRTY_STS_CLR_REG_STAT_RD_DATA (0x1<<9)
#define USDM_USDM_PRTY_STS_CLR_REG_STAT_RD_DATA_SIZE 9
#define USDM_USDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define USDM_USDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA_SIZE 10
#define USDM_REG_USDM_PRTY_STS_WR 0xc42bcUL //ACCESS:WR DataWidth:0xb Description: Parity register #0 bit set or clear
#define USDM_USDM_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define USDM_USDM_PRTY_STS_WR_REG_PARITY_SIZE 0
#define USDM_USDM_PRTY_STS_WR_REG_TIMERS (0x1<<1)
#define USDM_USDM_PRTY_STS_WR_REG_TIMERS_SIZE 1
#define USDM_USDM_PRTY_STS_WR_REG_INP_QUEUE (0x1<<2)
#define USDM_USDM_PRTY_STS_WR_REG_INP_QUEUE_SIZE 2
#define USDM_USDM_PRTY_STS_WR_REG_ASYNC_RD_DATA (0x1<<3)
#define USDM_USDM_PRTY_STS_WR_REG_ASYNC_RD_DATA_SIZE 3
#define USDM_USDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define USDM_USDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define USDM_USDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA (0x1<<5)
#define USDM_USDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA_SIZE 5
#define USDM_USDM_PRTY_STS_WR_REG_PB_RD_DATA (0x1<<6)
#define USDM_USDM_PRTY_STS_WR_REG_PB_RD_DATA_SIZE 6
#define USDM_USDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define USDM_USDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA_SIZE 7
#define USDM_USDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA (0x1<<8)
#define USDM_USDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA_SIZE 8
#define USDM_USDM_PRTY_STS_WR_REG_STAT_RD_DATA (0x1<<9)
#define USDM_USDM_PRTY_STS_WR_REG_STAT_RD_DATA_SIZE 9
#define USDM_USDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define USDM_USDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA_SIZE 10
#define USDM_REG_USDM_PRTY_MASK 0xc42c0UL //ACCESS:RW DataWidth:0xb Description: Parity mask register #0 read/write
#define USDM_USDM_PRTY_MASK_REG_PARITY (0x1<<0)
#define USDM_USDM_PRTY_MASK_REG_PARITY_SIZE 0
#define USDM_USDM_PRTY_MASK_REG_TIMERS (0x1<<1)
#define USDM_USDM_PRTY_MASK_REG_TIMERS_SIZE 1
#define USDM_USDM_PRTY_MASK_REG_INP_QUEUE (0x1<<2)
#define USDM_USDM_PRTY_MASK_REG_INP_QUEUE_SIZE 2
#define USDM_USDM_PRTY_MASK_REG_ASYNC_RD_DATA (0x1<<3)
#define USDM_USDM_PRTY_MASK_REG_ASYNC_RD_DATA_SIZE 3
#define USDM_USDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define USDM_USDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define USDM_USDM_PRTY_MASK_REG_BRB1_DP_RD_DATA (0x1<<5)
#define USDM_USDM_PRTY_MASK_REG_BRB1_DP_RD_DATA_SIZE 5
#define USDM_USDM_PRTY_MASK_REG_PB_RD_DATA (0x1<<6)
#define USDM_USDM_PRTY_MASK_REG_PB_RD_DATA_SIZE 6
#define USDM_USDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define USDM_USDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA_SIZE 7
#define USDM_USDM_PRTY_MASK_REG_INT_RAM_RD_DATA (0x1<<8)
#define USDM_USDM_PRTY_MASK_REG_INT_RAM_RD_DATA_SIZE 8
#define USDM_USDM_PRTY_MASK_REG_STAT_RD_DATA (0x1<<9)
#define USDM_USDM_PRTY_MASK_REG_STAT_RD_DATA_SIZE 9
#define USDM_USDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define USDM_USDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA_SIZE 10
#define USDM_REG_CMP_COUNTER_MAX4 0xc42d8UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #4
#define USDM_REG_CMP_COUNTER_MAX5 0xc42dcUL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #5
#define USDM_REG_CMP_COUNTER_MAX6 0xc42e0UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #6
#define USDM_REG_CMP_COUNTER_MAX7 0xc42e4UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #7
#define USDM_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD 0xc42e8UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define USDM_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD 0xc42ecUL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define USDM_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD 0xc42f0UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0]
#define USDM_REG_CPU_MBIST_MEMCTRL_0_STATUS_0 0xc42f4UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits.
#define USDM_REG_CPU_MBIST_MEMCTRL_1_STATUS_0 0xc42f8UL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits.
#define USDM_REG_CPU_MBIST_MEMCTRL_2_STATUS_0 0xc42fcUL //ACCESS:R DataWidth:0x20 Description: Bit 0 - mbist_done; Bit 1 - mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits.
#define USDM_REG_CM_QUEUE_TM 0xc4578UL //ACCESS:RW DataWidth:0x8 Description: TM bits CM_QUEUE
#define USDM_REG_INP_QUEUE_TM 0xc457cUL //ACCESS:RW DataWidth:0x8 Description: TM bits INP_QUEUE
#define USDM_REG_FIFOS_TM 0xc4580UL //ACCESS:RW DataWidth:0x8 Description: TM bits fifos: BRB1_CTRL[1:0]; BRB1_DP[3:2];PB[5:4];PXP_CTRL[7:6]
#define USDM_REG_TIMERS_TM 0xc4584UL //ACCESS:RW DataWidth:0x2 Description: TM bits for timers sram
#define USDM_REG_ECO_RESERVED 0xc4588UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO
#define USDM_REG_AGGREG_INTERRUPT_LSB 0xc4400UL //ACCESS:R DataWidth:0x20 Description: lsb register of aggregated interrupt in sdm_cm block
#define USDM_REG_AGGREG_INTERRUPT_LSB_SIZE 1
#define USDM_REG_AGGREG_INTERRUPT_MSB 0xc4404UL //ACCESS:R DataWidth:0x20 Description: msb register of aggregated interrupt in sdm_cm block
#define USDM_REG_AGGREG_INTERRUPT_MSB_SIZE 1
#define USDM_REG_ASYNC_HOST_EMPTY 0xc4408UL //ACCESS:R DataWidth:0x1 Description: async fifo empty in sdm_async block
#define USDM_REG_ASYNC_HOST_EMPTY_SIZE 1
#define USDM_REG_ASYNC_HOST_FULL 0xc440cUL //ACCESS:R DataWidth:0x1 Description: async fifo full in sdm_async block
#define USDM_REG_ASYNC_HOST_FULL_SIZE 1
#define USDM_REG_CFC_LOAD_PEND_EMPTY 0xc4410UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo empty in sdm_dma_dst block
#define USDM_REG_CFC_LOAD_PEND_EMPTY_SIZE 1
#define USDM_REG_CFC_LOAD_PEND_FULL 0xc4414UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo full in sdm_cfc block
#define USDM_REG_CFC_LOAD_PEND_FULL_SIZE 1
#define USDM_REG_CFC_LOAD_RSP_EMPTY 0xc4418UL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo empty in sdm_dma_dst block
#define USDM_REG_CFC_LOAD_RSP_EMPTY_SIZE 1
#define USDM_REG_CFC_LOAD_RSP_FULL 0xc441cUL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo full in sdm_cfcblock
#define USDM_REG_CFC_LOAD_RSP_FULL_SIZE 1
#define USDM_REG_CM_DELAY_EMPTY 0xc4420UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo empty in sdm_dma_dst block
#define USDM_REG_CM_DELAY_EMPTY_SIZE 1
#define USDM_REG_CM_DELAY_FULL 0xc4424UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo full in sdm_cm block
#define USDM_REG_CM_DELAY_FULL_SIZE 1
#define USDM_REG_CM_QUEUE_EMPTY 0xc4428UL //ACCESS:R DataWidth:0x1 Description: cm queue fifo empty in sdm_dma_dst block
#define USDM_REG_CM_QUEUE_EMPTY_SIZE 1
#define USDM_REG_CM_QUEUE_FULL 0xc442cUL //ACCESS:R DataWidth:0x1 Description: cm queue fifo full in sdm_cm block
#define USDM_REG_CM_QUEUE_FULL_SIZE 1
#define USDM_REG_DELAY_FIFO_EMPTY 0xc4430UL //ACCESS:R DataWidth:0x1 Description: delay FIFO empty in sdm_inp block
#define USDM_REG_DELAY_FIFO_EMPTY_SIZE 1
#define USDM_REG_DELAY_FIFO_FULL 0xc4434UL //ACCESS:R DataWidth:0x1 Description: delay FIFO full in sdm_inp block
#define USDM_REG_DELAY_FIFO_FULL_SIZE 1
#define USDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY 0xc4438UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo empty in sdm_dma_dst block
#define USDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY_SIZE 1
#define USDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL 0xc443cUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo full in sdm_dma_dst block
#define USDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL_SIZE 1
#define USDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY 0xc4440UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo empty in sdm_dma_dst block
#define USDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY_SIZE 1
#define USDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL 0xc4444UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo full in sdm_dma_dst block
#define USDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL_SIZE 1
#define USDM_REG_DST_INT_RAM_IF_FULL 0xc4448UL //ACCESS:R DataWidth:0x1 Description: int_ram if full in sdm_dma_dst block
#define USDM_REG_DST_INT_RAM_IF_FULL_SIZE 1
#define USDM_REG_DST_INT_RAM_WAIT_EMPTY 0xc444cUL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo empty in sdm_dma_dst block
#define USDM_REG_DST_INT_RAM_WAIT_EMPTY_SIZE 1
#define USDM_REG_DST_INT_RAM_WAIT_FULL 0xc4450UL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo full in sdm_dma_dst block
#define USDM_REG_DST_INT_RAM_WAIT_FULL_SIZE 1
#define USDM_REG_DST_NONE_PEND_EMPTY 0xc4454UL //ACCESS:R DataWidth:0x1 Description: none pending fifo empty in sdm_dma_dst block
#define USDM_REG_DST_NONE_PEND_EMPTY_SIZE 1
#define USDM_REG_DST_NONE_PEND_FULL 0xc4458UL //ACCESS:R DataWidth:0x1 Description: none pending fifo full in sdm_dma_dst block
#define USDM_REG_DST_NONE_PEND_FULL_SIZE 1
#define USDM_REG_DST_PAS_BUF_IF_FULL 0xc445cUL //ACCESS:R DataWidth:0x1 Description: pas_buf if full in sdm_dma_dst block
#define USDM_REG_DST_PAS_BUF_IF_FULL_SIZE 1
#define USDM_REG_DST_PAS_BUF_WAIT_EMPTY 0xc4460UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo empty in sdm_dma_dst block
#define USDM_REG_DST_PAS_BUF_WAIT_EMPTY_SIZE 1
#define USDM_REG_DST_PAS_BUF_WAIT_FULL 0xc4464UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo full in sdm_dma_dst block
#define USDM_REG_DST_PAS_BUF_WAIT_FULL_SIZE 1
#define USDM_REG_DST_PB_IF_FULL 0xc4468UL //ACCESS:R DataWidth:0x1 Description: pb if full in sdm_dma_dst block
#define USDM_REG_DST_PB_IF_FULL_SIZE 1
#define USDM_REG_DST_PB_IMMED_EMPTY 0xc446cUL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo empty in sdm_dma_dst block
#define USDM_REG_DST_PB_IMMED_EMPTY_SIZE 1
#define USDM_REG_DST_PB_IMMED_FULL 0xc4470UL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo full in sdm_dma_dst block
#define USDM_REG_DST_PB_IMMED_FULL_SIZE 1
#define USDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY 0xc4474UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo empty in sdm_dma_dst block
#define USDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY_SIZE 1
#define USDM_REG_DST_PXP_CTRL_DST_PEND_FULL 0xc4478UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo full in sdm_dma_dst block
#define USDM_REG_DST_PXP_CTRL_DST_PEND_FULL_SIZE 1
#define USDM_REG_DST_PXP_CTRL_IF_FULL 0xc447cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl if full in sdm_dma_dst block
#define USDM_REG_DST_PXP_CTRL_IF_FULL_SIZE 1
#define USDM_REG_DST_PXP_CTRL_IMMED_EMPTY 0xc4480UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo empty in sdm_dma_dst block
#define USDM_REG_DST_PXP_CTRL_IMMED_EMPTY_SIZE 1
#define USDM_REG_DST_PXP_CTRL_IMMED_FULL 0xc4484UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo full in sdm_dma_dst block
#define USDM_REG_DST_PXP_CTRL_IMMED_FULL_SIZE 1
#define USDM_REG_DST_PXP_CTRL_LINK_EMPTY 0xc4488UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list empty in sdm_dma_dst block
#define USDM_REG_DST_PXP_CTRL_LINK_EMPTY_SIZE 1
#define USDM_REG_DST_PXP_CTRL_LINK_FULL 0xc448cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list full in sdm_dma_dst block
#define USDM_REG_DST_PXP_CTRL_LINK_FULL_SIZE 1
#define USDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY 0xc4490UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo empty in sdm_dma_dst block
#define USDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY_SIZE 1
#define USDM_REG_DST_PXP_CTRL_SRC_PEND_FULL 0xc4494UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo full in sdm_dma_dst block
#define USDM_REG_DST_PXP_CTRL_SRC_PEND_FULL_SIZE 1
#define USDM_REG_DST_PXP_DP_DST_PEND_EMPTY 0xc4498UL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo empty in sdm_dma_dst block
#define USDM_REG_DST_PXP_DP_DST_PEND_EMPTY_SIZE 1
#define USDM_REG_DST_PXP_DP_DST_PEND_FULL 0xc449cUL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo full in sdm_dma_dst block
#define USDM_REG_DST_PXP_DP_DST_PEND_FULL_SIZE 1
#define USDM_REG_DST_PXP_DP_IF_FULL 0xc44a0UL //ACCESS:R DataWidth:0x1 Description: pxp_dp if full in sdm_dma_dst block
#define USDM_REG_DST_PXP_DP_IF_FULL_SIZE 1
#define USDM_REG_DST_PXP_DP_LINK_EMPTY 0xc44a4UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list empty in sdm_dma_dst block
#define USDM_REG_DST_PXP_DP_LINK_EMPTY_SIZE 1
#define USDM_REG_DST_PXP_DP_LINK_FULL 0xc44a8UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list full in sdm_dma_dst block
#define USDM_REG_DST_PXP_DP_LINK_FULL_SIZE 1
#define USDM_REG_INIT_CREDIT_CFC_ACDEC 0xc44acUL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC activity counters interface without receiving any ACK
#define USDM_REG_INIT_CREDIT_CFC_ACDEC_SIZE 1
#define USDM_REG_INIT_CREDIT_CFC_ACINC 0xc44b0UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC activity counters interface without receiving any ACK.
#define USDM_REG_INIT_CREDIT_CFC_ACINC_SIZE 1
#define USDM_REG_INIT_CREDIT_CFC_LOAD 0xc44b4UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC load interface without receiving any ACK.
#define USDM_REG_INIT_CREDIT_CFC_LOAD_SIZE 1
#define USDM_REG_INIT_CREDIT_CFC_PB 0xc44b8UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC activity counters interface 3 without receiving any ACK.
#define USDM_REG_INIT_CREDIT_CFC_PB_SIZE 1
#define USDM_REG_INIT_CREDIT_CM 0xc44bcUL //ACCESS:RW DataWidth:0x4 Description: The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block
#define USDM_REG_INIT_CREDIT_CM_SIZE 1
#define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the pxp control interface without receiving any ACK.
#define USDM_REG_INIT_CREDIT_PXP_CTRL_SIZE 1
#define USDM_REG_INIT_CREDIT_PXP_DP 0xc44c4UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the pxp dp interface without receiving any ACK
#define USDM_REG_INIT_CREDIT_PXP_DP_SIZE 1
#define USDM_REG_INT_RAM_RR_REQ 0xc44c8UL //ACCESS:R DataWidth:0x6 Description: round robin for int_ram arbiter: b0-pas_buf; b1-int_ram;b2-pxp_dp;b3-pxp_ctrl;b4-brb1_ctrl;b5-brb1_dp;
#define USDM_REG_INT_RAM_RR_REQ_SIZE 1
#define USDM_REG_OPERATION_GEN 0xc44ccUL //ACCESS:W DataWidth:0x11 Description: Generate an operation after completion; bit-16 is AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and bits 4:0 are the T124Param[4:0]
#define USDM_REG_OPERATION_GEN_SIZE 1
#define USDM_REG_PB_FULL 0xc44d0UL //ACCESS:R DataWidth:0x1 Description: UPB IF full in sdm_inp block
#define USDM_REG_PB_FULL_SIZE 1
#define USDM_REG_PBF_FULL 0xc44d4UL //ACCESS:R DataWidth:0x1 Description: PBF if full in sdm_inp block
#define USDM_REG_PBF_FULL_SIZE 1
#define USDM_REG_PXP_DELAY_EMPTY 0xc44d8UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo empty in sdm_dma_dst block
#define USDM_REG_PXP_DELAY_EMPTY_SIZE 1
#define USDM_REG_PXP_DELAY_FULL 0xc44dcUL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo full in sdm_cm block
#define USDM_REG_PXP_DELAY_FULL_SIZE 1
#define USDM_REG_QM_FULL 0xc44e0UL //ACCESS:R DataWidth:0x1 Description: QM IF full in sdm_inp block
#define USDM_REG_QM_FULL_SIZE 1
#define USDM_REG_QUEUE_EMPTY 0xc44e4UL //ACCESS:R DataWidth:0xc Description: Input queue fifo empty in sdm_inp block
#define USDM_REG_QUEUE_EMPTY_SIZE 1
#define USDM_REG_QUEUE_FULL 0xc44e8UL //ACCESS:R DataWidth:0xc Description: Input queue fifo full in sdm_inp block
#define USDM_REG_QUEUE_FULL_SIZE 1
#define USDM_REG_RR_CNT_COUNTERS_STATUS 0xc44ecUL //ACCESS:R DataWidth:0x15 Description: round robin for all completion counters
#define USDM_REG_RR_CNT_COUNTERS_STATUS_SIZE 1
#define USDM_REG_RR_COMPLETE_REQ 0xc44f0UL //ACCESS:R DataWidth:0x7 Description: round robin for all completion requests in sdm_cm block: b0-async b1-nop;b2-pxp_int; b3-timers;b4-dma;b5-grc;b6-rbc
#define USDM_REG_RR_COMPLETE_REQ_SIZE 1
#define USDM_REG_RR_PTR_REQ 0xc44f4UL //ACCESS:R DataWidth:0x7 Description: round robin for cm pointer: b0-async; b1-dma_dp; b2 - dma_ctrl; b3-cfc; b4-nop; b5-timers; b6-pxp_int
#define USDM_REG_RR_PTR_REQ_SIZE 1
#define USDM_REG_RSP_BRB1_CTRL_IF_FULL 0xc44f8UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl if is full in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_CTRL_IF_FULL_SIZE 1
#define USDM_REG_RSP_BRB1_CTRL_PEND_EMPTY 0xc44fcUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo empty in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_CTRL_PEND_EMPTY_SIZE 1
#define USDM_REG_RSP_BRB1_CTRL_PEND_FULL 0xc4500UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo full in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_CTRL_PEND_FULL_SIZE 1
#define USDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY 0xc4504UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo empty in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY_SIZE 1
#define USDM_REG_RSP_BRB1_CTRL_RDATA_FULL 0xc4508UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo full in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_CTRL_RDATA_FULL_SIZE 1
#define USDM_REG_RSP_BRB1_DP_DST_EMPTY 0xc450cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo empty in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_DP_DST_EMPTY_SIZE 1
#define USDM_REG_RSP_BRB1_DP_DST_FULL 0xc4510UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo full in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_DP_DST_FULL_SIZE 1
#define USDM_REG_RSP_BRB1_DP_IF_FULL 0xc4514UL //ACCESS:R DataWidth:0x1 Description: brb1_dp if is full in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_DP_IF_FULL_SIZE 1
#define USDM_REG_RSP_BRB1_DP_PEND_EMPTY 0xc4518UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo empty in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_DP_PEND_EMPTY_SIZE 1
#define USDM_REG_RSP_BRB1_DP_PEND_FULL 0xc451cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo full in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_DP_PEND_FULL_SIZE 1
#define USDM_REG_RSP_BRB1_DP_RDATA_EMPTY 0xc4520UL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo empty in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_DP_RDATA_EMPTY_SIZE 1
#define USDM_REG_RSP_BRB1_DP_RDATA_FULL 0xc4524UL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo full in sdm_dma_rsp block
#define USDM_REG_RSP_BRB1_DP_RDATA_FULL_SIZE 1
#define USDM_REG_RSP_INT_RAM_PEND_EMPTY 0xc4528UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo empty in sdm_dma_rsp block
#define USDM_REG_RSP_INT_RAM_PEND_EMPTY_SIZE 1
#define USDM_REG_RSP_INT_RAM_PEND_FULL 0xc452cUL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo full in sdm_dma_rsp block
#define USDM_REG_RSP_INT_RAM_PEND_FULL_SIZE 1
#define USDM_REG_RSP_INT_RAM_RDATA_EMPTY 0xc4530UL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo empty in sdm_dma_rsp block
#define USDM_REG_RSP_INT_RAM_RDATA_EMPTY_SIZE 1
#define USDM_REG_RSP_INT_RAM_RDATA_FULL 0xc4534UL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo full in sdm_dma_rsp block
#define USDM_REG_RSP_INT_RAM_RDATA_FULL_SIZE 1
#define USDM_REG_RSP_PB_IF_FULL 0xc4538UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
#define USDM_REG_RSP_PB_IF_FULL_SIZE 1
#define USDM_REG_RSP_PB_PEND_EMPTY 0xc453cUL //ACCESS:R DataWidth:0x1 Description: pb pending fifo empty in sdm_dma_rsp block
#define USDM_REG_RSP_PB_PEND_EMPTY_SIZE 1
#define USDM_REG_RSP_PB_PEND_FULL 0xc4540UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo full in sdm_dma_rsp block
#define USDM_REG_RSP_PB_PEND_FULL_SIZE 1
#define USDM_REG_RSP_PB_RDATA_EMPTY 0xc4544UL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo empty in sdm_dma_rsp block
#define USDM_REG_RSP_PB_RDATA_EMPTY_SIZE 1
#define USDM_REG_RSP_PB_RDATA_FULL 0xc4548UL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo full in sdm_dma_rsp block
#define USDM_REG_RSP_PB_RDATA_FULL_SIZE 1
#define USDM_REG_RSP_PXP_CTRL_IF_FULL 0xc454cUL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
#define USDM_REG_RSP_PXP_CTRL_IF_FULL_SIZE 1
#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo empty in sdm_dma_rsp block
#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
#define USDM_REG_RSP_PXP_CTRL_RDATA_FULL 0xc4554UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo full in sdm_dma_rsp block
#define USDM_REG_RSP_PXP_CTRL_RDATA_FULL_SIZE 1
#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558UL //ACCESS:R DataWidth:0x1 Description: parser fifo empty in sdm_sync block
#define USDM_REG_SYNC_PARSER_EMPTY_SIZE 1
#define USDM_REG_SYNC_PARSER_FULL 0xc455cUL //ACCESS:R DataWidth:0x1 Description: parser fifo full in sdm_sync block
#define USDM_REG_SYNC_PARSER_FULL_SIZE 1
#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560UL //ACCESS:R DataWidth:0x1 Description: parser serial fifo empty in sdm_sync block
#define USDM_REG_SYNC_SYNC_EMPTY_SIZE 1
#define USDM_REG_SYNC_SYNC_FULL 0xc4564UL //ACCESS:R DataWidth:0x1 Description: parser serial fifo full in sdm_sync block
#define USDM_REG_SYNC_SYNC_FULL_SIZE 1
#define USDM_REG_TIMERS_ADDR_EMPTY 0xc4568UL //ACCESS:R DataWidth:0x1 Description: address FIFO empty in sdm_timers block
#define USDM_REG_TIMERS_ADDR_EMPTY_SIZE 1
#define USDM_REG_TIMERS_ADDR_FULL 0xc456cUL //ACCESS:R DataWidth:0x1 Description: address FIFO full in sdm_timers block
#define USDM_REG_TIMERS_ADDR_FULL_SIZE 1
#define USDM_REG_TIMERS_PEND_EMPTY 0xc4570UL //ACCESS:R DataWidth:0x1 Description: pending FIFO empty in sdm_timers block
#define USDM_REG_TIMERS_PEND_EMPTY_SIZE 1
#define USDM_REG_TIMERS_PEND_FULL 0xc4574UL //ACCESS:R DataWidth:0x1 Description: pending FIFO full in sdm_timers block
#define USDM_REG_TIMERS_PEND_FULL_SIZE 1
#define USDM_REG_STATISTICS 0xc4600UL //ACCESS:RW DataWidth:0x20 Description: Statistics memory. Each read from RBC resets the corresponding statistic counter
#define USDM_REG_STATISTICS_SIZE 48
#define USDM_REG_TIMERS 0xc4800UL //ACCESS:WB DataWidth:0x34 Description: Debug only. Timers memory.
#define USDM_REG_TIMERS_SIZE 108
#define USDM_REG_CM_QUEUE 0xc5000UL //ACCESS:WB DataWidth:0x40 Description: Debug only. CM queue memory.
#define USDM_REG_CM_QUEUE_SIZE 512
#define USDM_REG_INP_QUEUE 0xc5800UL //ACCESS:WB DataWidth:0x40 Description: Debug only. Input queue memory.
#define USDM_REG_INP_QUEUE_SIZE 448
#define USDM_REG_USDM_UNUSED_EMPTY_0 0xc42c4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USDM_REG_USDM_UNUSED_EMPTY_0_SIZE 5
#define USDM_REG_USDM_UNUSED_EMPTY_1 0xc4300UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USDM_REG_USDM_UNUSED_EMPTY_1_SIZE 64
#define USDM_REG_USDM_UNUSED_EMPTY_2 0xc458cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define USDM_REG_USDM_UNUSED_EMPTY_2_SIZE 29
#define USDM_REG_USDM_UNUSED_EMPTY_3 0xc4700UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USDM_REG_USDM_UNUSED_EMPTY_3_SIZE 64
#define USDM_REG_USDM_UNUSED_EMPTY_4 0xc4a00UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USDM_REG_USDM_UNUSED_EMPTY_4_SIZE 384
#define USEM_REG_MSG_NUM_FIC0 0x300000UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that entered through FIC0
#define USEM_REG_MSG_NUM_FIC1 0x300004UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that entered through FIC1
#define USEM_REG_MSG_NUM_FOC0 0x300008UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC0
#define USEM_REG_MSG_NUM_FOC1 0x30000cUL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC1
#define USEM_REG_MSG_NUM_FOC2 0x300010UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC2
#define USEM_REG_MSG_NUM_FOC3 0x300014UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC3
#define USEM_REG_THREAD_INTER_CNT_ENABLE 0x300018UL //ACCESS:RW DataWidth:0x1 Description: Enable for start count of counter ~usem_registers_thread_inter_cnt.thread_inter_cnt
#define USEM_REG_THREAD_INTER_CNT 0x30001cUL //ACCESS:RW DataWidth:0x10 Description: Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter. This register may be used only when ~usem_registers_thread_inter_cnt_enable.thread_inter_cnt_enable =1
#define USEM_REG_ARB_ELEMENT0 0x300020UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 0. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2
#define USEM_REG_ARB_ELEMENT1 0x300024UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 1. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~usem_registers_arb_element0.arb_element0
#define USEM_REG_ARB_ELEMENT2 0x300028UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 2. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~usem_registers_arb_element0.arb_element0 and ~usem_registers_arb_element1.arb_element1
#define USEM_REG_ARB_ELEMENT3 0x30002cUL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 3. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2.Could not be equal to register ~usem_registers_arb_element0.arb_element0 and ~usem_registers_arb_element1.arb_element1 and ~usem_registers_arb_element2.arb_element2
#define USEM_REG_ARB_ELEMENT4 0x300030UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 4. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~usem_registers_arb_element0.arb_element0 and ~usem_registers_arb_element1.arb_element1 and ~usem_registers_arb_element2.arb_element2 and ~usem_registers_arb_element3.arb_element3
#define USEM_REG_ARB_CYCLE_SIZE 0x300034UL //ACCESS:RW DataWidth:0x5 Description: The number of time_slots in the arbitration cycle
#define USEM_REG_TS_0_AS 0x300038UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 0
#define USEM_REG_TS_1_AS 0x30003cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 1
#define USEM_REG_TS_2_AS 0x300040UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 2
#define USEM_REG_TS_3_AS 0x300044UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 3
#define USEM_REG_TS_4_AS 0x300048UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 4
#define USEM_REG_TS_5_AS 0x30004cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 5
#define USEM_REG_TS_6_AS 0x300050UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 6
#define USEM_REG_TS_7_AS 0x300054UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 7
#define USEM_REG_TS_8_AS 0x300058UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 8
#define USEM_REG_TS_9_AS 0x30005cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 9
#define USEM_REG_TS_10_AS 0x300060UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 10
#define USEM_REG_TS_11_AS 0x300064UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 11
#define USEM_REG_TS_12_AS 0x300068UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 12
#define USEM_REG_TS_13_AS 0x30006cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 13
#define USEM_REG_TS_14_AS 0x300070UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 14
#define USEM_REG_TS_15_AS 0x300074UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 15
#define USEM_REG_TS_16_AS 0x300078UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 16
#define USEM_REG_TS_17_AS 0x30007cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 17
#define USEM_REG_TS_18_AS 0x300080UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 18
#define USEM_REG_TS_19_AS 0x300084UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 19
#define USEM_REG_FIC0_MIN_MSG_LINES 0x300088UL //ACCESS:RW DataWidth:0x6 Description: The minimum number of cycles in a message from FIC0 interfaces after which the message can be sent to the passive register_file. It must be always equal to 2; other way it may cause to deadlock in a chip.
#define USEM_REG_FIC1_MIN_MSG_LINES 0x30008cUL //ACCESS:RW DataWidth:0x6 Description: The minimum number of cycles in a message from FIC1 interfaces after which the message can be sent to the passive register_file. It must be always equal to 2; other way it may cause to deadlock in a chip.
#define USEM_REG_PASSIVE_ALM_FULL 0x300090UL //ACCESS:RW DataWidth:0x5 Description: The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted
#define USEM_REG_SYNC_DRA_WR_ALM_FULL 0x300094UL //ACCESS:RW DataWidth:0x5 Description: Almost full for sync dra_wr fifo (data from DRA to STORM)
#define USEM_REG_SYNC_RAM_WR_ALM_FULL 0x300098UL //ACCESS:RW DataWidth:0x6 Description: Almost full for sync ram_wr fifo (data from EXT_IF to STORM)
#define USEM_REG_DBG_ALM_FULL 0x30009cUL //ACCESS:RW DataWidth:0x6 Description: Almost full for slow debug fifo
#define USEM_REG_EXCEPTION_INT 0x3000a0UL //ACCESS:RW DataWidth:0xf Description: The PRAM address for the interrupt in a case the event ID is bigger then the INT table size. This register is always NA because this feature is removed
#define USEM_REG_ENABLE_IN 0x3000a4UL //ACCESS:RW DataWidth:0xf Multi Field Register
#define USEM_ENABLE_IN_REG_FIC0_ENABLE_IN (0x1<<0)
#define USEM_ENABLE_IN_REG_FIC0_ENABLE_IN_SIZE 0
#define USEM_ENABLE_IN_REG_FIC1_ENABLE_IN (0x1<<1)
#define USEM_ENABLE_IN_REG_FIC1_ENABLE_IN_SIZE 1
#define USEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN (0x1<<2)
#define USEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN_SIZE 2
#define USEM_ENABLE_IN_REG_GENERAL_ENABLE_IN (0x1<<3)
#define USEM_ENABLE_IN_REG_GENERAL_ENABLE_IN_SIZE 3
#define USEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN (0x1<<4)
#define USEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN_SIZE 4
#define USEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN (0x1<<5)
#define USEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN_SIZE 5
#define USEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN (0x1<<6)
#define USEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN_SIZE 6
#define USEM_ENABLE_IN_REG_RAM0_ENABLE_IN (0x1<<7)
#define USEM_ENABLE_IN_REG_RAM0_ENABLE_IN_SIZE 7
#define USEM_ENABLE_IN_REG_RAM1_ENABLE_IN (0x1<<8)
#define USEM_ENABLE_IN_REG_RAM1_ENABLE_IN_SIZE 8
#define USEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN (0x1<<9)
#define USEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN_SIZE 9
#define USEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN (0x1<<10)
#define USEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN_SIZE 10
#define USEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN (0x1<<11)
#define USEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN_SIZE 11
#define USEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN (0x1<<12)
#define USEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN_SIZE 12
#define USEM_ENABLE_IN_REG_WAITP_ENABLE_IN (0x1<<13)
#define USEM_ENABLE_IN_REG_WAITP_ENABLE_IN_SIZE 13
#define USEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN (0x1<<14)
#define USEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN_SIZE 14
#define USEM_REG_ENABLE_OUT 0x3000a8UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define USEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT (0x1<<0)
#define USEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT_SIZE 0
#define USEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT (0x1<<1)
#define USEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT_SIZE 1
#define USEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT (0x1<<2)
#define USEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT_SIZE 2
#define USEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT (0x1<<3)
#define USEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT_SIZE 3
#define USEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT (0x1<<4)
#define USEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT_SIZE 4
#define USEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT (0x1<<5)
#define USEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT_SIZE 5
#define USEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT (0x1<<6)
#define USEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT_SIZE 6
#define USEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT (0x1<<7)
#define USEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT_SIZE 7
#define USEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT (0x1<<8)
#define USEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT_SIZE 8
#define USEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT (0x1<<9)
#define USEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT_SIZE 9
#define USEM_REG_STORM0_H_TM 0x3000acUL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm0_h memory instance
#define USEM_REG_STORM1_H_TM 0x3000b0UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm1_h memory instance
#define USEM_REG_STORM0_L_TM 0x3000b4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm0_l memory instance
#define USEM_REG_STORM1_L_TM 0x3000b8UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm1_l memory instance
#define USEM_REG_CAM_TM 0x3000bcUL //ACCESS:RW DataWidth:0xe Description: TM bits for cam
#define USEM_REG_RAM0_TM 0x3000c0UL //ACCESS:RW DataWidth:0x5 Description: tm for ram0_0
#define USEM_REG_PAS_BUF_LSB_TMA 0x3000c4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_lsb
#define USEM_REG_PAS_BUF_LSB_TMB 0x3000c8UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_lsb
#define USEM_REG_PAS_BUF_MSB_TMA 0x3000ccUL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_msb
#define USEM_REG_PAS_BUF_MSB_TMB 0x3000d0UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_msb
#define USEM_REG_INT_TABLE_TM 0x3000d4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory int_table
#define USEM_REG_CLEAR_WAITP 0x3000d8UL //ACCESS:RW DataWidth:0x1 Description: Write 1 to this register will disable waitp from this storm to other storms
#define USEM_REG_SLOW_DBG_MODE 0x3000dcUL //ACCESS:RW DataWidth:0x3 Description: debug mode for slow debug bus. Applicable only when ~usem_registers_slow_dbg_active.slow_dbg_active =1. If mode =0 thread number; pram address and DRA WR data selected; if mode =1 fin command and DRA RD ; if mode =2 pram address and thread number and fin command and released thread from STORM; if mode =3 STORE data to SDM
#define USEM_REG_SLOW_DBG_ACTIVE 0x3000e0UL //ACCESS:RW DataWidth:0x1 Description: debug mode is active
#define USEM_REG_DBG_MSG_SRC 0x3000e4UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~usem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0only FIC-s output to debug bus; 1=both FIC-s and passive buffer.
#define USEM_REG_DBG_MODE0_CFG 0x3000e8UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~usem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0 all the message output to debug bus; 1=partial message.
#define USEM_REG_DBG_MODE0_CFG_CYCLE 0x3000ecUL //ACCESS:RW DataWidth:0x5 Description: Applicable only when ~usem_registers_dbg_mode0_cfg.dbg_mode0_cfg =1. If =1 the additional cycles to extract to the debug bus.
#define USEM_REG_DBG_MODE1_CFG 0x3000f0UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~usem_registers_slow_dbg_mode.slow_dbg_mode =1. If=0 output to debug bus without the data; 1=with the data.
#define USEM_REG_DBG_EACH_CYLE 0x3000f4UL //ACCESS:RW DataWidth:0x1 Description: If=0 output every cycle full indication or thread status; 1= output only when there is a change.
#define USEM_REG_DBG_SELECT 0x3000f8UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from USEMI to the DBG block) - for selecting a line to output to the DBG block
#define USEM_REG_DBG_BYTE_ENABLE 0x3000fcUL //ACCESS:RW DataWidth:0x8 Description: Debug only.For dbgmux usage (debug data that goes from USEM to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define USEM_REG_DBG_SHIFT 0x300100UL //ACCESS:RW DataWidth:0x3 Description: Debug only.For dbgmux usage (debug data that goes from USEM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define USEM_REG_USEM_INT_STS_0 0x300104UL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define USEM_USEM_INT_STS_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define USEM_USEM_INT_STS_0_REG_FIC0_LAST_ERROR_SIZE 1
#define USEM_USEM_INT_STS_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define USEM_USEM_INT_STS_0_REG_FIC1_LAST_ERROR_SIZE 2
#define USEM_USEM_INT_STS_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define USEM_USEM_INT_STS_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define USEM_USEM_INT_STS_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define USEM_USEM_INT_STS_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define USEM_USEM_INT_STS_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define USEM_USEM_INT_STS_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define USEM_USEM_INT_STS_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define USEM_USEM_INT_STS_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define USEM_USEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define USEM_USEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define USEM_USEM_INT_STS_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define USEM_USEM_INT_STS_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define USEM_USEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define USEM_USEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define USEM_USEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define USEM_USEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define USEM_USEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define USEM_USEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define USEM_USEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define USEM_USEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define USEM_USEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define USEM_USEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define USEM_USEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define USEM_USEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define USEM_USEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define USEM_USEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define USEM_USEM_INT_STS_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define USEM_USEM_INT_STS_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define USEM_USEM_INT_STS_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define USEM_USEM_INT_STS_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define USEM_USEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define USEM_USEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define USEM_USEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define USEM_USEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define USEM_USEM_INT_STS_0_REG_RD_EMPTY_CAM (0x1<<20)
#define USEM_USEM_INT_STS_0_REG_RD_EMPTY_CAM_SIZE 20
#define USEM_USEM_INT_STS_0_REG_WR_FULL_CAM (0x1<<21)
#define USEM_USEM_INT_STS_0_REG_WR_FULL_CAM_SIZE 21
#define USEM_USEM_INT_STS_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define USEM_USEM_INT_STS_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define USEM_USEM_INT_STS_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define USEM_USEM_INT_STS_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define USEM_USEM_INT_STS_0_REG_CAM_OUT_FIFO (0x1<<24)
#define USEM_USEM_INT_STS_0_REG_CAM_OUT_FIFO_SIZE 24
#define USEM_USEM_INT_STS_0_REG_FIN_FIFO (0x1<<25)
#define USEM_USEM_INT_STS_0_REG_FIN_FIFO_SIZE 25
#define USEM_USEM_INT_STS_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define USEM_USEM_INT_STS_0_REG_SET0_THREAD_ERROR_SIZE 26
#define USEM_USEM_INT_STS_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define USEM_USEM_INT_STS_0_REG_SET1_THREAD_ERROR_SIZE 27
#define USEM_USEM_INT_STS_0_REG_THREAD_OVERRUN (0x1<<28)
#define USEM_USEM_INT_STS_0_REG_THREAD_OVERRUN_SIZE 28
#define USEM_USEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define USEM_USEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define USEM_USEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define USEM_USEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define USEM_USEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define USEM_USEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define USEM_REG_USEM_INT_STS_CLR_0 0x300108UL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define USEM_USEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define USEM_USEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR_SIZE 1
#define USEM_USEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define USEM_USEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR_SIZE 2
#define USEM_USEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define USEM_USEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define USEM_USEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define USEM_USEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define USEM_USEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define USEM_USEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define USEM_USEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define USEM_USEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define USEM_USEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define USEM_USEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define USEM_USEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define USEM_USEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define USEM_USEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define USEM_USEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define USEM_USEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define USEM_USEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define USEM_USEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define USEM_USEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define USEM_USEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM (0x1<<20)
#define USEM_USEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM_SIZE 20
#define USEM_USEM_INT_STS_CLR_0_REG_WR_FULL_CAM (0x1<<21)
#define USEM_USEM_INT_STS_CLR_0_REG_WR_FULL_CAM_SIZE 21
#define USEM_USEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define USEM_USEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define USEM_USEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define USEM_USEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define USEM_USEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO (0x1<<24)
#define USEM_USEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO_SIZE 24
#define USEM_USEM_INT_STS_CLR_0_REG_FIN_FIFO (0x1<<25)
#define USEM_USEM_INT_STS_CLR_0_REG_FIN_FIFO_SIZE 25
#define USEM_USEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define USEM_USEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR_SIZE 26
#define USEM_USEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define USEM_USEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR_SIZE 27
#define USEM_USEM_INT_STS_CLR_0_REG_THREAD_OVERRUN (0x1<<28)
#define USEM_USEM_INT_STS_CLR_0_REG_THREAD_OVERRUN_SIZE 28
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define USEM_USEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define USEM_REG_USEM_INT_STS_WR_0 0x30010cUL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define USEM_USEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define USEM_USEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR_SIZE 1
#define USEM_USEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define USEM_USEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR_SIZE 2
#define USEM_USEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define USEM_USEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define USEM_USEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define USEM_USEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define USEM_USEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define USEM_USEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define USEM_USEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define USEM_USEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define USEM_USEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define USEM_USEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define USEM_USEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define USEM_USEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define USEM_USEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define USEM_USEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define USEM_USEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define USEM_USEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define USEM_USEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define USEM_USEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define USEM_USEM_INT_STS_WR_0_REG_RD_EMPTY_CAM (0x1<<20)
#define USEM_USEM_INT_STS_WR_0_REG_RD_EMPTY_CAM_SIZE 20
#define USEM_USEM_INT_STS_WR_0_REG_WR_FULL_CAM (0x1<<21)
#define USEM_USEM_INT_STS_WR_0_REG_WR_FULL_CAM_SIZE 21
#define USEM_USEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define USEM_USEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define USEM_USEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define USEM_USEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define USEM_USEM_INT_STS_WR_0_REG_CAM_OUT_FIFO (0x1<<24)
#define USEM_USEM_INT_STS_WR_0_REG_CAM_OUT_FIFO_SIZE 24
#define USEM_USEM_INT_STS_WR_0_REG_FIN_FIFO (0x1<<25)
#define USEM_USEM_INT_STS_WR_0_REG_FIN_FIFO_SIZE 25
#define USEM_USEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define USEM_USEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR_SIZE 26
#define USEM_USEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define USEM_USEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR_SIZE 27
#define USEM_USEM_INT_STS_WR_0_REG_THREAD_OVERRUN (0x1<<28)
#define USEM_USEM_INT_STS_WR_0_REG_THREAD_OVERRUN_SIZE 28
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define USEM_USEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define USEM_REG_USEM_INT_MASK_0 0x300110UL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define USEM_USEM_INT_MASK_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define USEM_USEM_INT_MASK_0_REG_FIC0_LAST_ERROR_SIZE 1
#define USEM_USEM_INT_MASK_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define USEM_USEM_INT_MASK_0_REG_FIC1_LAST_ERROR_SIZE 2
#define USEM_USEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define USEM_USEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define USEM_USEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define USEM_USEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define USEM_USEM_INT_MASK_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define USEM_USEM_INT_MASK_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define USEM_USEM_INT_MASK_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define USEM_USEM_INT_MASK_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define USEM_USEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define USEM_USEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define USEM_USEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define USEM_USEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define USEM_USEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define USEM_USEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define USEM_USEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define USEM_USEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define USEM_USEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define USEM_USEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define USEM_USEM_INT_MASK_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define USEM_USEM_INT_MASK_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define USEM_USEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define USEM_USEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define USEM_USEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define USEM_USEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define USEM_USEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define USEM_USEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define USEM_USEM_INT_MASK_0_REG_RD_EMPTY_CAM (0x1<<20)
#define USEM_USEM_INT_MASK_0_REG_RD_EMPTY_CAM_SIZE 20
#define USEM_USEM_INT_MASK_0_REG_WR_FULL_CAM (0x1<<21)
#define USEM_USEM_INT_MASK_0_REG_WR_FULL_CAM_SIZE 21
#define USEM_USEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define USEM_USEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define USEM_USEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define USEM_USEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define USEM_USEM_INT_MASK_0_REG_CAM_OUT_FIFO (0x1<<24)
#define USEM_USEM_INT_MASK_0_REG_CAM_OUT_FIFO_SIZE 24
#define USEM_USEM_INT_MASK_0_REG_FIN_FIFO (0x1<<25)
#define USEM_USEM_INT_MASK_0_REG_FIN_FIFO_SIZE 25
#define USEM_USEM_INT_MASK_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define USEM_USEM_INT_MASK_0_REG_SET0_THREAD_ERROR_SIZE 26
#define USEM_USEM_INT_MASK_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define USEM_USEM_INT_MASK_0_REG_SET1_THREAD_ERROR_SIZE 27
#define USEM_USEM_INT_MASK_0_REG_THREAD_OVERRUN (0x1<<28)
#define USEM_USEM_INT_MASK_0_REG_THREAD_OVERRUN_SIZE 28
#define USEM_USEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define USEM_USEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define USEM_USEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define USEM_USEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define USEM_USEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define USEM_USEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define USEM_REG_USEM_INT_STS_1 0x300114UL //ACCESS:R DataWidth:0xb Description: Interrupt register #1 read
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define USEM_USEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define USEM_USEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define USEM_USEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define USEM_USEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define USEM_USEM_INT_STS_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define USEM_USEM_INT_STS_1_REG_DBG_FIFO_ERROR_SIZE 9
#define USEM_USEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define USEM_USEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define USEM_REG_USEM_INT_STS_CLR_1 0x300118UL //ACCESS:RC DataWidth:0xb Description: Interrupt register #1 read clear
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define USEM_USEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define USEM_USEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define USEM_USEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR_SIZE 9
#define USEM_USEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define USEM_USEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define USEM_REG_USEM_INT_STS_WR_1 0x30011cUL //ACCESS:WR DataWidth:0xb Description: Interrupt register #1 bit set or clear
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define USEM_USEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define USEM_USEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define USEM_USEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR_SIZE 9
#define USEM_USEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define USEM_USEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define USEM_REG_USEM_INT_MASK_1 0x300120UL //ACCESS:RW DataWidth:0xb Description: Interrupt mask register #1 read/write
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define USEM_USEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define USEM_USEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define USEM_USEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define USEM_USEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define USEM_USEM_INT_MASK_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define USEM_USEM_INT_MASK_1_REG_DBG_FIFO_ERROR_SIZE 9
#define USEM_USEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define USEM_USEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define USEM_REG_USEM_PRTY_STS_0 0x300124UL //ACCESS:R DataWidth:0x20 Description: Parity register #0 read
#define USEM_USEM_PRTY_STS_0_REG_PARITY (0x1<<0)
#define USEM_USEM_PRTY_STS_0_REG_PARITY_SIZE 0
#define USEM_USEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define USEM_USEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define USEM_USEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define USEM_USEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define USEM_USEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define USEM_USEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define USEM_USEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define USEM_USEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define USEM_USEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define USEM_USEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define USEM_USEM_PRTY_STS_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define USEM_USEM_PRTY_STS_0_REG_PAS_FIFO_PARITY_SIZE 10
#define USEM_USEM_PRTY_STS_0_REG_PAS_PARITY0 (0x1<<11)
#define USEM_USEM_PRTY_STS_0_REG_PAS_PARITY0_SIZE 11
#define USEM_USEM_PRTY_STS_0_REG_PAS_PARITY1 (0x1<<12)
#define USEM_USEM_PRTY_STS_0_REG_PAS_PARITY1_SIZE 12
#define USEM_USEM_PRTY_STS_0_REG_INT_TABLE_PARITY (0x1<<13)
#define USEM_USEM_PRTY_STS_0_REG_INT_TABLE_PARITY_SIZE 13
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY0 (0x1<<14)
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY0_SIZE 14
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY1 (0x1<<15)
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY1_SIZE 15
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY2 (0x1<<16)
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY2_SIZE 16
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY3 (0x1<<17)
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY3_SIZE 17
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY4 (0x1<<18)
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY4_SIZE 18
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY5 (0x1<<19)
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY5_SIZE 19
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY6 (0x1<<20)
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY6_SIZE 20
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY7 (0x1<<21)
#define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY7_SIZE 21
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY0 (0x1<<22)
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY0_SIZE 22
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY1 (0x1<<23)
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY1_SIZE 23
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY2 (0x1<<24)
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY2_SIZE 24
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY3 (0x1<<25)
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY3_SIZE 25
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY4 (0x1<<26)
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY4_SIZE 26
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY5 (0x1<<27)
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY5_SIZE 27
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY6 (0x1<<28)
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY6_SIZE 28
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY7 (0x1<<29)
#define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY7_SIZE 29
#define USEM_USEM_PRTY_STS_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define USEM_USEM_PRTY_STS_0_REG_PRAM_LOW_PARITY_SIZE 30
#define USEM_USEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define USEM_USEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128UL //ACCESS:RC DataWidth:0x20 Description: Parity register #0 read clear
#define USEM_USEM_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
#define USEM_USEM_PRTY_STS_CLR_0_REG_PARITY_SIZE 0
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define USEM_USEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define USEM_USEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define USEM_USEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define USEM_USEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define USEM_USEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define USEM_USEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY_SIZE 10
#define USEM_USEM_PRTY_STS_CLR_0_REG_PAS_PARITY0 (0x1<<11)
#define USEM_USEM_PRTY_STS_CLR_0_REG_PAS_PARITY0_SIZE 11
#define USEM_USEM_PRTY_STS_CLR_0_REG_PAS_PARITY1 (0x1<<12)
#define USEM_USEM_PRTY_STS_CLR_0_REG_PAS_PARITY1_SIZE 12
#define USEM_USEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY (0x1<<13)
#define USEM_USEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY_SIZE 13
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0 (0x1<<14)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0_SIZE 14
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1 (0x1<<15)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1_SIZE 15
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2 (0x1<<16)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2_SIZE 16
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3 (0x1<<17)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3_SIZE 17
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4 (0x1<<18)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4_SIZE 18
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5 (0x1<<19)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5_SIZE 19
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6 (0x1<<20)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6_SIZE 20
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7 (0x1<<21)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7_SIZE 21
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0 (0x1<<22)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0_SIZE 22
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1 (0x1<<23)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1_SIZE 23
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2 (0x1<<24)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2_SIZE 24
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3 (0x1<<25)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3_SIZE 25
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4 (0x1<<26)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4_SIZE 26
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5 (0x1<<27)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5_SIZE 27
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6 (0x1<<28)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6_SIZE 28
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7 (0x1<<29)
#define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7_SIZE 29
#define USEM_USEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define USEM_USEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY_SIZE 30
#define USEM_USEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define USEM_USEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define USEM_REG_USEM_PRTY_STS_WR_0 0x30012cUL //ACCESS:WR DataWidth:0x20 Description: Parity register #0 bit set or clear
#define USEM_USEM_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
#define USEM_USEM_PRTY_STS_WR_0_REG_PARITY_SIZE 0
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define USEM_USEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define USEM_USEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define USEM_USEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define USEM_USEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define USEM_USEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define USEM_USEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY_SIZE 10
#define USEM_USEM_PRTY_STS_WR_0_REG_PAS_PARITY0 (0x1<<11)
#define USEM_USEM_PRTY_STS_WR_0_REG_PAS_PARITY0_SIZE 11
#define USEM_USEM_PRTY_STS_WR_0_REG_PAS_PARITY1 (0x1<<12)
#define USEM_USEM_PRTY_STS_WR_0_REG_PAS_PARITY1_SIZE 12
#define USEM_USEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY (0x1<<13)
#define USEM_USEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY_SIZE 13
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY0 (0x1<<14)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY0_SIZE 14
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY1 (0x1<<15)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY1_SIZE 15
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY2 (0x1<<16)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY2_SIZE 16
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY3 (0x1<<17)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY3_SIZE 17
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY4 (0x1<<18)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY4_SIZE 18
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY5 (0x1<<19)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY5_SIZE 19
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY6 (0x1<<20)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY6_SIZE 20
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY7 (0x1<<21)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY7_SIZE 21
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY0 (0x1<<22)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY0_SIZE 22
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY1 (0x1<<23)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY1_SIZE 23
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY2 (0x1<<24)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY2_SIZE 24
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY3 (0x1<<25)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY3_SIZE 25
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY4 (0x1<<26)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY4_SIZE 26
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY5 (0x1<<27)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY5_SIZE 27
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY6 (0x1<<28)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY6_SIZE 28
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY7 (0x1<<29)
#define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY7_SIZE 29
#define USEM_USEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define USEM_USEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY_SIZE 30
#define USEM_USEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define USEM_USEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define USEM_REG_USEM_PRTY_MASK_0 0x300130UL //ACCESS:RW DataWidth:0x20 Description: Parity mask register #0 read/write
#define USEM_USEM_PRTY_MASK_0_REG_PARITY (0x1<<0)
#define USEM_USEM_PRTY_MASK_0_REG_PARITY_SIZE 0
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define USEM_USEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define USEM_USEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define USEM_USEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define USEM_USEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define USEM_USEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define USEM_USEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define USEM_USEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY_SIZE 10
#define USEM_USEM_PRTY_MASK_0_REG_PAS_PARITY0 (0x1<<11)
#define USEM_USEM_PRTY_MASK_0_REG_PAS_PARITY0_SIZE 11
#define USEM_USEM_PRTY_MASK_0_REG_PAS_PARITY1 (0x1<<12)
#define USEM_USEM_PRTY_MASK_0_REG_PAS_PARITY1_SIZE 12
#define USEM_USEM_PRTY_MASK_0_REG_INT_TABLE_PARITY (0x1<<13)
#define USEM_USEM_PRTY_MASK_0_REG_INT_TABLE_PARITY_SIZE 13
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY0 (0x1<<14)
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY0_SIZE 14
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY1 (0x1<<15)
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY1_SIZE 15
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY2 (0x1<<16)
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY2_SIZE 16
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY3 (0x1<<17)
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY3_SIZE 17
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY4 (0x1<<18)
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY4_SIZE 18
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY5 (0x1<<19)
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY5_SIZE 19
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY6 (0x1<<20)
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY6_SIZE 20
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY7 (0x1<<21)
#define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY7_SIZE 21
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY0 (0x1<<22)
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY0_SIZE 22
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY1 (0x1<<23)
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY1_SIZE 23
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY2 (0x1<<24)
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY2_SIZE 24
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY3 (0x1<<25)
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY3_SIZE 25
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY4 (0x1<<26)
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY4_SIZE 26
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY5 (0x1<<27)
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY5_SIZE 27
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY6 (0x1<<28)
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY6_SIZE 28
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY7 (0x1<<29)
#define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY7_SIZE 29
#define USEM_USEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define USEM_USEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY_SIZE 30
#define USEM_USEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define USEM_USEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define USEM_REG_USEM_PRTY_STS_1 0x300134UL //ACCESS:R DataWidth:0x5 Description: Parity register #1 read
#define USEM_USEM_PRTY_STS_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define USEM_USEM_PRTY_STS_1_REG_SYNC_DBG_PARITY_SIZE 0
#define USEM_USEM_PRTY_STS_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define USEM_USEM_PRTY_STS_1_REG_SLOW_DBG_PARITY_SIZE 1
#define USEM_USEM_PRTY_STS_1_REG_CAM_PARITY (0x1<<2)
#define USEM_USEM_PRTY_STS_1_REG_CAM_PARITY_SIZE 2
#define USEM_USEM_PRTY_STS_1_REG_STORM_RF0_PARITY (0x1<<3)
#define USEM_USEM_PRTY_STS_1_REG_STORM_RF0_PARITY_SIZE 3
#define USEM_USEM_PRTY_STS_1_REG_STORM_RF1_PARITY (0x1<<4)
#define USEM_USEM_PRTY_STS_1_REG_STORM_RF1_PARITY_SIZE 4
#define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138UL //ACCESS:RC DataWidth:0x5 Description: Parity register #1 read clear
#define USEM_USEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define USEM_USEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY_SIZE 0
#define USEM_USEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define USEM_USEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY_SIZE 1
#define USEM_USEM_PRTY_STS_CLR_1_REG_CAM_PARITY (0x1<<2)
#define USEM_USEM_PRTY_STS_CLR_1_REG_CAM_PARITY_SIZE 2
#define USEM_USEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY (0x1<<3)
#define USEM_USEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY_SIZE 3
#define USEM_USEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY (0x1<<4)
#define USEM_USEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY_SIZE 4
#define USEM_REG_USEM_PRTY_STS_WR_1 0x30013cUL //ACCESS:WR DataWidth:0x5 Description: Parity register #1 bit set or clear
#define USEM_USEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define USEM_USEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY_SIZE 0
#define USEM_USEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define USEM_USEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY_SIZE 1
#define USEM_USEM_PRTY_STS_WR_1_REG_CAM_PARITY (0x1<<2)
#define USEM_USEM_PRTY_STS_WR_1_REG_CAM_PARITY_SIZE 2
#define USEM_USEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY (0x1<<3)
#define USEM_USEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY_SIZE 3
#define USEM_USEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY (0x1<<4)
#define USEM_USEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY_SIZE 4
#define USEM_REG_USEM_PRTY_MASK_1 0x300140UL //ACCESS:RW DataWidth:0x5 Description: Parity mask register #1 read/write
#define USEM_USEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define USEM_USEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY_SIZE 0
#define USEM_USEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define USEM_USEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY_SIZE 1
#define USEM_USEM_PRTY_MASK_1_REG_CAM_PARITY (0x1<<2)
#define USEM_USEM_PRTY_MASK_1_REG_CAM_PARITY_SIZE 2
#define USEM_USEM_PRTY_MASK_1_REG_STORM_RF0_PARITY (0x1<<3)
#define USEM_USEM_PRTY_MASK_1_REG_STORM_RF0_PARITY_SIZE 3
#define USEM_USEM_PRTY_MASK_1_REG_STORM_RF1_PARITY (0x1<<4)
#define USEM_USEM_PRTY_MASK_1_REG_STORM_RF1_PARITY_SIZE 4
#define USEM_REG_RAM0_TM1 0x30014cUL //ACCESS:RW DataWidth:0x5 Description: tm for ram0_1
#define USEM_REG_RAM0_TM2 0x300150UL //ACCESS:RW DataWidth:0x5 Description: tm for ram0_2
#define USEM_REG_ECO_RESERVED 0x3003a8UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO
#define USEM_REG_FIFOS_TM 0x3003acUL //ACCESS:RW DataWidth:0xe Description: TM bits for FIC0_LSB [1:0]; FIC0_MSB[3:2]; FIC1_LSB[5:4]; FIC1_MSB[7:6]; DBG_LSB[9:8];DBG_MSB[11:10]; EXT_PAS[13:12]
#define USEM_REG_ARBITER_REQUEST 0x300200UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2
#define USEM_REG_ARBITER_REQUEST_SIZE 1
#define USEM_REG_ARBITER_SELECT 0x300204UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2
#define USEM_REG_ARBITER_SELECT_SIZE 1
#define USEM_REG_ARBITER_SLOT 0x300208UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last slot
#define USEM_REG_ARBITER_SLOT_SIZE 1
#define USEM_REG_DBG_IF_FULL 0x30020cUL //ACCESS:R DataWidth:0x1 Description: DBG IF is full in sem_slow_ls_dbg
#define USEM_REG_DBG_IF_FULL_SIZE 1
#define USEM_REG_DRA_EMPTY 0x300210UL //ACCESS:R DataWidth:0x1 Description: This register is active when FIN FIO is empty and DRA RD FIFO is empty
#define USEM_REG_DRA_EMPTY_SIZE 1
#define USEM_REG_EXT_PAS_EMPTY 0x300214UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO empty in sem_slow
#define USEM_REG_EXT_PAS_EMPTY_SIZE 1
#define USEM_REG_EXT_PAS_FULL 0x300218UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO Full in sem_slow
#define USEM_REG_EXT_PAS_FULL_SIZE 1
#define USEM_REG_EXT_STORE_FREE_ENTRIES 0x30021cUL //ACCESS:R DataWidth:0x6 Description: Number of free entries in the external STORE sync FIFO.
#define USEM_REG_EXT_STORE_FREE_ENTRIES_SIZE 1
#define USEM_REG_EXT_STORE_IF_FULL 0x300220UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE IF is full in sem_slow_ls_ext
#define USEM_REG_EXT_STORE_IF_FULL_SIZE 1
#define USEM_REG_FIC0_DISABLE 0x300224UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC0 May be updated during run_time by the microcode
#define USEM_REG_FIC0_DISABLE_SIZE 1
#define USEM_REG_FIC0_EMPTY 0x300228UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
#define USEM_REG_FIC0_EMPTY_SIZE 1
#define USEM_REG_FIC0_FULL 0x30022cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
#define USEM_REG_FIC0_FULL_SIZE 1
#define USEM_REG_FIC0_LENGTH 0x300230UL //ACCESS:R DataWidth:0x8 Description: Length from FIC0. Active only with ~usem_registers_fic0_length_error.fic0_length_error interrupt
#define USEM_REG_FIC0_LENGTH_SIZE 1
#define USEM_REG_FIC1_DISABLE 0x300234UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC1 May be updated during run_time by the microcode
#define USEM_REG_FIC1_DISABLE_SIZE 1
#define USEM_REG_FIC1_EMPTY 0x300238UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
#define USEM_REG_FIC1_EMPTY_SIZE 1
#define USEM_REG_FIC1_FULL 0x30023cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
#define USEM_REG_FIC1_FULL_SIZE 1
#define USEM_REG_FIC1_LENGTH 0x300240UL //ACCESS:R DataWidth:0x8 Description: Length from FIC1. Active only with ~usem_registers_fic1_length_error.fic1_length_error interrupt
#define USEM_REG_FIC1_LENGTH_SIZE 1
#define USEM_REG_GPI_DATA 0x300244UL //ACCESS:R DataWidth:0x18 Description: GPI signals that are inputs to SEMI
#define USEM_REG_GPI_DATA_SIZE 1
#define USEM_REG_NUM_OF_THREADS 0x300248UL //ACCESS:R DataWidth:0x6 Description: The number of threads currently active
#define USEM_REG_NUM_OF_THREADS_SIZE 1
#define USEM_REG_PAS_DISABLE 0x30024cUL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from the passive buffer May be updated during run_time by the microcode
#define USEM_REG_PAS_DISABLE_SIZE 1
#define USEM_REG_PAS_IF_FULL 0x300250UL //ACCESS:R DataWidth:0x1 Description: Full from passive buffer asserted toward SDM
#define USEM_REG_PAS_IF_FULL_SIZE 1
#define USEM_REG_RAM0_IF_FULL 0x300254UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM0 IF is full in sem_slow_ls_ram
#define USEM_REG_RAM0_IF_FULL_SIZE 1
#define USEM_REG_RAM1_IF_FULL 0x300258UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM1 IF is full in sem_slow_ls_ram
#define USEM_REG_RAM1_IF_FULL_SIZE 1
#define USEM_REG_SET0_THREAD_EMPTY 0x30025cUL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is empty in sem_slow_dra_wr
#define USEM_REG_SET0_THREAD_EMPTY_SIZE 1
#define USEM_REG_SET0_THREAD_FULL 0x300260UL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is full in sem_slow_dra_wr
#define USEM_REG_SET0_THREAD_FULL_SIZE 1
#define USEM_REG_SET1_THREAD_EMPTY 0x300264UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is empty in sem_slow_dra_wr
#define USEM_REG_SET1_THREAD_EMPTY_SIZE 1
#define USEM_REG_SET1_THREAD_FULL 0x300268UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is full in sem_slow_dra_wr
#define USEM_REG_SET1_THREAD_FULL_SIZE 1
#define USEM_REG_SLEEP_THREADS_VALID 0x30026cUL //ACCESS:R DataWidth:0x14 Description: Valid sleeping threads indication have bit per thread
#define USEM_REG_SLEEP_THREADS_VALID_SIZE 1
#define USEM_REG_SLOW_DBG_ALM_EMPTY 0x300270UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg (31 entry inside fifo)
#define USEM_REG_SLOW_DBG_ALM_EMPTY_SIZE 1
#define USEM_REG_SLOW_DBG_ALM_FULL 0x300274UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg according to configuration
#define USEM_REG_SLOW_DBG_ALM_FULL_SIZE 1
#define USEM_REG_SLOW_DBG_EMPTY 0x300278UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is empty in sem_slow_ls_dbg
#define USEM_REG_SLOW_DBG_EMPTY_SIZE 1
#define USEM_REG_SLOW_DBG_FULL 0x30027cUL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is full in sem_slow_ls_dbg
#define USEM_REG_SLOW_DBG_FULL_SIZE 1
#define USEM_REG_SLOW_DRA_FIN_EMPTY 0x300280UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is empty in sem_slow_dra_sync
#define USEM_REG_SLOW_DRA_FIN_EMPTY_SIZE 1
#define USEM_REG_SLOW_DRA_FIN_FULL 0x300284UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is full in sem_slow_dra_sync (never may be active)
#define USEM_REG_SLOW_DRA_FIN_FULL_SIZE 1
#define USEM_REG_SLOW_DRA_INT_EMPTY 0x300288UL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is empty in sem_slow_dra_sync
#define USEM_REG_SLOW_DRA_INT_EMPTY_SIZE 1
#define USEM_REG_SLOW_DRA_INT_FULL 0x30028cUL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is full in sem_slow_dra_int
#define USEM_REG_SLOW_DRA_INT_FULL_SIZE 1
#define USEM_REG_SLOW_DRA_RD_EMPTY 0x300290UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is empty in sem_slow_dra_sync
#define USEM_REG_SLOW_DRA_RD_EMPTY_SIZE 1
#define USEM_REG_SLOW_DRA_RD_FULL 0x300294UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is full in sem_slow_dra_sync
#define USEM_REG_SLOW_DRA_RD_FULL_SIZE 1
#define USEM_REG_SLOW_DRA_WR_EMPTY 0x300298UL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is empty in sem_slow_dra_sync
#define USEM_REG_SLOW_DRA_WR_EMPTY_SIZE 1
#define USEM_REG_SLOW_DRA_WR_FULL 0x30029cUL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is full in sem_slow_dra_sync
#define USEM_REG_SLOW_DRA_WR_FULL_SIZE 1
#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is empty in sem_slow_ls_ext
#define USEM_REG_SLOW_EXT_STORE_EMPTY_SIZE 1
#define USEM_REG_SLOW_EXT_STORE_FULL 0x3002a4UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is full in sem_slow_ls_ext
#define USEM_REG_SLOW_EXT_STORE_FULL_SIZE 1
#define USEM_REG_SLOW_RAM0_RD_EMPTY 0x3002a8UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is empty in sem_slow_ls_ext
#define USEM_REG_SLOW_RAM0_RD_EMPTY_SIZE 1
#define USEM_REG_SLOW_RAM0_RD_FULL 0x3002acUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is full in sem_slow_ls_ext
#define USEM_REG_SLOW_RAM0_RD_FULL_SIZE 1
#define USEM_REG_SLOW_RAM0_WR_ALM_FULL 0x3002b0UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
#define USEM_REG_SLOW_RAM0_WR_ALM_FULL_SIZE 1
#define USEM_REG_SLOW_RAM0_WR_EMPTY 0x3002b4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is empty in sem_slow_ls_ext
#define USEM_REG_SLOW_RAM0_WR_EMPTY_SIZE 1
#define USEM_REG_SLOW_RAM0_WR_FULL 0x3002b8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is full in sem_slow_ls_ext
#define USEM_REG_SLOW_RAM0_WR_FULL_SIZE 1
#define USEM_REG_SLOW_RAM1_RD_EMPTY 0x3002bcUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is empty in sem_slow_ls_ext
#define USEM_REG_SLOW_RAM1_RD_EMPTY_SIZE 1
#define USEM_REG_SLOW_RAM1_RD_FULL 0x3002c0UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is full in sem_slow_ls_ext
#define USEM_REG_SLOW_RAM1_RD_FULL_SIZE 1
#define USEM_REG_SLOW_RAM1_WR_ALM_FULL 0x3002c4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
#define USEM_REG_SLOW_RAM1_WR_ALM_FULL_SIZE 1
#define USEM_REG_SLOW_RAM1_WR_EMPTY 0x3002c8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is empty in sem_slow_ls_ext
#define USEM_REG_SLOW_RAM1_WR_EMPTY_SIZE 1
#define USEM_REG_SLOW_RAM1_WR_FULL 0x3002ccUL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is full in sem_slow_ls_ext
#define USEM_REG_SLOW_RAM1_WR_FULL_SIZE 1
#define USEM_REG_SYNC_DBG_EMPTY 0x3002d0UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is empty in sem_slow_ls_sync
#define USEM_REG_SYNC_DBG_EMPTY_SIZE 1
#define USEM_REG_SYNC_DBG_FULL 0x3002d4UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is full in sem_slow_ls_sync
#define USEM_REG_SYNC_DBG_FULL_SIZE 1
#define USEM_REG_THREAD_ERROR 0x3002d8UL //ACCESS:R DataWidth:0x14 Description: Thread error indication have bit per thread
#define USEM_REG_THREAD_ERROR_SIZE 1
#define USEM_REG_THREAD_OVERRUN_NUM 0x3002dcUL //ACCESS:R DataWidth:0x14 Description: Threads are sleeping in passive buffer more than ~usem_registers_thread_inter_cnt.thread_inter_cnt number of cycles
#define USEM_REG_THREAD_OVERRUN_NUM_SIZE 1
#define USEM_REG_THREAD_RDY 0x3002e0UL //ACCESS:R DataWidth:0x14 Description: Thread ready indication have bit per thread
#define USEM_REG_THREAD_RDY_SIZE 1
#define USEM_REG_THREADS_LIST 0x3002e4UL //ACCESS:RW DataWidth:0x14 Description: List of free threads . There is a bit per thread.
#define USEM_REG_THREADS_LIST_SIZE 1
#define USEM_REG_WB_MSB 0x3002e8UL //ACCESS:R DataWidth:0x2 Description: Reset value of this register is right when was not read to ~usem_registers_fic0_fifo.fic0_fifo or ~usem_registers_fic1_fifo.fic1_fifo or ~usem_registers_passive_buffer.passive_buffer. For read from ~usem_registers_passive_buffer.passive_buffer :b0- parity0; b1 parity1. For read from ~usem_registers_fic0_fifo.fic0_fifo and ~usem_registers_fic1_fifo.fic1_fifo :b1=0 data from ~usem_registers_fic0_fifo.fic0_fifo and ~usem_registers_fic1_fifo.fic1_fifo is valid; b1 =1 ~usem_registers_fic0_fifo.fic0_fifo and ~usem_registers_fic1_fifo.fic1_fifo is empty and data from it must be equal to 0; b0 - parity from ~usem_registers_fic0_fifo.fic0_fifo and ~usem_registers_fic1_fifo.fic1_fifo
#define USEM_REG_WB_MSB_SIZE 1
#define USEM_REG_FIC0_FIFO 0x300300UL //ACCESS:WB_R DataWidth:0x80 Description: Debug only. FIC0_fifo: b[127:0] data; b128-parity;b129=1- fifo empty;b129=0-data is valid
#define USEM_REG_FIC0_FIFO_SIZE 4
#define USEM_REG_FIC1_FIFO 0x300320UL //ACCESS:WB_R DataWidth:0x80 Description: Debug only. FIC1_fifo read for debugging mode; b[127:0] data; b128-parity;
#define USEM_REG_FIC1_FIFO_SIZE 4
#define USEM_REG_FIN_COMMAND 0x300340UL //ACCESS:WB_R DataWidth:0x6d Description: last fin command that was read from fifo. Its spelling in ~usem_registers_fin_fifo.fin_fifo register
#define USEM_REG_FIN_COMMAND_SIZE 4
#define USEM_REG_FIN_FIFO 0x300360UL //ACCESS:WB_R DataWidth:0x6d Description: Debug only. FIn FIFO. [5:0] start_rp_foc3; [11:6] start_rp_foc2; [17:12] start_rp_foc1; [23:18] start_rp_foc0; [29:24] end_rp_foc3; [35:30] end_rp_foc2; [41:36] end_rp_foc1; [47:42] end_rp_foc0; [53:48] lowest rp; [59:54] highest rp; [65:60] store start rp; [71:66] store end rp; [77:72] load start rp; [83:78] load end rp; [85:84] priority; [101:86] pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid
#define USEM_REG_FIN_FIFO_SIZE 4
#define USEM_REG_VFPF_ERR_NUM 0x300380UL //ACCESS:W DataWidth:0x7 Description: VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
#define USEM_REG_VFPF_ERR_NUM_SIZE 1
#define USEM_REG_VF_ERR_VECTOR_LSB 0x300388UL //ACCESS:R DataWidth:0x20 Description: VF/PF error bitmap vector [0-31]
#define USEM_REG_VF_ERR_VECTOR_LSB_SIZE 1
#define USEM_REG_VF_ERR_VECTOR_MSB 0x300390UL //ACCESS:R DataWidth:0x20 Description: VF/PF error bitmap vector [32-63]
#define USEM_REG_VF_ERR_VECTOR_MSB_SIZE 1
#define USEM_REG_PF_ERR_VECTOR 0x300398UL //ACCESS:R DataWidth:0x8 Description: VF/PF error bitmap vector [0-7]
#define USEM_REG_PF_ERR_VECTOR_SIZE 1
#define USEM_REG_THREAD_SET_NUM 0x3003a0UL //ACCESS:W DataWidth:0x5 Description: Thread ID. Write thread ID will set ready indication for this thread ID
#define USEM_REG_THREAD_SET_NUM_SIZE 1
#define USEM_REG_INT_TABLE 0x300400UL //ACCESS:RW DataWidth:0xf Description: Interrupt table Read and write access to it is not possible in the middle of the work
#define USEM_REG_INT_TABLE_SIZE 256
#define USEM_REG_PASSIVE_BUFFER 0x302000UL //ACCESS:WB DataWidth:0x80 Description: Debug only. Passive buffer memory
#define USEM_REG_PASSIVE_BUFFER_SIZE 2048
#define USEM_REG_PASSIVE_BUFFER_MSB 0x304000UL //ACCESS:WB DataWidth:0x80 Description: Debug only. Passive buffer memory MSB that starts from row 512 of passive buffer till row 639
#define USEM_REG_PASSIVE_BUFFER_MSB_SIZE 512
#define USEM_REG_FAST_MEMORY 0x320000UL //ACCESS:RW DataWidth:0x20 Description: This address space contains all registers and memories that are placed in SEM_FAST block. The SEM_FAST registers are described in appendix B. In order to access the SEM_FAST registers the base address USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each SEM_FAST register offset.
#define USEM_REG_FAST_MEMORY_SIZE 32768
#define USEM_REG_PRAM 0x340000UL //ACCESS:WB DataWidth:0x2e Description: pram memory. B45 is parity; b[44:0] - data.
#define USEM_REG_PRAM_SIZE 65536
#define USEM_REG_USEM_UNUSED_EMPTY_0 0x300144UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_0_SIZE 2
#define USEM_REG_USEM_UNUSED_EMPTY_1 0x300154UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_1_SIZE 43
#define USEM_REG_USEM_UNUSED_EMPTY_2 0x3002ecUL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_2_SIZE 5
#define USEM_REG_USEM_UNUSED_EMPTY_3 0x300384UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_3_SIZE 1
#define USEM_REG_USEM_UNUSED_EMPTY_4 0x30038cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_4_SIZE 1
#define USEM_REG_USEM_UNUSED_EMPTY_5 0x300394UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_5_SIZE 1
#define USEM_REG_USEM_UNUSED_EMPTY_6 0x30039cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_6_SIZE 1
#define USEM_REG_USEM_UNUSED_EMPTY_7 0x3003a4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_7_SIZE 1
#define USEM_REG_USEM_UNUSED_EMPTY_8 0x3003b0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_8_SIZE 20
#define USEM_REG_USEM_UNUSED_EMPTY_9 0x300800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_9_SIZE 1536
#define USEM_REG_USEM_UNUSED_EMPTY_10 0x304800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define USEM_REG_USEM_UNUSED_EMPTY_10_SIZE 28160
#define VFC_REG_INTERRUPT_IND 0x19428UL //ACCESS:RW DataWidth:0xb Multi Field Register
#define VFC_INTERRUPT_IND_REG_ADDRESS_INTERRUPT (0x1<<0)
#define VFC_INTERRUPT_IND_REG_ADDRESS_INTERRUPT_SIZE 0
#define VFC_INTERRUPT_IND_REG_INP_FIFO_ITERRUPT (0x1<<1)
#define VFC_INTERRUPT_IND_REG_INP_FIFO_ITERRUPT_SIZE 1
#define VFC_INTERRUPT_IND_REG_LEN_FIFO_INTERRUPT (0x1<<2)
#define VFC_INTERRUPT_IND_REG_LEN_FIFO_INTERRUPT_SIZE 2
#define VFC_INTERRUPT_IND_REG_INP_BUF_INTERRUPT (0x1<<3)
#define VFC_INTERRUPT_IND_REG_INP_BUF_INTERRUPT_SIZE 3
#define VFC_INTERRUPT_IND_REG_OUT_BUF_INTERRUPT (0x1<<4)
#define VFC_INTERRUPT_IND_REG_OUT_BUF_INTERRUPT_SIZE 4
#define VFC_INTERRUPT_IND_REG_RSS_IND_INTERRUPT (0x1<<5)
#define VFC_INTERRUPT_IND_REG_RSS_IND_INTERRUPT_SIZE 5
#define VFC_INTERRUPT_IND_REG_RSS_INFO_INTERRUPT (0x1<<6)
#define VFC_INTERRUPT_IND_REG_RSS_INFO_INTERRUPT_SIZE 6
#define VFC_INTERRUPT_IND_REG_RSS_KEY_LSB_INTERRUPT (0x1<<7)
#define VFC_INTERRUPT_IND_REG_RSS_KEY_LSB_INTERRUPT_SIZE 7
#define VFC_INTERRUPT_IND_REG_RSS_KEY_MSB_INTERRUPT (0x1<<8)
#define VFC_INTERRUPT_IND_REG_RSS_KEY_MSB_INTERRUPT_SIZE 8
#define VFC_INTERRUPT_IND_REG_RBC_WRITE_INTERRUPT (0x1<<9)
#define VFC_INTERRUPT_IND_REG_RBC_WRITE_INTERRUPT_SIZE 9
#define VFC_INTERRUPT_IND_REG_DEADLOCK_INTERRUPT (0x1<<10)
#define VFC_INTERRUPT_IND_REG_DEADLOCK_INTERRUPT_SIZE 10
#define VFC_REG_PARITY_IND 0x1942cUL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define VFC_PARITY_IND_REG_RSS_RAM_PARITY (0x1<<0)
#define VFC_PARITY_IND_REG_RSS_RAM_PARITY_SIZE 0
#define VFC_PARITY_IND_REG_CAM_PARITY (0x1<<1)
#define VFC_PARITY_IND_REG_CAM_PARITY_SIZE 1
#define VFC_PARITY_IND_REG_INP_FIFO_PARITY (0x1<<2)
#define VFC_PARITY_IND_REG_INP_FIFO_PARITY_SIZE 2
#define VFC_REG_INDICATIONS1 0x19430UL //ACCESS:RW DataWidth:0x12 Multi Field Register
#define VFC_INDICATIONS1_REG_INP_FIFO_EMPTY (0x1<<0)
#define VFC_INDICATIONS1_REG_INP_FIFO_EMPTY_SIZE 0
#define VFC_INDICATIONS1_REG_LEN_FIFO_EMPTY (0x1<<1)
#define VFC_INDICATIONS1_REG_LEN_FIFO_EMPTY_SIZE 1
#define VFC_INDICATIONS1_REG_INP_BUF_EMPTY (0x1<<2)
#define VFC_INDICATIONS1_REG_INP_BUF_EMPTY_SIZE 2
#define VFC_INDICATIONS1_REG_OUT_FIFO_EMPTY (0x1<<3)
#define VFC_INDICATIONS1_REG_OUT_FIFO_EMPTY_SIZE 3
#define VFC_INDICATIONS1_REG_SEM_FIFO_EMPTY (0x1<<4)
#define VFC_INDICATIONS1_REG_SEM_FIFO_EMPTY_SIZE 4
#define VFC_INDICATIONS1_REG_RESERVED1_1 (0x7<<5)
#define VFC_INDICATIONS1_REG_RESERVED1_1_SIZE 5
#define VFC_INDICATIONS1_REG_INP_FIFO_FULL (0x1<<8)
#define VFC_INDICATIONS1_REG_INP_FIFO_FULL_SIZE 8
#define VFC_INDICATIONS1_REG_LEN_FIFO_FULL (0x1<<9)
#define VFC_INDICATIONS1_REG_LEN_FIFO_FULL_SIZE 9
#define VFC_INDICATIONS1_REG_INP_BUF_FULL (0x1<<10)
#define VFC_INDICATIONS1_REG_INP_BUF_FULL_SIZE 10
#define VFC_INDICATIONS1_REG_OUT_FIFO_FULL (0x1<<11)
#define VFC_INDICATIONS1_REG_OUT_FIFO_FULL_SIZE 11
#define VFC_INDICATIONS1_REG_SEM_FIFO_FULL (0x1<<12)
#define VFC_INDICATIONS1_REG_SEM_FIFO_FULL_SIZE 12
#define VFC_INDICATIONS1_REG_RESERVED1_2 (0x7<<13)
#define VFC_INDICATIONS1_REG_RESERVED1_2_SIZE 13
#define VFC_INDICATIONS1_REG_RBC_RSP_RDY (0x1<<16)
#define VFC_INDICATIONS1_REG_RBC_RSP_RDY_SIZE 16
#define VFC_INDICATIONS1_REG_VFC_WAITP (0x1<<17)
#define VFC_INDICATIONS1_REG_VFC_WAITP_SIZE 17
#define VFC_REG_INDICATIONS2 0x19434UL //ACCESS:RW DataWidth:0x1c Multi Field Register
#define VFC_INDICATIONS2_REG_INP_FIFO_CNT (0x1f<<0)
#define VFC_INDICATIONS2_REG_INP_FIFO_CNT_SIZE 0
#define VFC_INDICATIONS2_REG_RESERVED2_1 (0x7<<5)
#define VFC_INDICATIONS2_REG_RESERVED2_1_SIZE 5
#define VFC_INDICATIONS2_REG_LEN_FIFO_CNT (0x1f<<8)
#define VFC_INDICATIONS2_REG_LEN_FIFO_CNT_SIZE 8
#define VFC_INDICATIONS2_REG_RESERVED2_2 (0x7<<13)
#define VFC_INDICATIONS2_REG_RESERVED2_2_SIZE 13
#define VFC_INDICATIONS2_REG_INP_BUF_CNT (0xf<<16)
#define VFC_INDICATIONS2_REG_INP_BUF_CNT_SIZE 16
#define VFC_INDICATIONS2_REG_OUT_BUF_CNT (0xf<<20)
#define VFC_INDICATIONS2_REG_OUT_BUF_CNT_SIZE 20
#define VFC_INDICATIONS2_REG_SEM_FIFO_CNT (0xf<<24)
#define VFC_INDICATIONS2_REG_SEM_FIFO_CNT_SIZE 24
#define VFC_REG_MEMORIES_RST 0x1943cUL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
#define VFC_MEMORIES_RST_REG_CAM_RST_SIZE 0
#define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
#define VFC_MEMORIES_RST_REG_RAM_RST_SIZE 1
#define VFC_REG_RSS_RAM_TM_0 0x19450UL //ACCESS:RW DataWidth:0x5 Description: TM indication for RSS RAM instance 0
#define VFC_REG_RSS_RAM_TM_1 0x19454UL //ACCESS:RW DataWidth:0x5 Description: TM indication for RSS RAM instance 1
#define VFC_REG_INP_FIFO_TM 0x19458UL //ACCESS:RW DataWidth:0x8 Description: TM indication for Input fifo
#define VFC_REG_CAM_TM 0x1945cUL //ACCESS:RW DataWidth:0xe Description: TM indication for CAM
#define VFC_REG_STORM_CMD_DISABLE 0x19474UL //ACCESS:RW DataWidth:0x1 Description: When set then it disables selecting of commands from STORM. It will allow for RBC to configurate block. STORM command may be executed when this bit will be deasserted
#define VFC_REG_WAITP_STAT 0x19478UL //ACCESS:ST DataWidth:0x20 Description: Statistics for number of cycles when waitp was raised to STORM as a result of full input FIFO. This vector will be reset after reading from it. It is also possible to write to it.
#define VFC_REG_ECO_RESERVED 0x1947cUL //ACCESS:RW DataWidth:0x20 Description: Unused bits for future eco
#define VFC_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD 0x19480UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define VFC_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD 0x19484UL //ACCESS:RW DataWidth:0x5 Description: Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];
#define VFC_REG_CPU_MBIST_MEMCTRL_0_STATUS_0 0x19488UL //ACCESS:RW DataWidth:0x7 Description: Bit 0 - mbist_done; Bit 1 -mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define VFC_REG_CPU_MBIST_MEMCTRL_1_STATUS_0 0x1948cUL //ACCESS:RW DataWidth:0x7 Description: Bit 0 - mbist_done; Bit 1 -mbist_go (global go bit); Bits NUM_OF_MEM+1:2 - mbist_go0 (per mem go bit); Bits NUM_OF_SPARE+NUM_OF_MEM+1:NUM_OF_MEM+2 - spare bits
#define VFC_REG_DEBUG_DATA 0x19490UL //ACCESS:RW DataWidth:0x1e Multi Field Register
#define VFC_DEBUG_DATA_REG_CURRENT_MSG_LEN (0x7<<0)
#define VFC_DEBUG_DATA_REG_CURRENT_MSG_LEN_SIZE 0
#define VFC_DEBUG_DATA_REG_CUR_MSG_EMPTY (0x1<<3)
#define VFC_DEBUG_DATA_REG_CUR_MSG_EMPTY_SIZE 3
#define VFC_DEBUG_DATA_REG_MEXT_MSG_LEN (0x7<<4)
#define VFC_DEBUG_DATA_REG_MEXT_MSG_LEN_SIZE 4
#define VFC_DEBUG_DATA_REG_NEXT_MSG_EMTY (0x1<<7)
#define VFC_DEBUG_DATA_REG_NEXT_MSG_EMTY_SIZE 7
#define VFC_DEBUG_DATA_REG_RBC_CNT (0xff<<8)
#define VFC_DEBUG_DATA_REG_RBC_CNT_SIZE 8
#define VFC_DEBUG_DATA_REG_STORM_READY (0x1<<16)
#define VFC_DEBUG_DATA_REG_STORM_READY_SIZE 16
#define VFC_DEBUG_DATA_REG_RBC_READY (0x1<<17)
#define VFC_DEBUG_DATA_REG_RBC_READY_SIZE 17
#define VFC_DEBUG_DATA_REG_RESERVED2 (0x3<<18)
#define VFC_DEBUG_DATA_REG_RESERVED2_SIZE 18
#define VFC_DEBUG_DATA_REG_LAST_MATCH_ADDR (0x3ff<<20)
#define VFC_DEBUG_DATA_REG_LAST_MATCH_ADDR_SIZE 20
#define VFC_REG_STORM_CMD_ADDR 0x19494UL //ACCESS:R DataWidth:0xc Description: Address of command from STORM that is waiting for arbitration
#define VFC_REG_STORM_CMD_DATA_0 0x19498UL //ACCESS:R DataWidth:0x20 Description: Data bits[31:0] of VFC command from STORM that are waiting for arbitration
#define VFC_REG_STORM_CMD_DATA_1 0x1949cUL //ACCESS:R DataWidth:0x20 Description: Data bits[63:32] of VFC command from STORM that are waiting for arbitration
#define VFC_REG_STORM_CMD_DATA_2 0x194a0UL //ACCESS:R DataWidth:0x20 Description: Data bits[95:64] of VFC command from STORM that are waiting for arbitration
#define VFC_REG_STORM_CMD_DATA_3 0x194a4UL //ACCESS:R DataWidth:0x20 Description: Data bits[127:96] of VFC command from STORM that are waiting for arbitration
#define VFC_REG_STORM_CMD_DATA_4 0x194a8UL //ACCESS:R DataWidth:0x20 Description: Data bits[159:128] of VFC command from STORM that are waiting for arbitration
#define VFC_REG_STORM_CMD_DATA_5 0x194acUL //ACCESS:R DataWidth:0x20 Description: Data bits[191:160] of VFC command from STORM that are waiting for arbitration
#define VFC_REG_STORM_CMD_DATA_6 0x194b0UL //ACCESS:R DataWidth:0x20 Description: Data bits[223:192] of VFC command from STORM that are waiting for arbitration
#define VFC_REG_STORM_CMD_DATA_7 0x194b4UL //ACCESS:R DataWidth:0x20 Description: Data bits[255:224] of VFC command from STORM that are waiting for arbitration
#define VFC_REG_VFC_PRTY_MASK 0x194e0UL //ACCESS:RW DataWidth:0x1 Description: Parity mask register #0 read/write
#define VFC_VFC_PRTY_MASK_REG_PARITY (0x1<<0)
#define VFC_VFC_PRTY_MASK_REG_PARITY_SIZE 0
#define VFC_REG_VFC_PRTY_STS_WR 0x194e4UL //ACCESS:WR DataWidth:0x1 Description: Parity register #0 bit set or clear
#define VFC_VFC_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define VFC_VFC_PRTY_STS_WR_REG_PARITY_SIZE 0
#define VFC_REG_VFC_PRTY_STS_CLR 0x194e8UL //ACCESS:RC DataWidth:0x1 Description: Parity register #0 read clear
#define VFC_VFC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define VFC_VFC_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define VFC_REG_VFC_PRTY_STS 0x194ecUL //ACCESS:R DataWidth:0x1 Description: Parity register #0 read
#define VFC_VFC_PRTY_STS_REG_PARITY (0x1<<0)
#define VFC_VFC_PRTY_STS_REG_PARITY_SIZE 0
#define VFC_REG_VFC_INT_MASK 0x194f0UL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
#define VFC_VFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define VFC_VFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define VFC_REG_VFC_INT_STS_WR 0x194f4UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
#define VFC_VFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define VFC_VFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define VFC_REG_VFC_INT_STS_CLR 0x194f8UL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
#define VFC_VFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define VFC_VFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define VFC_REG_VFC_INT_STS 0x194fcUL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
#define VFC_VFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define VFC_VFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define VFC_REG_MASK_LSB_0_LOW 0x19400UL //ACCESS:RW DataWidth:0x20 Description: 64 LSB bits for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
#define VFC_REG_MASK_LSB_0_LOW_SIZE 1
#define VFC_REG_MASK_LSB_0_HIGH 0x19404UL //ACCESS:RW DataWidth:0x20 Description: 64 LSB bits for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
#define VFC_REG_MASK_LSB_0_HIGH_SIZE 1
#define VFC_REG_MASK_LSB_1_LOW 0x19408UL //ACCESS:RW DataWidth:0x20 Description: 64 LSB bits for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
#define VFC_REG_MASK_LSB_1_LOW_SIZE 1
#define VFC_REG_MASK_LSB_1_HIGH 0x1940cUL //ACCESS:RW DataWidth:0x20 Description: 64 LSB bits for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
#define VFC_REG_MASK_LSB_1_HIGH_SIZE 1
#define VFC_REG_MASK_LSB_2_LOW 0x19410UL //ACCESS:RW DataWidth:0x20 Description: 32 LSB bits [31:0] for vector CAM mask that are used for search and add commands.1 means the corresponding data bit should be compared and 0 means it should be ignored.
#define VFC_REG_MASK_LSB_2_LOW_SIZE 1
#define VFC_REG_MASK_LSB_2_HIGH 0x19414UL //ACCESS:RW DataWidth:0x20 Description: 32 LSB bits [63:32] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
#define VFC_REG_MASK_LSB_2_HIGH_SIZE 1
#define VFC_REG_MASK_LSB_3_LOW 0x19418UL //ACCESS:RW DataWidth:0x20 Description: 32 LSB bits [31:0] bits for vector CAM mask that are used for search and add commands.1 means the corresponding data bit should be compared and 0 means it should be ignored.
#define VFC_REG_MASK_LSB_3_LOW_SIZE 1
#define VFC_REG_MASK_LSB_3_HIGH 0x1941cUL //ACCESS:RW DataWidth:0x20 Description: 32 LSB bits [63:32] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
#define VFC_REG_MASK_LSB_3_HIGH_SIZE 1
#define VFC_REG_MASK_OPTIMIZED_LOW 0x19420UL //ACCESS:RW DataWidth:0x20 Description: This field contains 4 vectors of 8 bit [31:0]. Decoding of each field:Bo- 1 search is done for MAC address (48 bit LSB in CAM); 0 - search for MAC address disabled. B1- 1 search is done for IVLAN (bits59:48 in CAM); 0 - search for IVLAN disabled. B2- 1 search is done for b60 in CAM; 0 - search for b60 in CAM disabled. B3- 1 search is done for b61 in CAM; 0 - search for b61 in CAM disabled. B4- 1 search is done for b62 in CAM; 0 - search for b62 in CAM disabled. B5- 1 search is done for b63 in CAM; 0 - search for b63 in CAM disabled. B7:6 - reserved
#define VFC_REG_MASK_OPTIMIZED_LOW_SIZE 1
#define VFC_REG_MASK_OPTIMIZED_HIGH 0x19424UL //ACCESS:RW DataWidth:0x20 Description: This field contains 4 vectors of 8 bit[63:32]. Decoding of each field:Bo- 1 search is done for MAC address (48 bit LSB in CAM); 0 - search for MAC address disabled. B1- 1 search is done for IVLAN (bits59:48 in CAM); 0 - search for IVLAN disabled. B2- 1 search is done for b60 in CAM; 0 - search for b60 in CAM disabled. B3- 1 search is done for b61 in CAM; 0 - search for b61 in CAM disabled. B4- 1 search is done for b62 in CAM; 0 - search for b62 in CAM disabled. B5- 1 search is done for b63 in CAM; 0 - search for b63 in CAM disabled. B7:6 - reserved
#define VFC_REG_MASK_OPTIMIZED_HIGH_SIZE 1
#define VFC_REG_SW_RST 0x19438UL //ACCESS:W DataWidth:0x1 Description: Write to this bit will cause to block reset
#define VFC_REG_SW_RST_SIZE 1
#define VFC_REG_CAM_PARITY_EN 0x19440UL //ACCESS:RW DataWidth:0x1 Description: REQUIRED -If this bit is set then background mechanism for parity check will be enabled; 0 - disabled
#define VFC_REG_CAM_PARITY_EN_SIZE 1
#define VFC_REG_CAM_CLK_DIVIDER 0x19444UL //ACCESS:RW DataWidth:0x4 Description: Cam clock divider : (may be equal to 2; 4; or 8 only)
#define VFC_REG_CAM_CLK_DIVIDER_SIZE 1
#define VFC_REG_PARITY_MASK 0x19448UL //ACCESS:RW DataWidth:0x3 Description: REQUIRED - 0 - parity is enabled;1 parity check is disabled
#define VFC_REG_PARITY_MASK_SIZE 1
#define VFC_REG_INTERRUPT_MASK 0x1944cUL //ACCESS:RW DataWidth:0xb Description: REQUIRED - 0 - interrupt is enabled;1- interrupt check is disabled
#define VFC_REG_INTERRUPT_MASK_SIZE 1
#define VFC_REG_VFC_CAM_BIST_EN 0x19460UL //ACCESS:RW DataWidth:0x1 Description: Bist enable bit for Cam
#define VFC_REG_VFC_CAM_BIST_EN_SIZE 1
#define VFC_REG_VFC_CAM_BIST_DBG_SEL 0x19464UL //ACCESS:RW DataWidth:0x8 Description: This select the type of data present on bist_status bus (slixe or status select)
#define VFC_REG_VFC_CAM_BIST_DBG_SEL_SIZE 1
#define VFC_REG_VFC_CAM_BIST_STATUS 0x19468UL //ACCESS:R DataWidth:0x20 Description: This returns the bist_status which can be done/go/sX_status
#define VFC_REG_VFC_CAM_BIST_STATUS_SIZE 1
#define VFC_REG_KEY_RSS_EXT5 0x1946cUL //ACCESS:RW DataWidth:0x8 Description: Key extension for 5th tuple
#define VFC_REG_KEY_RSS_EXT5_SIZE 1
#define VFC_REG_INP_FIFO_ALM_FULL 0x19470UL //ACCESS:RW DataWidth:0x5 Description: Almost full for input FIFO. When number of entries inside input FIFO is bigger or equal to this number then waitp to STORM will be asserted
#define VFC_REG_INP_FIFO_ALM_FULL_SIZE 1
#define VFC_REG_VFC_UNUSED_EMPTY_0 0x194b8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define VFC_REG_VFC_UNUSED_EMPTY_0_SIZE 10
#define VFC_REG_VFC_UNUSED_EMPTY_1 0x19500UL //ACCESS:R DataWidth:0x20 Unused empty space
#define VFC_REG_VFC_UNUSED_EMPTY_1_SIZE 6848
#define XCM_REG_INIT 0x20000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
#define XCM_REG_XCM_STORM0_IFEN 0x20004UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_XCM_STORM1_IFEN 0x20008UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_XCM_XQM_IFEN 0x2000cUL //ACCESS:RW DataWidth:0x1 Description: CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_STORM_XCM_IFEN 0x20010UL //ACCESS:RW DataWidth:0x1 Description: STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_XQM_XCM_IFEN 0x20014UL //ACCESS:RW DataWidth:0x1 Description: QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_XSDM_IFEN 0x20018UL //ACCESS:RW DataWidth:0x1 Description: Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_TM_XCM_IFEN 0x2001cUL //ACCESS:RW DataWidth:0x1 Description: Timers - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_XCM_TM_IFEN 0x20020UL //ACCESS:RW DataWidth:0x1 Description: CM - Timers Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_TSEM_IFEN 0x20024UL //ACCESS:RW DataWidth:0x1 Description: Input tsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_CSEM_IFEN 0x20028UL //ACCESS:RW DataWidth:0x1 Description: Input csem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_USEM_IFEN 0x2002cUL //ACCESS:RW DataWidth:0x1 Description: Input usem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_DORQ_IFEN 0x20030UL //ACCESS:RW DataWidth:0x1 Description: Input dorq Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_PBF_IFEN 0x20034UL //ACCESS:RW DataWidth:0x1 Description: Input pbf Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_NIG0_IFEN 0x20038UL //ACCESS:RW DataWidth:0x1 Description: Input nig0 Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_NIG1_IFEN 0x2003cUL //ACCESS:RW DataWidth:0x1 Description: Input nig1 Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_CDU_AG_WR_IFEN 0x20040UL //ACCESS:RW DataWidth:0x1 Description: CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_CDU_AG_RD_IFEN 0x20044UL //ACCESS:RW DataWidth:0x1 Description: CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_CDU_SM_WR_IFEN 0x20048UL //ACCESS:RW DataWidth:0x1 Description: CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_CDU_SM_RD_IFEN 0x2004cUL //ACCESS:RW DataWidth:0x1 Description: CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_XCM_CFC_IFEN 0x20050UL //ACCESS:RW DataWidth:0x1 Description: CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
#define XCM_REG_XX_MAX_LL_SZ 0x20054UL //ACCESS:RW DataWidth:0x6 Description: Maximum link list size (number of pending messages) per connection in the XX protection.
#define XCM_REG_XX_OVFL_EVNT_ID 0x20058UL //ACCESS:RW DataWidth:0x8 Description: The Event ID; sent to the STORM in case of XX overflow.
#define XCM_REG_XX_MAX_NUM 0x2005cUL //ACCESS:RW DataWidth:0x5 Description: The maximum number of connections in the XX protection.
#define XCM_REG_N_SM_CTX_LD_0 0x20060UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_1 0x20064UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_2 0x20068UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_3 0x2006cUL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_4 0x20070UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_5 0x20074UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_6 0x20078UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_7 0x2007cUL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_8 0x20080UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_9 0x20084UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_10 0x20088UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_11 0x2008cUL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_12 0x20090UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_13 0x20094UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_14 0x20098UL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_N_SM_CTX_LD_15 0x2009cUL //ACCESS:RW DataWidth:0x5 Description: The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
#define XCM_REG_XQM_XCM_HDR_P 0x200a0UL //ACCESS:RW DataWidth:0x1c Description: The CM header value for QM request (primary).
#define XCM_REG_XQM_XCM_HDR_S 0x200a4UL //ACCESS:RW DataWidth:0x1c Description: The CM header value for QM request (secondary).
#define XCM_REG_TM_XCM_HDR 0x200a8UL //ACCESS:RW DataWidth:0x1c Description: The CM header for Timers expiration command.
#define XCM_REG_ERR_XCM_HDR 0x200acUL //ACCESS:RW DataWidth:0x1c Description: The CM erroneous header for QM and Timers formatting.
#define XCM_REG_ERR_EVNT_ID 0x200b0UL //ACCESS:RW DataWidth:0x8 Description: The Event ID in case the ErrorFlg input message bit is set.
#define XCM_REG_EXPR_EVNT_ID 0x200b4UL //ACCESS:RW DataWidth:0x8 Description: The Event ID for Timers expiration.
#define XCM_REG_STOP_EVNT_ID 0x200b8UL //ACCESS:RW DataWidth:0x8 Description: The Event ID for Timers formatting in case of stop done.
#define XCM_REG_STORM_WEIGHT 0x200bcUL //ACCESS:RW DataWidth:0x3 Description: The weight of the STORM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_TSEM_WEIGHT 0x200c0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input tsem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_CSEM_WEIGHT 0x200c4UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input csem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_USEM_WEIGHT 0x200c8UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input usem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_DORQ_WEIGHT 0x200ccUL //ACCESS:RW DataWidth:0x3 Description: The weight of the input dorq in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_PBF_WEIGHT 0x200d0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input pbf in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_NIG0_WEIGHT 0x200d4UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input nig0 in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_NIG1_WEIGHT 0x200d8UL //ACCESS:RW DataWidth:0x3 Description: The weight of the input nig1 in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_CP_WEIGHT 0x200dcUL //ACCESS:RW DataWidth:0x3 Description: The weight of the CP input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_XSDM_WEIGHT 0x200e0UL //ACCESS:RW DataWidth:0x3 Description: The weight of the SDM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_XQM_P_WEIGHT 0x200e4UL //ACCESS:RW DataWidth:0x3 Description: The weight of the QM (primary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_XQM_S_WEIGHT 0x200e8UL //ACCESS:RW DataWidth:0x3 Description: The weight of the QM (secondary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_TM_WEIGHT 0x200ecUL //ACCESS:RW DataWidth:0x3 Description: The weight of the Timers input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
#define XCM_REG_XCM_XQM_USE_Q 0x200f0UL //ACCESS:RW DataWidth:0x1 Description: If set the Q index; received from the QM is inserted to event ID.
#define XCM_REG_XCM_REG0_SZ 0x200f4UL //ACCESS:RW DataWidth:0x4 Description: The size of AG context region 0 in REG-pairs. Designates the MS REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). Is used to determine the number of the AG context REG-pairs written back; when the Reg1WbFlg isn't set.
#define XCM_REG_STOP_DONE_HDR 0x200f8UL //ACCESS:RW DataWidth:0x1c Description: The CM header for Timers expiration command; when Stop Done input bit is set.
#define XCM_REG_XQM_BYP_ACT_UPD 0x200fcUL //ACCESS:RW DataWidth:0x4 Description: The value by which CFC updates the activity counter at QM bypass.
#define XCM_REG_PERSIST_Q 0x20110UL //ACCESS:RW DataWidth:0x2 Description: The queue index on registration on Persist counter flag.
#define XCM_REG_FORCE_PURE_ACK_Q 0x20114UL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on Force ACK counter flag.
#define XCM_REG_UNA_GT_NXT_Q 0x20120UL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on UNA greater NXT decision rule.
#define XCM_REG_SEND_KA_Q 0x20124UL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on SendKa counter flag.
#define XCM_REG_SET_KA_Q 0x20128UL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on SetKa counter flag.
#define XCM_REG_DA_EXPR_Q 0x2012cUL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on Da Timet expiration flag.
#define XCM_REG_DA_CNT_Q 0x20130UL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on Da counter.
#define XCM_REG_AUX1_Q 0x20134UL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on Aux1 counter flag.
#define XCM_REG_AUX2_Q 0x20138UL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on Aux2 counter flag.
#define XCM_REG_AUX3_Q 0x2013cUL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on Aux3 counter flag.
#define XCM_REG_AUX4_Q 0x20140UL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on Aux4 counter flag.
#define XCM_REG_DEC_RULE_Q_1 0x20144UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_DEC_RULE_Q_2 0x20148UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_DEC_RULE_Q_3 0x2014cUL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_DEC_RULE_Q_4 0x20150UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_DEC_RULE_Q_5 0x20154UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_DEC_RULE_Q_6 0x20158UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_DEC_RULE_Q_7 0x2015cUL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_DEC_RULE_Q_8 0x20160UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_DEC_RULE_Q_10 0x20164UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_DEC_RULE_Q_11 0x20168UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_GOTO_SS_Q 0x2016cUL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on GoToSs counter flag.
#define XCM_REG_FAST_RXMIT_Q 0x20170UL //ACCESS:RW DataWidth:0x2 Description: The queue index for registration on Fast retransmit.
#define XCM_REG_MORE2_SEND_Q 0x20174UL //ACCESS:RW DataWidth:0x2 Description: The queu index for registration on More2Send rule.
#define XCM_REG_AUX_CNT_FLG_Q_5 0x20178UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_6 0x2017cUL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_7 0x20180UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_8 0x20184UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_9 0x20188UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_10 0x2018cUL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_11 0x20190UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_12 0x20194UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_13 0x20198UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_14 0x2019cUL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_15 0x201a0UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_16 0x201a4UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_17 0x201a8UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_18 0x201acUL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_20 0x201b4UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_AUX_CNT_FLG_Q_21 0x201b8UL //ACCESS:RW DataWidth:0x2 Description: Per each decision rule the queue index to register to.
#define XCM_REG_TX_FIN_FLG_Q 0x201bcUL //ACCESS:RW DataWidth:0x2 Description: Queue index for TxFin flag decision rule.
#define XCM_REG_DQ_SPR_FLG_Q 0x201c0UL //ACCESS:RW DataWidth:0x2 Description: Queue index for TxSpare flag decision rule.
#define XCM_REG_SM_CTX0_TM 0x201f4UL //ACCESS:RW DataWidth:0x5 Description: TM bits of STORM context.
#define XCM_REG_SM_CTX1_TM 0x201f8UL //ACCESS:RW DataWidth:0x4 Description: TM bits of STORM context.
#define XCM_REG_AG_CTX00_TM 0x201fcUL //ACCESS:RW DataWidth:0x5 Description: TM bits of AG context.
#define XCM_REG_AG_CTX10_TM 0x20204UL //ACCESS:RW DataWidth:0x5 Description: TM bits of AG context.
#define XCM_REG_GR_ARB_TYPE 0x2020cUL //ACCESS:RW DataWidth:0x1 Description: Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr; ~xcm_registers_gr_ld0_pr.gr_ld0_pr and ~xcm_registers_gr_ld1_pr.gr_ld1_pr.
#define XCM_REG_GR_AG_PR 0x20210UL //ACCESS:RW DataWidth:0x2 Description: AG channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Channel group is the compliment of the other 3 groups.
#define XCM_REG_GR_LD0_PR 0x20214UL //ACCESS:RW DataWidth:0x2 Description: Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Channel group is the compliment of the other 3 groups.
#define XCM_REG_GR_LD1_PR 0x20218UL //ACCESS:RW DataWidth:0x2 Description: Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Channel group is the compliment of the other 3 groups.
#define XCM_REG_STORM_LENGTH_MIS 0x2021cUL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the STORM interface.
#define XCM_REG_XSDM_LENGTH_MIS 0x20220UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the SDM interface.
#define XCM_REG_TSEM_LENGTH_MIS 0x20224UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the tsem interface.
#define XCM_REG_CSEM_LENGTH_MIS 0x20228UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the csem interface.
#define XCM_REG_USEM_LENGTH_MIS 0x2022cUL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the usem interface.
#define XCM_REG_DORQ_LENGTH_MIS 0x20230UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the dorq interface.
#define XCM_REG_PBF_LENGTH_MIS 0x20234UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the pbf interface.
#define XCM_REG_NIG0_LENGTH_MIS 0x20238UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the nig0 interface.
#define XCM_REG_NIG1_LENGTH_MIS 0x2023cUL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the nig1 interface.
#define XCM_REG_XX_FREE 0x20240UL //ACCESS:R DataWidth:0x6 Description: Used to read the XX protection Free counter.
#define XCM_REG_CAM_OCCUP 0x20244UL //ACCESS:R DataWidth:0x5 Description: Used to read the XX protection CAM occupancy counter.
#define XCM_REG_UNLOCK_MISS 0x20248UL //ACCESS:RC DataWidth:0x1 Description: Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM; happens.
#define XCM_REG_XQM_GLB_USE_CNTR 0x2024cUL //ACCESS:R DataWidth:0x1a Description: Used to read the QM global usage counter.
#define XCM_REG_CP_BUF_EMPTY 0x20250UL //ACCESS:R DataWidth:0x1 Description: CP buffer is empty indication.
#define XCM_REG_CP_BUF_STATUS 0x20254UL //ACCESS:R DataWidth:0x5 Description: CP buffer status.
#define XCM_REG_XX_OVFL_CNTR 0x20258UL //ACCESS:ST DataWidth:0x10 Description: Counter of XX 0verflow occurencies.
#define XCM_REG_STORM_MSG_CNTR 0x2025cUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the STORM input.
#define XCM_REG_XSDM_MSG_CNTR 0x20260UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input SDM.
#define XCM_REG_TSEM_MSG_CNTR 0x20264UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input tsem.
#define XCM_REG_CSEM_MSG_CNTR 0x20268UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input csem.
#define XCM_REG_USEM_MSG_CNTR 0x2026cUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input usem.
#define XCM_REG_DORQ_MSG_CNTR 0x20270UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input dorq.
#define XCM_REG_PBF_MSG_CNTR 0x20274UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input pbf.
#define XCM_REG_NIG0_MSG_CNTR 0x20278UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input nig0.
#define XCM_REG_NIG1_MSG_CNTR 0x2027cUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the input nig1.
#define XCM_REG_CP_MSG_CNTR 0x20280UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the CP input.
#define XCM_REG_XQM_P_MSG_CNTR 0x20284UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the QM input (primary).
#define XCM_REG_XQM_S_MSG_CNTR 0x20288UL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the QM input (secondary).
#define XCM_REG_TM_MSG_CNTR 0x2028cUL //ACCESS:ST DataWidth:0x18 Description: Counter of the input messages at the Timers input.
#define XCM_REG_STORM_OUT_CNTR 0x20290UL //ACCESS:ST DataWidth:0x18 Description: Counter of the output messages at FIC0 and FIC1 interfaces.
#define XCM_REG_XQM_OUT_CNTR 0x20294UL //ACCESS:ST DataWidth:0x18 Description: Counter of the output QM commands.
#define XCM_REG_TM_OUT_CNTR 0x20298UL //ACCESS:ST DataWidth:0x18 Description: Counter of the output Timers commands.
#define XCM_REG_DBG_SELECT 0x2029cUL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from XCM to the DBG block) - for selecting a line to output to the DBG block.
#define XCM_REG_DBG_BYTE_ENABLE 0x202a0UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from XCM to the DBG block) - for enabling bytes in the selected line (after the select; before the shift).
#define XCM_REG_DBG_SHIFT 0x202a4UL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from XCM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define XCM_REG_XCM_INT_STS 0x202a8UL //ACCESS:R DataWidth:0xe Description: Interrupt register #0 read
#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define XCM_XCM_INT_STS_REG_XX_UQ_ERR (0x1<<1)
#define XCM_XCM_INT_STS_REG_XX_UQ_ERR_SIZE 1
#define XCM_XCM_INT_STS_REG_STORM_ERR (0x1<<2)
#define XCM_XCM_INT_STS_REG_STORM_ERR_SIZE 2
#define XCM_XCM_INT_STS_REG_XSDM_ERR (0x1<<3)
#define XCM_XCM_INT_STS_REG_XSDM_ERR_SIZE 3
#define XCM_XCM_INT_STS_REG_TSEM_ERR (0x1<<4)
#define XCM_XCM_INT_STS_REG_TSEM_ERR_SIZE 4
#define XCM_XCM_INT_STS_REG_CSEM_ERR (0x1<<5)
#define XCM_XCM_INT_STS_REG_CSEM_ERR_SIZE 5
#define XCM_XCM_INT_STS_REG_USEM_ERR (0x1<<6)
#define XCM_XCM_INT_STS_REG_USEM_ERR_SIZE 6
#define XCM_XCM_INT_STS_REG_DORQ_ERR (0x1<<7)
#define XCM_XCM_INT_STS_REG_DORQ_ERR_SIZE 7
#define XCM_XCM_INT_STS_REG_PBF_ERR (0x1<<8)
#define XCM_XCM_INT_STS_REG_PBF_ERR_SIZE 8
#define XCM_XCM_INT_STS_REG_NIG0_ERR (0x1<<9)
#define XCM_XCM_INT_STS_REG_NIG0_ERR_SIZE 9
#define XCM_XCM_INT_STS_REG_NIG1_ERR (0x1<<10)
#define XCM_XCM_INT_STS_REG_NIG1_ERR_SIZE 10
#define XCM_XCM_INT_STS_REG_CP0_ERR (0x1<<11)
#define XCM_XCM_INT_STS_REG_CP0_ERR_SIZE 11
#define XCM_XCM_INT_STS_REG_CP1_ERR (0x1<<12)
#define XCM_XCM_INT_STS_REG_CP1_ERR_SIZE 12
#define XCM_XCM_INT_STS_REG_UM_ERR (0x1<<13)
#define XCM_XCM_INT_STS_REG_UM_ERR_SIZE 13
#define XCM_REG_XCM_INT_STS_CLR 0x202acUL //ACCESS:RC DataWidth:0xe Description: Interrupt register #0 read clear
#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
#define XCM_XCM_INT_STS_CLR_REG_XX_UQ_ERR (0x1<<1)
#define XCM_XCM_INT_STS_CLR_REG_XX_UQ_ERR_SIZE 1
#define XCM_XCM_INT_STS_CLR_REG_STORM_ERR (0x1<<2)
#define XCM_XCM_INT_STS_CLR_REG_STORM_ERR_SIZE 2
#define XCM_XCM_INT_STS_CLR_REG_XSDM_ERR (0x1<<3)
#define XCM_XCM_INT_STS_CLR_REG_XSDM_ERR_SIZE 3
#define XCM_XCM_INT_STS_CLR_REG_TSEM_ERR (0x1<<4)
#define XCM_XCM_INT_STS_CLR_REG_TSEM_ERR_SIZE 4
#define XCM_XCM_INT_STS_CLR_REG_CSEM_ERR (0x1<<5)
#define XCM_XCM_INT_STS_CLR_REG_CSEM_ERR_SIZE 5
#define XCM_XCM_INT_STS_CLR_REG_USEM_ERR (0x1<<6)
#define XCM_XCM_INT_STS_CLR_REG_USEM_ERR_SIZE 6
#define XCM_XCM_INT_STS_CLR_REG_DORQ_ERR (0x1<<7)
#define XCM_XCM_INT_STS_CLR_REG_DORQ_ERR_SIZE 7
#define XCM_XCM_INT_STS_CLR_REG_PBF_ERR (0x1<<8)
#define XCM_XCM_INT_STS_CLR_REG_PBF_ERR_SIZE 8
#define XCM_XCM_INT_STS_CLR_REG_NIG0_ERR (0x1<<9)
#define XCM_XCM_INT_STS_CLR_REG_NIG0_ERR_SIZE 9
#define XCM_XCM_INT_STS_CLR_REG_NIG1_ERR (0x1<<10)
#define XCM_XCM_INT_STS_CLR_REG_NIG1_ERR_SIZE 10
#define XCM_XCM_INT_STS_CLR_REG_CP0_ERR (0x1<<11)
#define XCM_XCM_INT_STS_CLR_REG_CP0_ERR_SIZE 11
#define XCM_XCM_INT_STS_CLR_REG_CP1_ERR (0x1<<12)
#define XCM_XCM_INT_STS_CLR_REG_CP1_ERR_SIZE 12
#define XCM_XCM_INT_STS_CLR_REG_UM_ERR (0x1<<13)
#define XCM_XCM_INT_STS_CLR_REG_UM_ERR_SIZE 13
#define XCM_REG_XCM_INT_STS_WR 0x202b0UL //ACCESS:WR DataWidth:0xe Description: Interrupt register #0 bit set or clear
#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define XCM_XCM_INT_STS_WR_REG_XX_UQ_ERR (0x1<<1)
#define XCM_XCM_INT_STS_WR_REG_XX_UQ_ERR_SIZE 1
#define XCM_XCM_INT_STS_WR_REG_STORM_ERR (0x1<<2)
#define XCM_XCM_INT_STS_WR_REG_STORM_ERR_SIZE 2
#define XCM_XCM_INT_STS_WR_REG_XSDM_ERR (0x1<<3)
#define XCM_XCM_INT_STS_WR_REG_XSDM_ERR_SIZE 3
#define XCM_XCM_INT_STS_WR_REG_TSEM_ERR (0x1<<4)
#define XCM_XCM_INT_STS_WR_REG_TSEM_ERR_SIZE 4
#define XCM_XCM_INT_STS_WR_REG_CSEM_ERR (0x1<<5)
#define XCM_XCM_INT_STS_WR_REG_CSEM_ERR_SIZE 5
#define XCM_XCM_INT_STS_WR_REG_USEM_ERR (0x1<<6)
#define XCM_XCM_INT_STS_WR_REG_USEM_ERR_SIZE 6
#define XCM_XCM_INT_STS_WR_REG_DORQ_ERR (0x1<<7)
#define XCM_XCM_INT_STS_WR_REG_DORQ_ERR_SIZE 7
#define XCM_XCM_INT_STS_WR_REG_PBF_ERR (0x1<<8)
#define XCM_XCM_INT_STS_WR_REG_PBF_ERR_SIZE 8
#define XCM_XCM_INT_STS_WR_REG_NIG0_ERR (0x1<<9)
#define XCM_XCM_INT_STS_WR_REG_NIG0_ERR_SIZE 9
#define XCM_XCM_INT_STS_WR_REG_NIG1_ERR (0x1<<10)
#define XCM_XCM_INT_STS_WR_REG_NIG1_ERR_SIZE 10
#define XCM_XCM_INT_STS_WR_REG_CP0_ERR (0x1<<11)
#define XCM_XCM_INT_STS_WR_REG_CP0_ERR_SIZE 11
#define XCM_XCM_INT_STS_WR_REG_CP1_ERR (0x1<<12)
#define XCM_XCM_INT_STS_WR_REG_CP1_ERR_SIZE 12
#define XCM_XCM_INT_STS_WR_REG_UM_ERR (0x1<<13)
#define XCM_XCM_INT_STS_WR_REG_UM_ERR_SIZE 13
#define XCM_REG_XCM_INT_MASK 0x202b4UL //ACCESS:RW DataWidth:0xe Description: Interrupt mask register #0 read/write
#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
#define XCM_XCM_INT_MASK_REG_XX_UQ_ERR (0x1<<1)
#define XCM_XCM_INT_MASK_REG_XX_UQ_ERR_SIZE 1
#define XCM_XCM_INT_MASK_REG_STORM_ERR (0x1<<2)
#define XCM_XCM_INT_MASK_REG_STORM_ERR_SIZE 2
#define XCM_XCM_INT_MASK_REG_XSDM_ERR (0x1<<3)
#define XCM_XCM_INT_MASK_REG_XSDM_ERR_SIZE 3
#define XCM_XCM_INT_MASK_REG_TSEM_ERR (0x1<<4)
#define XCM_XCM_INT_MASK_REG_TSEM_ERR_SIZE 4
#define XCM_XCM_INT_MASK_REG_CSEM_ERR (0x1<<5)
#define XCM_XCM_INT_MASK_REG_CSEM_ERR_SIZE 5
#define XCM_XCM_INT_MASK_REG_USEM_ERR (0x1<<6)
#define XCM_XCM_INT_MASK_REG_USEM_ERR_SIZE 6
#define XCM_XCM_INT_MASK_REG_DORQ_ERR (0x1<<7)
#define XCM_XCM_INT_MASK_REG_DORQ_ERR_SIZE 7
#define XCM_XCM_INT_MASK_REG_PBF_ERR (0x1<<8)
#define XCM_XCM_INT_MASK_REG_PBF_ERR_SIZE 8
#define XCM_XCM_INT_MASK_REG_NIG0_ERR (0x1<<9)
#define XCM_XCM_INT_MASK_REG_NIG0_ERR_SIZE 9
#define XCM_XCM_INT_MASK_REG_NIG1_ERR (0x1<<10)
#define XCM_XCM_INT_MASK_REG_NIG1_ERR_SIZE 10
#define XCM_XCM_INT_MASK_REG_CP0_ERR (0x1<<11)
#define XCM_XCM_INT_MASK_REG_CP0_ERR_SIZE 11
#define XCM_XCM_INT_MASK_REG_CP1_ERR (0x1<<12)
#define XCM_XCM_INT_MASK_REG_CP1_ERR_SIZE 12
#define XCM_XCM_INT_MASK_REG_UM_ERR (0x1<<13)
#define XCM_XCM_INT_MASK_REG_UM_ERR_SIZE 13
#define XCM_REG_XCM_PRTY_STS 0x202b8UL //ACCESS:R DataWidth:0x1e Description: Parity register #0 read
#define XCM_XCM_PRTY_STS_REG_PARITY (0x1<<0)
#define XCM_XCM_PRTY_STS_REG_PARITY_SIZE 0
#define XCM_XCM_PRTY_STS_REG_XT_PRTY (0x1<<1)
#define XCM_XCM_PRTY_STS_REG_XT_PRTY_SIZE 1
#define XCM_XCM_PRTY_STS_REG_DT_PRTY (0x1<<2)
#define XCM_XCM_PRTY_STS_REG_DT_PRTY_SIZE 2
#define XCM_XCM_PRTY_STS_REG_PM_PRTY0 (0x1<<3)
#define XCM_XCM_PRTY_STS_REG_PM_PRTY0_SIZE 3
#define XCM_XCM_PRTY_STS_REG_PM_PRTY1 (0x1<<4)
#define XCM_XCM_PRTY_STS_REG_PM_PRTY1_SIZE 4
#define XCM_XCM_PRTY_STS_REG_UQ_PRTY (0x1<<5)
#define XCM_XCM_PRTY_STS_REG_UQ_PRTY_SIZE 5
#define XCM_XCM_PRTY_STS_REG_AG_PRTY0 (0x1<<6)
#define XCM_XCM_PRTY_STS_REG_AG_PRTY0_SIZE 6
#define XCM_XCM_PRTY_STS_REG_AG_PRTY1 (0x1<<7)
#define XCM_XCM_PRTY_STS_REG_AG_PRTY1_SIZE 7
#define XCM_XCM_PRTY_STS_REG_AG_PRTY2 (0x1<<8)
#define XCM_XCM_PRTY_STS_REG_AG_PRTY2_SIZE 8
#define XCM_XCM_PRTY_STS_REG_AG_PRTY3 (0x1<<9)
#define XCM_XCM_PRTY_STS_REG_AG_PRTY3_SIZE 9
#define XCM_XCM_PRTY_STS_REG_AG_PRTY4 (0x1<<10)
#define XCM_XCM_PRTY_STS_REG_AG_PRTY4_SIZE 10
#define XCM_XCM_PRTY_STS_REG_AG_PRTY5 (0x1<<11)
#define XCM_XCM_PRTY_STS_REG_AG_PRTY5_SIZE 11
#define XCM_XCM_PRTY_STS_REG_AG_PRTY6 (0x1<<12)
#define XCM_XCM_PRTY_STS_REG_AG_PRTY6_SIZE 12
#define XCM_XCM_PRTY_STS_REG_AG_PRTY7 (0x1<<13)
#define XCM_XCM_PRTY_STS_REG_AG_PRTY7_SIZE 13
#define XCM_XCM_PRTY_STS_REG_SM_PRTY0 (0x1<<14)
#define XCM_XCM_PRTY_STS_REG_SM_PRTY0_SIZE 14
#define XCM_XCM_PRTY_STS_REG_SM_PRTY1 (0x1<<15)
#define XCM_XCM_PRTY_STS_REG_SM_PRTY1_SIZE 15
#define XCM_XCM_PRTY_STS_REG_SM_PRTY2 (0x1<<16)
#define XCM_XCM_PRTY_STS_REG_SM_PRTY2_SIZE 16
#define XCM_XCM_PRTY_STS_REG_SM_PRTY3 (0x1<<17)
#define XCM_XCM_PRTY_STS_REG_SM_PRTY3_SIZE 17
#define XCM_XCM_PRTY_STS_REG_STORM_PRTY (0x1<<18)
#define XCM_XCM_PRTY_STS_REG_STORM_PRTY_SIZE 18
#define XCM_XCM_PRTY_STS_REG_XSDM_PRTY (0x1<<19)
#define XCM_XCM_PRTY_STS_REG_XSDM_PRTY_SIZE 19
#define XCM_XCM_PRTY_STS_REG_TSEM_PRTY (0x1<<20)
#define XCM_XCM_PRTY_STS_REG_TSEM_PRTY_SIZE 20
#define XCM_XCM_PRTY_STS_REG_CSEM_PRTY (0x1<<21)
#define XCM_XCM_PRTY_STS_REG_CSEM_PRTY_SIZE 21
#define XCM_XCM_PRTY_STS_REG_USEM_PRTY (0x1<<22)
#define XCM_XCM_PRTY_STS_REG_USEM_PRTY_SIZE 22
#define XCM_XCM_PRTY_STS_REG_DORQ_PRTY (0x1<<23)
#define XCM_XCM_PRTY_STS_REG_DORQ_PRTY_SIZE 23
#define XCM_XCM_PRTY_STS_REG_PBF_PRTY (0x1<<24)
#define XCM_XCM_PRTY_STS_REG_PBF_PRTY_SIZE 24
#define XCM_XCM_PRTY_STS_REG_NIG0_PRTY (0x1<<25)
#define XCM_XCM_PRTY_STS_REG_NIG0_PRTY_SIZE 25
#define XCM_XCM_PRTY_STS_REG_NIG1_PRTY (0x1<<26)
#define XCM_XCM_PRTY_STS_REG_NIG1_PRTY_SIZE 26
#define XCM_XCM_PRTY_STS_REG_CP0_PRTY (0x1<<27)
#define XCM_XCM_PRTY_STS_REG_CP0_PRTY_SIZE 27
#define XCM_XCM_PRTY_STS_REG_CP1_PRTY (0x1<<28)
#define XCM_XCM_PRTY_STS_REG_CP1_PRTY_SIZE 28
#define XCM_XCM_PRTY_STS_REG_UM_PRTY (0x1<<29)
#define XCM_XCM_PRTY_STS_REG_UM_PRTY_SIZE 29
#define XCM_REG_XCM_PRTY_STS_CLR 0x202bcUL //ACCESS:RC DataWidth:0x1e Description: Parity register #0 read clear
#define XCM_XCM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define XCM_XCM_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define XCM_XCM_PRTY_STS_CLR_REG_XT_PRTY (0x1<<1)
#define XCM_XCM_PRTY_STS_CLR_REG_XT_PRTY_SIZE 1
#define XCM_XCM_PRTY_STS_CLR_REG_DT_PRTY (0x1<<2)
#define XCM_XCM_PRTY_STS_CLR_REG_DT_PRTY_SIZE 2
#define XCM_XCM_PRTY_STS_CLR_REG_PM_PRTY0 (0x1<<3)
#define XCM_XCM_PRTY_STS_CLR_REG_PM_PRTY0_SIZE 3
#define XCM_XCM_PRTY_STS_CLR_REG_PM_PRTY1 (0x1<<4)
#define XCM_XCM_PRTY_STS_CLR_REG_PM_PRTY1_SIZE 4
#define XCM_XCM_PRTY_STS_CLR_REG_UQ_PRTY (0x1<<5)
#define XCM_XCM_PRTY_STS_CLR_REG_UQ_PRTY_SIZE 5
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY0 (0x1<<6)
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY0_SIZE 6
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY1 (0x1<<7)
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY1_SIZE 7
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY2 (0x1<<8)
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY2_SIZE 8
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY3 (0x1<<9)
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY3_SIZE 9
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY4 (0x1<<10)
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY4_SIZE 10
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY5 (0x1<<11)
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY5_SIZE 11
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY6 (0x1<<12)
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY6_SIZE 12
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY7 (0x1<<13)
#define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY7_SIZE 13
#define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY0 (0x1<<14)
#define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY0_SIZE 14
#define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY1 (0x1<<15)
#define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY1_SIZE 15
#define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY2 (0x1<<16)
#define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY2_SIZE 16
#define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY3 (0x1<<17)
#define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY3_SIZE 17
#define XCM_XCM_PRTY_STS_CLR_REG_STORM_PRTY (0x1<<18)
#define XCM_XCM_PRTY_STS_CLR_REG_STORM_PRTY_SIZE 18
#define XCM_XCM_PRTY_STS_CLR_REG_XSDM_PRTY (0x1<<19)
#define XCM_XCM_PRTY_STS_CLR_REG_XSDM_PRTY_SIZE 19
#define XCM_XCM_PRTY_STS_CLR_REG_TSEM_PRTY (0x1<<20)
#define XCM_XCM_PRTY_STS_CLR_REG_TSEM_PRTY_SIZE 20
#define XCM_XCM_PRTY_STS_CLR_REG_CSEM_PRTY (0x1<<21)
#define XCM_XCM_PRTY_STS_CLR_REG_CSEM_PRTY_SIZE 21
#define XCM_XCM_PRTY_STS_CLR_REG_USEM_PRTY (0x1<<22)
#define XCM_XCM_PRTY_STS_CLR_REG_USEM_PRTY_SIZE 22
#define XCM_XCM_PRTY_STS_CLR_REG_DORQ_PRTY (0x1<<23)
#define XCM_XCM_PRTY_STS_CLR_REG_DORQ_PRTY_SIZE 23
#define XCM_XCM_PRTY_STS_CLR_REG_PBF_PRTY (0x1<<24)
#define XCM_XCM_PRTY_STS_CLR_REG_PBF_PRTY_SIZE 24
#define XCM_XCM_PRTY_STS_CLR_REG_NIG0_PRTY (0x1<<25)
#define XCM_XCM_PRTY_STS_CLR_REG_NIG0_PRTY_SIZE 25
#define XCM_XCM_PRTY_STS_CLR_REG_NIG1_PRTY (0x1<<26)
#define XCM_XCM_PRTY_STS_CLR_REG_NIG1_PRTY_SIZE 26
#define XCM_XCM_PRTY_STS_CLR_REG_CP0_PRTY (0x1<<27)
#define XCM_XCM_PRTY_STS_CLR_REG_CP0_PRTY_SIZE 27
#define XCM_XCM_PRTY_STS_CLR_REG_CP1_PRTY (0x1<<28)
#define XCM_XCM_PRTY_STS_CLR_REG_CP1_PRTY_SIZE 28
#define XCM_XCM_PRTY_STS_CLR_REG_UM_PRTY (0x1<<29)
#define XCM_XCM_PRTY_STS_CLR_REG_UM_PRTY_SIZE 29
#define XCM_REG_XCM_PRTY_STS_WR 0x202c0UL //ACCESS:WR DataWidth:0x1e Description: Parity register #0 bit set or clear
#define XCM_XCM_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define XCM_XCM_PRTY_STS_WR_REG_PARITY_SIZE 0
#define XCM_XCM_PRTY_STS_WR_REG_XT_PRTY (0x1<<1)
#define XCM_XCM_PRTY_STS_WR_REG_XT_PRTY_SIZE 1
#define XCM_XCM_PRTY_STS_WR_REG_DT_PRTY (0x1<<2)
#define XCM_XCM_PRTY_STS_WR_REG_DT_PRTY_SIZE 2
#define XCM_XCM_PRTY_STS_WR_REG_PM_PRTY0 (0x1<<3)
#define XCM_XCM_PRTY_STS_WR_REG_PM_PRTY0_SIZE 3
#define XCM_XCM_PRTY_STS_WR_REG_PM_PRTY1 (0x1<<4)
#define XCM_XCM_PRTY_STS_WR_REG_PM_PRTY1_SIZE 4
#define XCM_XCM_PRTY_STS_WR_REG_UQ_PRTY (0x1<<5)
#define XCM_XCM_PRTY_STS_WR_REG_UQ_PRTY_SIZE 5
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY0 (0x1<<6)
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY0_SIZE 6
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY1 (0x1<<7)
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY1_SIZE 7
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY2 (0x1<<8)
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY2_SIZE 8
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY3 (0x1<<9)
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY3_SIZE 9
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY4 (0x1<<10)
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY4_SIZE 10
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY5 (0x1<<11)
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY5_SIZE 11
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY6 (0x1<<12)
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY6_SIZE 12
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY7 (0x1<<13)
#define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY7_SIZE 13
#define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY0 (0x1<<14)
#define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY0_SIZE 14
#define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY1 (0x1<<15)
#define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY1_SIZE 15
#define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY2 (0x1<<16)
#define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY2_SIZE 16
#define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY3 (0x1<<17)
#define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY3_SIZE 17
#define XCM_XCM_PRTY_STS_WR_REG_STORM_PRTY (0x1<<18)
#define XCM_XCM_PRTY_STS_WR_REG_STORM_PRTY_SIZE 18
#define XCM_XCM_PRTY_STS_WR_REG_XSDM_PRTY (0x1<<19)
#define XCM_XCM_PRTY_STS_WR_REG_XSDM_PRTY_SIZE 19
#define XCM_XCM_PRTY_STS_WR_REG_TSEM_PRTY (0x1<<20)
#define XCM_XCM_PRTY_STS_WR_REG_TSEM_PRTY_SIZE 20
#define XCM_XCM_PRTY_STS_WR_REG_CSEM_PRTY (0x1<<21)
#define XCM_XCM_PRTY_STS_WR_REG_CSEM_PRTY_SIZE 21
#define XCM_XCM_PRTY_STS_WR_REG_USEM_PRTY (0x1<<22)
#define XCM_XCM_PRTY_STS_WR_REG_USEM_PRTY_SIZE 22
#define XCM_XCM_PRTY_STS_WR_REG_DORQ_PRTY (0x1<<23)
#define XCM_XCM_PRTY_STS_WR_REG_DORQ_PRTY_SIZE 23
#define XCM_XCM_PRTY_STS_WR_REG_PBF_PRTY (0x1<<24)
#define XCM_XCM_PRTY_STS_WR_REG_PBF_PRTY_SIZE 24
#define XCM_XCM_PRTY_STS_WR_REG_NIG0_PRTY (0x1<<25)
#define XCM_XCM_PRTY_STS_WR_REG_NIG0_PRTY_SIZE 25
#define XCM_XCM_PRTY_STS_WR_REG_NIG1_PRTY (0x1<<26)
#define XCM_XCM_PRTY_STS_WR_REG_NIG1_PRTY_SIZE 26
#define XCM_XCM_PRTY_STS_WR_REG_CP0_PRTY (0x1<<27)
#define XCM_XCM_PRTY_STS_WR_REG_CP0_PRTY_SIZE 27
#define XCM_XCM_PRTY_STS_WR_REG_CP1_PRTY (0x1<<28)
#define XCM_XCM_PRTY_STS_WR_REG_CP1_PRTY_SIZE 28
#define XCM_XCM_PRTY_STS_WR_REG_UM_PRTY (0x1<<29)
#define XCM_XCM_PRTY_STS_WR_REG_UM_PRTY_SIZE 29
#define XCM_REG_XCM_PRTY_MASK 0x202c4UL //ACCESS:RW DataWidth:0x1e Description: Parity mask register #0 read/write
#define XCM_XCM_PRTY_MASK_REG_PARITY (0x1<<0)
#define XCM_XCM_PRTY_MASK_REG_PARITY_SIZE 0
#define XCM_XCM_PRTY_MASK_REG_XT_PRTY (0x1<<1)
#define XCM_XCM_PRTY_MASK_REG_XT_PRTY_SIZE 1
#define XCM_XCM_PRTY_MASK_REG_DT_PRTY (0x1<<2)
#define XCM_XCM_PRTY_MASK_REG_DT_PRTY_SIZE 2
#define XCM_XCM_PRTY_MASK_REG_PM_PRTY0 (0x1<<3)
#define XCM_XCM_PRTY_MASK_REG_PM_PRTY0_SIZE 3
#define XCM_XCM_PRTY_MASK_REG_PM_PRTY1 (0x1<<4)
#define XCM_XCM_PRTY_MASK_REG_PM_PRTY1_SIZE 4
#define XCM_XCM_PRTY_MASK_REG_UQ_PRTY (0x1<<5)
#define XCM_XCM_PRTY_MASK_REG_UQ_PRTY_SIZE 5
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY0 (0x1<<6)
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY0_SIZE 6
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY1 (0x1<<7)
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY1_SIZE 7
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY2 (0x1<<8)
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY2_SIZE 8
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY3 (0x1<<9)
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY3_SIZE 9
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY4 (0x1<<10)
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY4_SIZE 10
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY5 (0x1<<11)
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY5_SIZE 11
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY6 (0x1<<12)
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY6_SIZE 12
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY7 (0x1<<13)
#define XCM_XCM_PRTY_MASK_REG_AG_PRTY7_SIZE 13
#define XCM_XCM_PRTY_MASK_REG_SM_PRTY0 (0x1<<14)
#define XCM_XCM_PRTY_MASK_REG_SM_PRTY0_SIZE 14
#define XCM_XCM_PRTY_MASK_REG_SM_PRTY1 (0x1<<15)
#define XCM_XCM_PRTY_MASK_REG_SM_PRTY1_SIZE 15
#define XCM_XCM_PRTY_MASK_REG_SM_PRTY2 (0x1<<16)
#define XCM_XCM_PRTY_MASK_REG_SM_PRTY2_SIZE 16
#define XCM_XCM_PRTY_MASK_REG_SM_PRTY3 (0x1<<17)
#define XCM_XCM_PRTY_MASK_REG_SM_PRTY3_SIZE 17
#define XCM_XCM_PRTY_MASK_REG_STORM_PRTY (0x1<<18)
#define XCM_XCM_PRTY_MASK_REG_STORM_PRTY_SIZE 18
#define XCM_XCM_PRTY_MASK_REG_XSDM_PRTY (0x1<<19)
#define XCM_XCM_PRTY_MASK_REG_XSDM_PRTY_SIZE 19
#define XCM_XCM_PRTY_MASK_REG_TSEM_PRTY (0x1<<20)
#define XCM_XCM_PRTY_MASK_REG_TSEM_PRTY_SIZE 20
#define XCM_XCM_PRTY_MASK_REG_CSEM_PRTY (0x1<<21)
#define XCM_XCM_PRTY_MASK_REG_CSEM_PRTY_SIZE 21
#define XCM_XCM_PRTY_MASK_REG_USEM_PRTY (0x1<<22)
#define XCM_XCM_PRTY_MASK_REG_USEM_PRTY_SIZE 22
#define XCM_XCM_PRTY_MASK_REG_DORQ_PRTY (0x1<<23)
#define XCM_XCM_PRTY_MASK_REG_DORQ_PRTY_SIZE 23
#define XCM_XCM_PRTY_MASK_REG_PBF_PRTY (0x1<<24)
#define XCM_XCM_PRTY_MASK_REG_PBF_PRTY_SIZE 24
#define XCM_XCM_PRTY_MASK_REG_NIG0_PRTY (0x1<<25)
#define XCM_XCM_PRTY_MASK_REG_NIG0_PRTY_SIZE 25
#define XCM_XCM_PRTY_MASK_REG_NIG1_PRTY (0x1<<26)
#define XCM_XCM_PRTY_MASK_REG_NIG1_PRTY_SIZE 26
#define XCM_XCM_PRTY_MASK_REG_CP0_PRTY (0x1<<27)
#define XCM_XCM_PRTY_MASK_REG_CP0_PRTY_SIZE 27
#define XCM_XCM_PRTY_MASK_REG_CP1_PRTY (0x1<<28)
#define XCM_XCM_PRTY_MASK_REG_CP1_PRTY_SIZE 28
#define XCM_XCM_PRTY_MASK_REG_UM_PRTY (0x1<<29)
#define XCM_XCM_PRTY_MASK_REG_UM_PRTY_SIZE 29
#define XCM_REG_IS_STORM_TM 0x202c8UL //ACCESS:RW DataWidth:0x8 Description: TM bits of input message STORM buffer.
#define XCM_REG_SM_CTX01_TM 0x202ccUL //ACCESS:RW DataWidth:0x4 Description: TM bits of STORM context.
#define XCM_REG_SM_CTX11_TM 0x202d0UL //ACCESS:RW DataWidth:0x4 Description: TM bits of STORM context.
#define XCM_REG_IS_UM_TM 0x202d4UL //ACCESS:RW DataWidth:0x2 Description: TM bits of input stage UM buffer.
#define XCM_REG_PM_RAM_TM 0x202d8UL //ACCESS:RW DataWidth:0x2 Description: TM bits of Pending messages RAM.
#define XCM_REG_IS_NIG0_TM 0x202dcUL //ACCESS:RW DataWidth:0x8 Description: TM bits of input stage NIG0 buffer.
#define XCM_REG_IS_NIG1_TM 0x202e0UL //ACCESS:RW DataWidth:0x8 Description: TM bits of input stage NIG1 buffer.
#define XCM_REG_ECO_RESERVED 0x202e4UL //ACCESS:RW DataWidth:0x8 Description: chicken bits
#define XCM_REG_IS_USEM_TM 0x202e8UL //ACCESS:RW DataWidth:0x2 Description: TM bits of input stage USEM buffer.
#define XCM_REG_IS_TSEM_TM 0x202ecUL //ACCESS:RW DataWidth:0x2 Description: TM bits of input stage TSEM buffer.
#define XCM_REG_UM_FIC1_FORCE 0x202f0UL //ACCESS:RW DataWidth:0x1 Description: 0-messages unlocked from Pending messages RAM go to the FIC for which they were designated in input message; 1-messages unlocked from Pending messages RAM are forced to FIC1 whether they were destined to FIC0 or FIC1 in original message.
#define XCM_REG_PHYS_QNUM3_0 0x20100UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 3 per port index (CID[23])
#define XCM_REG_PHYS_QNUM3_0_SIZE 1
#define XCM_REG_PHYS_QNUM3_1 0x20104UL //ACCESS:RW DataWidth:0x7 SPLIT:4 Description: The physical queue number 3 per port index (CID[23])
#define XCM_REG_PHYS_QNUM3_1_SIZE 1
#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108UL //ACCESS:RW DataWidth:0x1c SPLIT:4 Description: The delayed ACK timeout in ticks. Per port value.
#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0_SIZE 1
#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010cUL //ACCESS:RW DataWidth:0x1c SPLIT:4 Description: The delayed ACK timeout in ticks. Per port value.
#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1_SIZE 1
#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: The maximum delayed ACK counter value.Must be at least 2. Per port value.
#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0_SIZE 1
#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011cUL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: The maximum delayed ACK counter value.Must be at least 2. Per port value.
#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1_SIZE 1
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: DA timer command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00_SIZE 1
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: DA timer command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01_SIZE 1
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201ccUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: DA timer command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10_SIZE 1
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: DA timer command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11_SIZE 1
#define XCM_REG_WU_DA_CNT_CMD00 0x201d4UL //ACCESS:RW DataWidth:0x2 SPLIT:4 Description: DA counter command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_CNT_CMD00_SIZE 1
#define XCM_REG_WU_DA_CNT_CMD01 0x201d8UL //ACCESS:RW DataWidth:0x2 SPLIT:4 Description: DA counter command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_CNT_CMD01_SIZE 1
#define XCM_REG_WU_DA_CNT_CMD10 0x201dcUL //ACCESS:RW DataWidth:0x2 SPLIT:4 Description: DA counter command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_CNT_CMD10_SIZE 1
#define XCM_REG_WU_DA_CNT_CMD11 0x201e0UL //ACCESS:RW DataWidth:0x2 SPLIT:4 Description: DA counter command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_CNT_CMD11_SIZE 1
#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: DA counter update value used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_CNT_UPD_VAL00_SIZE 1
#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: DA counter update value; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_CNT_UPD_VAL01_SIZE 1
#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ecUL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: DA counter update value; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_CNT_UPD_VAL10_SIZE 1
#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0UL //ACCESS:RW DataWidth:0x8 SPLIT:4 Description: DA counter update value; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
#define XCM_REG_WU_DA_CNT_UPD_VAL11_SIZE 1
#define XCM_REG_CAM_OCCUP_ST 0x20400UL //ACCESS:RW DataWidth:0x5 Description: CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.
#define XCM_REG_CAM_OCCUP_ST_SIZE 1
#define XCM_REG_CFC_INIT_CRD 0x20404UL //ACCESS:RW DataWidth:0x4 Description: CFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 1 at start-up.
#define XCM_REG_CFC_INIT_CRD_SIZE 1
#define XCM_REG_CP_MSG 0x20408UL //ACCESS:W DataWidth:0x20 Description: Used to write the CP message. Write only.
#define XCM_REG_CP_MSG_SIZE 1
#define XCM_REG_FIC0_INIT_CRD 0x2040cUL //ACCESS:RW DataWidth:0x8 Description: FIC0 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up.
#define XCM_REG_FIC0_INIT_CRD_SIZE 1
#define XCM_REG_FIC1_INIT_CRD 0x20410UL //ACCESS:RW DataWidth:0x8 Description: FIC1 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up.
#define XCM_REG_FIC1_INIT_CRD_SIZE 1
#define XCM_REG_GLB_CNT_STICKY 0x20414UL //ACCESS:RW DataWidth:0x1a Description: QM global usage counter maximum sticky value.
#define XCM_REG_GLB_CNT_STICKY_SIZE 1
#define XCM_REG_LL_SZ_STICKY 0x20418UL //ACCESS:RW DataWidth:0x6 Description: XX LL maximum value ever reached sticky value for any connection. It has no write access. The write to the register is performed by the XX internal circuitry.
#define XCM_REG_LL_SZ_STICKY_SIZE 1
#define XCM_REG_TM_INIT_CRD 0x2041cUL //ACCESS:RW DataWidth:0x4 Description: Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 4 at start-up.
#define XCM_REG_TM_INIT_CRD_SIZE 1
#define XCM_REG_XQM_INIT_CRD 0x20420UL //ACCESS:RW DataWidth:0x6 Description: QM output initial credit. Max credit available - 32.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 32 at start-up.
#define XCM_REG_XQM_INIT_CRD_SIZE 1
#define XCM_REG_XX_INIT_CRD 0x20424UL //ACCESS:RW DataWidth:0x6 Description: Initial value for the credit counter; responsible for fulfilling of the Input Stage XX protection buffer by the XX protection pending messages. Max credit available - 3.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 2 at start-up.
#define XCM_REG_XX_INIT_CRD_SIZE 1
#define XCM_REG_XX_MSG_NUM 0x20428UL //ACCESS:RW DataWidth:0x6 Description: The maximum number of pending messages; which may be stored in XX protection. ~xcm_registers_xx_free.xx_free is also written on write.
#define XCM_REG_XX_MSG_NUM_SIZE 1
#define XCM_REG_LCID_CAM_0 0x2042cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_0_SIZE 1
#define XCM_REG_LCID_CAM_1 0x20430UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_1_SIZE 1
#define XCM_REG_LCID_CAM_2 0x20434UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_2_SIZE 1
#define XCM_REG_LCID_CAM_3 0x20438UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_3_SIZE 1
#define XCM_REG_LCID_CAM_4 0x2043cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_4_SIZE 1
#define XCM_REG_LCID_CAM_5 0x20440UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_5_SIZE 1
#define XCM_REG_LCID_CAM_6 0x20444UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_6_SIZE 1
#define XCM_REG_LCID_CAM_7 0x20448UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_7_SIZE 1
#define XCM_REG_LCID_CAM_8 0x2044cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_8_SIZE 1
#define XCM_REG_LCID_CAM_9 0x20450UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_9_SIZE 1
#define XCM_REG_LCID_CAM_10 0x20454UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_10_SIZE 1
#define XCM_REG_LCID_CAM_11 0x20458UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_11_SIZE 1
#define XCM_REG_LCID_CAM_12 0x2045cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_12_SIZE 1
#define XCM_REG_LCID_CAM_13 0x20460UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_13_SIZE 1
#define XCM_REG_LCID_CAM_14 0x20464UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_14_SIZE 1
#define XCM_REG_LCID_CAM_15 0x20468UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_15_SIZE 1
#define XCM_REG_LCID_CAM_16 0x2046cUL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_16_SIZE 1
#define XCM_REG_LCID_CAM_17 0x20470UL //ACCESS:R DataWidth:0x9 Description: Debug only. Read access to LCID CAM in XX protection mechanism.
#define XCM_REG_LCID_CAM_17_SIZE 1
#define XCM_REG_XX_DESCR_TABLE 0x20480UL //ACCESS:RW DataWidth:0x11 Description: Indirect access to the descriptor table of the XX protection mechanism. The fields are: [5:0] - message length;[11:6] - message pointer;[16:12] - next pointer.
#define XCM_REG_XX_DESCR_TABLE_SIZE 32
#define XCM_REG_XX_TABLE 0x20500UL //ACCESS:RW DataWidth:0x10 Description: Indirect access to the XX table of the XX protection mechanism. The fields are:[4:0] - tail pointer;[10:5] - Link List size;[15:11] - header pointer.
#define XCM_REG_XX_TABLE_SIZE 18
#define XCM_REG_XX_PEND_MSG 0x20600UL //ACCESS:RW DataWidth:0x20 Description: Indirect access to the Pending messages RAM of the XX protection mechanism.
#define XCM_REG_XX_PEND_MSG_SIZE 128
#define XCM_REG_AG_CTX 0x28000UL //ACCESS:RW DataWidth:0x20 Description: Indirect access to AG context with 32-bits granularity. The bits [12:8] of the address should be the offset within the accessed LCID context; the bits [7:0] are the accessed LCID.Example: to write to REG10 LCID100. The RBC address should be 13'ha64.
#define XCM_REG_AG_CTX_SIZE 8192
#define XCM_REG_STORM_CTX 0x30000UL //ACCESS:RW DataWidth:0x20 Description: Indirect access to STORM context with 32-bits granularity. The bits [13:8] of the address should be the offset within the accessed LCID context; the bits [7:0] are the accessed LCID.Example: to write to REG10 LCID100. The RBC address should be 14'ha64.
#define XCM_REG_STORM_CTX_SIZE 16384
#define XCM_REG_AG_CTX01_TM 0x20200UL //ACCESS:R DataWidth:0x4 Description: TM bits of AG context.
#define XCM_REG_AG_CTX01_TM_SIZE 1
#define XCM_REG_AG_CTX11_TM 0x20208UL //ACCESS:R DataWidth:0x4 Description: TM bits of AG context.
#define XCM_REG_AG_CTX11_TM_SIZE 1
#define XCM_REG_XCM_UNUSED_EMPTY_0 0x202f4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XCM_REG_XCM_UNUSED_EMPTY_0_SIZE 67
#define XCM_REG_XCM_UNUSED_EMPTY_1 0x20474UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XCM_REG_XCM_UNUSED_EMPTY_1_SIZE 3
#define XCM_REG_XCM_UNUSED_EMPTY_2 0x20580UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XCM_REG_XCM_UNUSED_EMPTY_2_SIZE 32
#define XCM_REG_XCM_UNUSED_EMPTY_3 0x20800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XCM_REG_XCM_UNUSED_EMPTY_3_SIZE 7680
#define XMAC_REG_CTRL 0UL //ACCESS:RW DataWidth:0xc Multi Field Register
#define XMAC_CTRL_REG_TX_EN (0x1<<0)
#define XMAC_CTRL_REG_TX_EN_SIZE 0
#define XMAC_CTRL_REG_RX_EN (0x1<<1)
#define XMAC_CTRL_REG_RX_EN_SIZE 1
#define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2)
#define XMAC_CTRL_REG_LINE_LOCAL_LPBK_SIZE 2
#define XMAC_CTRL_REG_CORE_LOCAL_LPBK (0x1<<3)
#define XMAC_CTRL_REG_CORE_LOCAL_LPBK_SIZE 3
#define XMAC_CTRL_REG_LINE_REMOTE_LPBK (0x1<<4)
#define XMAC_CTRL_REG_LINE_REMOTE_LPBK_SIZE 4
#define XMAC_CTRL_REG_CORE_REMOTE_LPBK (0x1<<5)
#define XMAC_CTRL_REG_CORE_REMOTE_LPBK_SIZE 5
#define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
#define XMAC_CTRL_REG_SOFT_RESET_SIZE 6
#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1<<7)
#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB_SIZE 7
#define XMAC_CTRL_REG_LOCAL_LPBK_LEAK_ENB (0x1<<8)
#define XMAC_CTRL_REG_LOCAL_LPBK_LEAK_ENB_SIZE 8
#define XMAC_CTRL_REG_REMOTE_LPBK_LEAK_ENB (0x1<<9)
#define XMAC_CTRL_REG_REMOTE_LPBK_LEAK_ENB_SIZE 9
#define XMAC_CTRL_REG_RS_SOFT_RESET (0x1<<10)
#define XMAC_CTRL_REG_RS_SOFT_RESET_SIZE 10
#define XMAC_CTRL_REG_XGMII_IPG_CHECK_DISABLE (0x1<<11)
#define XMAC_CTRL_REG_XGMII_IPG_CHECK_DISABLE_SIZE 11
#define XMAC_REG_MODE 0x8UL //ACCESS:RW DataWidth:0x7 Multi Field Register
#define XMAC_MODE_REG_HDR_MODE (0x7<<0)
#define XMAC_MODE_REG_HDR_MODE_SIZE 0
#define XMAC_MODE_REG_NO_SOP_FOR_CRC_HG (0x1<<3)
#define XMAC_MODE_REG_NO_SOP_FOR_CRC_HG_SIZE 3
#define XMAC_MODE_REG_SPEED_MODE (0x7<<4)
#define XMAC_MODE_REG_SPEED_MODE_SIZE 4
#define XMAC_REG_XMAC_SPARE0 0x10UL //ACCESS:RW DataWidth:0x20 Description: SPARE REGISTERS 0
#define XMAC_REG_XMAC_SPARE1 0x18UL //ACCESS:RW DataWidth:0x2 Description: SPARE REGISTERS 0
#define XMAC_REG_TX_CTRL 0x20UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define XMAC_TX_CTRL_REG_CRC_MODE (0x3<<0)
#define XMAC_TX_CTRL_REG_CRC_MODE_SIZE 0
#define XMAC_TX_CTRL_REG_DISCARD (0x1<<2)
#define XMAC_TX_CTRL_REG_DISCARD_SIZE 2
#define XMAC_TX_CTRL_REG_TX_ANY_START (0x1<<3)
#define XMAC_TX_CTRL_REG_TX_ANY_START_SIZE 3
#define XMAC_TX_CTRL_REG_PAD_EN (0x1<<4)
#define XMAC_TX_CTRL_REG_PAD_EN_SIZE 4
#define XMAC_TX_CTRL_REG_PAD_THRESHOLD (0x7f<<5)
#define XMAC_TX_CTRL_REG_PAD_THRESHOLD_SIZE 5
#define XMAC_TX_CTRL_REG_AVERAGE_IPG (0x7f<<12)
#define XMAC_TX_CTRL_REG_AVERAGE_IPG_SIZE 12
#define XMAC_TX_CTRL_REG_THROT_NUM (0x3f<<19)
#define XMAC_TX_CTRL_REG_THROT_NUM_SIZE 19
#define XMAC_TX_CTRL_REG_THROT_DENOM_LO (0x7f<<25)
#define XMAC_TX_CTRL_REG_THROT_DENOM_LO_SIZE 25
#define XMAC_REG_TX_CTRL_HI 0x24UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define XMAC_TX_CTRL_HI_REG_THROT_DENOM_HI (0x1<<0)
#define XMAC_TX_CTRL_HI_REG_THROT_DENOM_HI_SIZE 0
#define XMAC_TX_CTRL_HI_REG_TX_PREAMBLE_LENGTH (0xf<<1)
#define XMAC_TX_CTRL_HI_REG_TX_PREAMBLE_LENGTH_SIZE 1
#define XMAC_TX_CTRL_HI_REG_TX_64BYTE_BUFFER_EN (0x1<<5)
#define XMAC_TX_CTRL_HI_REG_TX_64BYTE_BUFFER_EN_SIZE 5
#define XMAC_REG_CTRL_SA_LO 0x28UL //ACCESS:RW DataWidth:0x20 Description: Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC packets transmitted by the MAC
#define XMAC_REG_CTRL_SA_HI 0x2cUL //ACCESS:RW DataWidth:0x10 Description: Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC packets transmitted by the MAC
#define XMAC_REG_RX_CTRL 0x30UL //ACCESS:RW DataWidth:0xd Multi Field Register
#define XMAC_RX_CTRL_REG_RX_PASS_CTRL (0x1<<0)
#define XMAC_RX_CTRL_REG_RX_PASS_CTRL_SIZE 0
#define XMAC_RX_CTRL_REG_RX_ANY_START (0x1<<1)
#define XMAC_RX_CTRL_REG_RX_ANY_START_SIZE 1
#define XMAC_RX_CTRL_REG_STRIP_CRC (0x1<<2)
#define XMAC_RX_CTRL_REG_STRIP_CRC_SIZE 2
#define XMAC_RX_CTRL_REG_STRICT_PREAMBLE (0x1<<3)
#define XMAC_RX_CTRL_REG_STRICT_PREAMBLE_SIZE 3
#define XMAC_RX_CTRL_REG_RUNT_THRESHOLD (0x7f<<4)
#define XMAC_RX_CTRL_REG_RUNT_THRESHOLD_SIZE 4
#define XMAC_RX_CTRL_REG_RECEIVE_18_BYTE_PKTS (0x1<<11)
#define XMAC_RX_CTRL_REG_RECEIVE_18_BYTE_PKTS_SIZE 11
#define XMAC_RX_CTRL_REG_PROCESS_VARIABLE_PREAMBLE (0x1<<12)
#define XMAC_RX_CTRL_REG_PROCESS_VARIABLE_PREAMBLE_SIZE 12
#define XMAC_REG_RX_SA_LO 0x38UL //ACCESS:RW DataWidth:0x20 Description: Lower 48 bits of rx_sa register. SA recognized for MAC control packets in addition to the standard 0x0180C2000001
#define XMAC_REG_RX_SA_HI 0x3cUL //ACCESS:RW DataWidth:0x10 Description: Upper 48 bits of rx_sa register. SA recognized for MAC control packets in addition to the standard 0x0180C2000001
#define XMAC_REG_RX_MAX_SIZE 0x40UL //ACCESS:RW DataWidth:0xe Description: Maximum packet size in receive direction; exclusive of preamble & CRC in strip mode
#define XMAC_REG_RX_VLAN_TAG 0x48UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define XMAC_RX_VLAN_TAG_REG_INNER_VLAN_TAG (0xffff<<0)
#define XMAC_RX_VLAN_TAG_REG_INNER_VLAN_TAG_SIZE 0
#define XMAC_RX_VLAN_TAG_REG_OUTER_VLAN_TAG (0xffff<<16)
#define XMAC_RX_VLAN_TAG_REG_OUTER_VLAN_TAG_SIZE 16
#define XMAC_REG_RX_VLAN_TAG_HI 0x4cUL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define XMAC_RX_VLAN_TAG_HI_REG_INNER_VLAN_TAG_ENABLE (0x1<<0)
#define XMAC_RX_VLAN_TAG_HI_REG_INNER_VLAN_TAG_ENABLE_SIZE 0
#define XMAC_RX_VLAN_TAG_HI_REG_OUTER_VLAN_TAG_ENABLE (0x1<<1)
#define XMAC_RX_VLAN_TAG_HI_REG_OUTER_VLAN_TAG_ENABLE_SIZE 1
#define XMAC_REG_RX_LSS_CTRL 0x50UL //ACCESS:RW DataWidth:0x3 Multi Field Register
#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1<<0)
#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE_SIZE 0
#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1<<1)
#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE_SIZE 1
#define XMAC_RX_LSS_CTRL_REG_USE_EXTERNAL_FAULTS_FOR_TX (0x1<<2)
#define XMAC_RX_LSS_CTRL_REG_USE_EXTERNAL_FAULTS_FOR_TX_SIZE 2
#define XMAC_REG_RX_LSS_STATUS 0x58UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define XMAC_RX_LSS_STATUS_REG_LOCAL_FAULT_STATUS (0x1<<0)
#define XMAC_RX_LSS_STATUS_REG_LOCAL_FAULT_STATUS_SIZE 0
#define XMAC_RX_LSS_STATUS_REG_REMOTE_FAULT_STATUS (0x1<<1)
#define XMAC_RX_LSS_STATUS_REG_REMOTE_FAULT_STATUS_SIZE 1
#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60UL //ACCESS:RW DataWidth:0x2 Multi Field Register
#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS_SIZE 0
#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS_SIZE 1
#define XMAC_REG_PAUSE_CTRL 0x68UL //ACCESS:RW DataWidth:0x15 Multi Field Register
#define XMAC_PAUSE_CTRL_REG_PAUSE_REFRESH_TIMER (0xffff<<0)
#define XMAC_PAUSE_CTRL_REG_PAUSE_REFRESH_TIMER_SIZE 0
#define XMAC_PAUSE_CTRL_REG_PAUSE_REFRESH_EN (0x1<<16)
#define XMAC_PAUSE_CTRL_REG_PAUSE_REFRESH_EN_SIZE 16
#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN_SIZE 17
#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN_SIZE 18
#define XMAC_PAUSE_CTRL_REG_RX_PASS_PAUSE (0x1<<19)
#define XMAC_PAUSE_CTRL_REG_RX_PASS_PAUSE_SIZE 19
#define XMAC_PAUSE_CTRL_REG_PAUSE_GMII_ON_TX_LINE_SIDE (0x1<<20)
#define XMAC_PAUSE_CTRL_REG_PAUSE_GMII_ON_TX_LINE_SIDE_SIZE 20
#define XMAC_REG_PFC_CTRL 0x70UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define XMAC_PFC_CTRL_REG_PFC_REFRESH_TIMER (0xffff<<0)
#define XMAC_PFC_CTRL_REG_PFC_REFRESH_TIMER_SIZE 0
#define XMAC_PFC_CTRL_REG_PFC_XOFF_TIMER (0xffff<<16)
#define XMAC_PFC_CTRL_REG_PFC_XOFF_TIMER_SIZE 16
#define XMAC_REG_PFC_CTRL_HI 0x74UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN_SIZE 0
#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1)
#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON_SIZE 1
#define XMAC_PFC_CTRL_HI_REG_RX_PASS_PFC (0x1<<2)
#define XMAC_PFC_CTRL_HI_REG_RX_PASS_PFC_SIZE 2
#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN_SIZE 3
#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN_SIZE 4
#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN_SIZE 5
#define XMAC_REG_PFC_ETH_TYPE 0x78UL //ACCESS:RW DataWidth:0x10 Description: The PFC packet generation and detection uses this Ethertype value
#define XMAC_REG_PFC_OPCODE 0x80UL //ACCESS:RW DataWidth:0x10 Description: The PFC packet generation and detection uses this Ethertype value
#define XMAC_REG_PFC_MACDA_LO 0x88UL //ACCESS:RW DataWidth:0x20 Description: Lower 48 bits of pfc_macda register. Used as the DA in PFC packets transmitted by the MAC
#define XMAC_REG_PFC_MACDA_HI 0x8cUL //ACCESS:RW DataWidth:0x10 Description: Upper 48 bits of pfc_macda register. Used as the DA in PFC packets transmitted by the MAC
#define XMAC_REG_LLFC_CTRL 0x90UL //ACCESS:RW DataWidth:0xe Multi Field Register
#define XMAC_LLFC_CTRL_REG_TX_LLFC_EN (0x1<<0)
#define XMAC_LLFC_CTRL_REG_TX_LLFC_EN_SIZE 0
#define XMAC_LLFC_CTRL_REG_RX_LLFC_EN (0x1<<1)
#define XMAC_LLFC_CTRL_REG_RX_LLFC_EN_SIZE 1
#define XMAC_LLFC_CTRL_REG_LLFC_IN_IPG_ONLY (0x1<<2)
#define XMAC_LLFC_CTRL_REG_LLFC_IN_IPG_ONLY_SIZE 2
#define XMAC_LLFC_CTRL_REG_LLFC_CUT_THROUGH_MODE (0x1<<3)
#define XMAC_LLFC_CTRL_REG_LLFC_CUT_THROUGH_MODE_SIZE 3
#define XMAC_LLFC_CTRL_REG_LLFC_CRC_IGNORE (0x1<<4)
#define XMAC_LLFC_CTRL_REG_LLFC_CRC_IGNORE_SIZE 4
#define XMAC_LLFC_CTRL_REG_NO_SOM_FOR_CRC_LLFC (0x1<<5)
#define XMAC_LLFC_CTRL_REG_NO_SOM_FOR_CRC_LLFC_SIZE 5
#define XMAC_LLFC_CTRL_REG_LLFC_IMG (0xff<<6)
#define XMAC_LLFC_CTRL_REG_LLFC_IMG_SIZE 6
#define XMAC_REG_TX_LLFC_MSG_FIELDS 0x98UL //ACCESS:RW DataWidth:0x1c Multi Field Register
#define XMAC_TX_LLFC_MSG_FIELDS_REG_TX_LLFC_MSG_TYPE_LOGICAL (0xff<<0)
#define XMAC_TX_LLFC_MSG_FIELDS_REG_TX_LLFC_MSG_TYPE_LOGICAL_SIZE 0
#define XMAC_TX_LLFC_MSG_FIELDS_REG_TX_LLFC_FC_OBJ_LOGICAL (0xf<<8)
#define XMAC_TX_LLFC_MSG_FIELDS_REG_TX_LLFC_FC_OBJ_LOGICAL_SIZE 8
#define XMAC_TX_LLFC_MSG_FIELDS_REG_LLFC_XOFF_TIME (0xffff<<12)
#define XMAC_TX_LLFC_MSG_FIELDS_REG_LLFC_XOFF_TIME_SIZE 12
#define XMAC_REG_RX_LLFC_MSG_FIELDS 0xa0UL //ACCESS:RW DataWidth:0x18 Multi Field Register
#define XMAC_RX_LLFC_MSG_FIELDS_REG_RX_LLFC_MSG_TYPE_LOGICAL (0xff<<0)
#define XMAC_RX_LLFC_MSG_FIELDS_REG_RX_LLFC_MSG_TYPE_LOGICAL_SIZE 0
#define XMAC_RX_LLFC_MSG_FIELDS_REG_RX_LLFC_FC_OBJ_LOGICAL (0xf<<8)
#define XMAC_RX_LLFC_MSG_FIELDS_REG_RX_LLFC_FC_OBJ_LOGICAL_SIZE 8
#define XMAC_RX_LLFC_MSG_FIELDS_REG_RX_LLFC_MSG_TYPE_PHYSICAL (0xff<<12)
#define XMAC_RX_LLFC_MSG_FIELDS_REG_RX_LLFC_MSG_TYPE_PHYSICAL_SIZE 12
#define XMAC_RX_LLFC_MSG_FIELDS_REG_RX_LLFC_FC_OBJ_PHYSICAL (0xf<<20)
#define XMAC_RX_LLFC_MSG_FIELDS_REG_RX_LLFC_FC_OBJ_PHYSICAL_SIZE 20
#define XMAC_REG_HCFC_CTRL 0xa8UL //ACCESS:RW DataWidth:0x15 Multi Field Register
#define XMAC_HCFC_CTRL_REG_TX_HCFC_EN (0x1<<0)
#define XMAC_HCFC_CTRL_REG_TX_HCFC_EN_SIZE 0
#define XMAC_HCFC_CTRL_REG_RX_HCFC_EN (0x1<<1)
#define XMAC_HCFC_CTRL_REG_RX_HCFC_EN_SIZE 1
#define XMAC_HCFC_CTRL_REG_HCFC_CRC_IGNORE (0x1<<2)
#define XMAC_HCFC_CTRL_REG_HCFC_CRC_IGNORE_SIZE 2
#define XMAC_HCFC_CTRL_REG_NO_SOM_FOR_CRC_HCFC (0x1<<3)
#define XMAC_HCFC_CTRL_REG_NO_SOM_FOR_CRC_HCFC_SIZE 3
#define XMAC_HCFC_CTRL_REG_HCFC_IN_IPG_ONLY (0x1<<4)
#define XMAC_HCFC_CTRL_REG_HCFC_IN_IPG_ONLY_SIZE 4
#define XMAC_HCFC_CTRL_REG_HCFC_SOM (0xff<<5)
#define XMAC_HCFC_CTRL_REG_HCFC_SOM_SIZE 5
#define XMAC_HCFC_CTRL_REG_HCFC_IMG (0xff<<13)
#define XMAC_HCFC_CTRL_REG_HCFC_IMG_SIZE 13
#define XMAC_REG_TIME_STAMP 0xb0UL //ACCESS:RW DataWidth:0x20 Description: The TimeStamp value of the Tx packets.
#define XMAC_REG_TX_TIMESTAMP_FIFO_DATA_HI 0xb4UL //ACCESS:RW DataWidth:0x11 Multi Field Register
#define XMAC_TX_TIMESTAMP_FIFO_DATA_HI_REG_SEQUENCE_ID (0xffff<<0)
#define XMAC_TX_TIMESTAMP_FIFO_DATA_HI_REG_SEQUENCE_ID_SIZE 0
#define XMAC_TX_TIMESTAMP_FIFO_DATA_HI_REG_TS_ENTRY_VALID (0x1<<16)
#define XMAC_TX_TIMESTAMP_FIFO_DATA_HI_REG_TS_ENTRY_VALID_SIZE 16
#define XMAC_REG_FIFO_STATUS 0xc0UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define XMAC_FIFO_STATUS_REG_RX_PKT_OVERFLOW (0x1<<0)
#define XMAC_FIFO_STATUS_REG_RX_PKT_OVERFLOW_SIZE 0
#define XMAC_FIFO_STATUS_REG_RX_MSG_OVERFLOW (0x1<<1)
#define XMAC_FIFO_STATUS_REG_RX_MSG_OVERFLOW_SIZE 1
#define XMAC_FIFO_STATUS_REG_TX_PKT_UNDERFLOW (0x1<<2)
#define XMAC_FIFO_STATUS_REG_TX_PKT_UNDERFLOW_SIZE 2
#define XMAC_FIFO_STATUS_REG_TX_PKT_OVERFLOW (0x1<<3)
#define XMAC_FIFO_STATUS_REG_TX_PKT_OVERFLOW_SIZE 3
#define XMAC_FIFO_STATUS_REG_TX_HCFC_MSG_OVERFLOW (0x1<<4)
#define XMAC_FIFO_STATUS_REG_TX_HCFC_MSG_OVERFLOW_SIZE 4
#define XMAC_FIFO_STATUS_REG_TX_LLFC_MSG_OVERFLOW (0x1<<5)
#define XMAC_FIFO_STATUS_REG_TX_LLFC_MSG_OVERFLOW_SIZE 5
#define XMAC_REG_CLEAR_FIFO_STATUS 0xc8UL //ACCESS:RW DataWidth:0x7 Multi Field Register
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_RX_PKT_OVERFLOW (0x1<<0)
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_RX_PKT_OVERFLOW_SIZE 0
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_RX_MSG_OVERFLOW (0x1<<1)
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_RX_MSG_OVERFLOW_SIZE 1
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_PKT_UNDERFLOW (0x1<<2)
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_PKT_UNDERFLOW_SIZE 2
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_PKT_OVERFLOW (0x1<<3)
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_PKT_OVERFLOW_SIZE 3
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_HCFC_MSG_OVERFLOW (0x1<<4)
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_HCFC_MSG_OVERFLOW_SIZE 4
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_LLFC_MSG_OVERFLOW (0x1<<5)
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_LLFC_MSG_OVERFLOW_SIZE 5
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_TS_FIFO_OVERFLOW (0x1<<6)
#define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_TS_FIFO_OVERFLOW_SIZE 6
#define XMAC_REG_TX_FIFO_CREDITS 0xd0UL //ACCESS:RW DataWidth:0x12 Multi Field Register
#define XMAC_TX_FIFO_CREDITS_REG_QUAD_PORT_TX_CREDITS (0x3f<<0)
#define XMAC_TX_FIFO_CREDITS_REG_QUAD_PORT_TX_CREDITS_SIZE 0
#define XMAC_TX_FIFO_CREDITS_REG_DUAL_PORT_TX_CREDITS (0x3f<<6)
#define XMAC_TX_FIFO_CREDITS_REG_DUAL_PORT_TX_CREDITS_SIZE 6
#define XMAC_TX_FIFO_CREDITS_REG_SINGLE_PORT_TX_CREDITS (0x3f<<12)
#define XMAC_TX_FIFO_CREDITS_REG_SINGLE_PORT_TX_CREDITS_SIZE 12
#define XMAC_REG_EEE_CTRL 0xd8UL //ACCESS:RW DataWidth:0x4 Multi Field Register
#define XMAC_EEE_CTRL_REG_EEE_EN (0x1<<0)
#define XMAC_EEE_CTRL_REG_EEE_EN_SIZE 0
#define XMAC_EEE_CTRL_REG_EEE_DISABLE_TX_PAUSE_XOFF (0x1<<1)
#define XMAC_EEE_CTRL_REG_EEE_DISABLE_TX_PAUSE_XOFF_SIZE 1
#define XMAC_EEE_CTRL_REG_EEE_DISABLE_TX_PFC_XOFF (0x1<<2)
#define XMAC_EEE_CTRL_REG_EEE_DISABLE_TX_PFC_XOFF_SIZE 2
#define XMAC_EEE_CTRL_REG_EEE_DISABLE_RX_PAUSE_ACTIVE (0x1<<3)
#define XMAC_EEE_CTRL_REG_EEE_DISABLE_RX_PAUSE_ACTIVE_SIZE 3
#define XMAC_REG_EEE_DELAY_ENTRY_TIMER 0xe0UL //ACCESS:RW DataWidth:0x20 Description: This is the duration for which condition to move to LPI state must be satisfied; at the end of which MAC transitions to LPI State. This is in terms of micro seconds
#define XMAC_REG_EEE_TIMERS_HI 0xe4UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define XMAC_EEE_TIMERS_HI_REG_EEE_WAKE_TIMER (0xffff<<0)
#define XMAC_EEE_TIMERS_HI_REG_EEE_WAKE_TIMER_SIZE 0
#define XMAC_EEE_TIMERS_HI_REG_EEE_REF_COUNT (0xffff<<16)
#define XMAC_EEE_TIMERS_HI_REG_EEE_REF_COUNT_SIZE 16
#define XMAC_REG_GMII_EEE_CTRL 0x110UL //ACCESS:RW DataWidth:0x12 Multi Field Register
#define XMAC_GMII_EEE_CTRL_REG_GMII_LPI_PREDICT_THRESHOLD (0xffff<<0)
#define XMAC_GMII_EEE_CTRL_REG_GMII_LPI_PREDICT_THRESHOLD_SIZE 0
#define XMAC_GMII_EEE_CTRL_REG_GMII_LPI_PREDICT_MODE_EN (0x1<<16)
#define XMAC_GMII_EEE_CTRL_REG_GMII_LPI_PREDICT_MODE_EN_SIZE 16
#define XMAC_GMII_EEE_CTRL_REG_GMII_TXCLK_DIS (0x1<<17)
#define XMAC_GMII_EEE_CTRL_REG_GMII_TXCLK_DIS_SIZE 17
#define XMAC_REG_MACSEC_CTRL 0x120UL //ACCESS:RW DataWidth:0x20 Multi Field Register
#define XMAC_MACSEC_CTRL_REG_MACSEC_TX_LAUNCH_EN (0x1<<0)
#define XMAC_MACSEC_CTRL_REG_MACSEC_TX_LAUNCH_EN_SIZE 0
#define XMAC_MACSEC_CTRL_REG_MACSEC_TX_CRC_CORRUPT_EN (0x1<<1)
#define XMAC_MACSEC_CTRL_REG_MACSEC_TX_CRC_CORRUPT_EN_SIZE 1
#define XMAC_MACSEC_CTRL_REG_MACSEC_TX_CRC_CORRUPTION_MODE (0x1<<2)
#define XMAC_MACSEC_CTRL_REG_MACSEC_TX_CRC_CORRUPTION_MODE_SIZE 2
#define XMAC_MACSEC_CTRL_REG_MACSEC_PROG_TX_CRC_LO (0x1fffffff<<3)
#define XMAC_MACSEC_CTRL_REG_MACSEC_PROG_TX_CRC_LO_SIZE 3
#define XMAC_REG_MACSEC_PROG_TX_CRC_HI 0x124UL //ACCESS:RW DataWidth:0x3 Description: Upper 32 bits of macsec_prog_tx_crc register. Programmable CRC value to corrupt the Tx CRC to be used in MACSEC. The computed CRC is replaced by this programmed CRC value
#define XMAC_REG_WB_TX_CTRL 0x420UL //ACCESS:WB DataWidth:0x26 Description: This is a WB access for version of the register at XMAC_TX_CTRL. The register can be access in either this loation or at XMAC_TX_CTRL; but normal WB access methods mus be used at this location. The fields within this WB register are:
1:0=XMAC_CRC_MODE; 2:2=XMAC_DISCARD; 3:3=XMAC_TX_ANY_START; 4:4=XMAC_PAD_EN; 11:5=XMAC_PAD_THRESHOLD; 18:12=XMAC_AVERAGE_IPG; 24:19=XMAC_THROT_NUM; 31:25=XMAC_THROT_DENOM_LO; 32:32=XMAC_THROT_DENOM_HI; 36:33=XMAC_TX_PREAMBLE_LENGTH; 37:37=XMAC_TX_64BYTE_BUFFER_EN; 63:38=XMAC_RESERVED.
#define XMAC_REG_WB_TX_CTRL_SIZE 2
#define XMAC_REG_WB_TX_MAC_SA 0x428UL //ACCESS:WB DataWidth:0x30 Description: This is a WB access for version of the register at XMAC_TX_MAC_SA. The register can be access in either this loation or at XMAC_TX_MAC_SA; but normal WB access methods mus be used at this location. The fields within this WB register are:
31:0=XMAC_CTRL_SA_LO; 47:32=XMAC_CTRL_SA_HI; 63:48=XMAC_RESERVED.
#define XMAC_REG_WB_TX_MAC_SA_SIZE 2
#define XMAC_REG_WB_RX_MAC_SA 0x438UL //ACCESS:WB DataWidth:0x30 Description: This is a WB access for version of the register at XMAC_RX_MAC_SA. The register can be access in either this loation or at XMAC_RX_MAC_SA; but normal WB access methods mus be used at this location. The fields within this WB register are:
31:0=XMAC_RX_SA_LO; 47:32=XMAC_RX_SA_HI; 63:48=XMAC_RESERVED.
#define XMAC_REG_WB_RX_MAC_SA_SIZE 2
#define XMAC_REG_WB_PFC_DA 0x488UL //ACCESS:WB DataWidth:0x30 Description: This is a WB access for version of the register at XMAC_PFC_DA. The register can be access in either this loation or at XMAC_PFC_DA; but normal WB access methods mus be used at this location. The fields within this WB register are:
31:0=XMAC_PFC_MACDA_LO; 47:32=XMAC_PFC_MACDA_HI; 63:48=XMAC_RESERVED.
#define XMAC_REG_WB_PFC_DA_SIZE 2
#define XMAC_REG_WB_MACSEC_CTRL 0x520UL //ACCESS:WB DataWidth:0x23 Description: This is a WB access for version of the register at XMAC_MACSEC_CTRL. The register can be access in either this loation or at XMAC_MACSEC_CTRL; but normal WB access methods mus be used at this location. The fields within this WB register are:
0:0=XMAC_MACSEC_TX_LAUNCH_EN; 1:1=XMAC_MACSEC_TX_CRC_CORRUPT_EN; 2:2=XMAC_MACSEC_TX_CRC_CORRUPTION_MODE; 31:3=XMAC_MACSEC_PROG_TX_CRC_LO; 34:32=XMAC_MACSEC_PROG_TX_CRC_HI; 63:35=XMAC_RESERVED.
#define XMAC_REG_WB_MACSEC_CTRL_SIZE 2
#define XMAC_REG_XMAC_UNUSED_EMPTY_0 0x4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_0_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_1 0xcUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_1_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_2 0x14UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_2_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_3 0x1cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_3_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_4 0x34UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_4_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_5 0x44UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_5_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_6 0x54UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_6_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_7 0x5cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_7_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_8 0x64UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_8_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_9 0x6cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_9_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_10 0x7cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_10_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_11 0x84UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_11_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_12 0x94UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_12_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_13 0x9cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_13_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_14 0xa4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_14_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_15 0xacUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_15_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_16 0xb8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_16_SIZE 2
#define XMAC_REG_XMAC_UNUSED_EMPTY_17 0xc4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_17_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_18 0xccUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_18_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_19 0xd4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_19_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_20 0xdcUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_20_SIZE 1
#define XMAC_REG_XMAC_UNUSED_EMPTY_21 0xe8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_21_SIZE 10
#define XMAC_REG_XMAC_UNUSED_EMPTY_22 0x114UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_22_SIZE 3
#define XMAC_REG_XMAC_UNUSED_EMPTY_23 0x128UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_23_SIZE 190
#define XMAC_REG_XMAC_UNUSED_EMPTY_24 0x430UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_24_SIZE 2
#define XMAC_REG_XMAC_UNUSED_EMPTY_25 0x440UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_25_SIZE 18
#define XMAC_REG_XMAC_UNUSED_EMPTY_26 0x490UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_26_SIZE 36
#define XMAC_REG_XMAC_UNUSED_EMPTY_27 0x528UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XMAC_REG_XMAC_UNUSED_EMPTY_27_SIZE 694
#define XSDM_REG_TIMER_TICK 0x166000UL //ACCESS:RW DataWidth:0x20 Description: Tick for timer counter. Applicable only when ~xsdm_registers_timer_tick_enable.timer_tick_enable =1
#define XSDM_REG_TIMERS_TICK_ENABLE 0x166004UL //ACCESS:RW DataWidth:0x1 Description: Enable for tick counter.
#define XSDM_REG_CFC_RSP_START_ADDR 0x166008UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the cfc_rsp lcid
#define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600cUL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the completion counters.
#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for queue counters
#define XSDM_REG_PCK_END_MSG_START_ADDR 0x166014UL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for the packet end message
#define XSDM_REG_COUNTERS_WRAP 0x166018UL //ACCESS:RW DataWidth:0x1 Description: Indicates if the 204 statistics counters should stop counting when reaching an all-ones value or should wrap-around 0=stop counting 1=wrap-around.
#define XSDM_REG_CMP_COUNTER_MAX0 0x16601cUL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #0
#define XSDM_REG_CMP_COUNTER_MAX1 0x166020UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #1
#define XSDM_REG_CMP_COUNTER_MAX2 0x166024UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #2
#define XSDM_REG_CMP_COUNTER_MAX3 0x166028UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #3
#define XSDM_REG_BRB1_ALMOST_FULL 0x16602cUL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from BRB1 in DMA_RSP block
#define XSDM_REG_PXP_ALMOST_FULL 0x166030UL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from pxp in DMA_RSP block
#define XSDM_REG_PB_ALMOST_FULL 0x166034UL //ACCESS:RW DataWidth:0x4 Description: Almost full signal for read data from PB in DMA_RSP block
#define XSDM_REG_AGG_INT_EVENT_0 0x166038UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 0
#define XSDM_REG_AGG_INT_EVENT_1 0x16603cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 1
#define XSDM_REG_AGG_INT_EVENT_2 0x166040UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 2
#define XSDM_REG_AGG_INT_EVENT_3 0x166044UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 3
#define XSDM_REG_AGG_INT_EVENT_4 0x166048UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 4
#define XSDM_REG_AGG_INT_EVENT_5 0x16604cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 5
#define XSDM_REG_AGG_INT_EVENT_6 0x166050UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 6
#define XSDM_REG_AGG_INT_EVENT_7 0x166054UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 7
#define XSDM_REG_AGG_INT_EVENT_8 0x166058UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 8
#define XSDM_REG_AGG_INT_EVENT_9 0x16605cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 9
#define XSDM_REG_AGG_INT_EVENT_10 0x166060UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 10
#define XSDM_REG_AGG_INT_EVENT_11 0x166064UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 11
#define XSDM_REG_AGG_INT_EVENT_12 0x166068UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 12
#define XSDM_REG_AGG_INT_EVENT_13 0x16606cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 13
#define XSDM_REG_AGG_INT_EVENT_14 0x166070UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 14
#define XSDM_REG_AGG_INT_EVENT_15 0x166074UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 15
#define XSDM_REG_AGG_INT_EVENT_16 0x166078UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 16
#define XSDM_REG_AGG_INT_EVENT_17 0x16607cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 17
#define XSDM_REG_AGG_INT_EVENT_18 0x166080UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 18
#define XSDM_REG_AGG_INT_EVENT_19 0x166084UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 19
#define XSDM_REG_AGG_INT_EVENT_20 0x166088UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 20
#define XSDM_REG_AGG_INT_EVENT_21 0x16608cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 21
#define XSDM_REG_AGG_INT_EVENT_22 0x166090UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 22
#define XSDM_REG_AGG_INT_EVENT_23 0x166094UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 23
#define XSDM_REG_AGG_INT_EVENT_24 0x166098UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 24
#define XSDM_REG_AGG_INT_EVENT_25 0x16609cUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 25
#define XSDM_REG_AGG_INT_EVENT_26 0x1660a0UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 26
#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 27
#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 28
#define XSDM_REG_AGG_INT_EVENT_29 0x1660acUL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 29
#define XSDM_REG_AGG_INT_EVENT_30 0x1660b0UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 30
#define XSDM_REG_AGG_INT_EVENT_31 0x1660b4UL //ACCESS:RW DataWidth:0x8 Description: The event id for aggregated interrupt 31
#define XSDM_REG_AGG_INT_T_0 0x1660b8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 0
#define XSDM_REG_AGG_INT_T_1 0x1660bcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 1
#define XSDM_REG_AGG_INT_T_2 0x1660c0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 2
#define XSDM_REG_AGG_INT_T_3 0x1660c4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 3
#define XSDM_REG_AGG_INT_T_4 0x1660c8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 4
#define XSDM_REG_AGG_INT_T_5 0x1660ccUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 5
#define XSDM_REG_AGG_INT_T_6 0x1660d0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 6
#define XSDM_REG_AGG_INT_T_7 0x1660d4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 7
#define XSDM_REG_AGG_INT_T_8 0x1660d8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 8
#define XSDM_REG_AGG_INT_T_9 0x1660dcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 9
#define XSDM_REG_AGG_INT_T_10 0x1660e0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 10
#define XSDM_REG_AGG_INT_T_11 0x1660e4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 11
#define XSDM_REG_AGG_INT_T_12 0x1660e8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 12
#define XSDM_REG_AGG_INT_T_13 0x1660ecUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 13
#define XSDM_REG_AGG_INT_T_14 0x1660f0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 14
#define XSDM_REG_AGG_INT_T_15 0x1660f4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 15
#define XSDM_REG_AGG_INT_T_16 0x1660f8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 16
#define XSDM_REG_AGG_INT_T_17 0x1660fcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 17
#define XSDM_REG_AGG_INT_T_18 0x166100UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 18
#define XSDM_REG_AGG_INT_T_19 0x166104UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 19
#define XSDM_REG_AGG_INT_T_20 0x166108UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 20
#define XSDM_REG_AGG_INT_T_21 0x16610cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 21
#define XSDM_REG_AGG_INT_T_22 0x166110UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 22
#define XSDM_REG_AGG_INT_T_23 0x166114UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 23
#define XSDM_REG_AGG_INT_T_24 0x166118UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 24
#define XSDM_REG_AGG_INT_T_25 0x16611cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 25
#define XSDM_REG_AGG_INT_T_26 0x166120UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 26
#define XSDM_REG_AGG_INT_T_27 0x166124UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 27
#define XSDM_REG_AGG_INT_T_28 0x166128UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 28
#define XSDM_REG_AGG_INT_T_29 0x16612cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 29
#define XSDM_REG_AGG_INT_T_30 0x166130UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 30
#define XSDM_REG_AGG_INT_T_31 0x166134UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 31
#define XSDM_REG_AGG_INT_FIC_0 0x166138UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 0
#define XSDM_REG_AGG_INT_FIC_1 0x16613cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 1
#define XSDM_REG_AGG_INT_FIC_2 0x166140UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 2
#define XSDM_REG_AGG_INT_FIC_3 0x166144UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 3
#define XSDM_REG_AGG_INT_FIC_4 0x166148UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 4
#define XSDM_REG_AGG_INT_FIC_5 0x16614cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 5
#define XSDM_REG_AGG_INT_FIC_6 0x166150UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 6
#define XSDM_REG_AGG_INT_FIC_7 0x166154UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 7
#define XSDM_REG_AGG_INT_FIC_8 0x166158UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 8
#define XSDM_REG_AGG_INT_FIC_9 0x16615cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 9
#define XSDM_REG_AGG_INT_FIC_10 0x166160UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 10
#define XSDM_REG_AGG_INT_FIC_11 0x166164UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 11
#define XSDM_REG_AGG_INT_FIC_12 0x166168UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 12
#define XSDM_REG_AGG_INT_FIC_13 0x16616cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 13
#define XSDM_REG_AGG_INT_FIC_14 0x166170UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 14
#define XSDM_REG_AGG_INT_FIC_15 0x166174UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 15
#define XSDM_REG_AGG_INT_FIC_16 0x166178UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 16
#define XSDM_REG_AGG_INT_FIC_17 0x16617cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 17
#define XSDM_REG_AGG_INT_FIC_18 0x166180UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 18
#define XSDM_REG_AGG_INT_FIC_19 0x166184UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 19
#define XSDM_REG_AGG_INT_FIC_20 0x166188UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 20
#define XSDM_REG_AGG_INT_FIC_21 0x16618cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 21
#define XSDM_REG_AGG_INT_FIC_22 0x166190UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 22
#define XSDM_REG_AGG_INT_FIC_23 0x166194UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 23
#define XSDM_REG_AGG_INT_FIC_24 0x166198UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 24
#define XSDM_REG_AGG_INT_FIC_25 0x16619cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 25
#define XSDM_REG_AGG_INT_FIC_26 0x1661a0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 26
#define XSDM_REG_AGG_INT_FIC_27 0x1661a4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 27
#define XSDM_REG_AGG_INT_FIC_28 0x1661a8UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 28
#define XSDM_REG_AGG_INT_FIC_29 0x1661acUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 29
#define XSDM_REG_AGG_INT_FIC_30 0x1661b0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 30
#define XSDM_REG_AGG_INT_FIC_31 0x1661b4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 31
#define XSDM_REG_AGG_INT_MODE_0 0x1661b8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_1 0x1661bcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_2 0x1661c0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_3 0x1661c4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_4 0x1661c8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_5 0x1661ccUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_6 0x1661d0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_7 0x1661d4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_8 0x1661d8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_9 0x1661dcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_10 0x1661e0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_11 0x1661e4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_12 0x1661e8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_13 0x1661ecUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_14 0x1661f0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_15 0x1661f4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_16 0x1661f8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (16) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_17 0x1661fcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (17)
#define XSDM_REG_AGG_INT_MODE_18 0x166200UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_19 0x166204UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_20 0x166208UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_21 0x16620cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_22 0x166210UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_23 0x166214UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_24 0x166218UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_25 0x16621cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_26 0x166220UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_27 0x166224UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_28 0x166228UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_29 0x16622cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_30 0x166230UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_AGG_INT_MODE_31 0x166234UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
#define XSDM_REG_ENABLE_IN1 0x166238UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define XSDM_ENABLE_IN1_REG_EXT_STORE_IN_EN (0x1<<0)
#define XSDM_ENABLE_IN1_REG_EXT_STORE_IN_EN_SIZE 0
#define XSDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN (0x1<<1)
#define XSDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN_SIZE 1
#define XSDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN (0x1<<2)
#define XSDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN_SIZE 2
#define XSDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN (0x1<<3)
#define XSDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN_SIZE 3
#define XSDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN (0x1<<4)
#define XSDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN_SIZE 4
#define XSDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN (0x1<<5)
#define XSDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN_SIZE 5
#define XSDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN (0x1<<6)
#define XSDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN_SIZE 6
#define XSDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN (0x1<<7)
#define XSDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN_SIZE 7
#define XSDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN (0x1<<8)
#define XSDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN_SIZE 8
#define XSDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN (0x1<<9)
#define XSDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN_SIZE 9
#define XSDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN (0x1<<10)
#define XSDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN_SIZE 10
#define XSDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN (0x1<<11)
#define XSDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN_SIZE 11
#define XSDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN (0x1<<12)
#define XSDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN_SIZE 12
#define XSDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN (0x1<<13)
#define XSDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN_SIZE 13
#define XSDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN (0x1<<14)
#define XSDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN_SIZE 14
#define XSDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN (0x1<<15)
#define XSDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN_SIZE 15
#define XSDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN (0x1<<16)
#define XSDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN_SIZE 16
#define XSDM_ENABLE_IN1_REG_PB_DATA_IN_EN (0x1<<17)
#define XSDM_ENABLE_IN1_REG_PB_DATA_IN_EN_SIZE 17
#define XSDM_ENABLE_IN1_REG_PRS_MSG_IN_EN (0x1<<18)
#define XSDM_ENABLE_IN1_REG_PRS_MSG_IN_EN_SIZE 18
#define XSDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN (0x1<<19)
#define XSDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN_SIZE 19
#define XSDM_ENABLE_IN1_REG_PXP_REQ_IN_EN (0x1<<20)
#define XSDM_ENABLE_IN1_REG_PXP_REQ_IN_EN_SIZE 20
#define XSDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN (0x1<<21)
#define XSDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN_SIZE 21
#define XSDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN (0x1<<22)
#define XSDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN_SIZE 22
#define XSDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN (0x1<<23)
#define XSDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN_SIZE 23
#define XSDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN (0x1<<24)
#define XSDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN_SIZE 24
#define XSDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN (0x1<<25)
#define XSDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN_SIZE 25
#define XSDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN (0x1<<26)
#define XSDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN_SIZE 26
#define XSDM_REG_ENABLE_IN2 0x16623cUL //ACCESS:RW DataWidth:0x7 Multi Field Register
#define XSDM_ENABLE_IN2_REG_SDM_ACK_IN_EN (0x1<<0)
#define XSDM_ENABLE_IN2_REG_SDM_ACK_IN_EN_SIZE 0
#define XSDM_ENABLE_IN2_REG_CM_ACK_IN_EN (0x1<<1)
#define XSDM_ENABLE_IN2_REG_CM_ACK_IN_EN_SIZE 1
#define XSDM_ENABLE_IN2_REG_PB_STATUS_IN_EN (0x1<<2)
#define XSDM_ENABLE_IN2_REG_PB_STATUS_IN_EN_SIZE 2
#define XSDM_ENABLE_IN2_REG_PB_FULL_IN_EN (0x1<<3)
#define XSDM_ENABLE_IN2_REG_PB_FULL_IN_EN_SIZE 3
#define XSDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN (0x1<<4)
#define XSDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN_SIZE 4
#define XSDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN (0x1<<5)
#define XSDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN_SIZE 5
#define XSDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN (0x1<<6)
#define XSDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN_SIZE 6
#define XSDM_REG_ENABLE_OUT1 0x166240UL //ACCESS:RW DataWidth:0x1b Multi Field Register
#define XSDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN (0x1<<0)
#define XSDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN_SIZE 0
#define XSDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN (0x1<<1)
#define XSDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN_SIZE 1
#define XSDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN (0x1<<2)
#define XSDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN_SIZE 2
#define XSDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN (0x1<<3)
#define XSDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN_SIZE 3
#define XSDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN (0x1<<4)
#define XSDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN_SIZE 4
#define XSDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN (0x1<<5)
#define XSDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN_SIZE 5
#define XSDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN (0x1<<6)
#define XSDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN_SIZE 6
#define XSDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN (0x1<<7)
#define XSDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN_SIZE 7
#define XSDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN (0x1<<8)
#define XSDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN_SIZE 8
#define XSDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN (0x1<<9)
#define XSDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN_SIZE 9
#define XSDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN (0x1<<10)
#define XSDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN_SIZE 10
#define XSDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN (0x1<<11)
#define XSDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN_SIZE 11
#define XSDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN (0x1<<12)
#define XSDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN_SIZE 12
#define XSDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN (0x1<<13)
#define XSDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN_SIZE 13
#define XSDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN (0x1<<14)
#define XSDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN_SIZE 14
#define XSDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN (0x1<<15)
#define XSDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN_SIZE 15
#define XSDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN (0x1<<16)
#define XSDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN_SIZE 16
#define XSDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN (0x1<<17)
#define XSDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN_SIZE 17
#define XSDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN (0x1<<18)
#define XSDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN_SIZE 18
#define XSDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN (0x1<<19)
#define XSDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN_SIZE 19
#define XSDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN (0x1<<20)
#define XSDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN_SIZE 20
#define XSDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN (0x1<<21)
#define XSDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN_SIZE 21
#define XSDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN (0x1<<22)
#define XSDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN_SIZE 22
#define XSDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN (0x1<<23)
#define XSDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN_SIZE 23
#define XSDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN (0x1<<24)
#define XSDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN_SIZE 24
#define XSDM_ENABLE_OUT1_REG_PB_OUT_EN (0x1<<25)
#define XSDM_ENABLE_OUT1_REG_PB_OUT_EN_SIZE 25
#define XSDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN (0x1<<26)
#define XSDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN_SIZE 26
#define XSDM_REG_ENABLE_OUT2 0x166244UL //ACCESS:RW DataWidth:0x6 Multi Field Register
#define XSDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN (0x1<<0)
#define XSDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN_SIZE 0
#define XSDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN (0x1<<1)
#define XSDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN_SIZE 1
#define XSDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN (0x1<<2)
#define XSDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN_SIZE 2
#define XSDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN (0x1<<3)
#define XSDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN_SIZE 3
#define XSDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN (0x1<<4)
#define XSDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN_SIZE 4
#define XSDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN (0x1<<5)
#define XSDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN_SIZE 5
#define XSDM_REG_NUM_OF_Q0_CMD 0x166248UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 0
#define XSDM_REG_NUM_OF_Q1_CMD 0x16624cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 1
#define XSDM_REG_NUM_OF_Q3_CMD 0x166250UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 3
#define XSDM_REG_NUM_OF_Q4_CMD 0x166254UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 4
#define XSDM_REG_NUM_OF_Q5_CMD 0x166258UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 5
#define XSDM_REG_NUM_OF_Q6_CMD 0x16625cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 6
#define XSDM_REG_NUM_OF_Q7_CMD 0x166260UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 7
#define XSDM_REG_NUM_OF_Q8_CMD 0x166264UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 8
#define XSDM_REG_NUM_OF_Q9_CMD 0x166268UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 9
#define XSDM_REG_NUM_OF_Q10_CMD 0x16626cUL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 10
#define XSDM_REG_NUM_OF_Q11_CMD 0x166270UL //ACCESS:ST DataWidth:0x20 Description: The number of commands received in queue 11
#define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274UL //ACCESS:ST DataWidth:0x20 Description: The number of packet end messages received from the parser
#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278UL //ACCESS:ST DataWidth:0x20 Description: The number of requests received from the pxp async if
#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627cUL //ACCESS:ST DataWidth:0x20 Description: The number of ACK after placement messages received
#define XSDM_REG_STATISTICS_TM 0x166280UL //ACCESS:RW DataWidth:0x5 Description: TM bits for statistics sram
#define XSDM_REG_DBG_SELECT 0x166284UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from XSDM to the DBG block) - for selecting a line to output to the DBG block
#define XSDM_REG_DBG_BYTE_ENABLE 0x166288UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from XSDM to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define XSDM_REG_DBG_SHIFT 0x16628cUL //ACCESS:RW DataWidth:0x3 Description: Debug only. For dbgmux usage (debug data that goes from XSDM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define XSDM_REG_XSDM_INT_STS_0 0x166290UL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define XSDM_XSDM_INT_STS_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define XSDM_XSDM_INT_STS_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define XSDM_XSDM_INT_STS_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define XSDM_XSDM_INT_STS_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define XSDM_XSDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define XSDM_XSDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define XSDM_XSDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define XSDM_XSDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define XSDM_XSDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define XSDM_XSDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define XSDM_XSDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define XSDM_XSDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define XSDM_XSDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define XSDM_XSDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define XSDM_XSDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define XSDM_XSDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define XSDM_XSDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define XSDM_XSDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define XSDM_XSDM_INT_STS_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define XSDM_XSDM_INT_STS_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define XSDM_XSDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define XSDM_XSDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define XSDM_XSDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define XSDM_XSDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define XSDM_XSDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define XSDM_XSDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define XSDM_XSDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define XSDM_XSDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define XSDM_XSDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define XSDM_XSDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define XSDM_XSDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define XSDM_XSDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define XSDM_XSDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define XSDM_XSDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define XSDM_XSDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define XSDM_XSDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define XSDM_XSDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define XSDM_XSDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define XSDM_REG_XSDM_INT_STS_CLR_0 0x166294UL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define XSDM_XSDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define XSDM_XSDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define XSDM_XSDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define XSDM_XSDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define XSDM_XSDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define XSDM_XSDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define XSDM_XSDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define XSDM_XSDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define XSDM_XSDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define XSDM_XSDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define XSDM_XSDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define XSDM_XSDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define XSDM_XSDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define XSDM_REG_XSDM_INT_STS_WR_0 0x166298UL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define XSDM_XSDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define XSDM_XSDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define XSDM_XSDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define XSDM_XSDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define XSDM_XSDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define XSDM_XSDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define XSDM_XSDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define XSDM_XSDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define XSDM_XSDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define XSDM_XSDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define XSDM_XSDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define XSDM_XSDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define XSDM_XSDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define XSDM_XSDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define XSDM_XSDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define XSDM_XSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define XSDM_XSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define XSDM_XSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define XSDM_XSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define XSDM_XSDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define XSDM_XSDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define XSDM_REG_XSDM_INT_MASK_0 0x16629cUL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE0_ERROR (0x1<<1)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE0_ERROR_SIZE 1
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE1_ERROR (0x1<<2)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE1_ERROR_SIZE 2
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE2_ERROR (0x1<<3)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE2_ERROR_SIZE 3
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE3_ERROR (0x1<<4)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE3_ERROR_SIZE 4
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE4_ERROR (0x1<<5)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE4_ERROR_SIZE 5
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE5_ERROR (0x1<<6)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE5_ERROR_SIZE 6
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE6_ERROR (0x1<<7)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE6_ERROR_SIZE 7
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE7_ERROR (0x1<<8)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE7_ERROR_SIZE 8
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE8_ERROR (0x1<<9)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE8_ERROR_SIZE 9
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE9_ERROR (0x1<<10)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE9_ERROR_SIZE 10
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE10_ERROR (0x1<<11)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE10_ERROR_SIZE 11
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE11_ERROR (0x1<<12)
#define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE11_ERROR_SIZE 12
#define XSDM_XSDM_INT_MASK_0_REG_DELAY_FIFO_ERROR (0x1<<13)
#define XSDM_XSDM_INT_MASK_0_REG_DELAY_FIFO_ERROR_SIZE 13
#define XSDM_XSDM_INT_MASK_0_REG_ASYNC_HOST_ERROR (0x1<<14)
#define XSDM_XSDM_INT_MASK_0_REG_ASYNC_HOST_ERROR_SIZE 14
#define XSDM_XSDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
#define XSDM_XSDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR_SIZE 15
#define XSDM_XSDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
#define XSDM_XSDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR_SIZE 16
#define XSDM_XSDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
#define XSDM_XSDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR_SIZE 17
#define XSDM_XSDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
#define XSDM_XSDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR_SIZE 18
#define XSDM_XSDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
#define XSDM_XSDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR_SIZE 19
#define XSDM_XSDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
#define XSDM_XSDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR_SIZE 20
#define XSDM_XSDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
#define XSDM_XSDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR_SIZE 21
#define XSDM_XSDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
#define XSDM_XSDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR_SIZE 22
#define XSDM_XSDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
#define XSDM_XSDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR_SIZE 23
#define XSDM_XSDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
#define XSDM_XSDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR_SIZE 24
#define XSDM_XSDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
#define XSDM_XSDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR_SIZE 25
#define XSDM_XSDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
#define XSDM_XSDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR_SIZE 26
#define XSDM_XSDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
#define XSDM_XSDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR_SIZE 27
#define XSDM_XSDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
#define XSDM_XSDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR_SIZE 28
#define XSDM_XSDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
#define XSDM_XSDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR_SIZE 29
#define XSDM_XSDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
#define XSDM_XSDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR_SIZE 30
#define XSDM_XSDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
#define XSDM_XSDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR_SIZE 31
#define XSDM_REG_XSDM_INT_STS_1 0x1662a0UL //ACCESS:R DataWidth:0xe Description: Interrupt register #1 read
#define XSDM_XSDM_INT_STS_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define XSDM_XSDM_INT_STS_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define XSDM_XSDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define XSDM_XSDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define XSDM_XSDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define XSDM_XSDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define XSDM_XSDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define XSDM_XSDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define XSDM_XSDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define XSDM_XSDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define XSDM_XSDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define XSDM_XSDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define XSDM_XSDM_INT_STS_1_REG_CM_DELAY_ERROR (0x1<<6)
#define XSDM_XSDM_INT_STS_1_REG_CM_DELAY_ERROR_SIZE 6
#define XSDM_XSDM_INT_STS_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define XSDM_XSDM_INT_STS_1_REG_PXP_DELAY_ERROR_SIZE 7
#define XSDM_XSDM_INT_STS_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define XSDM_XSDM_INT_STS_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define XSDM_XSDM_INT_STS_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define XSDM_XSDM_INT_STS_1_REG_TIMER_PEND_ERROR_SIZE 9
#define XSDM_XSDM_INT_STS_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define XSDM_XSDM_INT_STS_1_REG_DORQ_DPM_ERROR_SIZE 10
#define XSDM_XSDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define XSDM_XSDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define XSDM_XSDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define XSDM_XSDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define XSDM_XSDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define XSDM_XSDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define XSDM_REG_XSDM_INT_STS_CLR_1 0x1662a4UL //ACCESS:RC DataWidth:0xe Description: Interrupt register #1 read clear
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define XSDM_XSDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR (0x1<<6)
#define XSDM_XSDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR_SIZE 6
#define XSDM_XSDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define XSDM_XSDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR_SIZE 7
#define XSDM_XSDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define XSDM_XSDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define XSDM_XSDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define XSDM_XSDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR_SIZE 9
#define XSDM_XSDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define XSDM_XSDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR_SIZE 10
#define XSDM_XSDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define XSDM_XSDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define XSDM_XSDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define XSDM_XSDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define XSDM_XSDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define XSDM_XSDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define XSDM_REG_XSDM_INT_STS_WR_1 0x1662a8UL //ACCESS:WR DataWidth:0xe Description: Interrupt register #1 bit set or clear
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define XSDM_XSDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define XSDM_XSDM_INT_STS_WR_1_REG_CM_DELAY_ERROR (0x1<<6)
#define XSDM_XSDM_INT_STS_WR_1_REG_CM_DELAY_ERROR_SIZE 6
#define XSDM_XSDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define XSDM_XSDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR_SIZE 7
#define XSDM_XSDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define XSDM_XSDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define XSDM_XSDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define XSDM_XSDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR_SIZE 9
#define XSDM_XSDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define XSDM_XSDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR_SIZE 10
#define XSDM_XSDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define XSDM_XSDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define XSDM_XSDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define XSDM_XSDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define XSDM_XSDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define XSDM_XSDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define XSDM_REG_XSDM_INT_MASK_1 0x1662acUL //ACCESS:RW DataWidth:0xe Description: Interrupt mask register #1 read/write
#define XSDM_XSDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
#define XSDM_XSDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR_SIZE 0
#define XSDM_XSDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
#define XSDM_XSDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR_SIZE 1
#define XSDM_XSDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
#define XSDM_XSDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR_SIZE 2
#define XSDM_XSDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
#define XSDM_XSDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR_SIZE 3
#define XSDM_XSDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
#define XSDM_XSDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR_SIZE 4
#define XSDM_XSDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
#define XSDM_XSDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR_SIZE 5
#define XSDM_XSDM_INT_MASK_1_REG_CM_DELAY_ERROR (0x1<<6)
#define XSDM_XSDM_INT_MASK_1_REG_CM_DELAY_ERROR_SIZE 6
#define XSDM_XSDM_INT_MASK_1_REG_PXP_DELAY_ERROR (0x1<<7)
#define XSDM_XSDM_INT_MASK_1_REG_PXP_DELAY_ERROR_SIZE 7
#define XSDM_XSDM_INT_MASK_1_REG_TIMER_ADDR_ERROR (0x1<<8)
#define XSDM_XSDM_INT_MASK_1_REG_TIMER_ADDR_ERROR_SIZE 8
#define XSDM_XSDM_INT_MASK_1_REG_TIMER_PEND_ERROR (0x1<<9)
#define XSDM_XSDM_INT_MASK_1_REG_TIMER_PEND_ERROR_SIZE 9
#define XSDM_XSDM_INT_MASK_1_REG_DORQ_DPM_ERROR (0x1<<10)
#define XSDM_XSDM_INT_MASK_1_REG_DORQ_DPM_ERROR_SIZE 10
#define XSDM_XSDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
#define XSDM_XSDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR_SIZE 11
#define XSDM_XSDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
#define XSDM_XSDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR_SIZE 12
#define XSDM_XSDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
#define XSDM_XSDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR_SIZE 13
#define XSDM_REG_XSDM_PRTY_STS 0x1662b0UL //ACCESS:R DataWidth:0xb Description: Parity register #0 read
#define XSDM_XSDM_PRTY_STS_REG_PARITY (0x1<<0)
#define XSDM_XSDM_PRTY_STS_REG_PARITY_SIZE 0
#define XSDM_XSDM_PRTY_STS_REG_TIMERS (0x1<<1)
#define XSDM_XSDM_PRTY_STS_REG_TIMERS_SIZE 1
#define XSDM_XSDM_PRTY_STS_REG_INP_QUEUE (0x1<<2)
#define XSDM_XSDM_PRTY_STS_REG_INP_QUEUE_SIZE 2
#define XSDM_XSDM_PRTY_STS_REG_ASYNC_RD_DATA (0x1<<3)
#define XSDM_XSDM_PRTY_STS_REG_ASYNC_RD_DATA_SIZE 3
#define XSDM_XSDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define XSDM_XSDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define XSDM_XSDM_PRTY_STS_REG_BRB1_DP_RD_DATA (0x1<<5)
#define XSDM_XSDM_PRTY_STS_REG_BRB1_DP_RD_DATA_SIZE 5
#define XSDM_XSDM_PRTY_STS_REG_PB_RD_DATA (0x1<<6)
#define XSDM_XSDM_PRTY_STS_REG_PB_RD_DATA_SIZE 6
#define XSDM_XSDM_PRTY_STS_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define XSDM_XSDM_PRTY_STS_REG_PXP_CTRL_RD_DATA_SIZE 7
#define XSDM_XSDM_PRTY_STS_REG_INT_RAM_RD_DATA (0x1<<8)
#define XSDM_XSDM_PRTY_STS_REG_INT_RAM_RD_DATA_SIZE 8
#define XSDM_XSDM_PRTY_STS_REG_STAT_RD_DATA (0x1<<9)
#define XSDM_XSDM_PRTY_STS_REG_STAT_RD_DATA_SIZE 9
#define XSDM_XSDM_PRTY_STS_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define XSDM_XSDM_PRTY_STS_REG_CM_QUEUE_RD_DATA_SIZE 10
#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4UL //ACCESS:RC DataWidth:0xb Description: Parity register #0 read clear
#define XSDM_XSDM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
#define XSDM_XSDM_PRTY_STS_CLR_REG_PARITY_SIZE 0
#define XSDM_XSDM_PRTY_STS_CLR_REG_TIMERS (0x1<<1)
#define XSDM_XSDM_PRTY_STS_CLR_REG_TIMERS_SIZE 1
#define XSDM_XSDM_PRTY_STS_CLR_REG_INP_QUEUE (0x1<<2)
#define XSDM_XSDM_PRTY_STS_CLR_REG_INP_QUEUE_SIZE 2
#define XSDM_XSDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA (0x1<<3)
#define XSDM_XSDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA_SIZE 3
#define XSDM_XSDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define XSDM_XSDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define XSDM_XSDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA (0x1<<5)
#define XSDM_XSDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA_SIZE 5
#define XSDM_XSDM_PRTY_STS_CLR_REG_PB_RD_DATA (0x1<<6)
#define XSDM_XSDM_PRTY_STS_CLR_REG_PB_RD_DATA_SIZE 6
#define XSDM_XSDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define XSDM_XSDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA_SIZE 7
#define XSDM_XSDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA (0x1<<8)
#define XSDM_XSDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA_SIZE 8
#define XSDM_XSDM_PRTY_STS_CLR_REG_STAT_RD_DATA (0x1<<9)
#define XSDM_XSDM_PRTY_STS_CLR_REG_STAT_RD_DATA_SIZE 9
#define XSDM_XSDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define XSDM_XSDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA_SIZE 10
#define XSDM_REG_XSDM_PRTY_STS_WR 0x1662b8UL //ACCESS:WR DataWidth:0xb Description: Parity register #0 bit set or clear
#define XSDM_XSDM_PRTY_STS_WR_REG_PARITY (0x1<<0)
#define XSDM_XSDM_PRTY_STS_WR_REG_PARITY_SIZE 0
#define XSDM_XSDM_PRTY_STS_WR_REG_TIMERS (0x1<<1)
#define XSDM_XSDM_PRTY_STS_WR_REG_TIMERS_SIZE 1
#define XSDM_XSDM_PRTY_STS_WR_REG_INP_QUEUE (0x1<<2)
#define XSDM_XSDM_PRTY_STS_WR_REG_INP_QUEUE_SIZE 2
#define XSDM_XSDM_PRTY_STS_WR_REG_ASYNC_RD_DATA (0x1<<3)
#define XSDM_XSDM_PRTY_STS_WR_REG_ASYNC_RD_DATA_SIZE 3
#define XSDM_XSDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define XSDM_XSDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define XSDM_XSDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA (0x1<<5)
#define XSDM_XSDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA_SIZE 5
#define XSDM_XSDM_PRTY_STS_WR_REG_PB_RD_DATA (0x1<<6)
#define XSDM_XSDM_PRTY_STS_WR_REG_PB_RD_DATA_SIZE 6
#define XSDM_XSDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define XSDM_XSDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA_SIZE 7
#define XSDM_XSDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA (0x1<<8)
#define XSDM_XSDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA_SIZE 8
#define XSDM_XSDM_PRTY_STS_WR_REG_STAT_RD_DATA (0x1<<9)
#define XSDM_XSDM_PRTY_STS_WR_REG_STAT_RD_DATA_SIZE 9
#define XSDM_XSDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define XSDM_XSDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA_SIZE 10
#define XSDM_REG_XSDM_PRTY_MASK 0x1662bcUL //ACCESS:RW DataWidth:0xb Description: Parity mask register #0 read/write
#define XSDM_XSDM_PRTY_MASK_REG_PARITY (0x1<<0)
#define XSDM_XSDM_PRTY_MASK_REG_PARITY_SIZE 0
#define XSDM_XSDM_PRTY_MASK_REG_TIMERS (0x1<<1)
#define XSDM_XSDM_PRTY_MASK_REG_TIMERS_SIZE 1
#define XSDM_XSDM_PRTY_MASK_REG_INP_QUEUE (0x1<<2)
#define XSDM_XSDM_PRTY_MASK_REG_INP_QUEUE_SIZE 2
#define XSDM_XSDM_PRTY_MASK_REG_ASYNC_RD_DATA (0x1<<3)
#define XSDM_XSDM_PRTY_MASK_REG_ASYNC_RD_DATA_SIZE 3
#define XSDM_XSDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA (0x1<<4)
#define XSDM_XSDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA_SIZE 4
#define XSDM_XSDM_PRTY_MASK_REG_BRB1_DP_RD_DATA (0x1<<5)
#define XSDM_XSDM_PRTY_MASK_REG_BRB1_DP_RD_DATA_SIZE 5
#define XSDM_XSDM_PRTY_MASK_REG_PB_RD_DATA (0x1<<6)
#define XSDM_XSDM_PRTY_MASK_REG_PB_RD_DATA_SIZE 6
#define XSDM_XSDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA (0x1<<7)
#define XSDM_XSDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA_SIZE 7
#define XSDM_XSDM_PRTY_MASK_REG_INT_RAM_RD_DATA (0x1<<8)
#define XSDM_XSDM_PRTY_MASK_REG_INT_RAM_RD_DATA_SIZE 8
#define XSDM_XSDM_PRTY_MASK_REG_STAT_RD_DATA (0x1<<9)
#define XSDM_XSDM_PRTY_MASK_REG_STAT_RD_DATA_SIZE 9
#define XSDM_XSDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA (0x1<<10)
#define XSDM_XSDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA_SIZE 10
#define XSDM_REG_DORQ_DPM_START_ADDR 0x1662ccUL //ACCESS:RW DataWidth:0xe Description: The start address in the internal RAM for DORQ DPM messages.
#define XSDM_REG_DORQ_ALMOST_FULL 0x1662d0UL //ACCESS:RW DataWidth:0x6 Description: Almost full signal for read data from DORq in SDM_DORQ block
#define XSDM_REG_NUM_OF_DPM_REQ 0x1662d4UL //ACCESS:ST DataWidth:0x20 Description: The number of DORQ DPM messages received
#define XSDM_REG_CMP_COUNTER_MAX4 0x1662d8UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #4
#define XSDM_REG_CMP_COUNTER_MAX5 0x1662dcUL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #5
#define XSDM_REG_CMP_COUNTER_MAX6 0x1662e0UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #6
#define XSDM_REG_CMP_COUNTER_MAX7 0x1662e4UL //ACCESS:RW DataWidth:0x10 Description: The maximum value of the competion counter #7
#define XSDM_REG_CM_QUEUE_TM 0x166570UL //ACCESS:RW DataWidth:0x8 Description: TM bits CM_QUEUE
#define XSDM_REG_INP_QUEUE_TM 0x166574UL //ACCESS:RW DataWidth:0x8 Description: TM bits INP_QUEUE
#define XSDM_REG_FIFOS_TM 0x166578UL //ACCESS:RW DataWidth:0x2 Description: TM bits fifos: BRB1_CTRL[1:0]; Reserved[3:2];Reserved[5:4];PXP_CTRL[7:6]
#define XSDM_REG_TIMERS_TM 0x16657cUL //ACCESS:RW DataWidth:0x2 Description: TM bits for timers sram
#define XSDM_REG_ECO_RESERVED 0x166580UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO
#define XSDM_REG_AGGREG_INTERRUPT_LSB 0x166400UL //ACCESS:R DataWidth:0x20 Description: lsb register of aggregated interrupt in sdm_cm block
#define XSDM_REG_AGGREG_INTERRUPT_LSB_SIZE 1
#define XSDM_REG_AGGREG_INTERRUPT_MSB 0x166404UL //ACCESS:R DataWidth:0x20 Description: msb register of aggregated interrupt in sdm_cm block
#define XSDM_REG_AGGREG_INTERRUPT_MSB_SIZE 1
#define XSDM_REG_ASYNC_HOST_EMPTY 0x166408UL //ACCESS:R DataWidth:0x1 Description: async fifo empty in sdm_async block
#define XSDM_REG_ASYNC_HOST_EMPTY_SIZE 1
#define XSDM_REG_ASYNC_HOST_FULL 0x16640cUL //ACCESS:R DataWidth:0x1 Description: async fifo full in sdm_async block
#define XSDM_REG_ASYNC_HOST_FULL_SIZE 1
#define XSDM_REG_CFC_LOAD_PEND_EMPTY 0x166410UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo empty in sdm_dma_dst block
#define XSDM_REG_CFC_LOAD_PEND_EMPTY_SIZE 1
#define XSDM_REG_CFC_LOAD_PEND_FULL 0x166414UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo full in sdm_cfc block
#define XSDM_REG_CFC_LOAD_PEND_FULL_SIZE 1
#define XSDM_REG_CFC_LOAD_RSP_EMPTY 0x166418UL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo empty in sdm_dma_dst block
#define XSDM_REG_CFC_LOAD_RSP_EMPTY_SIZE 1
#define XSDM_REG_CFC_LOAD_RSP_FULL 0x16641cUL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo full in sdm_cfcblock
#define XSDM_REG_CFC_LOAD_RSP_FULL_SIZE 1
#define XSDM_REG_CM_DELAY_EMPTY 0x166420UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo empty in sdm_dma_dst block
#define XSDM_REG_CM_DELAY_EMPTY_SIZE 1
#define XSDM_REG_CM_DELAY_FULL 0x166424UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo full in sdm_cm block
#define XSDM_REG_CM_DELAY_FULL_SIZE 1
#define XSDM_REG_CM_QUEUE_EMPTY 0x166428UL //ACCESS:R DataWidth:0x1 Description: cm queue fifo empty in sdm_dma_dst block
#define XSDM_REG_CM_QUEUE_EMPTY_SIZE 1
#define XSDM_REG_CM_QUEUE_FULL 0x16642cUL //ACCESS:R DataWidth:0x1 Description: cm queue fifo full in sdm_cm block
#define XSDM_REG_CM_QUEUE_FULL_SIZE 1
#define XSDM_REG_DELAY_FIFO_EMPTY 0x166430UL //ACCESS:R DataWidth:0x1 Description: delay FIFO empty in sdm_inp block
#define XSDM_REG_DELAY_FIFO_EMPTY_SIZE 1
#define XSDM_REG_DELAY_FIFO_FULL 0x166434UL //ACCESS:R DataWidth:0x1 Description: delay FIFO full in sdm_inp block
#define XSDM_REG_DELAY_FIFO_FULL_SIZE 1
#define XSDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY 0x166438UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo empty in sdm_dma_dst block
#define XSDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY_SIZE 1
#define XSDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL 0x16643cUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo full in sdm_dma_dst block
#define XSDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL_SIZE 1
#define XSDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY 0x166440UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo empty in sdm_dma_dst block
#define XSDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY_SIZE 1
#define XSDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL 0x166444UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo full in sdm_dma_dst block
#define XSDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL_SIZE 1
#define XSDM_REG_DST_INT_RAM_IF_FULL 0x166448UL //ACCESS:R DataWidth:0x1 Description: int_ram if full in sdm_dma_dst block
#define XSDM_REG_DST_INT_RAM_IF_FULL_SIZE 1
#define XSDM_REG_DST_INT_RAM_WAIT_EMPTY 0x16644cUL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo empty in sdm_dma_dst block
#define XSDM_REG_DST_INT_RAM_WAIT_EMPTY_SIZE 1
#define XSDM_REG_DST_INT_RAM_WAIT_FULL 0x166450UL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo full in sdm_dma_dst block
#define XSDM_REG_DST_INT_RAM_WAIT_FULL_SIZE 1
#define XSDM_REG_DST_NONE_PEND_EMPTY 0x166454UL //ACCESS:R DataWidth:0x1 Description: none pending fifo empty in sdm_dma_dst block
#define XSDM_REG_DST_NONE_PEND_EMPTY_SIZE 1
#define XSDM_REG_DST_NONE_PEND_FULL 0x166458UL //ACCESS:R DataWidth:0x1 Description: none pending fifo full in sdm_dma_dst block
#define XSDM_REG_DST_NONE_PEND_FULL_SIZE 1
#define XSDM_REG_DST_PAS_BUF_IF_FULL 0x16645cUL //ACCESS:R DataWidth:0x1 Description: pas_buf if full in sdm_dma_dst block
#define XSDM_REG_DST_PAS_BUF_IF_FULL_SIZE 1
#define XSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0x166460UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo empty in sdm_dma_dst block
#define XSDM_REG_DST_PAS_BUF_WAIT_EMPTY_SIZE 1
#define XSDM_REG_DST_PAS_BUF_WAIT_FULL 0x166464UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo full in sdm_dma_dst block
#define XSDM_REG_DST_PAS_BUF_WAIT_FULL_SIZE 1
#define XSDM_REG_DST_PB_IF_FULL 0x166468UL //ACCESS:R DataWidth:0x1 Description: pb if full in sdm_dma_dst block
#define XSDM_REG_DST_PB_IF_FULL_SIZE 1
#define XSDM_REG_DST_PB_IMMED_EMPTY 0x16646cUL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo empty in sdm_dma_dst block
#define XSDM_REG_DST_PB_IMMED_EMPTY_SIZE 1
#define XSDM_REG_DST_PB_IMMED_FULL 0x166470UL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo full in sdm_dma_dst block
#define XSDM_REG_DST_PB_IMMED_FULL_SIZE 1
#define XSDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY 0x166474UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo empty in sdm_dma_dst block
#define XSDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY_SIZE 1
#define XSDM_REG_DST_PXP_CTRL_DST_PEND_FULL 0x166478UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo full in sdm_dma_dst block
#define XSDM_REG_DST_PXP_CTRL_DST_PEND_FULL_SIZE 1
#define XSDM_REG_DST_PXP_CTRL_IF_FULL 0x16647cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl if full in sdm_dma_dst block
#define XSDM_REG_DST_PXP_CTRL_IF_FULL_SIZE 1
#define XSDM_REG_DST_PXP_CTRL_IMMED_EMPTY 0x166480UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo empty in sdm_dma_dst block
#define XSDM_REG_DST_PXP_CTRL_IMMED_EMPTY_SIZE 1
#define XSDM_REG_DST_PXP_CTRL_IMMED_FULL 0x166484UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo full in sdm_dma_dst block
#define XSDM_REG_DST_PXP_CTRL_IMMED_FULL_SIZE 1
#define XSDM_REG_DST_PXP_CTRL_LINK_EMPTY 0x166488UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list empty in sdm_dma_dst block
#define XSDM_REG_DST_PXP_CTRL_LINK_EMPTY_SIZE 1
#define XSDM_REG_DST_PXP_CTRL_LINK_FULL 0x16648cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list full in sdm_dma_dst block
#define XSDM_REG_DST_PXP_CTRL_LINK_FULL_SIZE 1
#define XSDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY 0x166490UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo empty in sdm_dma_dst block
#define XSDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY_SIZE 1
#define XSDM_REG_DST_PXP_CTRL_SRC_PEND_FULL 0x166494UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo full in sdm_dma_dst block
#define XSDM_REG_DST_PXP_CTRL_SRC_PEND_FULL_SIZE 1
#define XSDM_REG_DST_PXP_DP_DST_PEND_EMPTY 0x166498UL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo empty in sdm_dma_dst block
#define XSDM_REG_DST_PXP_DP_DST_PEND_EMPTY_SIZE 1
#define XSDM_REG_DST_PXP_DP_DST_PEND_FULL 0x16649cUL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo full in sdm_dma_dst block
#define XSDM_REG_DST_PXP_DP_DST_PEND_FULL_SIZE 1
#define XSDM_REG_DST_PXP_DP_IF_FULL 0x1664a0UL //ACCESS:R DataWidth:0x1 Description: pxp_dp if full in sdm_dma_dst block
#define XSDM_REG_DST_PXP_DP_IF_FULL_SIZE 1
#define XSDM_REG_DST_PXP_DP_LINK_EMPTY 0x1664a4UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list empty in sdm_dma_dst block
#define XSDM_REG_DST_PXP_DP_LINK_EMPTY_SIZE 1
#define XSDM_REG_DST_PXP_DP_LINK_FULL 0x1664a8UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list full in sdm_dma_dst block
#define XSDM_REG_DST_PXP_DP_LINK_FULL_SIZE 1
#define XSDM_REG_INIT_CREDIT_CFC_ACDEC 0x1664acUL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC activity counters interface without receiving any ACK
#define XSDM_REG_INIT_CREDIT_CFC_ACDEC_SIZE 1
#define XSDM_REG_INIT_CREDIT_CFC_ACINC 0x1664b0UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC activity counters interface without receiving any ACK.
#define XSDM_REG_INIT_CREDIT_CFC_ACINC_SIZE 1
#define XSDM_REG_INIT_CREDIT_CFC_LOAD 0x1664b4UL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the CFC load interface without receiving any ACK.
#define XSDM_REG_INIT_CREDIT_CFC_LOAD_SIZE 1
#define XSDM_REG_INIT_CREDIT_CM 0x1664b8UL //ACCESS:RW DataWidth:0x4 Description: The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block
#define XSDM_REG_INIT_CREDIT_CM_SIZE 1
#define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bcUL //ACCESS:RW DataWidth:0x4 Description: The initial number of messages that can be sent to the pxp control interface without receiving any ACK.
#define XSDM_REG_INIT_CREDIT_PXP_CTRL_SIZE 1
#define XSDM_REG_INT_RAM_RR_REQ 0x1664c0UL //ACCESS:R DataWidth:0x6 Description: round robin for int_ram arbiter: b0-pas_buf; b1-int_ram;b2-pxp_dp;b3-pxp_ctrl;b4-brb1_ctrl;b5-brb1_dp;
#define XSDM_REG_INT_RAM_RR_REQ_SIZE 1
#define XSDM_REG_OPERATION_GEN 0x1664c4UL //ACCESS:W DataWidth:0x11 Description: Generate an operation after completion; bit-16 is AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and bits 4:0 are the T124Param[4:0]
#define XSDM_REG_OPERATION_GEN_SIZE 1
#define XSDM_REG_PB_FULL 0x1664c8UL //ACCESS:R DataWidth:0x1 Description: UPB IF full in sdm_inp block
#define XSDM_REG_PB_FULL_SIZE 1
#define XSDM_REG_PBF_FULL 0x1664ccUL //ACCESS:R DataWidth:0x1 Description: PBF if full in sdm_inp block
#define XSDM_REG_PBF_FULL_SIZE 1
#define XSDM_REG_PXP_DELAY_EMPTY 0x1664d0UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo empty in sdm_dma_dst block
#define XSDM_REG_PXP_DELAY_EMPTY_SIZE 1
#define XSDM_REG_PXP_DELAY_FULL 0x1664d4UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo full in sdm_cm block
#define XSDM_REG_PXP_DELAY_FULL_SIZE 1
#define XSDM_REG_QM_FULL 0x1664d8UL //ACCESS:R DataWidth:0x1 Description: QM IF full in sdm_inp block
#define XSDM_REG_QM_FULL_SIZE 1
#define XSDM_REG_QUEUE_EMPTY 0x1664dcUL //ACCESS:R DataWidth:0xc Description: Input queue fifo empty in sdm_inp block
#define XSDM_REG_QUEUE_EMPTY_SIZE 1
#define XSDM_REG_QUEUE_FULL 0x1664e0UL //ACCESS:R DataWidth:0xc Description: Input queue fifo full in sdm_inp block
#define XSDM_REG_QUEUE_FULL_SIZE 1
#define XSDM_REG_RR_CNT_COUNTERS_STATUS 0x1664e4UL //ACCESS:R DataWidth:0x15 Description: round robin for all completion counters
#define XSDM_REG_RR_CNT_COUNTERS_STATUS_SIZE 1
#define XSDM_REG_RR_COMPLETE_REQ 0x1664e8UL //ACCESS:R DataWidth:0x7 Description: round robin for all completion requests in sdm_cm block: b0-async b1-nop;b2-pxp_int; b3-timers;b4-dma;b5-grc;b6-rbc
#define XSDM_REG_RR_COMPLETE_REQ_SIZE 1
#define XSDM_REG_RR_PTR_REQ 0x1664ecUL //ACCESS:R DataWidth:0x7 Description: round robin for cm pointer: b0-async; b1-dma_dp; b2 - dma_ctrl; b3-cfc; b4-nop; b5-timers; b6-pxp_int
#define XSDM_REG_RR_PTR_REQ_SIZE 1
#define XSDM_REG_RSP_BRB1_CTRL_IF_FULL 0x1664f0UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl if is full in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_CTRL_IF_FULL_SIZE 1
#define XSDM_REG_RSP_BRB1_CTRL_PEND_EMPTY 0x1664f4UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo empty in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_CTRL_PEND_EMPTY_SIZE 1
#define XSDM_REG_RSP_BRB1_CTRL_PEND_FULL 0x1664f8UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo full in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_CTRL_PEND_FULL_SIZE 1
#define XSDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY 0x1664fcUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo empty in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY_SIZE 1
#define XSDM_REG_RSP_BRB1_CTRL_RDATA_FULL 0x166500UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo full in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_CTRL_RDATA_FULL_SIZE 1
#define XSDM_REG_RSP_BRB1_DP_DST_EMPTY 0x166504UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo empty in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_DP_DST_EMPTY_SIZE 1
#define XSDM_REG_RSP_BRB1_DP_DST_FULL 0x166508UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo full in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_DP_DST_FULL_SIZE 1
#define XSDM_REG_RSP_BRB1_DP_IF_FULL 0x16650cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp if is full in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_DP_IF_FULL_SIZE 1
#define XSDM_REG_RSP_BRB1_DP_PEND_EMPTY 0x166510UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo empty in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_DP_PEND_EMPTY_SIZE 1
#define XSDM_REG_RSP_BRB1_DP_PEND_FULL 0x166514UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo full in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_DP_PEND_FULL_SIZE 1
#define XSDM_REG_RSP_BRB1_DP_RDATA_EMPTY 0x166518UL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo empty in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_DP_RDATA_EMPTY_SIZE 1
#define XSDM_REG_RSP_BRB1_DP_RDATA_FULL 0x16651cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo full in sdm_dma_rsp block
#define XSDM_REG_RSP_BRB1_DP_RDATA_FULL_SIZE 1
#define XSDM_REG_RSP_INT_RAM_PEND_EMPTY 0x166520UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo empty in sdm_dma_rsp block
#define XSDM_REG_RSP_INT_RAM_PEND_EMPTY_SIZE 1
#define XSDM_REG_RSP_INT_RAM_PEND_FULL 0x166524UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo full in sdm_dma_rsp block
#define XSDM_REG_RSP_INT_RAM_PEND_FULL_SIZE 1
#define XSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0x166528UL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo empty in sdm_dma_rsp block
#define XSDM_REG_RSP_INT_RAM_RDATA_EMPTY_SIZE 1
#define XSDM_REG_RSP_INT_RAM_RDATA_FULL 0x16652cUL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo full in sdm_dma_rsp block
#define XSDM_REG_RSP_INT_RAM_RDATA_FULL_SIZE 1
#define XSDM_REG_RSP_PB_IF_FULL 0x166530UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
#define XSDM_REG_RSP_PB_IF_FULL_SIZE 1
#define XSDM_REG_RSP_PB_PEND_EMPTY 0x166534UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo empty in sdm_dma_rsp block
#define XSDM_REG_RSP_PB_PEND_EMPTY_SIZE 1
#define XSDM_REG_RSP_PB_PEND_FULL 0x166538UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo full in sdm_dma_rsp block
#define XSDM_REG_RSP_PB_PEND_FULL_SIZE 1
#define XSDM_REG_RSP_PB_RDATA_EMPTY 0x16653cUL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo empty in sdm_dma_rsp block
#define XSDM_REG_RSP_PB_RDATA_EMPTY_SIZE 1
#define XSDM_REG_RSP_PB_RDATA_FULL 0x166540UL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo full in sdm_dma_rsp block
#define XSDM_REG_RSP_PB_RDATA_FULL_SIZE 1
#define XSDM_REG_RSP_PXP_CTRL_IF_FULL 0x166544UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
#define XSDM_REG_RSP_PXP_CTRL_IF_FULL_SIZE 1
#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo empty in sdm_dma_rsp block
#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
#define XSDM_REG_RSP_PXP_CTRL_RDATA_FULL 0x16654cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo full in sdm_dma_rsp block
#define XSDM_REG_RSP_PXP_CTRL_RDATA_FULL_SIZE 1
#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550UL //ACCESS:R DataWidth:0x1 Description: parser fifo empty in sdm_sync block
#define XSDM_REG_SYNC_PARSER_EMPTY_SIZE 1
#define XSDM_REG_SYNC_PARSER_FULL 0x166554UL //ACCESS:R DataWidth:0x1 Description: parser fifo full in sdm_sync block
#define XSDM_REG_SYNC_PARSER_FULL_SIZE 1
#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558UL //ACCESS:R DataWidth:0x1 Description: parser serial fifo empty in sdm_sync block
#define XSDM_REG_SYNC_SYNC_EMPTY_SIZE 1
#define XSDM_REG_SYNC_SYNC_FULL 0x16655cUL //ACCESS:R DataWidth:0x1 Description: parser serial fifo full in sdm_sync block
#define XSDM_REG_SYNC_SYNC_FULL_SIZE 1
#define XSDM_REG_TIMERS_ADDR_EMPTY 0x166560UL //ACCESS:R DataWidth:0x1 Description: address FIFO empty in sdm_timers block
#define XSDM_REG_TIMERS_ADDR_EMPTY_SIZE 1
#define XSDM_REG_TIMERS_ADDR_FULL 0x166564UL //ACCESS:R DataWidth:0x1 Description: address FIFO full in sdm_timers block
#define XSDM_REG_TIMERS_ADDR_FULL_SIZE 1
#define XSDM_REG_TIMERS_PEND_EMPTY 0x166568UL //ACCESS:R DataWidth:0x1 Description: pending FIFO empty in sdm_timers block
#define XSDM_REG_TIMERS_PEND_EMPTY_SIZE 1
#define XSDM_REG_TIMERS_PEND_FULL 0x16656cUL //ACCESS:R DataWidth:0x1 Description: pending FIFO full in sdm_timers block
#define XSDM_REG_TIMERS_PEND_FULL_SIZE 1
#define XSDM_REG_TIMERS 0x166600UL //ACCESS:WB DataWidth:0x34 Description: Debug only. Timers memory.
#define XSDM_REG_TIMERS_SIZE 80
#define XSDM_REG_STATISTICS 0x166800UL //ACCESS:RW DataWidth:0x20 Description: Statistics memory. Each read from RBC resets the corresponding statistic counter
#define XSDM_REG_STATISTICS_SIZE 256
#define XSDM_REG_CM_QUEUE 0x167000UL //ACCESS:WB DataWidth:0x40 Description: Debug only. CM queue memory.
#define XSDM_REG_CM_QUEUE_SIZE 352
#define XSDM_REG_INP_QUEUE 0x167800UL //ACCESS:WB DataWidth:0x40 Description: Debug only. Input queue memory.
#define XSDM_REG_INP_QUEUE_SIZE 352
#define XSDM_REG_XSDM_UNUSED_EMPTY_0 0x1662c0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSDM_REG_XSDM_UNUSED_EMPTY_0_SIZE 3
#define XSDM_REG_XSDM_UNUSED_EMPTY_1 0x1662e8UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSDM_REG_XSDM_UNUSED_EMPTY_1_SIZE 70
#define XSDM_REG_XSDM_UNUSED_EMPTY_2 0x166584UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSDM_REG_XSDM_UNUSED_EMPTY_2_SIZE 31
#define XSDM_REG_XSDM_UNUSED_EMPTY_3 0x166c00UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSDM_REG_XSDM_UNUSED_EMPTY_3_SIZE 256
#define XSEM_REG_MSG_NUM_FIC0 0x280000UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that entered through FIC0
#define XSEM_REG_MSG_NUM_FIC1 0x280004UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that entered through FIC1
#define XSEM_REG_MSG_NUM_FOC0 0x280008UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC0
#define XSEM_REG_MSG_NUM_FOC1 0x28000cUL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC1
#define XSEM_REG_MSG_NUM_FOC2 0x280010UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC2
#define XSEM_REG_MSG_NUM_FOC3 0x280014UL //ACCESS:ST DataWidth:0x18 Description: Statistics register. The number of messages that were sent to FOC3
#define XSEM_REG_THREAD_INTER_CNT_ENABLE 0x280018UL //ACCESS:RW DataWidth:0x1 Description: Enable for start count of counter ~xsem_registers_thread_inter_cnt.thread_inter_cnt
#define XSEM_REG_THREAD_INTER_CNT 0x28001cUL //ACCESS:RW DataWidth:0x10 Description: Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter. This register may be used only when ~xsem_registers_thread_inter_cnt_enable.thread_inter_cnt_enable =1
#define XSEM_REG_ARB_ELEMENT0 0x280020UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 0. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2
#define XSEM_REG_ARB_ELEMENT1 0x280024UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 1. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~xsem_registers_arb_element0.arb_element0
#define XSEM_REG_ARB_ELEMENT2 0x280028UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 2. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~xsem_registers_arb_element0.arb_element0 and ~xsem_registers_arb_element1.arb_element1
#define XSEM_REG_ARB_ELEMENT3 0x28002cUL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 3. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2.Could not be equal to register ~xsem_registers_arb_element0.arb_element0 and ~xsem_registers_arb_element1.arb_element1 and ~xsem_registers_arb_element2.arb_element2
#define XSEM_REG_ARB_ELEMENT4 0x280030UL //ACCESS:RW DataWidth:0x3 Description: The source that is associated with arbitration element 4. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~xsem_registers_arb_element0.arb_element0 and ~xsem_registers_arb_element1.arb_element1 and ~xsem_registers_arb_element2.arb_element2 and ~xsem_registers_arb_element3.arb_element3
#define XSEM_REG_ARB_CYCLE_SIZE 0x280034UL //ACCESS:RW DataWidth:0x5 Description: The number of time_slots in the arbitration cycle
#define XSEM_REG_TS_0_AS 0x280038UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 0
#define XSEM_REG_TS_1_AS 0x28003cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 1
#define XSEM_REG_TS_2_AS 0x280040UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 2
#define XSEM_REG_TS_3_AS 0x280044UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 3
#define XSEM_REG_TS_4_AS 0x280048UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 4
#define XSEM_REG_TS_5_AS 0x28004cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 5
#define XSEM_REG_TS_6_AS 0x280050UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 6
#define XSEM_REG_TS_7_AS 0x280054UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 7
#define XSEM_REG_TS_8_AS 0x280058UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 8
#define XSEM_REG_TS_9_AS 0x28005cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 9
#define XSEM_REG_TS_10_AS 0x280060UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 10
#define XSEM_REG_TS_11_AS 0x280064UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 11
#define XSEM_REG_TS_12_AS 0x280068UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 12
#define XSEM_REG_TS_13_AS 0x28006cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 13
#define XSEM_REG_TS_14_AS 0x280070UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 14
#define XSEM_REG_TS_15_AS 0x280074UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 15
#define XSEM_REG_TS_16_AS 0x280078UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 16
#define XSEM_REG_TS_17_AS 0x28007cUL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 17
#define XSEM_REG_TS_18_AS 0x280080UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 18
#define XSEM_REG_TS_19_AS 0x280084UL //ACCESS:RW DataWidth:0x3 Description: The arbitration scheme of time_slot 19
#define XSEM_REG_FIC0_MIN_MSG_LINES 0x280088UL //ACCESS:RW DataWidth:0x6 Description: The minimum number of cycles in a message from FIC0 interfaces after which the message can be sent to the passive register_file. It must be always equal to 2; other way it may cause to deadlock in a chip.
#define XSEM_REG_FIC1_MIN_MSG_LINES 0x28008cUL //ACCESS:RW DataWidth:0x6 Description: The minimum number of cycles in a message from FIC1 interfaces after which the message can be sent to the passive register_file. It must be always equal to 2; other way it may cause to deadlock in a chip.
#define XSEM_REG_PASSIVE_ALM_FULL 0x280090UL //ACCESS:RW DataWidth:0x5 Description: The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted
#define XSEM_REG_SYNC_DRA_WR_ALM_FULL 0x280094UL //ACCESS:RW DataWidth:0x5 Description: Almost full for sync dra_wr fifo (data from DRA to STORM)
#define XSEM_REG_SYNC_RAM_WR_ALM_FULL 0x280098UL //ACCESS:RW DataWidth:0x6 Description: Almost full for sync ram_wr fifo (data from EXT_IF to STORM)
#define XSEM_REG_DBG_ALM_FULL 0x28009cUL //ACCESS:RW DataWidth:0x6 Description: Almost full for slow debug fifo
#define XSEM_REG_EXCEPTION_INT 0x2800a0UL //ACCESS:RW DataWidth:0xf Description: The PRAM address for the interrupt in a case the event ID is bigger then the INT table size. This register is always NA because this feature is removed
#define XSEM_REG_ENABLE_IN 0x2800a4UL //ACCESS:RW DataWidth:0xf Multi Field Register
#define XSEM_ENABLE_IN_REG_FIC0_ENABLE_IN (0x1<<0)
#define XSEM_ENABLE_IN_REG_FIC0_ENABLE_IN_SIZE 0
#define XSEM_ENABLE_IN_REG_FIC1_ENABLE_IN (0x1<<1)
#define XSEM_ENABLE_IN_REG_FIC1_ENABLE_IN_SIZE 1
#define XSEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN (0x1<<2)
#define XSEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN_SIZE 2
#define XSEM_ENABLE_IN_REG_GENERAL_ENABLE_IN (0x1<<3)
#define XSEM_ENABLE_IN_REG_GENERAL_ENABLE_IN_SIZE 3
#define XSEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN (0x1<<4)
#define XSEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN_SIZE 4
#define XSEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN (0x1<<5)
#define XSEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN_SIZE 5
#define XSEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN (0x1<<6)
#define XSEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN_SIZE 6
#define XSEM_ENABLE_IN_REG_RAM0_ENABLE_IN (0x1<<7)
#define XSEM_ENABLE_IN_REG_RAM0_ENABLE_IN_SIZE 7
#define XSEM_ENABLE_IN_REG_RAM1_ENABLE_IN (0x1<<8)
#define XSEM_ENABLE_IN_REG_RAM1_ENABLE_IN_SIZE 8
#define XSEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN (0x1<<9)
#define XSEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN_SIZE 9
#define XSEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN (0x1<<10)
#define XSEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN_SIZE 10
#define XSEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN (0x1<<11)
#define XSEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN_SIZE 11
#define XSEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN (0x1<<12)
#define XSEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN_SIZE 12
#define XSEM_ENABLE_IN_REG_WAITP_ENABLE_IN (0x1<<13)
#define XSEM_ENABLE_IN_REG_WAITP_ENABLE_IN_SIZE 13
#define XSEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN (0x1<<14)
#define XSEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN_SIZE 14
#define XSEM_REG_ENABLE_OUT 0x2800a8UL //ACCESS:RW DataWidth:0xa Multi Field Register
#define XSEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT (0x1<<0)
#define XSEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT_SIZE 0
#define XSEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT (0x1<<1)
#define XSEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT_SIZE 1
#define XSEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT (0x1<<2)
#define XSEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT_SIZE 2
#define XSEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT (0x1<<3)
#define XSEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT_SIZE 3
#define XSEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT (0x1<<4)
#define XSEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT_SIZE 4
#define XSEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT (0x1<<5)
#define XSEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT_SIZE 5
#define XSEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT (0x1<<6)
#define XSEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT_SIZE 6
#define XSEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT (0x1<<7)
#define XSEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT_SIZE 7
#define XSEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT (0x1<<8)
#define XSEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT_SIZE 8
#define XSEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT (0x1<<9)
#define XSEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT_SIZE 9
#define XSEM_REG_STORM0_H_TM 0x2800acUL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm0_h memory instance
#define XSEM_REG_STORM1_H_TM 0x2800b0UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm1_h memory instance
#define XSEM_REG_STORM0_L_TM 0x2800b4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm0_l memory instance
#define XSEM_REG_STORM1_L_TM 0x2800b8UL //ACCESS:RW DataWidth:0x5 Description: TM bits for storm1_l memory instance
#define XSEM_REG_CAM_TM 0x2800bcUL //ACCESS:RW DataWidth:0xe Description: TM bits for cam
#define XSEM_REG_RAM0_TM 0x2800c0UL //ACCESS:RW DataWidth:0x5 Description: tm for ram0_0
#define XSEM_REG_PAS_BUF_LSB_TMA 0x2800c4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_lsb
#define XSEM_REG_PAS_BUF_LSB_TMB 0x2800c8UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_lsb
#define XSEM_REG_PAS_BUF_MSB_TMA 0x2800ccUL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_msb
#define XSEM_REG_PAS_BUF_MSB_TMB 0x2800d0UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory pas_buf_msb
#define XSEM_REG_INT_TABLE_TM 0x2800d4UL //ACCESS:RW DataWidth:0x5 Description: TM bits for memory int_table
#define XSEM_REG_CLEAR_WAITP 0x2800d8UL //ACCESS:RW DataWidth:0x1 Description: Write 1 to this register will disable waitp from this storm to other storms
#define XSEM_REG_SLOW_DBG_MODE 0x2800dcUL //ACCESS:RW DataWidth:0x3 Description: debug mode for slow debug bus. Applicable only when ~xsem_registers_slow_dbg_active.slow_dbg_active =1. If mode =0 thread number; pram address and DRA WR data selected; if mode =1 fin command and DRA RD ; if mode =2 pram address and thread number and fin command and released thread from STORM; if mode =3 STORE data to SDM
#define XSEM_REG_SLOW_DBG_ACTIVE 0x2800e0UL //ACCESS:RW DataWidth:0x1 Description: debug mode is active
#define XSEM_REG_DBG_MSG_SRC 0x2800e4UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~xsem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0only FIC-s output to debug bus; 1=both FIC-s and passive buffer.
#define XSEM_REG_DBG_MODE0_CFG 0x2800e8UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~xsem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0 all the message output to debug bus; 1=partial message.
#define XSEM_REG_DBG_MODE0_CFG_CYCLE 0x2800ecUL //ACCESS:RW DataWidth:0x5 Description: Applicable only when ~xsem_registers_dbg_mode0_cfg.dbg_mode0_cfg =1. If =1 the additional cycles to extract to the debug bus.
#define XSEM_REG_DBG_MODE1_CFG 0x2800f0UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~xsem_registers_slow_dbg_mode.slow_dbg_mode =1. If=0 output to debug bus without the data; 1=with the data.
#define XSEM_REG_DBG_EACH_CYLE 0x2800f4UL //ACCESS:RW DataWidth:0x1 Description: If=0 output every cycle full indication or thread status; 1= output only when there is a change.
#define XSEM_REG_DBG_SELECT 0x2800f8UL //ACCESS:RW DataWidth:0x8 Description: Debug only. For dbgmux usage (debug data that goes from USEMI to the DBG block) - for selecting a line to output to the DBG block
#define XSEM_REG_DBG_BYTE_ENABLE 0x2800fcUL //ACCESS:RW DataWidth:0x8 Description: Debug only.For dbgmux usage (debug data that goes from USEM to the DBG block) - for enabling bytes in the selected line (after the select before the shift).
#define XSEM_REG_DBG_SHIFT 0x280100UL //ACCESS:RW DataWidth:0x3 Description: Debug only.For dbgmux usage (debug data that goes from USEM to the DBG block) - for circular right shifting of the selected line (after the enabling).
#define XSEM_REG_XSEM_INT_STS_0 0x280104UL //ACCESS:R DataWidth:0x20 Description: Interrupt register #0 read
#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define XSEM_XSEM_INT_STS_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define XSEM_XSEM_INT_STS_0_REG_FIC0_LAST_ERROR_SIZE 1
#define XSEM_XSEM_INT_STS_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define XSEM_XSEM_INT_STS_0_REG_FIC1_LAST_ERROR_SIZE 2
#define XSEM_XSEM_INT_STS_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define XSEM_XSEM_INT_STS_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define XSEM_XSEM_INT_STS_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define XSEM_XSEM_INT_STS_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define XSEM_XSEM_INT_STS_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define XSEM_XSEM_INT_STS_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define XSEM_XSEM_INT_STS_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define XSEM_XSEM_INT_STS_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define XSEM_XSEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define XSEM_XSEM_INT_STS_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define XSEM_XSEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define XSEM_XSEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define XSEM_XSEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define XSEM_XSEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define XSEM_XSEM_INT_STS_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define XSEM_XSEM_INT_STS_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define XSEM_XSEM_INT_STS_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define XSEM_XSEM_INT_STS_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define XSEM_XSEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define XSEM_XSEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define XSEM_XSEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define XSEM_XSEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define XSEM_XSEM_INT_STS_0_REG_RD_EMPTY_CAM (0x1<<20)
#define XSEM_XSEM_INT_STS_0_REG_RD_EMPTY_CAM_SIZE 20
#define XSEM_XSEM_INT_STS_0_REG_WR_FULL_CAM (0x1<<21)
#define XSEM_XSEM_INT_STS_0_REG_WR_FULL_CAM_SIZE 21
#define XSEM_XSEM_INT_STS_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define XSEM_XSEM_INT_STS_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define XSEM_XSEM_INT_STS_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define XSEM_XSEM_INT_STS_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define XSEM_XSEM_INT_STS_0_REG_CAM_OUT_FIFO (0x1<<24)
#define XSEM_XSEM_INT_STS_0_REG_CAM_OUT_FIFO_SIZE 24
#define XSEM_XSEM_INT_STS_0_REG_FIN_FIFO (0x1<<25)
#define XSEM_XSEM_INT_STS_0_REG_FIN_FIFO_SIZE 25
#define XSEM_XSEM_INT_STS_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define XSEM_XSEM_INT_STS_0_REG_SET0_THREAD_ERROR_SIZE 26
#define XSEM_XSEM_INT_STS_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define XSEM_XSEM_INT_STS_0_REG_SET1_THREAD_ERROR_SIZE 27
#define XSEM_XSEM_INT_STS_0_REG_THREAD_OVERRUN (0x1<<28)
#define XSEM_XSEM_INT_STS_0_REG_THREAD_OVERRUN_SIZE 28
#define XSEM_XSEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define XSEM_XSEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define XSEM_XSEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define XSEM_XSEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define XSEM_REG_XSEM_INT_STS_CLR_0 0x280108UL //ACCESS:RC DataWidth:0x20 Description: Interrupt register #0 read clear
#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR_SIZE 1
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR_SIZE 2
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define XSEM_XSEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define XSEM_XSEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define XSEM_XSEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define XSEM_XSEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define XSEM_XSEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define XSEM_XSEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define XSEM_XSEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define XSEM_XSEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define XSEM_XSEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define XSEM_XSEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define XSEM_XSEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM (0x1<<20)
#define XSEM_XSEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM_SIZE 20
#define XSEM_XSEM_INT_STS_CLR_0_REG_WR_FULL_CAM (0x1<<21)
#define XSEM_XSEM_INT_STS_CLR_0_REG_WR_FULL_CAM_SIZE 21
#define XSEM_XSEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define XSEM_XSEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define XSEM_XSEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define XSEM_XSEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define XSEM_XSEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO (0x1<<24)
#define XSEM_XSEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO_SIZE 24
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIN_FIFO (0x1<<25)
#define XSEM_XSEM_INT_STS_CLR_0_REG_FIN_FIFO_SIZE 25
#define XSEM_XSEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR_SIZE 26
#define XSEM_XSEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR_SIZE 27
#define XSEM_XSEM_INT_STS_CLR_0_REG_THREAD_OVERRUN (0x1<<28)
#define XSEM_XSEM_INT_STS_CLR_0_REG_THREAD_OVERRUN_SIZE 28
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define XSEM_REG_XSEM_INT_STS_WR_0 0x28010cUL //ACCESS:WR DataWidth:0x20 Description: Interrupt register #0 bit set or clear
#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR_SIZE 1
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR_SIZE 2
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define XSEM_XSEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define XSEM_XSEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define XSEM_XSEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define XSEM_XSEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define XSEM_XSEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define XSEM_XSEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define XSEM_XSEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define XSEM_XSEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define XSEM_XSEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define XSEM_XSEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define XSEM_XSEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define XSEM_XSEM_INT_STS_WR_0_REG_RD_EMPTY_CAM (0x1<<20)
#define XSEM_XSEM_INT_STS_WR_0_REG_RD_EMPTY_CAM_SIZE 20
#define XSEM_XSEM_INT_STS_WR_0_REG_WR_FULL_CAM (0x1<<21)
#define XSEM_XSEM_INT_STS_WR_0_REG_WR_FULL_CAM_SIZE 21
#define XSEM_XSEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define XSEM_XSEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define XSEM_XSEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define XSEM_XSEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define XSEM_XSEM_INT_STS_WR_0_REG_CAM_OUT_FIFO (0x1<<24)
#define XSEM_XSEM_INT_STS_WR_0_REG_CAM_OUT_FIFO_SIZE 24
#define XSEM_XSEM_INT_STS_WR_0_REG_FIN_FIFO (0x1<<25)
#define XSEM_XSEM_INT_STS_WR_0_REG_FIN_FIFO_SIZE 25
#define XSEM_XSEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define XSEM_XSEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR_SIZE 26
#define XSEM_XSEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define XSEM_XSEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR_SIZE 27
#define XSEM_XSEM_INT_STS_WR_0_REG_THREAD_OVERRUN (0x1<<28)
#define XSEM_XSEM_INT_STS_WR_0_REG_THREAD_OVERRUN_SIZE 28
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define XSEM_REG_XSEM_INT_MASK_0 0x280110UL //ACCESS:RW DataWidth:0x20 Description: Interrupt mask register #0 read/write
#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
#define XSEM_XSEM_INT_MASK_0_REG_FIC0_LAST_ERROR (0x1<<1)
#define XSEM_XSEM_INT_MASK_0_REG_FIC0_LAST_ERROR_SIZE 1
#define XSEM_XSEM_INT_MASK_0_REG_FIC1_LAST_ERROR (0x1<<2)
#define XSEM_XSEM_INT_MASK_0_REG_FIC1_LAST_ERROR_SIZE 2
#define XSEM_XSEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
#define XSEM_XSEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR_SIZE 3
#define XSEM_XSEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
#define XSEM_XSEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR_SIZE 4
#define XSEM_XSEM_INT_MASK_0_REG_FIC0_FIFO_ERROR (0x1<<5)
#define XSEM_XSEM_INT_MASK_0_REG_FIC0_FIFO_ERROR_SIZE 5
#define XSEM_XSEM_INT_MASK_0_REG_FIC1_FIFO_ERROR (0x1<<6)
#define XSEM_XSEM_INT_MASK_0_REG_FIC1_FIFO_ERROR_SIZE 6
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR_SIZE 7
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR_SIZE 8
#define XSEM_XSEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
#define XSEM_XSEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR_SIZE 9
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR_SIZE 10
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR_SIZE 11
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR_SIZE 12
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR_SIZE 13
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR_SIZE 14
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR_SIZE 15
#define XSEM_XSEM_INT_MASK_0_REG_MAX_HANDLER_ERROR (0x1<<16)
#define XSEM_XSEM_INT_MASK_0_REG_MAX_HANDLER_ERROR_SIZE 16
#define XSEM_XSEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
#define XSEM_XSEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR_SIZE 17
#define XSEM_XSEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
#define XSEM_XSEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO_SIZE 18
#define XSEM_XSEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
#define XSEM_XSEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO_SIZE 19
#define XSEM_XSEM_INT_MASK_0_REG_RD_EMPTY_CAM (0x1<<20)
#define XSEM_XSEM_INT_MASK_0_REG_RD_EMPTY_CAM_SIZE 20
#define XSEM_XSEM_INT_MASK_0_REG_WR_FULL_CAM (0x1<<21)
#define XSEM_XSEM_INT_MASK_0_REG_WR_FULL_CAM_SIZE 21
#define XSEM_XSEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
#define XSEM_XSEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO_SIZE 22
#define XSEM_XSEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
#define XSEM_XSEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO_SIZE 23
#define XSEM_XSEM_INT_MASK_0_REG_CAM_OUT_FIFO (0x1<<24)
#define XSEM_XSEM_INT_MASK_0_REG_CAM_OUT_FIFO_SIZE 24
#define XSEM_XSEM_INT_MASK_0_REG_FIN_FIFO (0x1<<25)
#define XSEM_XSEM_INT_MASK_0_REG_FIN_FIFO_SIZE 25
#define XSEM_XSEM_INT_MASK_0_REG_SET0_THREAD_ERROR (0x1<<26)
#define XSEM_XSEM_INT_MASK_0_REG_SET0_THREAD_ERROR_SIZE 26
#define XSEM_XSEM_INT_MASK_0_REG_SET1_THREAD_ERROR (0x1<<27)
#define XSEM_XSEM_INT_MASK_0_REG_SET1_THREAD_ERROR_SIZE 27
#define XSEM_XSEM_INT_MASK_0_REG_THREAD_OVERRUN (0x1<<28)
#define XSEM_XSEM_INT_MASK_0_REG_THREAD_OVERRUN_SIZE 28
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR_SIZE 29
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR_SIZE 30
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
#define XSEM_XSEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR_SIZE 31
#define XSEM_REG_XSEM_INT_STS_1 0x280114UL //ACCESS:R DataWidth:0xd Description: Interrupt register #1 read
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define XSEM_XSEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define XSEM_XSEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define XSEM_XSEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define XSEM_XSEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define XSEM_XSEM_INT_STS_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define XSEM_XSEM_INT_STS_1_REG_DBG_FIFO_ERROR_SIZE 9
#define XSEM_XSEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define XSEM_XSEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define XSEM_XSEM_INT_STS_1_REG_VFC_INTERRUPT (0x1<<11)
#define XSEM_XSEM_INT_STS_1_REG_VFC_INTERRUPT_SIZE 11
#define XSEM_XSEM_INT_STS_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
#define XSEM_XSEM_INT_STS_1_REG_VFC_OUT_FIFO_ERROR_SIZE 12
#define XSEM_REG_XSEM_INT_STS_CLR_1 0x280118UL //ACCESS:RC DataWidth:0xd Description: Interrupt register #1 read clear
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define XSEM_XSEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define XSEM_XSEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR_SIZE 9
#define XSEM_XSEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define XSEM_XSEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define XSEM_XSEM_INT_STS_CLR_1_REG_VFC_INTERRUPT (0x1<<11)
#define XSEM_XSEM_INT_STS_CLR_1_REG_VFC_INTERRUPT_SIZE 11
#define XSEM_XSEM_INT_STS_CLR_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
#define XSEM_XSEM_INT_STS_CLR_1_REG_VFC_OUT_FIFO_ERROR_SIZE 12
#define XSEM_REG_XSEM_INT_STS_WR_1 0x28011cUL //ACCESS:WR DataWidth:0xd Description: Interrupt register #1 bit set or clear
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define XSEM_XSEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define XSEM_XSEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR_SIZE 9
#define XSEM_XSEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define XSEM_XSEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define XSEM_XSEM_INT_STS_WR_1_REG_VFC_INTERRUPT (0x1<<11)
#define XSEM_XSEM_INT_STS_WR_1_REG_VFC_INTERRUPT_SIZE 11
#define XSEM_XSEM_INT_STS_WR_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
#define XSEM_XSEM_INT_STS_WR_1_REG_VFC_OUT_FIFO_ERROR_SIZE 12
#define XSEM_REG_XSEM_INT_MASK_1 0x280120UL //ACCESS:RW DataWidth:0xd Description: Interrupt mask register #1 read/write
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR_SIZE 0
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR_SIZE 1
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR_SIZE 2
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR_SIZE 3
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR_SIZE 4
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR_SIZE 5
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR_SIZE 6
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR_SIZE 7
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
#define XSEM_XSEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR_SIZE 8
#define XSEM_XSEM_INT_MASK_1_REG_DBG_FIFO_ERROR (0x1<<9)
#define XSEM_XSEM_INT_MASK_1_REG_DBG_FIFO_ERROR_SIZE 9
#define XSEM_XSEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
#define XSEM_XSEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO_SIZE 10
#define XSEM_XSEM_INT_MASK_1_REG_VFC_INTERRUPT (0x1<<11)
#define XSEM_XSEM_INT_MASK_1_REG_VFC_INTERRUPT_SIZE 11
#define XSEM_XSEM_INT_MASK_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
#define XSEM_XSEM_INT_MASK_1_REG_VFC_OUT_FIFO_ERROR_SIZE 12
#define XSEM_REG_XSEM_PRTY_STS_0 0x280124UL //ACCESS:R DataWidth:0x20 Description: Parity register #0 read
#define XSEM_XSEM_PRTY_STS_0_REG_PARITY (0x1<<0)
#define XSEM_XSEM_PRTY_STS_0_REG_PARITY_SIZE 0
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define XSEM_XSEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define XSEM_XSEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define XSEM_XSEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define XSEM_XSEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define XSEM_XSEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define XSEM_XSEM_PRTY_STS_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define XSEM_XSEM_PRTY_STS_0_REG_PAS_FIFO_PARITY_SIZE 10
#define XSEM_XSEM_PRTY_STS_0_REG_PAS_PARITY0 (0x1<<11)
#define XSEM_XSEM_PRTY_STS_0_REG_PAS_PARITY0_SIZE 11
#define XSEM_XSEM_PRTY_STS_0_REG_PAS_PARITY1 (0x1<<12)
#define XSEM_XSEM_PRTY_STS_0_REG_PAS_PARITY1_SIZE 12
#define XSEM_XSEM_PRTY_STS_0_REG_INT_TABLE_PARITY (0x1<<13)
#define XSEM_XSEM_PRTY_STS_0_REG_INT_TABLE_PARITY_SIZE 13
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY0 (0x1<<14)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY0_SIZE 14
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY1 (0x1<<15)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY1_SIZE 15
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY2 (0x1<<16)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY2_SIZE 16
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY3 (0x1<<17)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY3_SIZE 17
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY4 (0x1<<18)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY4_SIZE 18
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY5 (0x1<<19)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY5_SIZE 19
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY6 (0x1<<20)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY6_SIZE 20
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY7 (0x1<<21)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY7_SIZE 21
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY0 (0x1<<22)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY0_SIZE 22
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY1 (0x1<<23)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY1_SIZE 23
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY2 (0x1<<24)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY2_SIZE 24
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY3 (0x1<<25)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY3_SIZE 25
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY4 (0x1<<26)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY4_SIZE 26
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY5 (0x1<<27)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY5_SIZE 27
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY6 (0x1<<28)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY6_SIZE 28
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY7 (0x1<<29)
#define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY7_SIZE 29
#define XSEM_XSEM_PRTY_STS_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define XSEM_XSEM_PRTY_STS_0_REG_PRAM_LOW_PARITY_SIZE 30
#define XSEM_XSEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define XSEM_XSEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128UL //ACCESS:RC DataWidth:0x20 Description: Parity register #0 read clear
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PARITY_SIZE 0
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY_SIZE 10
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PAS_PARITY0 (0x1<<11)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PAS_PARITY0_SIZE 11
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PAS_PARITY1 (0x1<<12)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PAS_PARITY1_SIZE 12
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY (0x1<<13)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY_SIZE 13
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0 (0x1<<14)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0_SIZE 14
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1 (0x1<<15)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1_SIZE 15
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2 (0x1<<16)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2_SIZE 16
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3 (0x1<<17)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3_SIZE 17
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4 (0x1<<18)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4_SIZE 18
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5 (0x1<<19)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5_SIZE 19
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6 (0x1<<20)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6_SIZE 20
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7 (0x1<<21)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7_SIZE 21
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0 (0x1<<22)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0_SIZE 22
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1 (0x1<<23)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1_SIZE 23
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2 (0x1<<24)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2_SIZE 24
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3 (0x1<<25)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3_SIZE 25
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4 (0x1<<26)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4_SIZE 26
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5 (0x1<<27)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5_SIZE 27
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6 (0x1<<28)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6_SIZE 28
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7 (0x1<<29)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7_SIZE 29
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY_SIZE 30
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define XSEM_XSEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define XSEM_REG_XSEM_PRTY_STS_WR_0 0x28012cUL //ACCESS:WR DataWidth:0x20 Description: Parity register #0 bit set or clear
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PARITY_SIZE 0
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define XSEM_XSEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define XSEM_XSEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY_SIZE 10
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PAS_PARITY0 (0x1<<11)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PAS_PARITY0_SIZE 11
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PAS_PARITY1 (0x1<<12)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PAS_PARITY1_SIZE 12
#define XSEM_XSEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY (0x1<<13)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY_SIZE 13
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY0 (0x1<<14)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY0_SIZE 14
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY1 (0x1<<15)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY1_SIZE 15
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY2 (0x1<<16)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY2_SIZE 16
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY3 (0x1<<17)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY3_SIZE 17
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY4 (0x1<<18)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY4_SIZE 18
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY5 (0x1<<19)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY5_SIZE 19
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY6 (0x1<<20)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY6_SIZE 20
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY7 (0x1<<21)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY7_SIZE 21
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY0 (0x1<<22)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY0_SIZE 22
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY1 (0x1<<23)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY1_SIZE 23
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY2 (0x1<<24)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY2_SIZE 24
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY3 (0x1<<25)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY3_SIZE 25
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY4 (0x1<<26)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY4_SIZE 26
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY5 (0x1<<27)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY5_SIZE 27
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY6 (0x1<<28)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY6_SIZE 28
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY7 (0x1<<29)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY7_SIZE 29
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY_SIZE 30
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define XSEM_XSEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130UL //ACCESS:RW DataWidth:0x20 Description: Parity mask register #0 read/write
#define XSEM_XSEM_PRTY_MASK_0_REG_PARITY (0x1<<0)
#define XSEM_XSEM_PRTY_MASK_0_REG_PARITY_SIZE 0
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY_SIZE 1
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY_SIZE 2
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY_SIZE 3
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY_SIZE 4
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY_SIZE 5
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY_SIZE 6
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
#define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY_SIZE 7
#define XSEM_XSEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY (0x1<<8)
#define XSEM_XSEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY_SIZE 8
#define XSEM_XSEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY (0x1<<9)
#define XSEM_XSEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY_SIZE 9
#define XSEM_XSEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY (0x1<<10)
#define XSEM_XSEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY_SIZE 10
#define XSEM_XSEM_PRTY_MASK_0_REG_PAS_PARITY0 (0x1<<11)
#define XSEM_XSEM_PRTY_MASK_0_REG_PAS_PARITY0_SIZE 11
#define XSEM_XSEM_PRTY_MASK_0_REG_PAS_PARITY1 (0x1<<12)
#define XSEM_XSEM_PRTY_MASK_0_REG_PAS_PARITY1_SIZE 12
#define XSEM_XSEM_PRTY_MASK_0_REG_INT_TABLE_PARITY (0x1<<13)
#define XSEM_XSEM_PRTY_MASK_0_REG_INT_TABLE_PARITY_SIZE 13
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY0 (0x1<<14)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY0_SIZE 14
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY1 (0x1<<15)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY1_SIZE 15
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY2 (0x1<<16)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY2_SIZE 16
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY3 (0x1<<17)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY3_SIZE 17
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY4 (0x1<<18)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY4_SIZE 18
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY5 (0x1<<19)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY5_SIZE 19
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY6 (0x1<<20)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY6_SIZE 20
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY7 (0x1<<21)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY7_SIZE 21
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY0 (0x1<<22)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY0_SIZE 22
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY1 (0x1<<23)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY1_SIZE 23
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY2 (0x1<<24)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY2_SIZE 24
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY3 (0x1<<25)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY3_SIZE 25
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY4 (0x1<<26)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY4_SIZE 26
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY5 (0x1<<27)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY5_SIZE 27
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY6 (0x1<<28)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY6_SIZE 28
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY7 (0x1<<29)
#define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY7_SIZE 29
#define XSEM_XSEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY (0x1<<30)
#define XSEM_XSEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY_SIZE 30
#define XSEM_XSEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY (0x1<<31)
#define XSEM_XSEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY_SIZE 31
#define XSEM_REG_XSEM_PRTY_STS_1 0x280134UL //ACCESS:R DataWidth:0x6 Description: Parity register #1 read
#define XSEM_XSEM_PRTY_STS_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define XSEM_XSEM_PRTY_STS_1_REG_SYNC_DBG_PARITY_SIZE 0
#define XSEM_XSEM_PRTY_STS_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define XSEM_XSEM_PRTY_STS_1_REG_SLOW_DBG_PARITY_SIZE 1
#define XSEM_XSEM_PRTY_STS_1_REG_CAM_PARITY (0x1<<2)
#define XSEM_XSEM_PRTY_STS_1_REG_CAM_PARITY_SIZE 2
#define XSEM_XSEM_PRTY_STS_1_REG_STORM_RF0_PARITY (0x1<<3)
#define XSEM_XSEM_PRTY_STS_1_REG_STORM_RF0_PARITY_SIZE 3
#define XSEM_XSEM_PRTY_STS_1_REG_STORM_RF1_PARITY (0x1<<4)
#define XSEM_XSEM_PRTY_STS_1_REG_STORM_RF1_PARITY_SIZE 4
#define XSEM_XSEM_PRTY_STS_1_REG_VFC_PARITY (0x1<<5)
#define XSEM_XSEM_PRTY_STS_1_REG_VFC_PARITY_SIZE 5
#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138UL //ACCESS:RC DataWidth:0x6 Description: Parity register #1 read clear
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY_SIZE 0
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY_SIZE 1
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_CAM_PARITY (0x1<<2)
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_CAM_PARITY_SIZE 2
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY (0x1<<3)
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY_SIZE 3
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY (0x1<<4)
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY_SIZE 4
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_VFC_PARITY (0x1<<5)
#define XSEM_XSEM_PRTY_STS_CLR_1_REG_VFC_PARITY_SIZE 5
#define XSEM_REG_XSEM_PRTY_STS_WR_1 0x28013cUL //ACCESS:WR DataWidth:0x6 Description: Parity register #1 bit set or clear
#define XSEM_XSEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define XSEM_XSEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY_SIZE 0
#define XSEM_XSEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define XSEM_XSEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY_SIZE 1
#define XSEM_XSEM_PRTY_STS_WR_1_REG_CAM_PARITY (0x1<<2)
#define XSEM_XSEM_PRTY_STS_WR_1_REG_CAM_PARITY_SIZE 2
#define XSEM_XSEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY (0x1<<3)
#define XSEM_XSEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY_SIZE 3
#define XSEM_XSEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY (0x1<<4)
#define XSEM_XSEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY_SIZE 4
#define XSEM_XSEM_PRTY_STS_WR_1_REG_VFC_PARITY (0x1<<5)
#define XSEM_XSEM_PRTY_STS_WR_1_REG_VFC_PARITY_SIZE 5
#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140UL //ACCESS:RW DataWidth:0x6 Description: Parity mask register #1 read/write
#define XSEM_XSEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY (0x1<<0)
#define XSEM_XSEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY_SIZE 0
#define XSEM_XSEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY (0x1<<1)
#define XSEM_XSEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY_SIZE 1
#define XSEM_XSEM_PRTY_MASK_1_REG_CAM_PARITY (0x1<<2)
#define XSEM_XSEM_PRTY_MASK_1_REG_CAM_PARITY_SIZE 2
#define XSEM_XSEM_PRTY_MASK_1_REG_STORM_RF0_PARITY (0x1<<3)
#define XSEM_XSEM_PRTY_MASK_1_REG_STORM_RF0_PARITY_SIZE 3
#define XSEM_XSEM_PRTY_MASK_1_REG_STORM_RF1_PARITY (0x1<<4)
#define XSEM_XSEM_PRTY_MASK_1_REG_STORM_RF1_PARITY_SIZE 4
#define XSEM_XSEM_PRTY_MASK_1_REG_VFC_PARITY (0x1<<5)
#define XSEM_XSEM_PRTY_MASK_1_REG_VFC_PARITY_SIZE 5
#define XSEM_REG_RAM0_TM1 0x28014cUL //ACCESS:RW DataWidth:0x5 Description: tm for ram0_1
#define XSEM_REG_RAM0_TM2 0x280150UL //ACCESS:RW DataWidth:0x5 Description: tm for ram0_2
#define XSEM_REG_ECO_RESERVED 0x2803a8UL //ACCESS:RW DataWidth:0x8 Description: Reserved bits for ECO
#define XSEM_REG_FIFOS_TM 0x2803acUL //ACCESS:RW DataWidth:0xe Description: TM bits for FIC0_LSB [1:0]; FIC0_MSB[3:2]; FIC1_LSB[5:4]; FIC1_MSB[7:6]; DBG_LSB[9:8];DBG_MSB[11:10]; EXT_PAS[13:12]
#define XSEM_REG_ARBITER_REQUEST 0x280200UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2
#define XSEM_REG_ARBITER_REQUEST_SIZE 1
#define XSEM_REG_ARBITER_SELECT 0x280204UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2
#define XSEM_REG_ARBITER_SELECT_SIZE 1
#define XSEM_REG_ARBITER_SLOT 0x280208UL //ACCESS:R DataWidth:0x5 Description: dra arbiter last slot
#define XSEM_REG_ARBITER_SLOT_SIZE 1
#define XSEM_REG_DBG_IF_FULL 0x28020cUL //ACCESS:R DataWidth:0x1 Description: DBG IF is full in sem_slow_ls_dbg
#define XSEM_REG_DBG_IF_FULL_SIZE 1
#define XSEM_REG_DRA_EMPTY 0x280210UL //ACCESS:R DataWidth:0x1 Description: This register is active when FIN FIO is empty and DRA RD FIFO is empty
#define XSEM_REG_DRA_EMPTY_SIZE 1
#define XSEM_REG_EXT_PAS_EMPTY 0x280214UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO empty in sem_slow
#define XSEM_REG_EXT_PAS_EMPTY_SIZE 1
#define XSEM_REG_EXT_PAS_FULL 0x280218UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO Full in sem_slow
#define XSEM_REG_EXT_PAS_FULL_SIZE 1
#define XSEM_REG_EXT_STORE_FREE_ENTRIES 0x28021cUL //ACCESS:R DataWidth:0x6 Description: Number of free entries in the external STORE sync FIFO.
#define XSEM_REG_EXT_STORE_FREE_ENTRIES_SIZE 1
#define XSEM_REG_EXT_STORE_IF_FULL 0x280220UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE IF is full in sem_slow_ls_ext
#define XSEM_REG_EXT_STORE_IF_FULL_SIZE 1
#define XSEM_REG_FIC0_DISABLE 0x280224UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC0 May be updated during run_time by the microcode
#define XSEM_REG_FIC0_DISABLE_SIZE 1
#define XSEM_REG_FIC0_EMPTY 0x280228UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
#define XSEM_REG_FIC0_EMPTY_SIZE 1
#define XSEM_REG_FIC0_FULL 0x28022cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
#define XSEM_REG_FIC0_FULL_SIZE 1
#define XSEM_REG_FIC0_LENGTH 0x280230UL //ACCESS:R DataWidth:0x8 Description: Length from FIC0. Active only with ~xsem_registers_fic0_length_error.fic0_length_error interrupt
#define XSEM_REG_FIC0_LENGTH_SIZE 1
#define XSEM_REG_FIC1_DISABLE 0x280234UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC1 May be updated during run_time by the microcode
#define XSEM_REG_FIC1_DISABLE_SIZE 1
#define XSEM_REG_FIC1_EMPTY 0x280238UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
#define XSEM_REG_FIC1_EMPTY_SIZE 1
#define XSEM_REG_FIC1_FULL 0x28023cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
#define XSEM_REG_FIC1_FULL_SIZE 1
#define XSEM_REG_FIC1_LENGTH 0x280240UL //ACCESS:R DataWidth:0x8 Description: Length from FIC1. Active only with ~xsem_registers_fic1_length_error.fic1_length_error interrupt
#define XSEM_REG_FIC1_LENGTH_SIZE 1
#define XSEM_REG_GPI_DATA 0x280244UL //ACCESS:R DataWidth:0x18 Description: GPI signals that are inputs to SEMI
#define XSEM_REG_GPI_DATA_SIZE 1
#define XSEM_REG_NUM_OF_THREADS 0x280248UL //ACCESS:R DataWidth:0x6 Description: The number of threads currently active
#define XSEM_REG_NUM_OF_THREADS_SIZE 1
#define XSEM_REG_PAS_DISABLE 0x28024cUL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from the passive buffer May be updated during run_time by the microcode
#define XSEM_REG_PAS_DISABLE_SIZE 1
#define XSEM_REG_PAS_IF_FULL 0x280250UL //ACCESS:R DataWidth:0x1 Description: Full from passive buffer asserted toward SDM
#define XSEM_REG_PAS_IF_FULL_SIZE 1
#define XSEM_REG_RAM0_IF_FULL 0x280254UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM0 IF is full in sem_slow_ls_ram
#define XSEM_REG_RAM0_IF_FULL_SIZE 1
#define XSEM_REG_RAM1_IF_FULL 0x280258UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM1 IF is full in sem_slow_ls_ram
#define XSEM_REG_RAM1_IF_FULL_SIZE 1
#define XSEM_REG_SET0_THREAD_EMPTY 0x28025cUL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is empty in sem_slow_dra_wr
#define XSEM_REG_SET0_THREAD_EMPTY_SIZE 1
#define XSEM_REG_SET0_THREAD_FULL 0x280260UL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is full in sem_slow_dra_wr
#define XSEM_REG_SET0_THREAD_FULL_SIZE 1
#define XSEM_REG_SET1_THREAD_EMPTY 0x280264UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is empty in sem_slow_dra_wr
#define XSEM_REG_SET1_THREAD_EMPTY_SIZE 1
#define XSEM_REG_SET1_THREAD_FULL 0x280268UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is full in sem_slow_dra_wr
#define XSEM_REG_SET1_THREAD_FULL_SIZE 1
#define XSEM_REG_SLEEP_THREADS_VALID 0x28026cUL //ACCESS:R DataWidth:0x14 Description: Valid sleeping threads indication have bit per thread
#define XSEM_REG_SLEEP_THREADS_VALID_SIZE 1
#define XSEM_REG_SLOW_DBG_ALM_EMPTY 0x280270UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg (31 entry inside fifo)
#define XSEM_REG_SLOW_DBG_ALM_EMPTY_SIZE 1
#define XSEM_REG_SLOW_DBG_ALM_FULL 0x280274UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg according to configuration
#define XSEM_REG_SLOW_DBG_ALM_FULL_SIZE 1
#define XSEM_REG_SLOW_DBG_EMPTY 0x280278UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is empty in sem_slow_ls_dbg
#define XSEM_REG_SLOW_DBG_EMPTY_SIZE 1
#define XSEM_REG_SLOW_DBG_FULL 0x28027cUL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is full in sem_slow_ls_dbg
#define XSEM_REG_SLOW_DBG_FULL_SIZE 1
#define XSEM_REG_SLOW_DRA_FIN_EMPTY 0x280280UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is empty in sem_slow_dra_sync
#define XSEM_REG_SLOW_DRA_FIN_EMPTY_SIZE 1
#define XSEM_REG_SLOW_DRA_FIN_FULL 0x280284UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is full in sem_slow_dra_sync (never may be active)
#define XSEM_REG_SLOW_DRA_FIN_FULL_SIZE 1
#define XSEM_REG_SLOW_DRA_INT_EMPTY 0x280288UL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is empty in sem_slow_dra_sync
#define XSEM_REG_SLOW_DRA_INT_EMPTY_SIZE 1
#define XSEM_REG_SLOW_DRA_INT_FULL 0x28028cUL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is full in sem_slow_dra_int
#define XSEM_REG_SLOW_DRA_INT_FULL_SIZE 1
#define XSEM_REG_SLOW_DRA_RD_EMPTY 0x280290UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is empty in sem_slow_dra_sync
#define XSEM_REG_SLOW_DRA_RD_EMPTY_SIZE 1
#define XSEM_REG_SLOW_DRA_RD_FULL 0x280294UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is full in sem_slow_dra_sync
#define XSEM_REG_SLOW_DRA_RD_FULL_SIZE 1
#define XSEM_REG_SLOW_DRA_WR_EMPTY 0x280298UL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is empty in sem_slow_dra_sync
#define XSEM_REG_SLOW_DRA_WR_EMPTY_SIZE 1
#define XSEM_REG_SLOW_DRA_WR_FULL 0x28029cUL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is full in sem_slow_dra_sync
#define XSEM_REG_SLOW_DRA_WR_FULL_SIZE 1
#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is empty in sem_slow_ls_ext
#define XSEM_REG_SLOW_EXT_STORE_EMPTY_SIZE 1
#define XSEM_REG_SLOW_EXT_STORE_FULL 0x2802a4UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is full in sem_slow_ls_ext
#define XSEM_REG_SLOW_EXT_STORE_FULL_SIZE 1
#define XSEM_REG_SLOW_RAM0_RD_EMPTY 0x2802a8UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is empty in sem_slow_ls_ext
#define XSEM_REG_SLOW_RAM0_RD_EMPTY_SIZE 1
#define XSEM_REG_SLOW_RAM0_RD_FULL 0x2802acUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is full in sem_slow_ls_ext
#define XSEM_REG_SLOW_RAM0_RD_FULL_SIZE 1
#define XSEM_REG_SLOW_RAM0_WR_ALM_FULL 0x2802b0UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
#define XSEM_REG_SLOW_RAM0_WR_ALM_FULL_SIZE 1
#define XSEM_REG_SLOW_RAM0_WR_EMPTY 0x2802b4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is empty in sem_slow_ls_ext
#define XSEM_REG_SLOW_RAM0_WR_EMPTY_SIZE 1
#define XSEM_REG_SLOW_RAM0_WR_FULL 0x2802b8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is full in sem_slow_ls_ext
#define XSEM_REG_SLOW_RAM0_WR_FULL_SIZE 1
#define XSEM_REG_SLOW_RAM1_RD_EMPTY 0x2802bcUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is empty in sem_slow_ls_ext
#define XSEM_REG_SLOW_RAM1_RD_EMPTY_SIZE 1
#define XSEM_REG_SLOW_RAM1_RD_FULL 0x2802c0UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is full in sem_slow_ls_ext
#define XSEM_REG_SLOW_RAM1_RD_FULL_SIZE 1
#define XSEM_REG_SLOW_RAM1_WR_ALM_FULL 0x2802c4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
#define XSEM_REG_SLOW_RAM1_WR_ALM_FULL_SIZE 1
#define XSEM_REG_SLOW_RAM1_WR_EMPTY 0x2802c8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is empty in sem_slow_ls_ext
#define XSEM_REG_SLOW_RAM1_WR_EMPTY_SIZE 1
#define XSEM_REG_SLOW_RAM1_WR_FULL 0x2802ccUL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is full in sem_slow_ls_ext
#define XSEM_REG_SLOW_RAM1_WR_FULL_SIZE 1
#define XSEM_REG_SYNC_DBG_EMPTY 0x2802d0UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is empty in sem_slow_ls_sync
#define XSEM_REG_SYNC_DBG_EMPTY_SIZE 1
#define XSEM_REG_SYNC_DBG_FULL 0x2802d4UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is full in sem_slow_ls_sync
#define XSEM_REG_SYNC_DBG_FULL_SIZE 1
#define XSEM_REG_THREAD_ERROR 0x2802d8UL //ACCESS:R DataWidth:0x14 Description: Thread error indication have bit per thread
#define XSEM_REG_THREAD_ERROR_SIZE 1
#define XSEM_REG_THREAD_OVERRUN_NUM 0x2802dcUL //ACCESS:R DataWidth:0x14 Description: Threads are sleeping in passive buffer more than ~xsem_registers_thread_inter_cnt.thread_inter_cnt number of cycles
#define XSEM_REG_THREAD_OVERRUN_NUM_SIZE 1
#define XSEM_REG_THREAD_RDY 0x2802e0UL //ACCESS:R DataWidth:0x14 Description: Thread ready indication have bit per thread
#define XSEM_REG_THREAD_RDY_SIZE 1
#define XSEM_REG_THREADS_LIST 0x2802e4UL //ACCESS:RW DataWidth:0x14 Description: List of free threads . There is a bit per thread.
#define XSEM_REG_THREADS_LIST_SIZE 1
#define XSEM_REG_WB_MSB 0x2802e8UL //ACCESS:R DataWidth:0x2 Description: Reset value of this register is right when was not read to ~xsem_registers_fic0_fifo.fic0_fifo or ~xsem_registers_fic1_fifo.fic1_fifo or ~xsem_registers_passive_buffer.passive_buffer. For read from ~xsem_registers_passive_buffer.passive_buffer :b0- parity0; b1 parity1. For read from ~xsem_registers_fic0_fifo.fic0_fifo and ~xsem_registers_fic1_fifo.fic1_fifo :b1=0 data from ~xsem_registers_fic0_fifo.fic0_fifo and ~xsem_registers_fic1_fifo.fic1_fifo is valid; b1 =1 ~xsem_registers_fic0_fifo.fic0_fifo and ~xsem_registers_fic1_fifo.fic1_fifo is empty and data from it must be equal to 0; b0 - parity from ~xsem_registers_fic0_fifo.fic0_fifo and ~xsem_registers_fic1_fifo.fic1_fifo
#define XSEM_REG_WB_MSB_SIZE 1
#define XSEM_REG_FIC0_FIFO 0x280300UL //ACCESS:WB_R DataWidth:0x80 Description: Debug only. FIC0_fifo: b[127:0] data; b128-parity;b129=1- fifo empty;b129=0-data is valid
#define XSEM_REG_FIC0_FIFO_SIZE 4
#define XSEM_REG_FIC1_FIFO 0x280320UL //ACCESS:WB_R DataWidth:0x80 Description: Debug only. FIC1_fifo read for debugging mode; b[127:0] data; b128-parity;
#define XSEM_REG_FIC1_FIFO_SIZE 4
#define XSEM_REG_FIN_COMMAND 0x280340UL //ACCESS:WB_R DataWidth:0x6d Description: last fin command that was read from fifo. Its spelling in ~xsem_registers_fin_fifo.fin_fifo register
#define XSEM_REG_FIN_COMMAND_SIZE 4
#define XSEM_REG_FIN_FIFO 0x280360UL //ACCESS:WB_R DataWidth:0x6d Description: Debug only. FIn FIFO. [5:0] start_rp_foc3; [11:6] start_rp_foc2; [17:12] start_rp_foc1; [23:18] start_rp_foc0; [29:24] end_rp_foc3; [35:30] end_rp_foc2; [41:36] end_rp_foc1; [47:42] end_rp_foc0; [53:48] lowest rp; [59:54] highest rp; [65:60] store start rp; [71:66] store end rp; [77:72] load start rp; [83:78] load end rp; [85:84] priority; [101:86] pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid
#define XSEM_REG_FIN_FIFO_SIZE 4
#define XSEM_REG_VFPF_ERR_NUM 0x280380UL //ACCESS:W DataWidth:0x7 Description: VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 VF; values 64-67 reset error for 4 PF; values 68-127 are not valid.
#define XSEM_REG_VFPF_ERR_NUM_SIZE 1
#define XSEM_REG_VF_ERR_VECTOR_LSB 0x280388UL //ACCESS:R DataWidth:0x20 Description: VF/PF error bitmap vector [0-31]
#define XSEM_REG_VF_ERR_VECTOR_LSB_SIZE 1
#define XSEM_REG_VF_ERR_VECTOR_MSB 0x280390UL //ACCESS:R DataWidth:0x20 Description: VF/PF error bitmap vector [32-63]
#define XSEM_REG_VF_ERR_VECTOR_MSB_SIZE 1
#define XSEM_REG_PF_ERR_VECTOR 0x280398UL //ACCESS:R DataWidth:0x8 Description: VF/PF error bitmap vector [0-7]
#define XSEM_REG_PF_ERR_VECTOR_SIZE 1
#define XSEM_REG_THREAD_SET_NUM 0x2803a0UL //ACCESS:W DataWidth:0x5 Description: Thread ID. Write thread ID will set ready indication for this thread ID
#define XSEM_REG_THREAD_SET_NUM_SIZE 1
#define XSEM_REG_INT_TABLE 0x280400UL //ACCESS:RW DataWidth:0xf Description: Interrupt table Read and write access to it is not possible in the middle of the work
#define XSEM_REG_INT_TABLE_SIZE 256
#define XSEM_REG_PASSIVE_BUFFER 0x282000UL //ACCESS:WB DataWidth:0x80 Description: Debug only. Passive buffer memory
#define XSEM_REG_PASSIVE_BUFFER_SIZE 2048
#define XSEM_REG_PASSIVE_BUFFER_MSB 0x284000UL //ACCESS:WB DataWidth:0x80 Description: Debug only. Passive buffer memory MSB that starts from row 512 of passive buffer till row 639
#define XSEM_REG_PASSIVE_BUFFER_MSB_SIZE 512
#define XSEM_REG_FAST_MEMORY 0x2a0000UL //ACCESS:RW DataWidth:0x20 Description: This address space contains all registers and memories that are placed in SEM_FAST block. The SEM_FAST registers are described in appendix B. In order to access the SEM_FAST registers the base address XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each SEM_FAST register offset.
#define XSEM_REG_FAST_MEMORY_SIZE 32768
#define XSEM_REG_PRAM 0x2c0000UL //ACCESS:WB DataWidth:0x2e Description: pram memory. B45 is parity; b[44:0] - data.
#define XSEM_REG_PRAM_SIZE 65536
#define XSEM_REG_XSEM_UNUSED_EMPTY_0 0x280144UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_0_SIZE 2
#define XSEM_REG_XSEM_UNUSED_EMPTY_1 0x280154UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_1_SIZE 43
#define XSEM_REG_XSEM_UNUSED_EMPTY_2 0x2802ecUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_2_SIZE 5
#define XSEM_REG_XSEM_UNUSED_EMPTY_3 0x280384UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_3_SIZE 1
#define XSEM_REG_XSEM_UNUSED_EMPTY_4 0x28038cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_4_SIZE 1
#define XSEM_REG_XSEM_UNUSED_EMPTY_5 0x280394UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_5_SIZE 1
#define XSEM_REG_XSEM_UNUSED_EMPTY_6 0x28039cUL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_6_SIZE 1
#define XSEM_REG_XSEM_UNUSED_EMPTY_7 0x2803a4UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_7_SIZE 1
#define XSEM_REG_XSEM_UNUSED_EMPTY_8 0x2803b0UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_8_SIZE 20
#define XSEM_REG_XSEM_UNUSED_EMPTY_9 0x280800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_9_SIZE 1536
#define XSEM_REG_XSEM_UNUSED_EMPTY_10 0x284800UL //ACCESS:R DataWidth:0x20 Unused empty space
#define XSEM_REG_XSEM_UNUSED_EMPTY_10_SIZE 28160
#define MCP_REG_MCPR_UNUSED_A 0x80000 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED_A_COUNT 32
#define MCP_REG_MCPR_MCP_CONTROL 0x80080 //ACCESS:?? DataWidth:0x20
#define MCPR_MCP_CONTROL_SMBUS_SEL (1L<<30)
#define MCPR_MCP_CONTROL_SMBUS_SEL_BITSHIFT 30
#define MCPR_MCP_CONTROL_MCP_ISOLATE (1L<<31)
#define MCPR_MCP_CONTROL_MCP_ISOLATE_BITSHIFT 31
#define MCP_REG_MCPR_MCP_ATTENTION_STATUS 0x80084 //ACCESS:?? DataWidth:0x20
#define MCPR_MCP_ATTENTION_STATUS_DRV_DOORBELL (1L<<29)
#define MCPR_MCP_ATTENTION_STATUS_DRV_DOORBELL_BITSHIFT 29
#define MCPR_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT (1L<<30)
#define MCPR_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT_BITSHIFT 30
#define MCPR_MCP_ATTENTION_STATUS_CPU_EVENT (1L<<31)
#define MCPR_MCP_ATTENTION_STATUS_CPU_EVENT_BITSHIFT 31
#define MCP_REG_MCPR_MCP_HEARTBEAT_CONTROL 0x80088 //ACCESS:?? DataWidth:0x20
#define MCPR_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE (1L<<31)
#define MCPR_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE_BITSHIFT 31
#define MCP_REG_MCPR_MCP_HEARTBEAT_STATUS 0x8008c //ACCESS:?? DataWidth:0x20
#define MCPR_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD (0x7ffL<<0)
#define MCPR_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD_BITSHIFT 0
#define MCPR_MCP_HEARTBEAT_STATUS_VALID (1L<<31)
#define MCPR_MCP_HEARTBEAT_STATUS_VALID_BITSHIFT 31
#define MCP_REG_MCPR_MCP_HEARTBEAT 0x80090 //ACCESS:?? DataWidth:0x20
#define MCPR_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT (0x3fffffffL<<0)
#define MCPR_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT_BITSHIFT 0
#define MCPR_MCP_HEARTBEAT_MCP_HEARTBEAT_INC (1L<<30)
#define MCPR_MCP_HEARTBEAT_MCP_HEARTBEAT_INC_BITSHIFT 30
#define MCPR_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET (1L<<31)
#define MCPR_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET_BITSHIFT 31
#define MCP_REG_MCPR_WATCHDOG_RESET 0x80094 //ACCESS:?? DataWidth:0x20
#define MCPR_WATCHDOG_RESET_WATCHDOG_RESET (1L<<31)
#define MCPR_WATCHDOG_RESET_WATCHDOG_RESET_BITSHIFT 31
#define MCP_REG_MCPR_WATCHDOG_CONTROL 0x80098 //ACCESS:?? DataWidth:0x20
#define MCPR_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT (0xfffffffL<<0)
#define MCPR_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT_BITSHIFT 0
#define MCPR_WATCHDOG_CONTROL_WATCHDOG_ATTN (1L<<29)
#define MCPR_WATCHDOG_CONTROL_WATCHDOG_ATTN_BITSHIFT 29
#define MCPR_WATCHDOG_CONTROL_MCP_RST_ENABLE (1L<<30)
#define MCPR_WATCHDOG_CONTROL_MCP_RST_ENABLE_BITSHIFT 30
#define MCPR_WATCHDOG_CONTROL_WATCHDOG_ENABLE (1L<<31)
#define MCPR_WATCHDOG_CONTROL_WATCHDOG_ENABLE_BITSHIFT 31
#define MCP_REG_MCPR_ACCESS_LOCK 0x8009c //ACCESS:?? DataWidth:0x20
#define MCPR_ACCESS_LOCK_LOCK (1L<<31)
#define MCPR_ACCESS_LOCK_LOCK_BITSHIFT 31
#define MCP_REG_MCPR_TOE_ID 0x800a0 //ACCESS:?? DataWidth:0x20
#define MCPR_TOE_ID_FUNCTION_ID (1L<<31)
#define MCPR_TOE_ID_FUNCTION_ID_BITSHIFT 31
#define MCP_REG_MCPR_MAILBOX_CFG 0x800a4 //ACCESS:?? DataWidth:0x20
#define MCPR_MAILBOX_CFG_MAILBOX_OFFSET (0x3fffL<<0)
#define MCPR_MAILBOX_CFG_MAILBOX_OFFSET_BITSHIFT 0
#define MCPR_MAILBOX_CFG_MAILBOX_SIZE (0xfffL<<20)
#define MCPR_MAILBOX_CFG_MAILBOX_SIZE_BITSHIFT 20
#define MCP_REG_MCPR_MAILBOX_CFG_OTHER_FUNC 0x800a8 //ACCESS:?? DataWidth:0x20
#define MCPR_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET (0x3fffL<<0)
#define MCPR_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET_BITSHIFT 0
#define MCPR_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE (0xfffL<<20)
#define MCPR_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE_BITSHIFT 20
#define MCP_REG_MCPR_MCP_DOORBELL 0x800ac //ACCESS:?? DataWidth:0x20
#define MCPR_MCP_DOORBELL_MCP_DOORBELL (1L<<31)
#define MCPR_MCP_DOORBELL_MCP_DOORBELL_BITSHIFT 31
#define MCP_REG_MCPR_DRIVER_DOORBELL 0x800b0 //ACCESS:?? DataWidth:0x20
#define MCPR_DRIVER_DOORBELL_DRIVER_DOORBELL (1L<<31)
#define MCPR_DRIVER_DOORBELL_DRIVER_DOORBELL_BITSHIFT 31
#define MCP_REG_MCPR_DRIVER_DOORBELL_OTHER_FUNC 0x800b4 //ACCESS:?? DataWidth:0x20
#define MCPR_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL (1L<<31)
#define MCPR_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL_BITSHIFT 31
#define MCP_REG_MCPR_PORT4MODE_EN 0x800b8 //ACCESS:?? DataWidth:0x20
#define MCPR_PORT4MODE_EN_FOUR_PORT_MODE (1L<<0)
#define MCPR_PORT4MODE_EN_FOUR_PORT_MODE_BITSHIFT 0
#define MCP_REG_MCPR_MCP_VFID 0x800bc //ACCESS:?? DataWidth:0x20
#define MCPR_MCP_VFID_VFID (0x3fL<<0)
#define MCPR_MCP_VFID_VFID_BITSHIFT 0
#define MCPR_MCP_VFID_VFID_VALID (1L<<16)
#define MCPR_MCP_VFID_VFID_VALID_BITSHIFT 16
#define MCPR_MCP_VFID_PATHID (1L<<20)
#define MCPR_MCP_VFID_PATHID_BITSHIFT 20
#define MCPR_MCP_VFID_PATH_FORCE (1L<<31)
#define MCPR_MCP_VFID_PATH_FORCE_BITSHIFT 31
#define MCP_REG_MCPR_GP_INPUTS 0x800c0 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_GP_OENABLE 0x800c8 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_GP_MASK_HI_TO_LO 0x800cc //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_GP_MASK_LO_TO_HI 0x800d0 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_GP_HI_TO_LO 0x800d4 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_GP_LO_TO_HI 0x800d8 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_GP_EVENT_VEC 0x800dc //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED_B 0x800e0 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED_B_COUNT 5064
#define MCP_REG_MCPR_CPU_MODE 0x85000 //ACCESS:?? DataWidth:0x20
#define MCPR_CPU_MODE_LOCAL_RST (1L<<0)
#define MCPR_CPU_MODE_LOCAL_RST_BITSHIFT 0
#define MCPR_CPU_MODE_STEP_ENA (1L<<1)
#define MCPR_CPU_MODE_STEP_ENA_BITSHIFT 1
#define MCPR_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
#define MCPR_CPU_MODE_PAGE_0_DATA_ENA_BITSHIFT 2
#define MCPR_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
#define MCPR_CPU_MODE_PAGE_0_INST_ENA_BITSHIFT 3
#define MCPR_CPU_MODE_MSG_BIT1 (1L<<6)
#define MCPR_CPU_MODE_MSG_BIT1_BITSHIFT 6
#define MCPR_CPU_MODE_INTERRUPT_ENA (1L<<7)
#define MCPR_CPU_MODE_INTERRUPT_ENA_BITSHIFT 7
#define MCPR_CPU_MODE_SOFT_HALT (1L<<10)
#define MCPR_CPU_MODE_SOFT_HALT_BITSHIFT 10
#define MCPR_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
#define MCPR_CPU_MODE_BAD_DATA_HALT_ENA_BITSHIFT 11
#define MCPR_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
#define MCPR_CPU_MODE_BAD_INST_HALT_ENA_BITSHIFT 12
#define MCPR_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
#define MCPR_CPU_MODE_FIO_ABORT_HALT_ENA_BITSHIFT 13
#define MCPR_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
#define MCPR_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA_BITSHIFT 15
#define MCP_REG_MCPR_CPU_STATE 0x85004 //ACCESS:?? DataWidth:0x20
#define MCPR_CPU_STATE_BREAKPOINT (1L<<0)
#define MCPR_CPU_STATE_BREAKPOINT_BITSHIFT 0
#define MCPR_CPU_STATE_BAD_INST_HALTED (1L<<2)
#define MCPR_CPU_STATE_BAD_INST_HALTED_BITSHIFT 2
#define MCPR_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
#define MCPR_CPU_STATE_PAGE_0_DATA_HALTED_BITSHIFT 3
#define MCPR_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
#define MCPR_CPU_STATE_PAGE_0_INST_HALTED_BITSHIFT 4
#define MCPR_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
#define MCPR_CPU_STATE_BAD_DATA_ADDR_HALTED_BITSHIFT 5
#define MCPR_CPU_STATE_BAD_PC_HALTED (1L<<6)
#define MCPR_CPU_STATE_BAD_PC_HALTED_BITSHIFT 6
#define MCPR_CPU_STATE_ALIGN_HALTED (1L<<7)
#define MCPR_CPU_STATE_ALIGN_HALTED_BITSHIFT 7
#define MCPR_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
#define MCPR_CPU_STATE_FIO_ABORT_HALTED_BITSHIFT 8
#define MCPR_CPU_STATE_SOFT_HALTED (1L<<10)
#define MCPR_CPU_STATE_SOFT_HALTED_BITSHIFT 10
#define MCPR_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
#define MCPR_CPU_STATE_SPAD_UNDERFLOW_BITSHIFT 11
#define MCPR_CPU_STATE_INTERRRUPT (1L<<12)
#define MCPR_CPU_STATE_INTERRRUPT_BITSHIFT 12
#define MCPR_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
#define MCPR_CPU_STATE_DATA_ACCESS_STALL_BITSHIFT 14
#define MCPR_CPU_STATE_INST_FETCH_STALL (1L<<15)
#define MCPR_CPU_STATE_INST_FETCH_STALL_BITSHIFT 15
#define MCPR_CPU_STATE_BLOCKED_READ (1L<<31)
#define MCPR_CPU_STATE_BLOCKED_READ_BITSHIFT 31
#define MCP_REG_MCPR_CPU_EVENT_MASK 0x85008 //ACCESS:?? DataWidth:0x20
#define MCPR_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
#define MCPR_CPU_EVENT_MASK_BREAKPOINT_MASK_BITSHIFT 0
#define MCPR_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
#define MCPR_CPU_EVENT_MASK_BAD_INST_HALTED_MASK_BITSHIFT 2
#define MCPR_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
#define MCPR_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK_BITSHIFT 3
#define MCPR_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
#define MCPR_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK_BITSHIFT 4
#define MCPR_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
#define MCPR_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK_BITSHIFT 5
#define MCPR_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
#define MCPR_CPU_EVENT_MASK_BAD_PC_HALTED_MASK_BITSHIFT 6
#define MCPR_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
#define MCPR_CPU_EVENT_MASK_ALIGN_HALTED_MASK_BITSHIFT 7
#define MCPR_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
#define MCPR_CPU_EVENT_MASK_FIO_ABORT_MASK_BITSHIFT 8
#define MCPR_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
#define MCPR_CPU_EVENT_MASK_SOFT_HALTED_MASK_BITSHIFT 10
#define MCPR_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
#define MCPR_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK_BITSHIFT 11
#define MCPR_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
#define MCPR_CPU_EVENT_MASK_INTERRUPT_MASK_BITSHIFT 12
#define MCP_REG_MCPR_CPU_UNUSED_B 0x8500c //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_CPU_UNUSED_B_COUNT 4
#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_CPU_INSTRUCTION 0x85020 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_CPU_DATA_ACCESS 0x85024 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_CPU_INTERRUPT_ENABLE 0x85028 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_CPU_INTERRUPT_VECTOR 0x8502c //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_CPU_INTERRUPT_SAVED_PC 0x85030 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_CPU_HW_BREAKPOINT 0x85034 //ACCESS:?? DataWidth:0x20
#define MCPR_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
#define MCPR_CPU_HW_BREAKPOINT_DISABLE_BITSHIFT 0
#define MCPR_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
#define MCPR_CPU_HW_BREAKPOINT_ADDRESS_BITSHIFT 2
#define MCP_REG_MCPR_CPU_DEBUG_VECT_PEEK 0x85038 //ACCESS:?? DataWidth:0x20
#define MCPR_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
#define MCPR_CPU_DEBUG_VECT_PEEK_1_VALUE_BITSHIFT 0
#define MCPR_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
#define MCPR_CPU_DEBUG_VECT_PEEK_1_PEEK_EN_BITSHIFT 11
#define MCPR_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
#define MCPR_CPU_DEBUG_VECT_PEEK_1_SEL_BITSHIFT 12
#define MCPR_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
#define MCPR_CPU_DEBUG_VECT_PEEK_2_VALUE_BITSHIFT 16
#define MCPR_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
#define MCPR_CPU_DEBUG_VECT_PEEK_2_PEEK_EN_BITSHIFT 27
#define MCPR_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
#define MCPR_CPU_DEBUG_VECT_PEEK_2_SEL_BITSHIFT 28
#define MCP_REG_MCPR_CPU_UNUSED_D 0x8503c //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_CPU_UNUSED_D_COUNT 3
#define MCP_REG_MCPR_CPU_LAST_BRANCH_ADDR 0x85048 //ACCESS:?? DataWidth:0x20
#define MCPR_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
#define MCPR_CPU_LAST_BRANCH_ADDR_TYPE_BITSHIFT 1
#define MCPR_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
#define MCPR_CPU_LAST_BRANCH_ADDR_TYPE_JUMP_BITSHIFT 1
#define MCPR_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
#define MCPR_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH_BITSHIFT 1
#define MCPR_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
#define MCPR_CPU_LAST_BRANCH_ADDR_LBA_BITSHIFT 2
#define MCP_REG_MCPR_CPU_UNUSED_E 0x8504c //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_CPU_UNUSED_E_COUNT 109
#define MCP_REG_MCPR_CPU_REG_FILE 0x85200 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_CPU_REG_FILE_COUNT 32
#define MCP_REG_MCPR_UNUSED_C 0x85280 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED_C_COUNT 64
#define MCP_REG_MCPR_HMCPQ 0x85380 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_HMCPQ_COUNT 4
#define MCP_REG_MCPR_UNUSED1 0x85390 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED1_COUNT 10
#define MCP_REG_MCPR_HMCPQ_FTQ_CMD 0x853b8 //ACCESS:?? DataWidth:0x20
#define MCPR_HMCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
#define MCPR_HMCPQ_FTQ_CMD_OFFSET_BITSHIFT 0
#define MCPR_HMCPQ_FTQ_CMD_WR_TOP (1L<<10)
#define MCPR_HMCPQ_FTQ_CMD_WR_TOP_BITSHIFT 10
#define MCPR_HMCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
#define MCPR_HMCPQ_FTQ_CMD_WR_TOP_0_BITSHIFT 10
#define MCPR_HMCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
#define MCPR_HMCPQ_FTQ_CMD_WR_TOP_1_BITSHIFT 10
#define MCPR_HMCPQ_FTQ_CMD_SFT_RESET (1L<<25)
#define MCPR_HMCPQ_FTQ_CMD_SFT_RESET_BITSHIFT 25
#define MCPR_HMCPQ_FTQ_CMD_RD_DATA (1L<<26)
#define MCPR_HMCPQ_FTQ_CMD_RD_DATA_BITSHIFT 26
#define MCPR_HMCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
#define MCPR_HMCPQ_FTQ_CMD_ADD_INTERVEN_BITSHIFT 27
#define MCPR_HMCPQ_FTQ_CMD_ADD_DATA (1L<<28)
#define MCPR_HMCPQ_FTQ_CMD_ADD_DATA_BITSHIFT 28
#define MCPR_HMCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
#define MCPR_HMCPQ_FTQ_CMD_INTERVENE_CLR_BITSHIFT 29
#define MCPR_HMCPQ_FTQ_CMD_POP (1L<<30)
#define MCPR_HMCPQ_FTQ_CMD_POP_BITSHIFT 30
#define MCPR_HMCPQ_FTQ_CMD_BUSY (1L<<31)
#define MCPR_HMCPQ_FTQ_CMD_BUSY_BITSHIFT 31
#define MCP_REG_MCPR_HMCPQ_FTQ_CTL 0x853bc //ACCESS:?? DataWidth:0x20
#define MCPR_HMCPQ_FTQ_CTL_INTERVENE (1L<<0)
#define MCPR_HMCPQ_FTQ_CTL_INTERVENE_BITSHIFT 0
#define MCPR_HMCPQ_FTQ_CTL_OVERFLOW (1L<<1)
#define MCPR_HMCPQ_FTQ_CTL_OVERFLOW_BITSHIFT 1
#define MCPR_HMCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
#define MCPR_HMCPQ_FTQ_CTL_FORCE_INTERVENE_BITSHIFT 2
#define MCPR_HMCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
#define MCPR_HMCPQ_FTQ_CTL_MAX_DEPTH_BITSHIFT 12
#define MCPR_HMCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
#define MCPR_HMCPQ_FTQ_CTL_CUR_DEPTH_BITSHIFT 22
#define MCP_REG_MCPR_MCPQ 0x853c0 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_MCPQ_COUNT 4
#define MCP_REG_MCPR_UNUSED2 0x853d0 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED2_COUNT 10
#define MCP_REG_MCPR_MCPQ_FTQ_CMD 0x853f8 //ACCESS:?? DataWidth:0x20
#define MCPR_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
#define MCPR_MCPQ_FTQ_CMD_OFFSET_BITSHIFT 0
#define MCPR_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
#define MCPR_MCPQ_FTQ_CMD_WR_TOP_BITSHIFT 10
#define MCPR_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
#define MCPR_MCPQ_FTQ_CMD_WR_TOP_0_BITSHIFT 10
#define MCPR_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
#define MCPR_MCPQ_FTQ_CMD_WR_TOP_1_BITSHIFT 10
#define MCPR_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
#define MCPR_MCPQ_FTQ_CMD_SFT_RESET_BITSHIFT 25
#define MCPR_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
#define MCPR_MCPQ_FTQ_CMD_RD_DATA_BITSHIFT 26
#define MCPR_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
#define MCPR_MCPQ_FTQ_CMD_ADD_INTERVEN_BITSHIFT 27
#define MCPR_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
#define MCPR_MCPQ_FTQ_CMD_ADD_DATA_BITSHIFT 28
#define MCPR_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
#define MCPR_MCPQ_FTQ_CMD_INTERVENE_CLR_BITSHIFT 29
#define MCPR_MCPQ_FTQ_CMD_POP (1L<<30)
#define MCPR_MCPQ_FTQ_CMD_POP_BITSHIFT 30
#define MCPR_MCPQ_FTQ_CMD_BUSY (1L<<31)
#define MCPR_MCPQ_FTQ_CMD_BUSY_BITSHIFT 31
#define MCP_REG_MCPR_MCPQ_FTQ_CTL 0x853fc //ACCESS:?? DataWidth:0x20
#define MCPR_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
#define MCPR_MCPQ_FTQ_CTL_INTERVENE_BITSHIFT 0
#define MCPR_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
#define MCPR_MCPQ_FTQ_CTL_OVERFLOW_BITSHIFT 1
#define MCPR_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
#define MCPR_MCPQ_FTQ_CTL_FORCE_INTERVENE_BITSHIFT 2
#define MCPR_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
#define MCPR_MCPQ_FTQ_CTL_MAX_DEPTH_BITSHIFT 12
#define MCPR_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
#define MCPR_MCPQ_FTQ_CTL_CUR_DEPTH_BITSHIFT 22
#define MCP_REG_MCPR_UNUSED_D 0x85400 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED_D_COUNT 42
#define MCP_REG_MCPR_MDIO_AUTO_POLL 0x854a8 //ACCESS:?? DataWidth:0x20
#define MCPR_MDIO_AUTO_POLL_DATA_MASK (0xffffL<<0)
#define MCPR_MDIO_AUTO_POLL_DATA_MASK_BITSHIFT 0
#define MCPR_MDIO_AUTO_POLL_REG_ADDR (0xffffL<<16)
#define MCPR_MDIO_AUTO_POLL_REG_ADDR_BITSHIFT 16
#define MCP_REG_MCPR_MDIO_COMM 0x854ac //ACCESS:?? DataWidth:0x20
#define MCPR_MDIO_COMM_DATA (0xffffL<<0)
#define MCPR_MDIO_COMM_DATA_BITSHIFT 0
#define MCPR_MDIO_COMM_REG_ADDR (0x1fL<<16)
#define MCPR_MDIO_COMM_REG_ADDR_BITSHIFT 16
#define MCPR_MDIO_COMM_PHY_ADDR (0x1fL<<21)
#define MCPR_MDIO_COMM_PHY_ADDR_BITSHIFT 21
#define MCPR_MDIO_COMM_COMMAND (0x3L<<26)
#define MCPR_MDIO_COMM_COMMAND_BITSHIFT 26
#define MCPR_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
#define MCPR_MDIO_COMM_COMMAND_UNDEFINED_0_BITSHIFT 26
#define MCPR_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
#define MCPR_MDIO_COMM_COMMAND_ADDRESS_BITSHIFT 26
#define MCPR_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
#define MCPR_MDIO_COMM_COMMAND_WRITE_22_BITSHIFT 26
#define MCPR_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
#define MCPR_MDIO_COMM_COMMAND_WRITE_45_BITSHIFT 26
#define MCPR_MDIO_COMM_COMMAND_READ_22 (2L<<26)
#define MCPR_MDIO_COMM_COMMAND_READ_22_BITSHIFT 26
#define MCPR_MDIO_COMM_COMMAND_READ_INC_45 (2L<<26)
#define MCPR_MDIO_COMM_COMMAND_READ_INC_45_BITSHIFT 26
#define MCPR_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
#define MCPR_MDIO_COMM_COMMAND_UNDEFINED_3_BITSHIFT 26
#define MCPR_MDIO_COMM_COMMAND_READ_45 (3L<<26)
#define MCPR_MDIO_COMM_COMMAND_READ_45_BITSHIFT 26
#define MCPR_MDIO_COMM_FAIL (1L<<28)
#define MCPR_MDIO_COMM_FAIL_BITSHIFT 28
#define MCPR_MDIO_COMM_START_BUSY (1L<<29)
#define MCPR_MDIO_COMM_START_BUSY_BITSHIFT 29
#define MCP_REG_MCPR_MDIO_STATUS 0x854b0 //ACCESS:?? DataWidth:0x20
#define MCPR_MDIO_STATUS_LINK (1L<<0)
#define MCPR_MDIO_STATUS_LINK_BITSHIFT 0
#define MCPR_MDIO_STATUS_10MB (1L<<1)
#define MCPR_MDIO_STATUS_10MB_BITSHIFT 1
#define MCP_REG_MCPR_MDIO_MODE 0x854b4 //ACCESS:?? DataWidth:0x20
#define MCPR_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
#define MCPR_MDIO_MODE_SHORT_PREAMBLE_BITSHIFT 1
#define MCPR_MDIO_MODE_AUTO_POLL (1L<<4)
#define MCPR_MDIO_MODE_AUTO_POLL_BITSHIFT 4
#define MCPR_MDIO_MODE_BIT_BANG (1L<<8)
#define MCPR_MDIO_MODE_BIT_BANG_BITSHIFT 8
#define MCPR_MDIO_MODE_MDIO (1L<<9)
#define MCPR_MDIO_MODE_MDIO_BITSHIFT 9
#define MCPR_MDIO_MODE_MDIO_OE (1L<<10)
#define MCPR_MDIO_MODE_MDIO_OE_BITSHIFT 10
#define MCPR_MDIO_MODE_MDC (1L<<11)
#define MCPR_MDIO_MODE_MDC_BITSHIFT 11
#define MCPR_MDIO_MODE_MDINT (1L<<12)
#define MCPR_MDIO_MODE_MDINT_BITSHIFT 12
#define MCPR_MDIO_MODE_EXT_MDINT (1L<<13)
#define MCPR_MDIO_MODE_EXT_MDINT_BITSHIFT 13
#define MCPR_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
#define MCPR_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
#define MCPR_MDIO_MODE_CLAUSE_45 (1L<<31)
#define MCPR_MDIO_MODE_CLAUSE_45_BITSHIFT 31
#define MCP_REG_MCPR_MDIO_AUTO_STATUS 0x854b8 //ACCESS:?? DataWidth:0x20
#define MCPR_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
#define MCPR_MDIO_AUTO_STATUS_AUTO_ERR_BITSHIFT 0
#define MCP_REG_MCPR_UNUSED_F 0x854bc //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED_F_COUNT 209
#define MCP_REG_MCPR_UCINT_WARP_MODE 0x85800 //ACCESS:?? DataWidth:0x20
#define MCPR_UCINT_WARP_MODE_ACCESS_MODE (0x3L<<0)
#define MCPR_UCINT_WARP_MODE_ACCESS_MODE_BITSHIFT 0
#define MCPR_UCINT_WARP_MODE_ACCESS_MODE_MDIO (0L<<0)
#define MCPR_UCINT_WARP_MODE_ACCESS_MODE_MDIO_BITSHIFT 0
#define MCPR_UCINT_WARP_MODE_ACCESS_MODE_BROADCAST_WRITE (1L<<0)
#define MCPR_UCINT_WARP_MODE_ACCESS_MODE_BROADCAST_WRITE_BITSHIFT 0
#define MCPR_UCINT_WARP_MODE_ACCESS_MODE_SPECIFIC_WRITE (2L<<0)
#define MCPR_UCINT_WARP_MODE_ACCESS_MODE_SPECIFIC_WRITE_BITSHIFT 0
#define MCPR_UCINT_WARP_MODE_ACCESS_MODE_SPECIFIC_READ (3L<<0)
#define MCPR_UCINT_WARP_MODE_ACCESS_MODE_SPECIFIC_READ_BITSHIFT 0
#define MCPR_UCINT_WARP_MODE_TARGET (0x3L<<4)
#define MCPR_UCINT_WARP_MODE_TARGET_BITSHIFT 4
#define MCPR_UCINT_WARP_MODE_BYTE_SWAP (1L<<8)
#define MCPR_UCINT_WARP_MODE_BYTE_SWAP_BITSHIFT 8
#define MCPR_UCINT_WARP_MODE_BYTE_SWAP_LITTLE_ENDIAN (0L<<8)
#define MCPR_UCINT_WARP_MODE_BYTE_SWAP_LITTLE_ENDIAN_BITSHIFT 8
#define MCPR_UCINT_WARP_MODE_BYTE_SWAP_BIG_ENDIAN (1L<<8)
#define MCPR_UCINT_WARP_MODE_BYTE_SWAP_BIG_ENDIAN_BITSHIFT 8
#define MCPR_UCINT_WARP_MODE_DUMMY_CYCLES (0xffL<<16)
#define MCPR_UCINT_WARP_MODE_DUMMY_CYCLES_BITSHIFT 16
#define MCP_REG_MCPR_UCINT_WARP_CLK_DIV 0x85804 //ACCESS:?? DataWidth:0x20
#define MCPR_UCINT_WARP_CLK_DIV_CLOCK_RATE (0x3L<<0)
#define MCPR_UCINT_WARP_CLK_DIV_CLOCK_RATE_BITSHIFT 0
#define MCPR_UCINT_WARP_CLK_DIV_CLOCK_RATE_DIVIDE_BY_4 (0L<<0)
#define MCPR_UCINT_WARP_CLK_DIV_CLOCK_RATE_DIVIDE_BY_4_BITSHIFT 0
#define MCPR_UCINT_WARP_CLK_DIV_CLOCK_RATE_DIVIDE_BY_8 (1L<<0)
#define MCPR_UCINT_WARP_CLK_DIV_CLOCK_RATE_DIVIDE_BY_8_BITSHIFT 0
#define MCPR_UCINT_WARP_CLK_DIV_CLOCK_RATE_DIVIDE_BY_16 (2L<<0)
#define MCPR_UCINT_WARP_CLK_DIV_CLOCK_RATE_DIVIDE_BY_16_BITSHIFT 0
#define MCP_REG_MCPR_UCINT_WARP_ADDRESS 0x85808 //ACCESS:?? DataWidth:0x20
#define MCPR_UCINT_WARP_ADDRESS_ADDRESS (0xffffL<<0)
#define MCPR_UCINT_WARP_ADDRESS_ADDRESS_BITSHIFT 0
#define MCP_REG_MCPR_UCINT_WARP_DATA 0x8580c //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UCINT_WARP_TARGET_ENABLE 0x85810 //ACCESS:?? DataWidth:0x20
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_SET0 (1L<<0)
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_SET0_BITSHIFT 0
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_SET1 (1L<<1)
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_SET1_BITSHIFT 1
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_SET2 (1L<<2)
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_SET2_BITSHIFT 2
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_CLR0 (1L<<8)
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_CLR0_BITSHIFT 8
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_CLR1 (1L<<9)
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_CLR1_BITSHIFT 9
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_CLR2 (1L<<10)
#define MCPR_UCINT_WARP_TARGET_ENABLE_EN_CLR2_BITSHIFT 10
#define MCPR_UCINT_WARP_TARGET_ENABLE_UC_ENABLE0 (1L<<16)
#define MCPR_UCINT_WARP_TARGET_ENABLE_UC_ENABLE0_BITSHIFT 16
#define MCPR_UCINT_WARP_TARGET_ENABLE_UC_ENABLE1 (1L<<17)
#define MCPR_UCINT_WARP_TARGET_ENABLE_UC_ENABLE1_BITSHIFT 17
#define MCPR_UCINT_WARP_TARGET_ENABLE_UC_ENABLE2 (1L<<18)
#define MCPR_UCINT_WARP_TARGET_ENABLE_UC_ENABLE2_BITSHIFT 18
#define MCP_REG_MCPR_UCINT_PCIE_MODE 0x85814 //ACCESS:?? DataWidth:0x20
#define MCPR_UCINT_PCIE_MODE_ACCESS_MODE (0x3L<<0)
#define MCPR_UCINT_PCIE_MODE_ACCESS_MODE_BITSHIFT 0
#define MCPR_UCINT_PCIE_MODE_ACCESS_MODE_MDIO (0L<<0)
#define MCPR_UCINT_PCIE_MODE_ACCESS_MODE_MDIO_BITSHIFT 0
#define MCPR_UCINT_PCIE_MODE_ACCESS_MODE_BROADCAST_WRITE (1L<<0)
#define MCPR_UCINT_PCIE_MODE_ACCESS_MODE_BROADCAST_WRITE_BITSHIFT 0
#define MCPR_UCINT_PCIE_MODE_ACCESS_MODE_SPECIFIC_WRITE (2L<<0)
#define MCPR_UCINT_PCIE_MODE_ACCESS_MODE_SPECIFIC_WRITE_BITSHIFT 0
#define MCPR_UCINT_PCIE_MODE_ACCESS_MODE_SPECIFIC_READ (3L<<0)
#define MCPR_UCINT_PCIE_MODE_ACCESS_MODE_SPECIFIC_READ_BITSHIFT 0
#define MCPR_UCINT_PCIE_MODE_TARGET (0x3L<<4)
#define MCPR_UCINT_PCIE_MODE_TARGET_BITSHIFT 4
#define MCPR_UCINT_PCIE_MODE_BYTE_SWAP (1L<<8)
#define MCPR_UCINT_PCIE_MODE_BYTE_SWAP_BITSHIFT 8
#define MCPR_UCINT_PCIE_MODE_BYTE_SWAP_LITTLE_ENDIAN (0L<<8)
#define MCPR_UCINT_PCIE_MODE_BYTE_SWAP_LITTLE_ENDIAN_BITSHIFT 8
#define MCPR_UCINT_PCIE_MODE_BYTE_SWAP_BIG_ENDIAN (1L<<8)
#define MCPR_UCINT_PCIE_MODE_BYTE_SWAP_BIG_ENDIAN_BITSHIFT 8
#define MCPR_UCINT_PCIE_MODE_DUMMY_CYCLES (0xffL<<16)
#define MCPR_UCINT_PCIE_MODE_DUMMY_CYCLES_BITSHIFT 16
#define MCP_REG_MCPR_UCINT_PCIE_CLK_DIV 0x85818 //ACCESS:?? DataWidth:0x20
#define MCPR_UCINT_PCIE_CLK_DIV_CLOCK_RATE (0x3L<<0)
#define MCPR_UCINT_PCIE_CLK_DIV_CLOCK_RATE_BITSHIFT 0
#define MCPR_UCINT_PCIE_CLK_DIV_CLOCK_RATE_DIVIDE_BY_4 (0L<<0)
#define MCPR_UCINT_PCIE_CLK_DIV_CLOCK_RATE_DIVIDE_BY_4_BITSHIFT 0
#define MCPR_UCINT_PCIE_CLK_DIV_CLOCK_RATE_DIVIDE_BY_8 (1L<<0)
#define MCPR_UCINT_PCIE_CLK_DIV_CLOCK_RATE_DIVIDE_BY_8_BITSHIFT 0
#define MCPR_UCINT_PCIE_CLK_DIV_CLOCK_RATE_DIVIDE_BY_16 (2L<<0)
#define MCPR_UCINT_PCIE_CLK_DIV_CLOCK_RATE_DIVIDE_BY_16_BITSHIFT 0
#define MCP_REG_MCPR_UCINT_PCIE_ADDRESS 0x8581c //ACCESS:?? DataWidth:0x20
#define MCPR_UCINT_PCIE_ADDRESS_ADDRESS (0xffffL<<0)
#define MCPR_UCINT_PCIE_ADDRESS_ADDRESS_BITSHIFT 0
#define MCP_REG_MCPR_UCINT_PCIE_DATA 0x85820 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UCINT_PCIE_TARGET_ENABLE 0x85824 //ACCESS:?? DataWidth:0x20
#define MCPR_UCINT_PCIE_TARGET_ENABLE_EN_SET0 (1L<<0)
#define MCPR_UCINT_PCIE_TARGET_ENABLE_EN_SET0_BITSHIFT 0
#define MCPR_UCINT_PCIE_TARGET_ENABLE_EN_SET1 (1L<<1)
#define MCPR_UCINT_PCIE_TARGET_ENABLE_EN_SET1_BITSHIFT 1
#define MCPR_UCINT_PCIE_TARGET_ENABLE_EN_CLR0 (1L<<8)
#define MCPR_UCINT_PCIE_TARGET_ENABLE_EN_CLR0_BITSHIFT 8
#define MCPR_UCINT_PCIE_TARGET_ENABLE_EN_CLR1 (1L<<9)
#define MCPR_UCINT_PCIE_TARGET_ENABLE_EN_CLR1_BITSHIFT 9
#define MCPR_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE0 (1L<<16)
#define MCPR_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE0_BITSHIFT 16
#define MCPR_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE1 (1L<<17)
#define MCPR_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE1_BITSHIFT 17
#define MCP_REG_MCPR_UNUSED_G 0x85828 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED_G_COUNT 54
#define MCP_REG_MCPR_IMC_COMMAND 0x85900 //ACCESS:?? DataWidth:0x20
#define MCPR_IMC_COMMAND_TRANSFER_COUNT (0x1fL<<0)
#define MCPR_IMC_COMMAND_TRANSFER_COUNT_BITSHIFT 0
#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS (0xfL<<8)
#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
#define MCPR_IMC_COMMAND_IMC_STATUS (0x3L<<16)
#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
#define MCPR_IMC_COMMAND_OPERATION (0x3L<<28)
#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
#define MCPR_IMC_COMMAND_ENABLE_BITSHIFT 31
#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904 //ACCESS:?? DataWidth:0x20
#define MCPR_IMC_SLAVE_CONTROL_SLAVE_ADDRESS (0xffL<<0)
#define MCPR_IMC_SLAVE_CONTROL_SLAVE_ADDRESS_BITSHIFT 0
#define MCPR_IMC_SLAVE_CONTROL_SLAVE_DEVICE_ID (0x7fL<<17)
#define MCPR_IMC_SLAVE_CONTROL_SLAVE_DEVICE_ID_BITSHIFT 17
#define MCP_REG_MCPR_IMC_RESERVED0 0x85908 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_IMC_RESERVED1 0x8590c //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_IMC_RESERVED2 0x85910 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_IMC_TIMING0 0x85914 //ACCESS:?? DataWidth:0x20
#define MCPR_IMC_TIMING0_SCL_LOW_PERIOD (0x7ffL<<0)
#define MCPR_IMC_TIMING0_SCL_LOW_PERIOD_BITSHIFT 0
#define MCPR_IMC_TIMING0_SCL_HIGH_PERIOD (0x7ffL<<16)
#define MCPR_IMC_TIMING0_SCL_HIGH_PERIOD_BITSHIFT 16
#define MCP_REG_MCPR_IMC_TIMING1 0x85918 //ACCESS:?? DataWidth:0x20
#define MCPR_IMC_TIMING1_START_TO_SCL_LOW (0x7ffL<<0)
#define MCPR_IMC_TIMING1_START_TO_SCL_LOW_BITSHIFT 0
#define MCPR_IMC_TIMING1_DATA_HOLD_TIME (0x7ffL<<16)
#define MCPR_IMC_TIMING1_DATA_HOLD_TIME_BITSHIFT 16
#define MCP_REG_MCPR_IMC_TIMING2 0x8591c //ACCESS:?? DataWidth:0x20
#define MCPR_IMC_TIMING2_STOP_TO_SDA_HIGH (0x7ffL<<0)
#define MCPR_IMC_TIMING2_STOP_TO_SDA_HIGH_BITSHIFT 0
#define MCPR_IMC_TIMING2_STOP_TO_START (0x7ffL<<16)
#define MCPR_IMC_TIMING2_STOP_TO_START_BITSHIFT 16
#define MCP_REG_MCPR_IMC_DATAREG0 0x85920 //ACCESS:?? DataWidth:0x20
#define MCPR_IMC_DATAREG0_DATA (0xffffffffL<<0)
#define MCPR_IMC_DATAREG0_DATA_BITSHIFT 0
#define MCP_REG_MCPR_IMC_DATAREG1 0x85924 //ACCESS:?? DataWidth:0x20
#define MCPR_IMC_DATAREG1_DATA (0xffffffffL<<0)
#define MCPR_IMC_DATAREG1_DATA_BITSHIFT 0
#define MCP_REG_MCPR_IMC_DATAREG2 0x85928 //ACCESS:?? DataWidth:0x20
#define MCPR_IMC_DATAREG2_DATA (0xffffffffL<<0)
#define MCPR_IMC_DATAREG2_DATA_BITSHIFT 0
#define MCP_REG_MCPR_IMC_DATAREG3 0x8592c //ACCESS:?? DataWidth:0x20
#define MCPR_IMC_DATAREG3_DATA (0xffffffffL<<0)
#define MCPR_IMC_DATAREG3_DATA_BITSHIFT 0
#define MCP_REG_MCPR_IMC_UNUSED 0x85930 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_IMC_UNUSED_COUNT 4
#define MCP_REG_MCPR_UNUSED_H 0x85940 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED_H_COUNT 688
#define MCP_REG_MCPR_NVM_COMMAND 0x86400 //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_COMMAND_RST (1L<<0)
#define MCPR_NVM_COMMAND_RST_BITSHIFT 0
#define MCPR_NVM_COMMAND_DONE (1L<<3)
#define MCPR_NVM_COMMAND_DONE_BITSHIFT 3
#define MCPR_NVM_COMMAND_DOIT (1L<<4)
#define MCPR_NVM_COMMAND_DOIT_BITSHIFT 4
#define MCPR_NVM_COMMAND_WR (1L<<5)
#define MCPR_NVM_COMMAND_WR_BITSHIFT 5
#define MCPR_NVM_COMMAND_ERASE (1L<<6)
#define MCPR_NVM_COMMAND_ERASE_BITSHIFT 6
#define MCPR_NVM_COMMAND_FIRST (1L<<7)
#define MCPR_NVM_COMMAND_FIRST_BITSHIFT 7
#define MCPR_NVM_COMMAND_LAST (1L<<8)
#define MCPR_NVM_COMMAND_LAST_BITSHIFT 8
#define MCPR_NVM_COMMAND_WREN (1L<<16)
#define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
#define MCPR_NVM_COMMAND_WRDI (1L<<17)
#define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
#define MCPR_NVM_COMMAND_RD_ID (1L<<20)
#define MCPR_NVM_COMMAND_RD_ID_BITSHIFT 20
#define MCPR_NVM_COMMAND_RD_STATUS (1L<<21)
#define MCPR_NVM_COMMAND_RD_STATUS_BITSHIFT 21
#define MCPR_NVM_COMMAND_MODE_256 (1L<<22)
#define MCPR_NVM_COMMAND_MODE_256_BITSHIFT 22
#define MCP_REG_MCPR_NVM_STATUS 0x86404 //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_STATUS_SPI_FSM_STATE (0x1fL<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE (0L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0 (1L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1 (2L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0 (3L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1 (4L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0 (5L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0 (6L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1 (7L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2 (8L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0 (9L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1 (10L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2 (11L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0 (12L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1 (13L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2 (14L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3 (15L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4 (16L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0 (17L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN (18L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_BITSHIFT 0
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT (19L<<0)
#define MCPR_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_BITSHIFT 0
#define MCP_REG_MCPR_NVM_WRITE 0x86408 //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_BITSHIFT 0
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG_BITSHIFT 0
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_SI (1L<<0)
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_SI_BITSHIFT 0
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_SO (2L<<0)
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_SO_BITSHIFT 0
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_CS_B (4L<<0)
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_CS_B_BITSHIFT 0
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_SCLK (8L<<0)
#define MCPR_NVM_WRITE_NVM_WRITE_VALUE_SCLK_BITSHIFT 0
#define MCP_REG_MCPR_NVM_ADDR 0x8640c //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_BITSHIFT 0
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG_BITSHIFT 0
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SI (1L<<0)
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SI_BITSHIFT 0
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SO (2L<<0)
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SO_BITSHIFT 0
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_CS_B (4L<<0)
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_CS_B_BITSHIFT 0
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SCLK (8L<<0)
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SCLK_BITSHIFT 0
#define MCP_REG_MCPR_NVM_READ 0x86410 //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
#define MCPR_NVM_READ_NVM_READ_VALUE_BITSHIFT 0
#define MCPR_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
#define MCPR_NVM_READ_NVM_READ_VALUE_BIT_BANG_BITSHIFT 0
#define MCPR_NVM_READ_NVM_READ_VALUE_SI (1L<<0)
#define MCPR_NVM_READ_NVM_READ_VALUE_SI_BITSHIFT 0
#define MCPR_NVM_READ_NVM_READ_VALUE_SO (2L<<0)
#define MCPR_NVM_READ_NVM_READ_VALUE_SO_BITSHIFT 0
#define MCPR_NVM_READ_NVM_READ_VALUE_CS_B (4L<<0)
#define MCPR_NVM_READ_NVM_READ_VALUE_CS_B_BITSHIFT 0
#define MCPR_NVM_READ_NVM_READ_VALUE_SCLK (8L<<0)
#define MCPR_NVM_READ_NVM_READ_VALUE_SCLK_BITSHIFT 0
#define MCP_REG_MCPR_NVM_CFG1 0x86414 //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_CFG1_FLASH_MODE (1L<<0)
#define MCPR_NVM_CFG1_FLASH_MODE_BITSHIFT 0
#define MCPR_NVM_CFG1_BUFFER_MODE (1L<<1)
#define MCPR_NVM_CFG1_BUFFER_MODE_BITSHIFT 1
#define MCPR_NVM_CFG1_PASS_MODE (1L<<2)
#define MCPR_NVM_CFG1_PASS_MODE_BITSHIFT 2
#define MCPR_NVM_CFG1_BITBANG_MODE (1L<<3)
#define MCPR_NVM_CFG1_BITBANG_MODE_BITSHIFT 3
#define MCPR_NVM_CFG1_STATUS_BIT (0x7L<<4)
#define MCPR_NVM_CFG1_STATUS_BIT_BITSHIFT 4
#define MCPR_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
#define MCPR_NVM_CFG1_SPI_CLK_DIV_BITSHIFT 7
#define MCPR_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
#define MCPR_NVM_CFG1_SEE_CLK_DIV_BITSHIFT 11
#define MCPR_NVM_CFG1_STRAP_CONTROL_0 (1L<<23)
#define MCPR_NVM_CFG1_STRAP_CONTROL_0_BITSHIFT 23
#define MCPR_NVM_CFG1_PROTECT_MODE (1L<<24)
#define MCPR_NVM_CFG1_PROTECT_MODE_BITSHIFT 24
#define MCPR_NVM_CFG1_FLASH_SIZE (1L<<25)
#define MCPR_NVM_CFG1_FLASH_SIZE_BITSHIFT 25
#define MCPR_NVM_CFG1_FW_USTRAP_1 (1L<<26)
#define MCPR_NVM_CFG1_FW_USTRAP_1_BITSHIFT 26
#define MCPR_NVM_CFG1_FW_USTRAP_0 (1L<<27)
#define MCPR_NVM_CFG1_FW_USTRAP_0_BITSHIFT 27
#define MCPR_NVM_CFG1_FW_USTRAP_2 (1L<<28)
#define MCPR_NVM_CFG1_FW_USTRAP_2_BITSHIFT 28
#define MCPR_NVM_CFG1_FW_USTRAP_3 (1L<<29)
#define MCPR_NVM_CFG1_FW_USTRAP_3_BITSHIFT 29
#define MCPR_NVM_CFG1_FW_FLASH_TYPE_EN (1L<<30)
#define MCPR_NVM_CFG1_FW_FLASH_TYPE_EN_BITSHIFT 30
#define MCPR_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
#define MCPR_NVM_CFG1_COMPAT_BYPASSS_BITSHIFT 31
#define MCP_REG_MCPR_NVM_CFG2 0x86418 //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_CFG2_ERASE_CMD (0xffL<<0)
#define MCPR_NVM_CFG2_ERASE_CMD_BITSHIFT 0
#define MCPR_NVM_CFG2_CSB_W (0xffL<<8)
#define MCPR_NVM_CFG2_CSB_W_BITSHIFT 8
#define MCPR_NVM_CFG2_STATUS_CMD (0xffL<<16)
#define MCPR_NVM_CFG2_STATUS_CMD_BITSHIFT 16
#define MCPR_NVM_CFG2_READ_ID (0xffL<<24)
#define MCPR_NVM_CFG2_READ_ID_BITSHIFT 24
#define MCP_REG_MCPR_NVM_CFG3 0x8641c //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
#define MCPR_NVM_CFG3_BUFFER_RD_CMD_BITSHIFT 0
#define MCPR_NVM_CFG3_WRITE_CMD (0xffL<<8)
#define MCPR_NVM_CFG3_WRITE_CMD_BITSHIFT 8
#define MCPR_NVM_CFG3_FAST_READ_CMD (0xffL<<16)
#define MCPR_NVM_CFG3_FAST_READ_CMD_BITSHIFT 16
#define MCPR_NVM_CFG3_READ_CMD (0xffL<<24)
#define MCPR_NVM_CFG3_READ_CMD_BITSHIFT 24
#define MCP_REG_MCPR_NVM_SW_ARB 0x86420 //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
#define MCPR_NVM_SW_ARB_ARB_REQ_SET0_BITSHIFT 0
#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
#define MCPR_NVM_SW_ARB_ARB_REQ_SET1_BITSHIFT 1
#define MCPR_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
#define MCPR_NVM_SW_ARB_ARB_REQ_SET2_BITSHIFT 2
#define MCPR_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
#define MCPR_NVM_SW_ARB_ARB_REQ_SET3_BITSHIFT 3
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR0_BITSHIFT 4
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1_BITSHIFT 5
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR2_BITSHIFT 6
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR3_BITSHIFT 7
#define MCPR_NVM_SW_ARB_ARB_ARB0 (1L<<8)
#define MCPR_NVM_SW_ARB_ARB_ARB0_BITSHIFT 8
#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
#define MCPR_NVM_SW_ARB_ARB_ARB1_BITSHIFT 9
#define MCPR_NVM_SW_ARB_ARB_ARB2 (1L<<10)
#define MCPR_NVM_SW_ARB_ARB_ARB2_BITSHIFT 10
#define MCPR_NVM_SW_ARB_ARB_ARB3 (1L<<11)
#define MCPR_NVM_SW_ARB_ARB_ARB3_BITSHIFT 11
#define MCPR_NVM_SW_ARB_REQ0 (1L<<12)
#define MCPR_NVM_SW_ARB_REQ0_BITSHIFT 12
#define MCPR_NVM_SW_ARB_REQ1 (1L<<13)
#define MCPR_NVM_SW_ARB_REQ1_BITSHIFT 13
#define MCPR_NVM_SW_ARB_REQ2 (1L<<14)
#define MCPR_NVM_SW_ARB_REQ2_BITSHIFT 14
#define MCPR_NVM_SW_ARB_REQ3 (1L<<15)
#define MCPR_NVM_SW_ARB_REQ3_BITSHIFT 15
#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424 //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
#define MCPR_NVM_ACCESS_ENABLE_EN_BITSHIFT 0
#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
#define MCPR_NVM_ACCESS_ENABLE_WR_EN_BITSHIFT 1
#define MCP_REG_MCPR_NVM_WRITE1 0x86428 //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_WRITE1_WREN_CMD (0xffL<<0)
#define MCPR_NVM_WRITE1_WREN_CMD_BITSHIFT 0
#define MCPR_NVM_WRITE1_WRDI_CMD (0xffL<<8)
#define MCPR_NVM_WRITE1_WRDI_CMD_BITSHIFT 8
#define MCP_REG_MCPR_NVM_CFG4 0x8642c //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
#define MCPR_NVM_CFG4_FLASH_SIZE_BITSHIFT 0
#define MCPR_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0)
#define MCPR_NVM_CFG4_FLASH_SIZE_1MBIT_BITSHIFT 0
#define MCPR_NVM_CFG4_FLASH_SIZE_2MBIT (1L<<0)
#define MCPR_NVM_CFG4_FLASH_SIZE_2MBIT_BITSHIFT 0
#define MCPR_NVM_CFG4_FLASH_SIZE_4MBIT (2L<<0)
#define MCPR_NVM_CFG4_FLASH_SIZE_4MBIT_BITSHIFT 0
#define MCPR_NVM_CFG4_FLASH_SIZE_8MBIT (3L<<0)
#define MCPR_NVM_CFG4_FLASH_SIZE_8MBIT_BITSHIFT 0
#define MCPR_NVM_CFG4_FLASH_SIZE_16MBIT (4L<<0)
#define MCPR_NVM_CFG4_FLASH_SIZE_16MBIT_BITSHIFT 0
#define MCPR_NVM_CFG4_FLASH_SIZE_32MBIT (5L<<0)
#define MCPR_NVM_CFG4_FLASH_SIZE_32MBIT_BITSHIFT 0
#define MCPR_NVM_CFG4_FLASH_SIZE_64MBIT (6L<<0)
#define MCPR_NVM_CFG4_FLASH_SIZE_64MBIT_BITSHIFT 0
#define MCPR_NVM_CFG4_FLASH_SIZE_128MBIT (7L<<0)
#define MCPR_NVM_CFG4_FLASH_SIZE_128MBIT_BITSHIFT 0
#define MCPR_NVM_CFG4_FLASH_VENDOR (1L<<3)
#define MCPR_NVM_CFG4_FLASH_VENDOR_BITSHIFT 3
#define MCPR_NVM_CFG4_FLASH_VENDOR_ST (0L<<3)
#define MCPR_NVM_CFG4_FLASH_VENDOR_ST_BITSHIFT 3
#define MCPR_NVM_CFG4_FLASH_VENDOR_ATMEL (1L<<3)
#define MCPR_NVM_CFG4_FLASH_VENDOR_ATMEL_BITSHIFT 3
#define MCPR_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3L<<4)
#define MCPR_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BITSHIFT 4
#define MCPR_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0L<<4)
#define MCPR_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8_BITSHIFT 4
#define MCPR_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1L<<4)
#define MCPR_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9_BITSHIFT 4
#define MCPR_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2L<<4)
#define MCPR_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10_BITSHIFT 4
#define MCPR_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3L<<4)
#define MCPR_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11_BITSHIFT 4
#define MCPR_NVM_CFG4_STATUS_BIT_POLARITY (1L<<6)
#define MCPR_NVM_CFG4_STATUS_BIT_POLARITY_BITSHIFT 6
#define MCPR_NVM_CFG4_FAST (1L<<7)
#define MCPR_NVM_CFG4_FAST_BITSHIFT 7
#define MCPR_NVM_CFG4_SI_INPUT_RELAXED_TIMING (1L<<8)
#define MCPR_NVM_CFG4_SI_INPUT_RELAXED_TIMING_BITSHIFT 8
#define MCPR_NVM_CFG4_PASS_MODE_RELAXED_TIMING (1L<<9)
#define MCPR_NVM_CFG4_PASS_MODE_RELAXED_TIMING_BITSHIFT 9
#define MCPR_NVM_CFG4_RESERVED (0x3fffffL<<10)
#define MCPR_NVM_CFG4_RESERVED_BITSHIFT 10
#define MCP_REG_MCPR_NVM_RECONFIG 0x86430 //ACCESS:?? DataWidth:0x20
#define MCPR_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfL<<0)
#define MCPR_NVM_RECONFIG_ORIG_STRAP_VALUE_BITSHIFT 0
#define MCPR_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0L<<0)
#define MCPR_NVM_RECONFIG_ORIG_STRAP_VALUE_ST_BITSHIFT 0
#define MCPR_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1L<<0)
#define MCPR_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL_BITSHIFT 0
#define MCPR_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfL<<4)
#define MCPR_NVM_RECONFIG_RECONFIG_STRAP_VALUE_BITSHIFT 4
#define MCPR_NVM_RECONFIG_RESERVED (0x7fffffL<<8)
#define MCPR_NVM_RECONFIG_RESERVED_BITSHIFT 8
#define MCPR_NVM_RECONFIG_RECONFIG_DONE (1L<<31)
#define MCPR_NVM_RECONFIG_RECONFIG_DONE_BITSHIFT 31
#define MCP_REG_MCPR_UNUSED3 0x86434 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED3_COUNT 243
#define MCP_REG_MCPR_ERNGN_EXP_ROM_CTRL 0x86800 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_EXP_ROM_CTRL_ENA (1L<<0)
#define MCPR_ERNGN_EXP_ROM_CTRL_ENA_BITSHIFT 0
#define MCPR_ERNGN_EXP_ROM_CTRL_BFRD (1L<<1)
#define MCPR_ERNGN_EXP_ROM_CTRL_BFRD_BITSHIFT 1
#define MCPR_ERNGN_EXP_ROM_CTRL_ARB_NUM (0x3L<<4)
#define MCPR_ERNGN_EXP_ROM_CTRL_ARB_NUM_BITSHIFT 4
#define MCPR_ERNGN_EXP_ROM_CTRL_STATE (0x3fL<<16)
#define MCPR_ERNGN_EXP_ROM_CTRL_STATE_BITSHIFT 16
#define MCPR_ERNGN_EXP_ROM_CTRL_CACHE_VALID (1L<<28)
#define MCPR_ERNGN_EXP_ROM_CTRL_CACHE_VALID_BITSHIFT 28
#define MCPR_ERNGN_EXP_ROM_CTRL_ARB_TIMEOUT (1L<<29)
#define MCPR_ERNGN_EXP_ROM_CTRL_ARB_TIMEOUT_BITSHIFT 29
#define MCPR_ERNGN_EXP_ROM_CTRL_READ_TIMEOUT (1L<<30)
#define MCPR_ERNGN_EXP_ROM_CTRL_READ_TIMEOUT_BITSHIFT 30
#define MCPR_ERNGN_EXP_ROM_CTRL_ACTIVE (1L<<31)
#define MCPR_ERNGN_EXP_ROM_CTRL_ACTIVE_BITSHIFT 31
#define MCP_REG_MCPR_ERNGN_EXP_ROM_BADDR 0x86804 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_EXP_ROM_BADDR_VALUE (0x3fffffL<<2)
#define MCPR_ERNGN_EXP_ROM_BADDR_VALUE_BITSHIFT 2
#define MCP_REG_MCPR_ERNGN_EXP_ROM_CFG 0x86808 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_EXP_ROM_CFG_ARB_TIMEOUT_SHFT (0xfL<<0)
#define MCPR_ERNGN_EXP_ROM_CFG_ARB_TIMEOUT_SHFT_BITSHIFT 0
#define MCPR_ERNGN_EXP_ROM_CFG_READ_TIMEOUT_SHFT (0xfL<<4)
#define MCPR_ERNGN_EXP_ROM_CFG_READ_TIMEOUT_SHFT_BITSHIFT 4
#define MCP_REG_MCPR_ERNGN_EXP_ROM_ADR 0x8680c //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_EXP_ROM_ADR_ADDRESS (0x3fffffL<<2)
#define MCPR_ERNGN_EXP_ROM_ADR_ADDRESS_BITSHIFT 2
#define MCPR_ERNGN_EXP_ROM_ADR_ADDR_SIZE (0x3L<<24)
#define MCPR_ERNGN_EXP_ROM_ADR_ADDR_SIZE_BITSHIFT 24
#define MCPR_ERNGN_EXP_ROM_ADR_ACT_FUNC (0x1fL<<26)
#define MCPR_ERNGN_EXP_ROM_ADR_ACT_FUNC_BITSHIFT 26
#define MCPR_ERNGN_EXP_ROM_ADR_REQ (1L<<31)
#define MCPR_ERNGN_EXP_ROM_ADR_REQ_BITSHIFT 31
#define MCP_REG_MCPR_ERNGN_EXP_ROM_DATA0 0x86810 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_ERNGN_EXP_ROM_DATA1 0x86814 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_ERNGN_EXP_ROM_DATA2 0x86818 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_ERNGN_IMG_LOADER0_BADDR 0x8681c //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER0_BADDR_VALUE (0x3fffffL<<2)
#define MCPR_ERNGN_IMG_LOADER0_BADDR_VALUE_BITSHIFT 2
#define MCP_REG_MCPR_ERNGN_IMG_LOADER0_GADDR 0x86820 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER0_GADDR_VALUE (0xfffffL<<2)
#define MCPR_ERNGN_IMG_LOADER0_GADDR_VALUE_BITSHIFT 2
#define MCP_REG_MCPR_ERNGN_IMG_LOADER0_CADDR 0x86824 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER0_CADDR_VALUE (0xfffffL<<2)
#define MCPR_ERNGN_IMG_LOADER0_CADDR_VALUE_BITSHIFT 2
#define MCP_REG_MCPR_ERNGN_IMG_LOADER0_CDATA 0x86828 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER0_CDATA_VALUE (0xffffffffL<<0)
#define MCPR_ERNGN_IMG_LOADER0_CDATA_VALUE_BITSHIFT 0
#define MCP_REG_MCPR_ERNGN_IMG_LOADER0_CFG 0x8682c //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER0_CFG_XFER_SIZE (0x3fffL<<2)
#define MCPR_ERNGN_IMG_LOADER0_CFG_XFER_SIZE_BITSHIFT 2
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE (0xfL<<20)
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_B0 (0L<<20)
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_B0_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_B1 (1L<<20)
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_B1_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_B2 (2L<<20)
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_B2_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_B3 (3L<<20)
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_B3_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_B4 (4L<<20)
#define MCPR_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_B4_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER0_CFG_AUTO_INC (1L<<24)
#define MCPR_ERNGN_IMG_LOADER0_CFG_AUTO_INC_BITSHIFT 24
#define MCPR_ERNGN_IMG_LOADER0_CFG_ARB_TO (1L<<28)
#define MCPR_ERNGN_IMG_LOADER0_CFG_ARB_TO_BITSHIFT 28
#define MCPR_ERNGN_IMG_LOADER0_CFG_READ_TO (1L<<29)
#define MCPR_ERNGN_IMG_LOADER0_CFG_READ_TO_BITSHIFT 29
#define MCPR_ERNGN_IMG_LOADER0_CFG_BUSY (1L<<30)
#define MCPR_ERNGN_IMG_LOADER0_CFG_BUSY_BITSHIFT 30
#define MCPR_ERNGN_IMG_LOADER0_CFG_ACTIVE (1L<<31)
#define MCPR_ERNGN_IMG_LOADER0_CFG_ACTIVE_BITSHIFT 31
#define MCP_REG_MCPR_ERNGN_IMG_LOADER1_BADDR 0x86830 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER1_BADDR_VALUE (0x3fffffL<<2)
#define MCPR_ERNGN_IMG_LOADER1_BADDR_VALUE_BITSHIFT 2
#define MCP_REG_MCPR_ERNGN_IMG_LOADER1_GADDR 0x86834 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER1_GADDR_VALUE (0xfffffL<<2)
#define MCPR_ERNGN_IMG_LOADER1_GADDR_VALUE_BITSHIFT 2
#define MCP_REG_MCPR_ERNGN_IMG_LOADER1_CADDR 0x86838 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER1_CADDR_VALUE (0xfffffL<<2)
#define MCPR_ERNGN_IMG_LOADER1_CADDR_VALUE_BITSHIFT 2
#define MCP_REG_MCPR_ERNGN_IMG_LOADER1_CDATA 0x8683c //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER1_CDATA_VALUE (0xffffffffL<<0)
#define MCPR_ERNGN_IMG_LOADER1_CDATA_VALUE_BITSHIFT 0
#define MCP_REG_MCPR_ERNGN_IMG_LOADER1_CFG 0x86840 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER1_CFG_XFER_SIZE (0x3fffL<<2)
#define MCPR_ERNGN_IMG_LOADER1_CFG_XFER_SIZE_BITSHIFT 2
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE (0xfL<<20)
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_B0 (0L<<20)
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_B0_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_B1 (1L<<20)
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_B1_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_B2 (2L<<20)
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_B2_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_B3 (3L<<20)
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_B3_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_B4 (4L<<20)
#define MCPR_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_B4_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER1_CFG_AUTO_INC (1L<<24)
#define MCPR_ERNGN_IMG_LOADER1_CFG_AUTO_INC_BITSHIFT 24
#define MCPR_ERNGN_IMG_LOADER1_CFG_ARB_TO (1L<<28)
#define MCPR_ERNGN_IMG_LOADER1_CFG_ARB_TO_BITSHIFT 28
#define MCPR_ERNGN_IMG_LOADER1_CFG_READ_TO (1L<<29)
#define MCPR_ERNGN_IMG_LOADER1_CFG_READ_TO_BITSHIFT 29
#define MCPR_ERNGN_IMG_LOADER1_CFG_BUSY (1L<<30)
#define MCPR_ERNGN_IMG_LOADER1_CFG_BUSY_BITSHIFT 30
#define MCPR_ERNGN_IMG_LOADER1_CFG_ACTIVE (1L<<31)
#define MCPR_ERNGN_IMG_LOADER1_CFG_ACTIVE_BITSHIFT 31
#define MCP_REG_MCPR_ERNGN_IMG_LOADER2_BADDR 0x86844 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER2_BADDR_VALUE (0x3fffffL<<2)
#define MCPR_ERNGN_IMG_LOADER2_BADDR_VALUE_BITSHIFT 2
#define MCP_REG_MCPR_ERNGN_IMG_LOADER2_GADDR 0x86848 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER2_GADDR_VALUE (0xfffffL<<2)
#define MCPR_ERNGN_IMG_LOADER2_GADDR_VALUE_BITSHIFT 2
#define MCP_REG_MCPR_ERNGN_IMG_LOADER2_CADDR 0x8684c //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER2_CADDR_VALUE (0xfffffL<<2)
#define MCPR_ERNGN_IMG_LOADER2_CADDR_VALUE_BITSHIFT 2
#define MCP_REG_MCPR_ERNGN_IMG_LOADER2_CDATA 0x86850 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER2_CDATA_VALUE (0xffffffffL<<0)
#define MCPR_ERNGN_IMG_LOADER2_CDATA_VALUE_BITSHIFT 0
#define MCP_REG_MCPR_ERNGN_IMG_LOADER2_CFG 0x86854 //ACCESS:?? DataWidth:0x20
#define MCPR_ERNGN_IMG_LOADER2_CFG_XFER_SIZE (0x3fffL<<2)
#define MCPR_ERNGN_IMG_LOADER2_CFG_XFER_SIZE_BITSHIFT 2
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE (0xfL<<20)
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_B0 (0L<<20)
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_B0_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_B1 (1L<<20)
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_B1_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_B2 (2L<<20)
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_B2_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_B3 (3L<<20)
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_B3_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_B4 (4L<<20)
#define MCPR_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_B4_BITSHIFT 20
#define MCPR_ERNGN_IMG_LOADER2_CFG_AUTO_INC (1L<<24)
#define MCPR_ERNGN_IMG_LOADER2_CFG_AUTO_INC_BITSHIFT 24
#define MCPR_ERNGN_IMG_LOADER2_CFG_ARB_TO (1L<<28)
#define MCPR_ERNGN_IMG_LOADER2_CFG_ARB_TO_BITSHIFT 28
#define MCPR_ERNGN_IMG_LOADER2_CFG_READ_TO (1L<<29)
#define MCPR_ERNGN_IMG_LOADER2_CFG_READ_TO_BITSHIFT 29
#define MCPR_ERNGN_IMG_LOADER2_CFG_BUSY (1L<<30)
#define MCPR_ERNGN_IMG_LOADER2_CFG_BUSY_BITSHIFT 30
#define MCPR_ERNGN_IMG_LOADER2_CFG_ACTIVE (1L<<31)
#define MCPR_ERNGN_IMG_LOADER2_CFG_ACTIVE_BITSHIFT 31
#define MCP_REG_MCPR_ERNGN_UNUSED_ERNGN 0x86858 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_ERNGN_UNUSED_ERNGN_COUNT 10
#define MCP_REG_MCPR_UNUSED_E 0x86880 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED_E_COUNT 1504
#define MCP_REG_MCPR_SMBUS_CONFIG 0x88000 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR (1L<<7)
#define MCPR_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR_BITSHIFT 7
#define MCPR_SMBUS_CONFIG_ARP_EN0 (1L<<8)
#define MCPR_SMBUS_CONFIG_ARP_EN0_BITSHIFT 8
#define MCPR_SMBUS_CONFIG_ARP_EN1 (1L<<9)
#define MCPR_SMBUS_CONFIG_ARP_EN1_BITSHIFT 9
#define MCPR_SMBUS_CONFIG_MASTER_RTRY_CNT (0xfL<<16)
#define MCPR_SMBUS_CONFIG_MASTER_RTRY_CNT_BITSHIFT 16
#define MCPR_SMBUS_CONFIG_TIMESTAMP_CNT_EN (1L<<26)
#define MCPR_SMBUS_CONFIG_TIMESTAMP_CNT_EN_BITSHIFT 26
#define MCPR_SMBUS_CONFIG_PROMISCOUS_MODE (1L<<27)
#define MCPR_SMBUS_CONFIG_PROMISCOUS_MODE_BITSHIFT 27
#define MCPR_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0 (1L<<28)
#define MCPR_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0_BITSHIFT 28
#define MCPR_SMBUS_CONFIG_BIT_BANG_EN (1L<<29)
#define MCPR_SMBUS_CONFIG_BIT_BANG_EN_BITSHIFT 29
#define MCPR_SMBUS_CONFIG_SMB_EN (1L<<30)
#define MCPR_SMBUS_CONFIG_SMB_EN_BITSHIFT 30
#define MCPR_SMBUS_CONFIG_RESET (1L<<31)
#define MCPR_SMBUS_CONFIG_RESET_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_TIMING_CONFIG 0x88004 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME (0xffL<<8)
#define MCPR_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME_BITSHIFT 8
#define MCPR_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH (0xffL<<16)
#define MCPR_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH_BITSHIFT 16
#define MCPR_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH (0x7fL<<24)
#define MCPR_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH_BITSHIFT 24
#define MCPR_SMBUS_TIMING_CONFIG_MODE_400 (1L<<31)
#define MCPR_SMBUS_TIMING_CONFIG_MODE_400_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_ADDRESS 0x88008 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_ADDRESS_NIC_SMB_ADDR0 (0x7fL<<0)
#define MCPR_SMBUS_ADDRESS_NIC_SMB_ADDR0_BITSHIFT 0
#define MCPR_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0 (1L<<7)
#define MCPR_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0_BITSHIFT 7
#define MCPR_SMBUS_ADDRESS_NIC_SMB_ADDR1 (0x7fL<<8)
#define MCPR_SMBUS_ADDRESS_NIC_SMB_ADDR1_BITSHIFT 8
#define MCPR_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1 (1L<<15)
#define MCPR_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1_BITSHIFT 15
#define MCPR_SMBUS_ADDRESS_NIC_SMB_ADDR2 (0x7fL<<16)
#define MCPR_SMBUS_ADDRESS_NIC_SMB_ADDR2_BITSHIFT 16
#define MCPR_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2 (1L<<23)
#define MCPR_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2_BITSHIFT 23
#define MCPR_SMBUS_ADDRESS_NIC_SMB_ADDR3 (0x7fL<<24)
#define MCPR_SMBUS_ADDRESS_NIC_SMB_ADDR3_BITSHIFT 24
#define MCPR_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3 (1L<<31)
#define MCPR_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_MASTER_FIFO_CONTROL 0x8800c //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD (0x7fL<<8)
#define MCPR_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD_BITSHIFT 8
#define MCPR_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT (0x7fL<<16)
#define MCPR_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT_BITSHIFT 16
#define MCPR_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH (1L<<30)
#define MCPR_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH_BITSHIFT 30
#define MCPR_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH (1L<<31)
#define MCPR_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_SLAVE_FIFO_CONTROL 0x88010 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD (0x7fL<<8)
#define MCPR_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD_BITSHIFT 8
#define MCPR_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT (0x7fL<<16)
#define MCPR_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT_BITSHIFT 16
#define MCPR_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH (1L<<30)
#define MCPR_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH_BITSHIFT 30
#define MCPR_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH (1L<<31)
#define MCPR_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_BIT_BANG_CONTROL 0x88014 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN (1L<<28)
#define MCPR_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN_BITSHIFT 28
#define MCPR_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN (1L<<29)
#define MCPR_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN_BITSHIFT 29
#define MCPR_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN (1L<<30)
#define MCPR_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN_BITSHIFT 30
#define MCPR_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN (1L<<31)
#define MCPR_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_WATCHDOG 0x88018 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_WATCHDOG_WATCHDOG (0xffffL<<0)
#define MCPR_SMBUS_WATCHDOG_WATCHDOG_BITSHIFT 0
#define MCP_REG_MCPR_SMBUS_HEARTBEAT 0x8801c //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_HEARTBEAT_HEARTBEAT (0xffffL<<0)
#define MCPR_SMBUS_HEARTBEAT_HEARTBEAT_BITSHIFT 0
#define MCP_REG_MCPR_SMBUS_POLL_ASF 0x88020 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_POLL_ASF_POLL_ASF (0xffffL<<0)
#define MCPR_SMBUS_POLL_ASF_POLL_ASF_BITSHIFT 0
#define MCP_REG_MCPR_SMBUS_POLL_LEGACY 0x88024 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
#define MCPR_SMBUS_POLL_LEGACY_POLL_LEGACY_BITSHIFT 0
#define MCP_REG_MCPR_SMBUS_RETRAN 0x88028 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_RETRAN_RETRAN (0xffL<<0)
#define MCPR_SMBUS_RETRAN_RETRAN_BITSHIFT 0
#define MCP_REG_MCPR_SMBUS_TIMESTAMP 0x8802c //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
#define MCPR_SMBUS_TIMESTAMP_TIMESTAMP_BITSHIFT 0
#define MCP_REG_MCPR_SMBUS_MASTER_COMMAND 0x88030 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT (0xffL<<0)
#define MCPR_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT_BITSHIFT 0
#define MCPR_SMBUS_MASTER_COMMAND_PEC (1L<<8)
#define MCPR_SMBUS_MASTER_COMMAND_PEC_BITSHIFT 8
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL (0xfL<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0000 (0L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0000_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0001 (1L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0001_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0010 (2L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0010_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0011 (3L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0011_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0100 (4L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0100_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0101 (5L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0101_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0110 (6L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0110_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0111 (7L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0111_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1000 (8L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1000_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1001 (9L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1001_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1010 (10L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1010_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1011 (11L<<9)
#define MCPR_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1011_BITSHIFT 9
#define MCPR_SMBUS_MASTER_COMMAND_STATUS (0x7L<<25)
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_BITSHIFT 25
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_000 (0L<<25)
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_000_BITSHIFT 25
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_001 (1L<<25)
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_001_BITSHIFT 25
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_010 (2L<<25)
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_010_BITSHIFT 25
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_011 (3L<<25)
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_011_BITSHIFT 25
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_100 (4L<<25)
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_100_BITSHIFT 25
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_101 (5L<<25)
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_101_BITSHIFT 25
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_110 (6L<<25)
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_110_BITSHIFT 25
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_111 (7L<<25)
#define MCPR_SMBUS_MASTER_COMMAND_STATUS_111_BITSHIFT 25
#define MCPR_SMBUS_MASTER_COMMAND_ABORT (1L<<30)
#define MCPR_SMBUS_MASTER_COMMAND_ABORT_BITSHIFT 30
#define MCPR_SMBUS_MASTER_COMMAND_START_BUSY (1L<<31)
#define MCPR_SMBUS_MASTER_COMMAND_START_BUSY_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_SLAVE_COMMAND 0x88034 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_SLAVE_COMMAND_PEC (1L<<8)
#define MCPR_SMBUS_SLAVE_COMMAND_PEC_BITSHIFT 8
#define MCPR_SMBUS_SLAVE_COMMAND_STATUS (0x7L<<23)
#define MCPR_SMBUS_SLAVE_COMMAND_STATUS_BITSHIFT 23
#define MCPR_SMBUS_SLAVE_COMMAND_STATUS_000 (0L<<23)
#define MCPR_SMBUS_SLAVE_COMMAND_STATUS_000_BITSHIFT 23
#define MCPR_SMBUS_SLAVE_COMMAND_STATUS_101 (5L<<23)
#define MCPR_SMBUS_SLAVE_COMMAND_STATUS_101_BITSHIFT 23
#define MCPR_SMBUS_SLAVE_COMMAND_STATUS_111 (7L<<23)
#define MCPR_SMBUS_SLAVE_COMMAND_STATUS_111_BITSHIFT 23
#define MCPR_SMBUS_SLAVE_COMMAND_ABORT (1L<<30)
#define MCPR_SMBUS_SLAVE_COMMAND_ABORT_BITSHIFT 30
#define MCPR_SMBUS_SLAVE_COMMAND_START (1L<<31)
#define MCPR_SMBUS_SLAVE_COMMAND_START_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_EVENT_ENABLE 0x88038 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN (1L<<0)
#define MCPR_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN_BITSHIFT 0
#define MCPR_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN (1L<<1)
#define MCPR_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN_BITSHIFT 1
#define MCPR_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN (1L<<2)
#define MCPR_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN_BITSHIFT 2
#define MCPR_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN (1L<<3)
#define MCPR_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN_BITSHIFT 3
#define MCPR_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN (1L<<4)
#define MCPR_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN_BITSHIFT 4
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN (1L<<20)
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN_BITSHIFT 20
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN (1L<<21)
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN_BITSHIFT 21
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN (1L<<22)
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN_BITSHIFT 22
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN (1L<<23)
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN_BITSHIFT 23
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN (1L<<24)
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN_BITSHIFT 24
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN (1L<<25)
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN_BITSHIFT 25
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN (1L<<26)
#define MCPR_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN_BITSHIFT 26
#define MCPR_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN (1L<<27)
#define MCPR_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN_BITSHIFT 27
#define MCPR_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN (1L<<28)
#define MCPR_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN_BITSHIFT 28
#define MCPR_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN (1L<<29)
#define MCPR_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN_BITSHIFT 29
#define MCPR_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN (1L<<30)
#define MCPR_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN_BITSHIFT 30
#define MCPR_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN (1L<<31)
#define MCPR_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_EVENT_STATUS 0x8803c //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_EVENT_STATUS_WATCHDOG_TO (1L<<0)
#define MCPR_SMBUS_EVENT_STATUS_WATCHDOG_TO_BITSHIFT 0
#define MCPR_SMBUS_EVENT_STATUS_HEARTBEAT_TO (1L<<1)
#define MCPR_SMBUS_EVENT_STATUS_HEARTBEAT_TO_BITSHIFT 1
#define MCPR_SMBUS_EVENT_STATUS_POLL_ASF_TO (1L<<2)
#define MCPR_SMBUS_EVENT_STATUS_POLL_ASF_TO_BITSHIFT 2
#define MCPR_SMBUS_EVENT_STATUS_POLL_LEGACY_TO (1L<<3)
#define MCPR_SMBUS_EVENT_STATUS_POLL_LEGACY_TO_BITSHIFT 3
#define MCPR_SMBUS_EVENT_STATUS_RETRANSMIT_TO (1L<<4)
#define MCPR_SMBUS_EVENT_STATUS_RETRANSMIT_TO_BITSHIFT 4
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT (1L<<20)
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT_BITSHIFT 20
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT (1L<<21)
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT_BITSHIFT 21
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN (1L<<22)
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN_BITSHIFT 22
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_START_BUSY (1L<<23)
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_START_BUSY_BITSHIFT 23
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT (1L<<24)
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT_BITSHIFT 24
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT (1L<<25)
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT_BITSHIFT 25
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL (1L<<26)
#define MCPR_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL_BITSHIFT 26
#define MCPR_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN (1L<<27)
#define MCPR_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN_BITSHIFT 27
#define MCPR_SMBUS_EVENT_STATUS_MASTER_START_BUSY (1L<<28)
#define MCPR_SMBUS_EVENT_STATUS_MASTER_START_BUSY_BITSHIFT 28
#define MCPR_SMBUS_EVENT_STATUS_MASTER_RX_EVENT (1L<<29)
#define MCPR_SMBUS_EVENT_STATUS_MASTER_RX_EVENT_BITSHIFT 29
#define MCPR_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT (1L<<30)
#define MCPR_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT_BITSHIFT 30
#define MCPR_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL (1L<<31)
#define MCPR_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_MASTER_DATA_WRITE 0x88040 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA (0xffL<<0)
#define MCPR_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA_BITSHIFT 0
#define MCPR_SMBUS_MASTER_DATA_WRITE_WR_STATUS (1L<<31)
#define MCPR_SMBUS_MASTER_DATA_WRITE_WR_STATUS_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_MASTER_DATA_READ 0x88044 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA (0xffL<<0)
#define MCPR_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA_BITSHIFT 0
#define MCPR_SMBUS_MASTER_DATA_READ_PEC_ERR (1L<<29)
#define MCPR_SMBUS_MASTER_DATA_READ_PEC_ERR_BITSHIFT 29
#define MCPR_SMBUS_MASTER_DATA_READ_RD_STATUS (0x3L<<30)
#define MCPR_SMBUS_MASTER_DATA_READ_RD_STATUS_BITSHIFT 30
#define MCPR_SMBUS_MASTER_DATA_READ_RD_STATUS_00 (0L<<30)
#define MCPR_SMBUS_MASTER_DATA_READ_RD_STATUS_00_BITSHIFT 30
#define MCPR_SMBUS_MASTER_DATA_READ_RD_STATUS_01 (1L<<30)
#define MCPR_SMBUS_MASTER_DATA_READ_RD_STATUS_01_BITSHIFT 30
#define MCPR_SMBUS_MASTER_DATA_READ_RD_STATUS_10 (2L<<30)
#define MCPR_SMBUS_MASTER_DATA_READ_RD_STATUS_10_BITSHIFT 30
#define MCPR_SMBUS_MASTER_DATA_READ_RD_STATUS_11 (3L<<30)
#define MCPR_SMBUS_MASTER_DATA_READ_RD_STATUS_11_BITSHIFT 30
#define MCP_REG_MCPR_SMBUS_SLAVE_DATA_WRITE 0x88048 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA (0xffL<<0)
#define MCPR_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA_BITSHIFT 0
#define MCPR_SMBUS_SLAVE_DATA_WRITE_WR_STATUS (1L<<31)
#define MCPR_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_BITSHIFT 31
#define MCPR_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_0 (0L<<31)
#define MCPR_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_0_BITSHIFT 31
#define MCPR_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_1 (1L<<31)
#define MCPR_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_1_BITSHIFT 31
#define MCP_REG_MCPR_SMBUS_SLAVE_DATA_READ 0x8804c //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA (0xffL<<0)
#define MCPR_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA_BITSHIFT 0
#define MCPR_SMBUS_SLAVE_DATA_READ_ERR_STATUS (0x3L<<28)
#define MCPR_SMBUS_SLAVE_DATA_READ_ERR_STATUS_BITSHIFT 28
#define MCPR_SMBUS_SLAVE_DATA_READ_ERR_STATUS_00 (0L<<28)
#define MCPR_SMBUS_SLAVE_DATA_READ_ERR_STATUS_00_BITSHIFT 28
#define MCPR_SMBUS_SLAVE_DATA_READ_ERR_STATUS_01 (1L<<28)
#define MCPR_SMBUS_SLAVE_DATA_READ_ERR_STATUS_01_BITSHIFT 28
#define MCPR_SMBUS_SLAVE_DATA_READ_ERR_STATUS_10 (2L<<28)
#define MCPR_SMBUS_SLAVE_DATA_READ_ERR_STATUS_10_BITSHIFT 28
#define MCPR_SMBUS_SLAVE_DATA_READ_ERR_STATUS_11 (3L<<28)
#define MCPR_SMBUS_SLAVE_DATA_READ_ERR_STATUS_11_BITSHIFT 28
#define MCPR_SMBUS_SLAVE_DATA_READ_RD_STATUS (0x3L<<30)
#define MCPR_SMBUS_SLAVE_DATA_READ_RD_STATUS_BITSHIFT 30
#define MCPR_SMBUS_SLAVE_DATA_READ_RD_STATUS_00 (0L<<30)
#define MCPR_SMBUS_SLAVE_DATA_READ_RD_STATUS_00_BITSHIFT 30
#define MCPR_SMBUS_SLAVE_DATA_READ_RD_STATUS_01 (1L<<30)
#define MCPR_SMBUS_SLAVE_DATA_READ_RD_STATUS_01_BITSHIFT 30
#define MCPR_SMBUS_SLAVE_DATA_READ_RD_STATUS_10 (2L<<30)
#define MCPR_SMBUS_SLAVE_DATA_READ_RD_STATUS_10_BITSHIFT 30
#define MCPR_SMBUS_SLAVE_DATA_READ_RD_STATUS_11 (3L<<30)
#define MCPR_SMBUS_SLAVE_DATA_READ_RD_STATUS_11_BITSHIFT 30
#define MCP_REG_MCPR_UNUSED4 0x88050 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED4_COUNT 12
#define MCP_REG_MCPR_SMBUS_ARP_STATE 0x88080 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_ARP_STATE_AV_FLAG0 (1L<<0)
#define MCPR_SMBUS_ARP_STATE_AV_FLAG0_BITSHIFT 0
#define MCPR_SMBUS_ARP_STATE_AR_FLAG0 (1L<<1)
#define MCPR_SMBUS_ARP_STATE_AR_FLAG0_BITSHIFT 1
#define MCPR_SMBUS_ARP_STATE_AV_FLAG1 (1L<<4)
#define MCPR_SMBUS_ARP_STATE_AV_FLAG1_BITSHIFT 4
#define MCPR_SMBUS_ARP_STATE_AR_FLAG1 (1L<<5)
#define MCPR_SMBUS_ARP_STATE_AR_FLAG1_BITSHIFT 5
#define MCP_REG_MCPR_UNUSED5 0x88084 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED5_COUNT 3
#define MCP_REG_MCPR_SMBUS_UDID0_3 0x88090 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_UDID0_3_BYTE_12 (0xffL<<0)
#define MCPR_SMBUS_UDID0_3_BYTE_12_BITSHIFT 0
#define MCPR_SMBUS_UDID0_3_BYTE_13 (0xffL<<8)
#define MCPR_SMBUS_UDID0_3_BYTE_13_BITSHIFT 8
#define MCPR_SMBUS_UDID0_3_BYTE_14 (0xffL<<16)
#define MCPR_SMBUS_UDID0_3_BYTE_14_BITSHIFT 16
#define MCPR_SMBUS_UDID0_3_BYTE_15 (0xffL<<24)
#define MCPR_SMBUS_UDID0_3_BYTE_15_BITSHIFT 24
#define MCP_REG_MCPR_SMBUS_UDID0_2 0x88094 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_UDID0_2_BYTE_8 (0xffL<<0)
#define MCPR_SMBUS_UDID0_2_BYTE_8_BITSHIFT 0
#define MCPR_SMBUS_UDID0_2_BYTE_9 (0xffL<<8)
#define MCPR_SMBUS_UDID0_2_BYTE_9_BITSHIFT 8
#define MCPR_SMBUS_UDID0_2_BYTE_10 (0xffL<<16)
#define MCPR_SMBUS_UDID0_2_BYTE_10_BITSHIFT 16
#define MCPR_SMBUS_UDID0_2_BYTE_11 (0xffL<<24)
#define MCPR_SMBUS_UDID0_2_BYTE_11_BITSHIFT 24
#define MCP_REG_MCPR_SMBUS_UDID0_1 0x88098 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_UDID0_1_BYTE_4 (0xffL<<0)
#define MCPR_SMBUS_UDID0_1_BYTE_4_BITSHIFT 0
#define MCPR_SMBUS_UDID0_1_BYTE_5 (0xffL<<8)
#define MCPR_SMBUS_UDID0_1_BYTE_5_BITSHIFT 8
#define MCPR_SMBUS_UDID0_1_BYTE_6 (0xffL<<16)
#define MCPR_SMBUS_UDID0_1_BYTE_6_BITSHIFT 16
#define MCPR_SMBUS_UDID0_1_BYTE_7 (0xffL<<24)
#define MCPR_SMBUS_UDID0_1_BYTE_7_BITSHIFT 24
#define MCP_REG_MCPR_SMBUS_UDID0_0 0x8809c //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_UDID0_0_BYTE_0 (0xffL<<0)
#define MCPR_SMBUS_UDID0_0_BYTE_0_BITSHIFT 0
#define MCPR_SMBUS_UDID0_0_BYTE_1 (0xffL<<8)
#define MCPR_SMBUS_UDID0_0_BYTE_1_BITSHIFT 8
#define MCPR_SMBUS_UDID0_0_BYTE_2 (0xffL<<16)
#define MCPR_SMBUS_UDID0_0_BYTE_2_BITSHIFT 16
#define MCPR_SMBUS_UDID0_0_BYTE_3 (0xffL<<24)
#define MCPR_SMBUS_UDID0_0_BYTE_3_BITSHIFT 24
#define MCP_REG_MCPR_SMBUS_UDID1_3 0x880a0 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_UDID1_3_BYTE_12 (0xffL<<0)
#define MCPR_SMBUS_UDID1_3_BYTE_12_BITSHIFT 0
#define MCPR_SMBUS_UDID1_3_BYTE_13 (0xffL<<8)
#define MCPR_SMBUS_UDID1_3_BYTE_13_BITSHIFT 8
#define MCPR_SMBUS_UDID1_3_BYTE_14 (0xffL<<16)
#define MCPR_SMBUS_UDID1_3_BYTE_14_BITSHIFT 16
#define MCPR_SMBUS_UDID1_3_BYTE_15 (0xffL<<24)
#define MCPR_SMBUS_UDID1_3_BYTE_15_BITSHIFT 24
#define MCP_REG_MCPR_SMBUS_UDID1_2 0x880a4 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_UDID1_2_BYTE_8 (0xffL<<0)
#define MCPR_SMBUS_UDID1_2_BYTE_8_BITSHIFT 0
#define MCPR_SMBUS_UDID1_2_BYTE_9 (0xffL<<8)
#define MCPR_SMBUS_UDID1_2_BYTE_9_BITSHIFT 8
#define MCPR_SMBUS_UDID1_2_BYTE_10 (0xffL<<16)
#define MCPR_SMBUS_UDID1_2_BYTE_10_BITSHIFT 16
#define MCPR_SMBUS_UDID1_2_BYTE_11 (0xffL<<24)
#define MCPR_SMBUS_UDID1_2_BYTE_11_BITSHIFT 24
#define MCP_REG_MCPR_SMBUS_UDID1_1 0x880a8 //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_UDID1_1_BYTE_4 (0xffL<<0)
#define MCPR_SMBUS_UDID1_1_BYTE_4_BITSHIFT 0
#define MCPR_SMBUS_UDID1_1_BYTE_5 (0xffL<<8)
#define MCPR_SMBUS_UDID1_1_BYTE_5_BITSHIFT 8
#define MCPR_SMBUS_UDID1_1_BYTE_6 (0xffL<<16)
#define MCPR_SMBUS_UDID1_1_BYTE_6_BITSHIFT 16
#define MCPR_SMBUS_UDID1_1_BYTE_7 (0xffL<<24)
#define MCPR_SMBUS_UDID1_1_BYTE_7_BITSHIFT 24
#define MCP_REG_MCPR_SMBUS_UDID1_0 0x880ac //ACCESS:?? DataWidth:0x20
#define MCPR_SMBUS_UDID1_0_BYTE_0 (0xffL<<0)
#define MCPR_SMBUS_UDID1_0_BYTE_0_BITSHIFT 0
#define MCPR_SMBUS_UDID1_0_BYTE_1 (0xffL<<8)
#define MCPR_SMBUS_UDID1_0_BYTE_1_BITSHIFT 8
#define MCPR_SMBUS_UDID1_0_BYTE_2 (0xffL<<16)
#define MCPR_SMBUS_UDID1_0_BYTE_2_BITSHIFT 16
#define MCPR_SMBUS_UDID1_0_BYTE_3 (0xffL<<24)
#define MCPR_SMBUS_UDID1_0_BYTE_3_BITSHIFT 24
#define MCP_REG_MCPR_UNUSED6 0x880b0 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED6_COUNT 212
#define MCP_REG_MCPR_UNUSED7 0x88400 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED7_COUNT 256
#define MCP_REG_MCPR_LEGACY_UNUSED_LEGACY_SMB 0x88800 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_LEGACY_UNUSED_LEGACY_SMB_COUNT 9
#define MCP_REG_MCPR_UNUSED8 0x88824 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED8_COUNT 247
#define MCP_REG_MCPR_UNUSED9 0x88c00 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED9_COUNT 7424
#define MCP_REG_MCPR_ROM 0x90000 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_ROM_COUNT 320
#define MCP_REG_MCPR_UNUSED10 0x90500 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED10_COUNT 7872
#define MCP_REG_MCPR_UMP_UMP_CMD 0x98000 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_CMD_EGRESS_FIFO_ENABLED (1L<<0)
#define MCPR_UMP_UMP_CMD_EGRESS_FIFO_ENABLED_BITSHIFT 0
#define MCPR_UMP_UMP_CMD_INGRESS_FIFO_ENABLED (1L<<1)
#define MCPR_UMP_UMP_CMD_INGRESS_FIFO_ENABLED_BITSHIFT 1
#define MCPR_UMP_UMP_CMD_FC_EN (1L<<2)
#define MCPR_UMP_UMP_CMD_FC_EN_BITSHIFT 2
#define MCPR_UMP_UMP_CMD_MAC_LOOPBACK (1L<<3)
#define MCPR_UMP_UMP_CMD_MAC_LOOPBACK_BITSHIFT 3
#define MCPR_UMP_UMP_CMD_EGRESS_MAC_DISABLE (1L<<5)
#define MCPR_UMP_UMP_CMD_EGRESS_MAC_DISABLE_BITSHIFT 5
#define MCPR_UMP_UMP_CMD_INGRESS_MAC_DISABLE (1L<<6)
#define MCPR_UMP_UMP_CMD_INGRESS_MAC_DISABLE_BITSHIFT 6
#define MCPR_UMP_UMP_CMD_INGRESS_DRIVE (1L<<8)
#define MCPR_UMP_UMP_CMD_INGRESS_DRIVE_BITSHIFT 8
#define MCPR_UMP_UMP_CMD_SW_PAUSE (1L<<9)
#define MCPR_UMP_UMP_CMD_SW_PAUSE_BITSHIFT 9
#define MCPR_UMP_UMP_CMD_AUTO_DRIVE (1L<<13)
#define MCPR_UMP_UMP_CMD_AUTO_DRIVE_BITSHIFT 13
#define MCPR_UMP_UMP_CMD_INGRESS_RESET (1L<<14)
#define MCPR_UMP_UMP_CMD_INGRESS_RESET_BITSHIFT 14
#define MCPR_UMP_UMP_CMD_NO_PLUS_TWO (1L<<15)
#define MCPR_UMP_UMP_CMD_NO_PLUS_TWO_BITSHIFT 15
#define MCPR_UMP_UMP_CMD_EGRESS_PKT_FLUSH (1L<<16)
#define MCPR_UMP_UMP_CMD_EGRESS_PKT_FLUSH_BITSHIFT 16
#define MCPR_UMP_UMP_CMD_CMD_IPG (0x1fL<<17)
#define MCPR_UMP_UMP_CMD_CMD_IPG_BITSHIFT 17
#define MCPR_UMP_UMP_CMD_EGRESS_FIO_RESET (1L<<28)
#define MCPR_UMP_UMP_CMD_EGRESS_FIO_RESET_BITSHIFT 28
#define MCPR_UMP_UMP_CMD_INGRESS_FIO_RESET (1L<<29)
#define MCPR_UMP_UMP_CMD_INGRESS_FIO_RESET_BITSHIFT 29
#define MCPR_UMP_UMP_CMD_EGRESS_MAC_RESET (1L<<30)
#define MCPR_UMP_UMP_CMD_EGRESS_MAC_RESET_BITSHIFT 30
#define MCPR_UMP_UMP_CMD_INGRESS_MAC_RESET (1L<<31)
#define MCPR_UMP_UMP_CMD_INGRESS_MAC_RESET_BITSHIFT 31
#define MCP_REG_MCPR_UMP_UMP_CONFIG 0x98004 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_CONFIG_RMII_MODE (1L<<4)
#define MCPR_UMP_UMP_CONFIG_RMII_MODE_BITSHIFT 4
#define MCPR_UMP_UMP_CONFIG_RVMII_MODE (1L<<6)
#define MCPR_UMP_UMP_CONFIG_RVMII_MODE_BITSHIFT 6
#define MCPR_UMP_UMP_CONFIG_INGRESS_MODE (1L<<7)
#define MCPR_UMP_UMP_CONFIG_INGRESS_MODE_BITSHIFT 7
#define MCPR_UMP_UMP_CONFIG_INGRESS_WORD_ACCM (0xffL<<8)
#define MCPR_UMP_UMP_CONFIG_INGRESS_WORD_ACCM_BITSHIFT 8
#define MCPR_UMP_UMP_CONFIG_OLD_BCNT_RDY (1L<<24)
#define MCPR_UMP_UMP_CONFIG_OLD_BCNT_RDY_BITSHIFT 24
#define MCP_REG_MCPR_UMP_UMP_FC_TRIP 0x98008 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_FC_TRIP_XON_TRIP (0x1ffL<<0)
#define MCPR_UMP_UMP_FC_TRIP_XON_TRIP_BITSHIFT 0
#define MCPR_UMP_UMP_FC_TRIP_XOFF_TRIP (0x1ffL<<16)
#define MCPR_UMP_UMP_FC_TRIP_XOFF_TRIP_BITSHIFT 16
#define MCP_REG_MCPR_UMP_UNUSED_E 0x9800c //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UMP_UNUSED_E_COUNT 33
#define MCP_REG_MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS 0x98090 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_NEW_FRM (1L<<0)
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_NEW_FRM_BITSHIFT 0
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_FRM_IN_PRO (1L<<1)
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_FRM_IN_PRO_BITSHIFT 1
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_FIFO_EMPTY (1L<<2)
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_FIFO_EMPTY_BITSHIFT 2
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_BCNT (0x7ffL<<3)
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_BCNT_BITSHIFT 3
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE (0x1fL<<27)
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_BITSHIFT 27
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_IDLE (0L<<27)
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_IDLE_BITSHIFT 27
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_READY (1L<<27)
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_READY_BITSHIFT 27
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_BUSY (2L<<27)
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_BUSY_BITSHIFT 27
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_EXTRA_RD (3L<<27)
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_EXTRA_RD_BITSHIFT 27
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_LATCH_IP_HDR (4L<<27)
#define MCPR_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_LATCH_IP_HDR_BITSHIFT 27
#define MCP_REG_MCPR_UMP_UMP_EGRESS_FRM_RD_DATA 0x98094 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UMP_UMP_INGRESS_FRM_WR_CTL 0x98098 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_NEW_FRM (1L<<0)
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_NEW_FRM_BITSHIFT 0
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_FIFO_RDY (1L<<1)
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_FIFO_RDY_BITSHIFT 1
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_BCNT_RDY (1L<<2)
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_BCNT_RDY_BITSHIFT 2
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_BCNT (0x7ffL<<3)
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_BCNT_BITSHIFT 3
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE (0x3L<<30)
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_BITSHIFT 30
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_IDLE (0L<<30)
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_IDLE_BITSHIFT 30
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_WAIT (1L<<30)
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_WAIT_BITSHIFT 30
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_BUSY (2L<<30)
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_BUSY_BITSHIFT 30
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_EXTRA_WR (3L<<30)
#define MCPR_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_EXTRA_WR_BITSHIFT 30
#define MCP_REG_MCPR_UMP_UMP_INGRESS_FRM_WR_DATA 0x9809c //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UMP_UMP_EGRESS_FRAME_TYPE 0x980a0 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UMP_UMP_FIFO_REMAINING_WORDS 0x980a4 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_EGRESS_FIFO_DEPTH (0x7ffL<<0)
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_EGRESS_FIFO_DEPTH_BITSHIFT 0
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_EGRESS_FIFO_UNDERFLOW (1L<<14)
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_EGRESS_FIFO_UNDERFLOW_BITSHIFT 14
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_EGRESS_FIFO_OVERFLOW (1L<<15)
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_EGRESS_FIFO_OVERFLOW_BITSHIFT 15
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_INGRESS_FIFO_DEPTH (0x3ffL<<16)
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_INGRESS_FIFO_DEPTH_BITSHIFT 16
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_INGRESS_FIFO_UNDERFLOW (1L<<30)
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_INGRESS_FIFO_UNDERFLOW_BITSHIFT 30
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_INGRESS_FIFO_OVERFLOW (1L<<31)
#define MCPR_UMP_UMP_FIFO_REMAINING_WORDS_INGRESS_FIFO_OVERFLOW_BITSHIFT 31
#define MCP_REG_MCPR_UMP_UMP_EGRESS_FIFO_PTRS 0x980a8 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_RD_PTR (0xfffL<<0)
#define MCPR_UMP_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_RD_PTR_BITSHIFT 0
#define MCPR_UMP_UMP_EGRESS_FIFO_PTRS_UPDATE_RDPTR (1L<<15)
#define MCPR_UMP_UMP_EGRESS_FIFO_PTRS_UPDATE_RDPTR_BITSHIFT 15
#define MCPR_UMP_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_WR_PTR (0xfffL<<16)
#define MCPR_UMP_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_WR_PTR_BITSHIFT 16
#define MCPR_UMP_UMP_EGRESS_FIFO_PTRS_UPDATE_WRPTR (1L<<31)
#define MCPR_UMP_UMP_EGRESS_FIFO_PTRS_UPDATE_WRPTR_BITSHIFT 31
#define MCP_REG_MCPR_UMP_UMP_INGRESS_FIFO_PTRS 0x980ac //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_RD_PTR (0x7ffL<<0)
#define MCPR_UMP_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_RD_PTR_BITSHIFT 0
#define MCPR_UMP_UMP_INGRESS_FIFO_PTRS_UPDATE_RDPTR (1L<<15)
#define MCPR_UMP_UMP_INGRESS_FIFO_PTRS_UPDATE_RDPTR_BITSHIFT 15
#define MCPR_UMP_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_WR_PTR (0x7ffL<<16)
#define MCPR_UMP_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_WR_PTR_BITSHIFT 16
#define MCPR_UMP_UMP_INGRESS_FIFO_PTRS_UPDATE_WRPTR (1L<<31)
#define MCPR_UMP_UMP_INGRESS_FIFO_PTRS_UPDATE_WRPTR_BITSHIFT 31
#define MCP_REG_MCPR_UMP_UNUSED_Z 0x980b0 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UMP_UNUSED_Z_COUNT 1
#define MCP_REG_MCPR_UMP_UMP_EGRESS_PACKET_SA_0 0x980b4 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_EGRESS_PACKET_SA_0_EGRESS_SA (0xffffL<<0)
#define MCPR_UMP_UMP_EGRESS_PACKET_SA_0_EGRESS_SA_BITSHIFT 0
#define MCP_REG_MCPR_UMP_UMP_EGRESS_PACKET_SA_1 0x980b8 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_EGRESS_PACKET_SA_1_EGRESS_SA (0xffffffffL<<0)
#define MCPR_UMP_UMP_EGRESS_PACKET_SA_1_EGRESS_SA_BITSHIFT 0
#define MCP_REG_MCPR_UMP_UMP_INGRESS_BURST_COMMAND 0x980bc //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_INGRESS_BURST_COMMAND_INGRESS_DMA_START (1L<<0)
#define MCPR_UMP_UMP_INGRESS_BURST_COMMAND_INGRESS_DMA_START_BITSHIFT 0
#define MCPR_UMP_UMP_INGRESS_BURST_COMMAND_INGRESS_PORT (1L<<1)
#define MCPR_UMP_UMP_INGRESS_BURST_COMMAND_INGRESS_PORT_BITSHIFT 1
#define MCPR_UMP_UMP_INGRESS_BURST_COMMAND_DMA_LENGTH (0x7ffL<<2)
#define MCPR_UMP_UMP_INGRESS_BURST_COMMAND_DMA_LENGTH_BITSHIFT 2
#define MCPR_UMP_UMP_INGRESS_BURST_COMMAND_INGRESS_PORT_EXT (0x3L<<13)
#define MCPR_UMP_UMP_INGRESS_BURST_COMMAND_INGRESS_PORT_EXT_BITSHIFT 13
#define MCPR_UMP_UMP_INGRESS_BURST_COMMAND_RBUF_OFFSET (0x3fffL<<16)
#define MCPR_UMP_UMP_INGRESS_BURST_COMMAND_RBUF_OFFSET_BITSHIFT 16
#define MCP_REG_MCPR_UMP_UMP_INGRESS_RBUF_CLUSTER 0x980c0 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_INGRESS_RBUF_CLUSTER_RBUF_CLUSTER (0x1ffffffL<<0)
#define MCPR_UMP_UMP_INGRESS_RBUF_CLUSTER_RBUF_CLUSTER_BITSHIFT 0
#define MCP_REG_MCPR_UMP_UMP_INGRESS_VLAN 0x980c4 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_INGRESS_VLAN_INGRESS_VLAN_TAG (0xffffL<<0)
#define MCPR_UMP_UMP_INGRESS_VLAN_INGRESS_VLAN_TAG_BITSHIFT 0
#define MCPR_UMP_UMP_INGRESS_VLAN_VLAN_INS (1L<<16)
#define MCPR_UMP_UMP_INGRESS_VLAN_VLAN_INS_BITSHIFT 16
#define MCPR_UMP_UMP_INGRESS_VLAN_VLAN_DEL (1L<<17)
#define MCPR_UMP_UMP_INGRESS_VLAN_VLAN_DEL_BITSHIFT 17
#define MCP_REG_MCPR_UMP_UMP_INGRESS_BURST_STATUS 0x980c8 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_INGRESS_BURST_STATUS_RESULT (0x3L<<0)
#define MCPR_UMP_UMP_INGRESS_BURST_STATUS_RESULT_BITSHIFT 0
#define MCPR_UMP_UMP_INGRESS_BURST_STATUS_RESULT_BUSY (0L<<0)
#define MCPR_UMP_UMP_INGRESS_BURST_STATUS_RESULT_BUSY_BITSHIFT 0
#define MCPR_UMP_UMP_INGRESS_BURST_STATUS_RESULT_DONE (1L<<0)
#define MCPR_UMP_UMP_INGRESS_BURST_STATUS_RESULT_DONE_BITSHIFT 0
#define MCPR_UMP_UMP_INGRESS_BURST_STATUS_RESULT_ERR (2L<<0)
#define MCPR_UMP_UMP_INGRESS_BURST_STATUS_RESULT_ERR_BITSHIFT 0
#define MCPR_UMP_UMP_INGRESS_BURST_STATUS_RESULT_ERR1 (3L<<0)
#define MCPR_UMP_UMP_INGRESS_BURST_STATUS_RESULT_ERR1_BITSHIFT 0
#define MCP_REG_MCPR_UMP_UMP_EGRESS_BURST_COMMAND 0x980cc //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_EGRESS_BURST_COMMAND_EGRESS_DMA_START (1L<<0)
#define MCPR_UMP_UMP_EGRESS_BURST_COMMAND_EGRESS_DMA_START_BITSHIFT 0
#define MCPR_UMP_UMP_EGRESS_BURST_COMMAND_EGRESS_PORT (1L<<1)
#define MCPR_UMP_UMP_EGRESS_BURST_COMMAND_EGRESS_PORT_BITSHIFT 1
#define MCPR_UMP_UMP_EGRESS_BURST_COMMAND_DMA_LENGTH (0x7ffL<<2)
#define MCPR_UMP_UMP_EGRESS_BURST_COMMAND_DMA_LENGTH_BITSHIFT 2
#define MCPR_UMP_UMP_EGRESS_BURST_COMMAND_EGRESS_PORT_EXT (1L<<13)
#define MCPR_UMP_UMP_EGRESS_BURST_COMMAND_EGRESS_PORT_EXT_BITSHIFT 13
#define MCPR_UMP_UMP_EGRESS_BURST_COMMAND_TPBUF_OFFSET (0x1fffL<<16)
#define MCPR_UMP_UMP_EGRESS_BURST_COMMAND_TPBUF_OFFSET_BITSHIFT 16
#define MCP_REG_MCPR_UMP_UMP_EGRESS_VLAN 0x980d0 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_EGRESS_VLAN_EGRESS_VLAN_TAG (0xffffL<<0)
#define MCPR_UMP_UMP_EGRESS_VLAN_EGRESS_VLAN_TAG_BITSHIFT 0
#define MCPR_UMP_UMP_EGRESS_VLAN_VLAN_INS (1L<<16)
#define MCPR_UMP_UMP_EGRESS_VLAN_VLAN_INS_BITSHIFT 16
#define MCPR_UMP_UMP_EGRESS_VLAN_VLAN_DEL (1L<<17)
#define MCPR_UMP_UMP_EGRESS_VLAN_VLAN_DEL_BITSHIFT 17
#define MCP_REG_MCPR_UMP_UMP_EGRESS_BURST_STATUS 0x980d4 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_EGRESS_BURST_STATUS_RESULT (0x3L<<0)
#define MCPR_UMP_UMP_EGRESS_BURST_STATUS_RESULT_BITSHIFT 0
#define MCPR_UMP_UMP_EGRESS_BURST_STATUS_RESULT_BUSY (0L<<0)
#define MCPR_UMP_UMP_EGRESS_BURST_STATUS_RESULT_BUSY_BITSHIFT 0
#define MCPR_UMP_UMP_EGRESS_BURST_STATUS_RESULT_DONE (1L<<0)
#define MCPR_UMP_UMP_EGRESS_BURST_STATUS_RESULT_DONE_BITSHIFT 0
#define MCPR_UMP_UMP_EGRESS_BURST_STATUS_RESULT_ERR0 (2L<<0)
#define MCPR_UMP_UMP_EGRESS_BURST_STATUS_RESULT_ERR0_BITSHIFT 0
#define MCPR_UMP_UMP_EGRESS_BURST_STATUS_RESULT_RSVD (3L<<0)
#define MCPR_UMP_UMP_EGRESS_BURST_STATUS_RESULT_RSVD_BITSHIFT 0
#define MCP_REG_MCPR_UMP_UMP_EGRESS_STATISTIC 0x980d8 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_EGRESS_STATISTIC_EGRESS_GOOD_CNT (0xffffL<<0)
#define MCPR_UMP_UMP_EGRESS_STATISTIC_EGRESS_GOOD_CNT_BITSHIFT 0
#define MCPR_UMP_UMP_EGRESS_STATISTIC_EGRESS_ERROR_CNT (0xffL<<16)
#define MCPR_UMP_UMP_EGRESS_STATISTIC_EGRESS_ERROR_CNT_BITSHIFT 16
#define MCPR_UMP_UMP_EGRESS_STATISTIC_EGRESS_DROP_CNT (0xffL<<24)
#define MCPR_UMP_UMP_EGRESS_STATISTIC_EGRESS_DROP_CNT_BITSHIFT 24
#define MCP_REG_MCPR_UMP_UMP_INGRESS_STATISTIC 0x980dc //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_INGRESS_STATISTIC_INGRESS_PKT_CNT (0xffffL<<0)
#define MCPR_UMP_UMP_INGRESS_STATISTIC_INGRESS_PKT_CNT_BITSHIFT 0
#define MCP_REG_MCPR_UMP_UMP_ARB_CMD 0x980e0 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_ARB_CMD_UMP_ID (0x7L<<0)
#define MCPR_UMP_UMP_ARB_CMD_UMP_ID_BITSHIFT 0
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_DISABLE (1L<<4)
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_DISABLE_BITSHIFT 4
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_START (1L<<5)
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_START_BITSHIFT 5
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_BYPASS (1L<<6)
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_BYPASS_BITSHIFT 6
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_AUTOBYPASS (1L<<7)
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_AUTOBYPASS_BITSHIFT 7
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_TOKEN_IPG (0x1fL<<8)
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_TOKEN_IPG_BITSHIFT 8
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_TOKEN_VALID (1L<<13)
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_TOKEN_VALID_BITSHIFT 13
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_FC_DISABLE (1L<<15)
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_FC_DISABLE_BITSHIFT 15
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_TIMEOUT (0xffffL<<16)
#define MCPR_UMP_UMP_ARB_CMD_UMP_ARB_TIMEOUT_BITSHIFT 16
#define MCP_REG_MCPR_UMP_UNUSED_F 0x980e4 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UMP_UNUSED_F_COUNT 2
#define MCP_REG_MCPR_UMP_UMP_FRAME_COUNT 0x980ec //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_FRAME_COUNT_EGRESS_FRAME_COUNT (0x7fL<<0)
#define MCPR_UMP_UMP_FRAME_COUNT_EGRESS_FRAME_COUNT_BITSHIFT 0
#define MCPR_UMP_UMP_FRAME_COUNT_INRESS_FRAME_COUNT (0x1fL<<16)
#define MCPR_UMP_UMP_FRAME_COUNT_INRESS_FRAME_COUNT_BITSHIFT 16
#define MCP_REG_MCPR_UMP_UMP_EGRESS_STATISTIC_AC 0x980f0 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_GOOD_CNT (0xffffL<<0)
#define MCPR_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_GOOD_CNT_BITSHIFT 0
#define MCPR_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_ERROR_CNT (0xffL<<16)
#define MCPR_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_ERROR_CNT_BITSHIFT 16
#define MCPR_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_DROP_CNT (0xffL<<24)
#define MCPR_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_DROP_CNT_BITSHIFT 24
#define MCP_REG_MCPR_UMP_UMP_INGRESS_STATISTIC_AC 0x980f4 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_INGRESS_STATISTIC_AC_INGRESS_PKT_CNT (0xffffL<<0)
#define MCPR_UMP_UMP_INGRESS_STATISTIC_AC_INGRESS_PKT_CNT_BITSHIFT 0
#define MCP_REG_MCPR_UMP_UMP_EVENT 0x980f8 //ACCESS:?? DataWidth:0x20
#define MCPR_UMP_UMP_EVENT_INGRESS_RDY_EVENT (1L<<0)
#define MCPR_UMP_UMP_EVENT_INGRESS_RDY_EVENT_BITSHIFT 0
#define MCPR_UMP_UMP_EVENT_EGRESS_RDY_EVENT (1L<<1)
#define MCPR_UMP_UMP_EVENT_EGRESS_RDY_EVENT_BITSHIFT 1
#define MCPR_UMP_UMP_EVENT_INGRESSBURST_DONE_EVENT (1L<<2)
#define MCPR_UMP_UMP_EVENT_INGRESSBURST_DONE_EVENT_BITSHIFT 2
#define MCPR_UMP_UMP_EVENT_EGRESSBURST_DONE_EVENT (1L<<3)
#define MCPR_UMP_UMP_EVENT_EGRESSBURST_DONE_EVENT_BITSHIFT 3
#define MCPR_UMP_UMP_EVENT_EGRESS_FRAME_DROP_EVENT (1L<<4)
#define MCPR_UMP_UMP_EVENT_EGRESS_FRAME_DROP_EVENT_BITSHIFT 4
#define MCPR_UMP_UMP_EVENT_INGRESS_RDY_EVENT_EN (1L<<16)
#define MCPR_UMP_UMP_EVENT_INGRESS_RDY_EVENT_EN_BITSHIFT 16
#define MCPR_UMP_UMP_EVENT_EGRESS_RDY_EVENT_EN (1L<<17)
#define MCPR_UMP_UMP_EVENT_EGRESS_RDY_EVENT_EN_BITSHIFT 17
#define MCPR_UMP_UMP_EVENT_INGRESSBURST_DONE_EVENT_EN (1L<<18)
#define MCPR_UMP_UMP_EVENT_INGRESSBURST_DONE_EVENT_EN_BITSHIFT 18
#define MCPR_UMP_UMP_EVENT_EGRESSBURST_DONE_EVENT_EN (1L<<19)
#define MCPR_UMP_UMP_EVENT_EGRESSBURST_DONE_EVENT_EN_BITSHIFT 19
#define MCPR_UMP_UMP_EVENT_EGRESS_FRAME_DROP_EVENT_EN (1L<<20)
#define MCPR_UMP_UMP_EVENT_EGRESS_FRAME_DROP_EVENT_EN_BITSHIFT 20
#define MCP_REG_MCPR_UNUSED11 0x980fc //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED11_COUNT 4033
#define MCP_REG_MCPR_UMP_UMP_EGRESS_FIFO_FLAT_SPACE 0x9c000 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UMP_UMP_EGRESS_FIFO_FLAT_SPACE_COUNT 1920
#define MCP_REG_MCPR_UNUSED12 0x9de00 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED12_COUNT 128
#define MCP_REG_MCPR_UMP_UMP_INGRESS_FIFO_FLAT_SPACE 0x9e000 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UMP_UMP_INGRESS_FIFO_FLAT_SPACE_COUNT 768
#define MCP_REG_MCPR_UNUSED13 0x9ec00 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_UNUSED13_COUNT 1280
#define MCP_REG_MCPR_SCRATCH 0xa0000 //ACCESS:?? DataWidth:0x20
#define MCP_REG_MCPR_SCRATCH_COUNT 32768
#define MCP_A_REG_MCPR_SCRATCH 0x3a0000 //ACCESS:?? DataWidth:0x20
#define MCP_A_REG_MCPR_SCRATCH_COUNT 40960
#define MCP_A_REG_MCPR_UNUSED14 0x3c8000 //ACCESS:?? DataWidth:0x20
#define MCP_A_REG_MCPR_UNUSED14_COUNT 57344