'\" te
.\" Copyright (c) 2005 Innovative Computing Labs Computer Science Department, University of Tennessee, Knoxville, TN. All Rights Reserved.
.\" Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:  * Redistributions of source code must retain the above copyright notice,   this list of conditions and the following disclaimer.
.\" * Redistributions in binary form must reproduce the above copyright notice,   this list of conditions and the following disclaimer in the documentation   and/or other materials provided with the distribution. * Neither the name of the University of Tennessee nor the names of its   contributors
.\" may be used to endorse or promote products derived from this   software without specific prior written permission.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
.\" AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
.\" OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  This open source software
.\" license conforms to the BSD License template.
.\" Portions Copyright (c) 2008, Sun Microsystems Inc. All Rights Reserved.
.TH generic_events 3CPC "8 Oct 2008" "SunOS 5.11" "CPU Performance Counters Library Functions"
.SH NAME
generic_events \- generic performance counter events
.SH DESCRIPTION
.sp
.LP
The Solaris \fBcpc\fR(3CPC) subsystem implements a number of predefined,
generic performance counter events. Each generic event maps onto a single
platform specific event and one or more optional attributes.  Each hardware
platform only need support a subset of the total set of generic events.
.sp
.LP
The defined generic events are:
.sp
.ne 2
.mk
.na
\fB\fBPAPI_br_cn\fR\fR
.ad
.RS 16n
.rt  
Conditional branch instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_br_ins\fR\fR
.ad
.RS 16n
.rt  
Branch instructions taken
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_br_msp\fR\fR
.ad
.RS 16n
.rt  
Conditional branch instructions mispredicted
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_br_ntk\fR\fR
.ad
.RS 16n
.rt  
Conditional branch instructions not taken
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_br_prc\fR\fR
.ad
.RS 16n
.rt  
Conditional branch instructions correctly predicted
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_br_ucn\fR\fR
.ad
.RS 16n
.rt  
Unconditional branch instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_bru_idl\fR\fR
.ad
.RS 16n
.rt  
Cycles branch units are idle
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_btac_m\fR\fR
.ad
.RS 16n
.rt  
Branch target address cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_ca_cln\fR\fR
.ad
.RS 16n
.rt  
Requests for exclusive access to clean cache line
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_ca_inv\fR\fR
.ad
.RS 16n
.rt  
Requests for cache invalidation
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_ca_itv\fR\fR
.ad
.RS 16n
.rt  
Requests for cache line intervention
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_ca_shr\fR\fR
.ad
.RS 16n
.rt  
Request for exclusive access to shared cache line
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_ca_snp\fR\fR
.ad
.RS 16n
.rt  
Request for cache snoop
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_csr_fal\fR\fR
.ad
.RS 16n
.rt  
Failed conditional store instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_csr_suc\fR\fR
.ad
.RS 16n
.rt  
Successful conditional store instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_csr_tot\fR\fR
.ad
.RS 16n
.rt  
Total conditional store instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_fad_ins\fR\fR
.ad
.RS 16n
.rt  
Floating point add instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_fdv_ins\fR\fR
.ad
.RS 16n
.rt  
Floating point divide instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_fma_ins\fR\fR
.ad
.RS 16n
.rt  
Floating point multiply and add instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_fml_ins\fR\fR
.ad
.RS 16n
.rt  
Floating point multiply instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_fnv_ins\fR\fR
.ad
.RS 16n
.rt  
Floating point inverse instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_fp_ops\fR\fR
.ad
.RS 16n
.rt  
Floating point operations
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_fp_stal\fR\fR
.ad
.RS 16n
.rt  
Cycles the floating point unit stalled
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_fpu_idl\fR\fR
.ad
.RS 16n
.rt  
Cycles the floating point units are idle
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_fsq_ins\fR\fR
.ad
.RS 16n
.rt  
Floating point sqrt instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_ful_ccy\fR\fR
.ad
.RS 16n
.rt  
Cycles with maximum instructions completed
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_ful_icy\fR\fR
.ad
.RS 16n
.rt  
Cycles with maximum instruction issue
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_fxu_idl\fR\fR
.ad
.RS 16n
.rt  
Cycles when units are idle
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_hw_int\fR\fR
.ad
.RS 16n
.rt  
Hardware interrupts
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_int_ins\fR\fR
.ad
.RS 16n
.rt  
Integer instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_tot_cyc\fR\fR
.ad
.RS 16n
.rt  
Total cycles
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_tot_iis\fR\fR
.ad
.RS 16n
.rt  
Instructions issued
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_tot_ins\fR\fR
.ad
.RS 16n
.rt  
Instructions completed
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_vec_ins\fR\fR
.ad
.RS 16n
.rt  
VectorSIMD instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_dca\fR\fR
.ad
.RS 16n
.rt  
Level 1 data cache accesses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_dch\fR\fR
.ad
.RS 16n
.rt  
Level 1 data cache hits
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_dcm\fR\fR
.ad
.RS 16n
.rt  
Level 1 data cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_dcr\fR\fR
.ad
.RS 16n
.rt  
Level 1 data cache reads
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_dcw\fR\fR
.ad
.RS 16n
.rt  
Level 1 data cache writes
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_ica\fR\fR
.ad
.RS 16n
.rt  
Level 1 instruction cache accesses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_ich\fR\fR
.ad
.RS 16n
.rt  
Level 1 instruction cache hits
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_icm\fR\fR
.ad
.RS 16n
.rt  
Level 1 instruction cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_icr\fR\fR
.ad
.RS 16n
.rt  
Level 1 instruction cache reads
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_icw\fR\fR
.ad
.RS 16n
.rt  
Level 1 instruction cache writes
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_ldm\fR\fR
.ad
.RS 16n
.rt  
Level 1 cache load misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_stm\fR\fR
.ad
.RS 16n
.rt  
Level 1 cache store misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_tca\fR\fR
.ad
.RS 16n
.rt  
Level 1 cache accesses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_tch\fR\fR
.ad
.RS 16n
.rt  
Level 1 cache hits
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_tcm\fR\fR
.ad
.RS 16n
.rt  
Level 1 cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_tcr\fR\fR
.ad
.RS 16n
.rt  
Level 1 cache reads
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l1_tcw\fR\fR
.ad
.RS 16n
.rt  
Level 1 cache writes
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_dca\fR\fR
.ad
.RS 16n
.rt  
Level 2 data cache accesses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_dch\fR\fR
.ad
.RS 16n
.rt  
Level 2 data cache hits
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_dcm\fR\fR
.ad
.RS 16n
.rt  
Level 2 data cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_dcr\fR\fR
.ad
.RS 16n
.rt  
Level 2 data cache reads
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_dcw\fR\fR
.ad
.RS 16n
.rt  
Level 2 data cache writes
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_ica\fR\fR
.ad
.RS 16n
.rt  
Level 2 instruction cache accesses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_ich\fR\fR
.ad
.RS 16n
.rt  
Level 2 instruction cache hits
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_icm\fR\fR
.ad
.RS 16n
.rt  
Level 2 instruction cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_icr\fR\fR
.ad
.RS 16n
.rt  
Level 2 instruction cache reads
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_icw\fR\fR
.ad
.RS 16n
.rt  
Level 2 instruction cache writes
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_ldm\fR\fR
.ad
.RS 16n
.rt  
Level 2 cache load misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_stm\fR\fR
.ad
.RS 16n
.rt  
Level 2 cache store misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_tca\fR\fR
.ad
.RS 16n
.rt  
Level 2 cache accesses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_tch\fR\fR
.ad
.RS 16n
.rt  
Level 2 cache hits
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_tcm\fR\fR
.ad
.RS 16n
.rt  
Level 2 cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_tcr\fR\fR
.ad
.RS 16n
.rt  
Level 2 cache reads
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l2_tcw\fR\fR
.ad
.RS 16n
.rt  
Level 2 cache writes
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_dca\fR\fR
.ad
.RS 16n
.rt  
Level 3 data cache accesses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_dch\fR\fR
.ad
.RS 16n
.rt  
Level 3 data cache hits
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_dcm\fR\fR
.ad
.RS 16n
.rt  
Level 3 data cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_dcr\fR\fR
.ad
.RS 16n
.rt  
Level 3 data cache reads
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_dcw\fR\fR
.ad
.RS 16n
.rt  
Level 3 data cache writes
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_ica\fR\fR
.ad
.RS 16n
.rt  
Level 3 instruction cache accesses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_ich\fR\fR
.ad
.RS 16n
.rt  
Level 3 instruction cache hits
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_icm\fR\fR
.ad
.RS 16n
.rt  
Level 3 instruction cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_icr\fR\fR
.ad
.RS 16n
.rt  
Level 3 instruction cache reads
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_icw\fR\fR
.ad
.RS 16n
.rt  
Level 3 instruction cache writes
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_ldm\fR\fR
.ad
.RS 16n
.rt  
Level 3 cache load misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_stm\fR\fR
.ad
.RS 16n
.rt  
Level 3 cache store misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_tca\fR\fR
.ad
.RS 16n
.rt  
Level 3 cache accesses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_tch\fR\fR
.ad
.RS 16n
.rt  
Level 3 cache hits
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_tcm\fR\fR
.ad
.RS 16n
.rt  
Level 3 cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_tcr\fR\fR
.ad
.RS 16n
.rt  
Level 3 cache reads
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_l3_tcw\fR\fR
.ad
.RS 16n
.rt  
Level 3 cache writes
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_ld_ins\fR\fR
.ad
.RS 16n
.rt  
Load Instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_lst_ins\fR\fR
.ad
.RS 16n
.rt  
Loadstore Instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_lsu_idl\fR\fR
.ad
.RS 16n
.rt  
Cycles load store units are idle
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_mem_rcy\fR\fR
.ad
.RS 16n
.rt  
Cycles stalled waiting for memory reads
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_mem_scy\fR\fR
.ad
.RS 16n
.rt  
Cycles stalled waiting for memory accesses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_mem_wcy\fR\fR
.ad
.RS 16n
.rt  
Cycles stalled waiting for memory writes
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_prf_dm\fR\fR
.ad
.RS 16n
.rt  
Data prefetch cache misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_res_stl\fR\fR
.ad
.RS 16n
.rt  
Cycles stalled on any resource
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_sr_ins\fR\fR
.ad
.RS 16n
.rt  
Store Instructions
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_stl_ccy\fR\fR
.ad
.RS 16n
.rt  
Cycles with no instructions completed
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_syc_ins\fR\fR
.ad
.RS 16n
.rt  
Synchronization instructions completed
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_tlb_dm\fR\fR
.ad
.RS 16n
.rt  
Data TLB misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_tlb_im\fR\fR
.ad
.RS 16n
.rt  
Instruction TLB misses
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_tlb_sd\fR\fR
.ad
.RS 16n
.rt  
TLB shootdowns
.RE

.sp
.ne 2
.mk
.na
\fB\fBPAPI_tlb_tl\fR\fR
.ad
.RS 16n
.rt  
Total TLB misses
.RE

.sp
.LP
The tables below define mappings of generic events to platform events and any
associated attribute for all supported platforms.
.SS "AMD Opteron Family 0xF Processor"
.sp

.sp
.TS
tab();
cw(1.81i) cw(2.32i) cw(1.36i) 
lw(1.81i) lw(2.32i) lw(1.36i) 
.
Generic EventPlatform EventUnit Mask
_
\fBPAPI_br_ins\fR\fBFR_retired_branches_w_excp_intr\fR0x0
\fBPAPI_br_msp\fR\fBFR_retired_branches_mispred\fR0x0
\fBPAPI_br_tkn\fR\fBFR_retired_taken_branches\fR0x0
\fBPAPI_fp_ops\fR\fBFP_dispatched_fpu_ops\fR0x3
\fBPAPI_fad_ins\fR\fBFP_dispatched_fpu_ops\fR0x1
\fBPAPI_fml_ins\fR\fBFP_dispatched_fpu_ops\fR0x2
\fBPAPI_fpu_idl\fR\fBFP_cycles_no_fpu_ops_retired\fR0x0
\fBPAPI_tot_cyc\fR\fBBU_cpu_clk_unhalted\fR0x0
\fBPAPI_tot_ins\fR\fBFR_retired_x86_instr_w_excp_intr\fR0x0
\fBPAPI_l1_dca\fR\fBDC_access\fR0x0
\fBPAPI_l1_dcm\fR\fBDC_miss\fR0x0
\fBPAPI_l1_ldm\fR\fBDC_refill_from_L2\fR0xe
\fBPAPI_l1_stm\fR\fBDC_refill_from_L2\fR0x10
\fBPAPI_l1_ica\fR\fBIC_fetch\fR0x0
\fBPAPI_l1_icm\fR\fBIC_miss\fR0x0
\fBPAPI_l1_icr\fR\fBIC_fetch\fR0x0
\fBPAPI_l2_dch\fR\fBDC_refill_from_L2\fR0x1e
\fBPAPI_l2_dcm\fR\fBDC_refill_from_system\fR0x1e
\fBPAPI_l2_dcr\fR\fBDC_refill_from_L2\fR0xe
\fBPAPI_l2_dcw\fR\fBDC_refill_from_L2\fR0x10
\fBPAPI_l2_ich\fR\fBIC_refill_from_L2\fR0x0
\fBPAPI_l2_icm\fR\fBIC_refill_from_system\fR0x0
\fBPAPI_l2_ldm\fR\fBDC_refill_from_system\fR0xe
\fBPAPI_l2_stm\fR\fBDC_refill_from_system\fR0x10
\fBPAPI_res_stl\fR\fBFR_dispatch_stalls\fR0x0
\fBPAPI_stl_icy\fR\fBFR_nothing_to_dispatch\fR0x0
\fBPAPI_hw_int\fR\fBFR_taken_hardware_intrs\fR0x0
\fBPAPI_tlb_dm\fR\fBDC_dtlb_L1_miss_L2_miss\fR0x0
\fBPAPI_tlb_im\fR\fBIC_itlb_L1_miss_L2_miss\fR0x0
\fBPAPI_fp_ins\fR\fBFR_retired_fpu_instr\fR0xd
\fBPAPI_vec_ins\fR\fBFR_retired_fpu_instr\fR0x4
.TE

.SS "AMD Opteron Family 0x10 Processors"
.sp

.sp
.TS
tab();
cw(1.81i) cw(2.32i) cw(1.36i) 
lw(1.81i) lw(2.32i) lw(1.36i) 
.
Generic EventPlatform EventEvent Mask
_
\fBPAPI_br_ins\fR\fBFR_retired_branches_w_excp_intr\fR0x0
\fBPAPI_br_msp\fR\fBFR_retired_branches_mispred\fR0x0
\fBPAPI_br_tkn\fR\fBFR_retired_taken_branches\fR0x0
\fBPAPI_fp_ops\fR\fBFP_dispatched_fpu_ops\fR0x3
\fBPAPI_fad_ins\fR\fBFP_dispatched_fpu_ops\fR0x1
\fBPAPI_fml_ins\fR\fBFP_dispatched_fpu_ops\fR0x2
\fBPAPI_fpu_idl\fR\fBFP_cycles_no_fpu_ops_retired\fR0x0
\fBPAPI_tot_cyc\fR\fBBU_cpu_clk_unhalted\fR0x0
\fBPAPI_tot_ins\fR\fBFR_retired_x86_instr_w_excp_intr\fR0x0
\fBPAPI_l1_dca\fR\fBDC_access\fR0x0
\fBPAPI_l1_dcm\fR\fBDC_miss\fR0x0
\fBPAPI_l1_ldm\fR\fBDC_refill_from_L2\fR0xe
\fBPAPI_l1_stm\fR\fBDC_refill_from_L2\fR0x10
\fBPAPI_l1_ica\fR\fBIC_fetch\fR0x0
\fBPAPI_l1_icm\fR\fBIC_miss\fR0x0
\fBPAPI_l1_icr\fR\fBIC_fetch\fR0x0
\fBPAPI_l2_dch\fR\fBDC_refill_from_L2\fR0x1e
\fBPAPI_l2_dcm\fR\fBDC_refill_from_system\fR0x1e
\fBPAPI_l2_dcr\fR\fBDC_refill_from_L2\fR0xe
\fBPAPI_l2_dcw\fR\fBDC_refill_from_L2\fR0x10
\fBPAPI_l2_ich\fR\fBIC_refill_from_L2\fR0x0
\fBPAPI_l2_icm\fR\fBIC_refill_from_system\fR0x0
\fBPAPI_l2_ldm\fR\fBDC_refill_from_system\fR0xe
\fBPAPI_l2_stm\fR\fBDC_refill_from_system\fR0x10
\fBPAPI_res_stl\fR\fBFR_dispatch_stalls\fR0x0
\fBPAPI_stl_icy\fR\fBFR_nothing_to_dispatch\fR0x0
\fBPAPI_hw_int\fR\fBFR_taken_hardware_intrs\fR0x0
\fBPAPI_tlb_dm\fR\fBDC_dtlb_L1_miss_L2_miss\fR0x7
\fBPAPI_tlb_im\fR\fBIC_itlb_L1_miss_L2_miss\fR0x3
\fBPAPI_fp_ins\fR\fBFR_retired_fpu_instr\fR0xd
\fBPAPI_vec_ins\fR\fBFR_retired_fpu_instr\fR0x4
\fBPAPI_l3_dcr\fR\fBL3_read_req\fR0xf1
\fBPAPI_l3_icr\fR\fBL3_read_req\fR0xf2
\fBPAPI_l3_tcr\fR\fBL3_read_req\fR0xf7
\fBPAPI_l3_stm\fR\fBL3_miss\fR0xf4
\fBPAPI_l3_ldm\fR\fBL3_miss\fR0xf3
\fBPAPI_l3_tcm\fR\fBL3_miss\fR0xf7
.TE

.SS "Intel Pentium IV Processor"
.sp

.sp
.TS
tab();
cw(1.81i) cw(2.32i) cw(1.36i) 
lw(1.81i) lw(2.32i) lw(1.36i) 
.
Generic EventPlatform EventEvent Mask
_
\fBPAPI_br_msp\fR\fBbranch_retired\fR0xa
\fBPAPI_br_ins\fR\fBbranch_retired\fR0xf
\fBPAPI_br_tkn\fR\fBbranch_retired\fR0xc
\fBPAPI_br_ntk\fR\fBbranch_retired\fR0x3
\fBPAPI_br_prc\fR\fBbranch_retired\fR0x5
\fBPAPI_tot_ins\fR\fBinstr_retired\fR0x3
\fBPAPI_tot_cyc\fR\fBglobal_power_events\fR0x1
\fBPAPI_tlb_dm\fR\fBpage_walk_type\fR0x1
\fBPAPI_tlb_im\fR\fBpage_walk_type\fR0x2
\fBPAPI_tlb_tm\fR\fBpage_walk_type\fR0x3
\fBPAPI_l2_ldm\fR\fBBSQ_cache_reference\fR0x100
\fBPAPI_l2_stm\fR\fBBSQ_cache_reference\fR0x400
\fBPAPI_l2_tcm\fR\fBBSQ_cache_reference\fR0x500
.TE

.SS "Intel Pentium Pro/II/III Processor"
.sp

.sp
.TS
tab();
cw(1.81i) cw(2.32i) cw(1.36i) 
lw(1.81i) lw(2.32i) lw(1.36i) 
.
Generic EventPlatform EventEvent Mask
_
\fBPAPI_ca_shr\fR\fBl2_ifetch\fR0xf
\fBPAPI_ca_cln\fR\fBbus_tran_rfo\fR0x0
\fBPAPI_ca_itv\fR\fBbus_tran_inval\fR0x0
\fBPAPI_tlb_im\fR\fBitlb_miss\fR0x0
\fBPAPI_btac_m\fR\fBbtb_misses\fR0x0
\fBPAPI_hw_int\fR\fBhw_int_rx\fR0x0
\fBPAPI_br_cn\fR\fBbr_inst_retired\fR0x0
\fBPAPI_br_tkn\fR\fBbr_taken_retired\fR0x0
\fBPAPI_br_msp\fR\fBbr_miss_pred_taken_ret\fR0x0
\fBPAPI_br_ins\fR\fBbr_inst_retired\fR0x0
\fBPAPI_res_stl\fR\fBresource_stalls\fR0x0
\fBPAPI_tot_iis\fR\fBinst_decoder\fR0x0
\fBPAPI_tot_ins\fR\fBinst_retired\fR0x0
\fBPAPI_tot_cyc\fR\fBcpu_clk_unhalted\fR0x0
\fBPAPI_l1_dcm\fR\fBdcu_lines_in\fR0x0
\fBPAPI_l1_icm\fR\fBl2_ifetch\fR0xf
\fBPAPI_l1_tcm\fR\fBl2_rqsts\fR0xf
\fBPAPI_l1_dca\fR\fBdata_mem_refs\fR0x0
\fBPAPI_l1_ldm\fR\fBl2_ld\fR0xf
\fBPAPI_l1_stm\fR\fBl2_st\fR0xf
\fBPAPI_l2_icm\fR\fBbus_tran_ifetch\fR0x0
\fBPAPI_l2_dcr\fR\fBl2_ld\fR0xf
\fBPAPI_l2_dcw\fR\fBl2_st\fR0xf
\fBPAPI_l2_tcm\fR\fBl2_lines_in\fR0x0
\fBPAPI_l2_tca\fR\fBl2_rqsts\fR0xf
\fBPAPI_l2_tcw\fR\fBl2_st\fR0xf
\fBPAPI_l2_stm\fR\fBl2_m_lines_inm\fR0x0
\fBPAPI_fp_ins\fR\fBflops\fR0x0
\fBPAPI_fp_ops\fR\fBflops\fR0x0
\fBPAPI_fml_ins\fR\fBmul\fR0x0
\fBPAPI_fdv_ins\fR\fBdiv\fR0x0
.TE

.SS "UltraSPARC I/II Processor"
.sp

.sp
.TS
tab();
cw(2.75i) cw(2.75i) 
lw(2.75i) lw(2.75i) 
.
Generic EventPlatform Event
_
\fBPAPI_tot_cyc\fR\fBCycle_cnt\fR
\fBPAPI_tot_ins\fR\fBInstr_cnt\fR
\fBPAPI_tot_iis\fR\fBInstr_cnt\fR
\fBPAPI_l1_dcr\fR\fBDC_rd\fR
\fBPAPI_l1_dcw\fR\fBDC_wr\fR
\fBPAPI_l1_ica\fR\fBIC_ref\fR
\fBPAPI_l1_ich\fR\fBIC_hit\fR
\fBPAPI_l2_tca\fR\fBEC_ref\fR
\fBPAPI_l2_dch\fR\fBEC_rd_hit\fR
\fBPAPI_l2_tch\fR\fBEC_hit\fR
\fBPAPI_l2_ich\fR\fBEC_ic_hit\fR
\fBPAPI_ca_inv\fR\fBEC_snoop_inv\fR
\fBPAPI_br_msp\fR\fBDispatch0_mispred\fR
\fBPAPI_ca_snp\fR\fBEC_snoop_cb\fR
.TE

.SS "UltraSPARC III/IIIi/IV Processor"
.sp

.sp
.TS
tab();
cw(2.75i) cw(2.75i) 
lw(2.75i) lw(2.75i) 
.
Generic EventPlatform Event
_
\fBPAPI_tot_cyc\fR\fBCycle_cnt\fR
\fBPAPI_tot_ins\fR\fBInstr_cnt\fR
\fBPAPI_tot_iis\fR\fBInstr_cnt\fR
\fBPAPI_fma_ins\fR\fBFA_pipe_completion\fR
\fBPAPI_fml_ins\fR\fBFM_pipe_completion\fR
\fBPAPI_l1_dcr\fR\fBDC_rd\fR
\fBPAPI_l1_dcw\fR\fBDC_wr\fR
\fBPAPI_l1_ica\fR\fBIC_ref\fR
\fBPAPI_l1_icm\fR\fBIC_miss\fR
\fBPAPI_l2_tca\fR\fBEC_ref\fR
\fBPAPI_l2_ldm\fR\fBEC_rd_miss\fR
\fBPAPI_l2_tcm\fR\fBEC_misses\fR
\fBPAPI_l2_icm\fR\fBEC_ic_miss\fR
\fBPAPI_tlb_dm\fR\fBDTLB_miss\fR
\fBPAPI_tlb_im\fR\fBITLB_miss\fR
\fBPAPI_br_ntk\fR\fBIU_Stat_Br_count_untaken\fR
\fBPAPI_br_msp\fR\fBDispatch0_mispred\fR
\fBPAPI_br_tkn\fR\fBIU_Stat_Br_count_taken\fR
\fBPAPI_ca_inv\fR\fBEC_snoop_inv\fR
\fBPAPI_ca_snp\fR\fBEC_snoop_cb\fR
.TE

.SS "UltraSPARC IV+ Processor"
.sp

.sp
.TS
tab();
cw(2.75i) cw(2.75i) 
lw(2.75i) lw(2.75i) 
.
Generic EventPlatform Event
_
\fBPAPI_tot_cyc\fR\fBCycle_cnt\fR
\fBPAPI_tot_ins\fR\fBInstr_cnt\fR
\fBPAPI_tot_iis\fR\fBInstr_cnt\fR
\fBPAPI_fma_ins\fR\fBFA_pipe_completion\fR
\fBPAPI_fml_ins\fR\fBFM_pipe_completion\fR
\fBPAPI_l1_dcr\fR\fBDC_rd\fR
\fBPAPI_l1_stm\fR\fBDC_wr_miss\fR
\fBPAPI_l1_ica\fR\fBIC_ref\fR
\fBPAPI_l1_icm\fR\fBIC_L2_req\fR
\fBPAPI_l1_ldm\fR\fBDC_rd_miss\fR
\fBPAPI_l1_dcw\fR\fBDC_wr\fR
\fBPAPI_l2_tca\fR\fBL2_ref\fR
\fBPAPI_l2_ldm\fR\fBL2_rd_miss\fR
\fBPAPI_l2_icm\fR\fBL2_IC_miss\fR
\fBPAPI_l2_stm\fR\fBL2_write_miss\fR
\fBPAPI_l2_tcm\fR\fBL2_miss\fR
\fBPAPI_l3_tcm\fR\fBL3_miss\fR
\fBPAPI_l3_icm\fR\fBL3_IC_miss\fR
\fBPAPI_l3_ldm\fR\fBL3_rd_miss\fR
\fBPAPI_tlb_im\fR\fBITLB_miss\fR
\fBPAPI_tlb_dm\fR\fBDTLB_miss\fR
\fBPAPI_br_tkn\fR\fBIU_stat_br_count_taken\fR
\fBPAPI_br_ntk\fR\fBIU_stat_br_count_untaken\fR
.TE

.SS "Niagara T1 Processor"
.sp

.sp
.TS
tab();
cw(2.75i) cw(2.75i) 
lw(2.75i) lw(2.75i) 
.
Generic EventPlatform Event
_
\fBPAPI_tot_cyc\fR\fBCycle_cnt\fR
\fBPAPI_l2_icm\fR\fBL2_imiss\fR
\fBPAPI_l2_ldm\fR\fBL2_dmiss_ld\fR
\fBPAPI_fp_ops\fR\fBFP_instr_cnt\fR
\fBPAPI_l1_icm\fR\fBIC_miss\fR
\fBPAPI_l1_dcm\fR\fBDC_miss\fR
\fBPAPI_tlb_im\fR\fBITLB_miss\fR
\fBPAPI_tlb_dm\fR\fBDTLB_miss\fR
.TE

.SS "Niagara T2 Processor"
.sp

.sp
.TS
tab();
cw(2.75i) cw(2.75i) 
lw(2.75i) lw(2.75i) 
.
Generic EventPlatform Event
_
\fBPAPI_tot_ins\fR\fBInstr_cnt\fR
\fBPAPI_l1_dcm\fR\fBDC_miss\fR
\fBPAPI_l1_icm\fR\fBIC_miss\fR
\fBPAPI_l2_icm\fR\fBL2_imiss\fR
\fBPAPI_l2_ldm\fR\fBL2_dmiss_ld\fR
\fBPAPI_tlb_dm\fR\fBDTLB_miss\fR
\fBPAPI_tlb_im\fR\fBITLB_miss\fR
\fBPAPI_tlb_tm\fR\fBTLB_miss\fR
\fBPAPI_br_tkn\fR\fBBr_taken\fR
\fBPAPI_br_ins\fR\fBBr_completed\fR
\fBPAPI_ld_ins\fR\fBInstr_ld\fR
\fBPAPI_sr_ins\fR\fBInstr_st\fR
.TE

.SS "SPARC64 VI/VII Processor"
.sp

.sp
.TS
tab();
cw(2.75i) cw(2.75i) 
lw(2.75i) lw(2.75i) 
.
Generic EventPlatform Event
_
\fBPAPI_tot_cyc\fR\fBcycle_counts\fR
\fBPAPI_tot_ins\fR\fBinstruction_counts\fR
\fBPAPI_br_tkn\fR\fBbranch_instructions\fR
\fBPAPI_fp_ops\fR\fBfloating_instructions\fR
\fBPAPI_fma_ins\fR\fBimpdep2_instructions\fR
\fBPAPI_l1_dcm\fR\fBop_r_iu_req_mi_go\fR
\fBPAPI_l1_icm\fR\fBif_r_iu_req_mi_go\fR
\fBPAPI_tlb_dm\fR\fBtrap_DMMU_miss\fR
\fBPAPI_tlb_im\fR\fBtrap_IMMU_miss\fR
.TE

.SH ATTRIBUTES
.sp
.LP
See \fBattributes\fR(5) for descriptions of the following attributes:
.sp

.sp
.TS
tab() box;
cw(2.75i) |cw(2.75i) 
lw(2.75i) |lw(2.75i) 
.
ATTRIBUTE TYPEATTRIBUTE VALUE
_
Interface StabilityVolatile
.TE

.SH SEE ALSO
.sp
.LP
\fBcpc\fR(3CPC), \fBattributes\fR(5)
.SH NOTES
.sp
.LP
Generic names prefixed with "PAPI_" are taken from the University of
Tennessee's PAPI project, http://icl.cs.utk.edu/papi\&.