'\" te
.\" Copyright (c) 2005, Sun Microsystems, Inc. All Rights Reserved.
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.TH MEMBAR_OPS 3C "Feb 14, 2005"
.SH NAME
membar_ops, membar_enter, membar_exit, membar_producer, membar_consumer \-
memory access synchronization barrier operations
.SH SYNOPSIS
.LP
.nf
#include <atomic.h>

\fBvoid\fR \fBmembar_enter\fR(\fBvoid\fR);
.fi

.LP
.nf
\fBvoid\fR \fBmembar_exit\fR(\fBvoid\fR);
.fi

.LP
.nf
\fBvoid\fR \fBmembar_producer\fR(\fBvoid\fR);
.fi

.LP
.nf
\fBvoid\fR \fBmembar_consumer\fR(\fBvoid\fR);
.fi

.SH DESCRIPTION
.sp
.LP
The \fBmembar_enter()\fR function is a generic memory barrier used during lock
entry. It is placed after the memory operation that acquires the lock to
guarantee that the lock protects its data. No stores from after the memory
barrier will reach visibility and no loads from after the barrier will be
resolved before the lock acquisition reaches global visibility.
.sp
.LP
The \fBmembar_exit()\fR function is a generic memory barrier used during lock
exit. It is placed before the      memory operation that releases the lock to
guarantee that the lock protects its data. All loads and stores issued before
the barrier      will be resolved before the subsequent lock update reaches
visibility.
.sp
.LP
The \fBmembar_enter()\fR and \fBmembar_exit()\fR functions are used together to
allow regions of code to be in relaxed store order and then ensure that the
load or store order is maintained at a higher level. They are useful in the
implementation of mutex exclusion locks.
.sp
.LP
The \fBmembar_producer()\fR function arranges for all stores issued before this
point in the code to reach global visibility before any stores that follow.
This is useful in producer modules that update a data item, then set a flag
that it is available. The memory barrier guarantees that the available flag is
not visible earlier than the updated data, thereby imposing store ordering.
.sp
.LP
The \fBmembar_consumer()\fR function arranges for all loads issued before this
point in the code to be completed before any subsequent loads. This is useful
in consumer modules that check if data is available and read the data. The
memory barrier guarantees that the data is not sampled until after the
available flag has been seen, thereby imposing load ordering.
.SH RETURN VALUES
.sp
.LP
No values are returned.
.SH ERRORS
.sp
.LP
No errors are defined.
.SH ATTRIBUTES
.sp
.LP
See \fBattributes\fR(5) for descriptions of the following attributes:
.sp

.sp
.TS
box;
c | c
l | l .
ATTRIBUTE TYPE	ATTRIBUTE VALUE
_
Interface Stability	Stable
_
MT-Level	MT-Safe
.TE

.SH SEE ALSO
.sp
.LP
\fBatomic_add\fR(3C), \fBatomic_and\fR(3C), \fBatomic_bits\fR(3C),
\fBatomic_cas\fR(3C), \fBatomic_dec\fR(3C), \fBatomic_inc\fR(3C),
\fBatomic_ops\fR(3C), \fBatomic_or\fR(3C), \fBatomic_swap\fR(3C),
\fBattributes\fR(5), \fBatomic_ops\fR(9F)
.SH NOTES
.sp
.LP
Atomic instructions (see \fBatomic_ops\fR(3C)) ensure global visibility of
atomically-modified variables on completion. In a relaxed store order system,
this does not guarantee that the visibility of other variables will be
synchronized with the completion of the atomic instruction. If such
synchronization is required, memory barrier instructions must be used.