'\" te
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.TH ATOMIC_OPS 3C "Aug 12, 2004"
.SH NAME
atomic_ops \- atomic operations
.SH SYNOPSIS
.LP
.nf
#include <\fBatomic.h\fR>
.fi

.SH DESCRIPTION
.sp
.LP
This collection of functions provides atomic memory operations. There are 8
different classes of atomic operations:
.sp
.ne 2
.na
\fB\fBatomic_add\fR(3C)\fR
.ad
.RS 19n
These functions provide an atomic addition of a signed value to a variable.
.RE

.sp
.ne 2
.na
\fB\fBatomic_and\fR(3C)\fR
.ad
.RS 19n
These functions provide an atomic logical 'and' of a value to a variable.
.RE

.sp
.ne 2
.na
\fB\fBatomic_bits\fR(3C)\fR
.ad
.RS 19n
These functions provide atomic bit setting and clearing within a variable.
.RE

.sp
.ne 2
.na
\fB\fBatomic_cas\fR(3C)\fR
.ad
.RS 19n
These functions provide an atomic comparison of a value with a variable. If the
comparison is equal, then swap in a new value for the variable, returning the
old value of the variable in either case.
.RE

.sp
.ne 2
.na
\fB\fBatomic_dec\fR(3C)\fR
.ad
.RS 19n
These functions provide an atomic decrement on a variable.
.RE

.sp
.ne 2
.na
\fB\fBatomic_inc\fR(3C)\fR
.ad
.RS 19n
These functions provide an atomic increment on a variable.
.RE

.sp
.ne 2
.na
\fB\fBatomic_or\fR(3C)\fR
.ad
.RS 19n
These functions provide an atomic logical 'or' of a value to a variable.
.RE

.sp
.ne 2
.na
\fB\fBatomic_swap\fR(3C)\fR
.ad
.RS 19n
These functions provide an atomic swap of a value with a variable, returning
the old value of the variable.
.RE

.SH ATTRIBUTES
.sp
.LP
See \fBattributes\fR(7) for descriptions of the following attributes:
.sp

.sp
.TS
box;
c | c
l | l .
ATTRIBUTE TYPE	ATTRIBUTE VALUE
_
Interface Stability	Stable
_
MT-Level	MT-Safe
.TE

.SH SEE ALSO
.sp
.LP
.BR atomic_add (3C),
.BR atomic_and (3C),
.BR atomic_bits (3C),
.BR atomic_cas (3C),
.BR atomic_dec (3C),
.BR atomic_inc (3C),
.BR atomic_or (3C),
.BR atomic_swap (3C),
.BR membar_ops (3C),
.BR attributes (7)
.SH NOTES
.sp
.LP
Atomic instructions ensure global visibility of atomically-modified variables
on completion.  In a relaxed store order system, this does not guarantee that
the visibility of other variables will be synchronized with the completion of
the atomic instruction. If such synchronization is required, memory barrier
instructions must be used. See \fBmembar_ops\fR(3C).
.sp
.LP
Atomic instructions can be expensive since they require synchronization to
occur at a hardware level. This means they should be used with care to ensure
that forcing hardware level synchronization occurs a minimum number of times.
For example, if you have several variables that need to be incremented as a
group, and each needs to be done atomically, then do so with a mutex lock
protecting all of them being incremented rather than using the
\fBatomic_inc\fR(3C) operation on each of them.