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.TH "LLI" "1" "2015-05-30" "3.7" "LLVM"
.SH NAME
lli \- directly execute programs from LLVM bitcode
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.SH SYNOPSIS
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\fBlli\fP [\fIoptions\fP] [\fIfilename\fP] [\fIprogram args\fP]
.SH DESCRIPTION
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\fBlli\fP directly executes programs in LLVM bitcode format.  It takes a program
in LLVM bitcode format and executes it using a just\-in\-time compiler, if one is
available for the current architecture, or an interpreter.  \fBlli\fP takes all of
the same code generator options as llc|llc, but they are only effective when
\fBlli\fP is using the just\-in\-time compiler.
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If \fIfilename\fP is not specified, then \fBlli\fP reads the LLVM bitcode for the
program from standard input.
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The optional \fIargs\fP specified on the command line are passed to the program as
arguments.
.SH GENERAL OPTIONS
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\fB\-fake\-argv0\fP=\fIexecutable\fP
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Override the \fBargv[0]\fP value passed into the executing program.
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\fB\-force\-interpreter\fP=\fI{false,true}\fP
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If set to true, use the interpreter even if a just\-in\-time compiler is available
for this architecture. Defaults to false.
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\fB\-help\fP
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Print a summary of command line options.
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\fB\-load\fP=\fIpluginfilename\fP
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Causes \fBlli\fP to load the plugin (shared object) named \fIpluginfilename\fP and use
it for optimization.
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\fB\-stats\fP
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Print statistics from the code\-generation passes. This is only meaningful for
the just\-in\-time compiler, at present.
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\fB\-time\-passes\fP
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Record the amount of time needed for each code\-generation pass and print it to
standard error.
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\fB\-version\fP
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Print out the version of \fBlli\fP and exit without doing anything else.
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.SH TARGET OPTIONS
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\fB\-mtriple\fP=\fItarget triple\fP
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Override the target triple specified in the input bitcode file with the
specified string.  This may result in a crash if you pick an
architecture which is not compatible with the current system.
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\fB\-march\fP=\fIarch\fP
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Specify the architecture for which to generate assembly, overriding the target
encoded in the bitcode file.  See the output of \fBllc \-help\fP for a list of
valid architectures.  By default this is inferred from the target triple or
autodetected to the current architecture.
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\fB\-mcpu\fP=\fIcpuname\fP
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Specify a specific chip in the current architecture to generate code for.
By default this is inferred from the target triple and autodetected to
the current architecture.  For a list of available CPUs, use:
\fBllvm\-as < /dev/null | llc \-march=xyz \-mcpu=help\fP
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\fB\-mattr\fP=\fIa1,+a2,\-a3,...\fP
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Override or control specific attributes of the target, such as whether SIMD
operations are enabled or not.  The default set of attributes is set by the
current CPU.  For a list of available attributes, use:
\fBllvm\-as < /dev/null | llc \-march=xyz \-mattr=help\fP
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.SH FLOATING POINT OPTIONS
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\fB\-disable\-excess\-fp\-precision\fP
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Disable optimizations that may increase floating point precision.
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\fB\-enable\-no\-infs\-fp\-math\fP
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Enable optimizations that assume no Inf values.
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\fB\-enable\-no\-nans\-fp\-math\fP
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Enable optimizations that assume no NAN values.
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\fB\-enable\-unsafe\-fp\-math\fP
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Causes \fBlli\fP to enable optimizations that may decrease floating point
precision.
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\fB\-soft\-float\fP
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Causes \fBlli\fP to generate software floating point library calls instead of
equivalent hardware instructions.
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.SH CODE GENERATION OPTIONS
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\fB\-code\-model\fP=\fImodel\fP
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Choose the code model from:
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.nf
.ft C
default: Target default code model
small: Small code model
kernel: Kernel code model
medium: Medium code model
large: Large code model
.ft P
.fi
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\fB\-disable\-post\-RA\-scheduler\fP
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Disable scheduling after register allocation.
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\fB\-disable\-spill\-fusing\fP
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Disable fusing of spill code into instructions.
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\fB\-jit\-enable\-eh\fP
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Exception handling should be enabled in the just\-in\-time compiler.
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\fB\-join\-liveintervals\fP
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Coalesce copies (default=true).
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\fB\-nozero\-initialized\-in\-bss\fP Don\(aqt place zero\-initialized symbols into the BSS section.
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\fB\-pre\-RA\-sched\fP=\fIscheduler\fP
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Instruction schedulers available (before register allocation):
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.nf
.ft C
=default: Best scheduler for the target
=none: No scheduling: breadth first sequencing
=simple: Simple two pass scheduling: minimize critical path and maximize processor utilization
=simple\-noitin: Simple two pass scheduling: Same as simple except using generic latency
=list\-burr: Bottom\-up register reduction list scheduling
=list\-tdrr: Top\-down register reduction list scheduling
=list\-td: Top\-down list scheduler \-print\-machineinstrs \- Print generated machine code
.ft P
.fi
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\fB\-regalloc\fP=\fIallocator\fP
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Register allocator to use (default=linearscan)
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.nf
.ft C
=bigblock: Big\-block register allocator
=linearscan: linear scan register allocator =local \-   local register allocator
=simple: simple register allocator
.ft P
.fi
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\fB\-relocation\-model\fP=\fImodel\fP
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Choose relocation model from:
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.nf
.ft C
=default: Target default relocation model
=static: Non\-relocatable code =pic \-   Fully relocatable, position independent code
=dynamic\-no\-pic: Relocatable external references, non\-relocatable code
.ft P
.fi
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\fB\-spiller\fP
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Spiller to use (default=local)
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.nf
.ft C
=simple: simple spiller
=local: local spiller
.ft P
.fi
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\fB\-x86\-asm\-syntax\fP=\fIsyntax\fP
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Choose style of code to emit from X86 backend:
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.nf
.ft C
=att: Emit AT&T\-style assembly
=intel: Emit Intel\-style assembly
.ft P
.fi
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.SH EXIT STATUS
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If \fBlli\fP fails to load the program, it will exit with an exit code of 1.
Otherwise, it will return the exit code of the program it executes.
.SH SEE ALSO
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llc|llc
.SH AUTHOR
Maintained by The LLVM Team (http://llvm.org/).
.SH COPYRIGHT
2003-2014, LLVM Project
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