/*- * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB * * Copyright (c) 2016 - 2021 Intel Corporation * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenFabrics.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef IRDMA_UDA_D_H #define IRDMA_UDA_D_H /* L4 packet type */ #define IRDMA_E_UDA_SQ_L4T_UNKNOWN 0 #define IRDMA_E_UDA_SQ_L4T_TCP 1 #define IRDMA_E_UDA_SQ_L4T_SCTP 2 #define IRDMA_E_UDA_SQ_L4T_UDP 3 /* Inner IP header type */ #define IRDMA_E_UDA_SQ_IIPT_UNKNOWN 0 #define IRDMA_E_UDA_SQ_IIPT_IPV6 1 #define IRDMA_E_UDA_SQ_IIPT_IPV4_NO_CSUM 2 #define IRDMA_E_UDA_SQ_IIPT_IPV4_CSUM 3 #define IRDMA_UDA_QPSQ_PUSHWQE_S 56 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56) #define IRDMA_UDA_QPSQ_INLINEDATAFLAG_S 57 #define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57) #define IRDMA_UDA_QPSQ_INLINEDATALEN_S 48 #define IRDMA_UDA_QPSQ_INLINEDATALEN GENMASK_ULL(55, 48) #define IRDMA_UDA_QPSQ_ADDFRAGCNT_S 38 #define IRDMA_UDA_QPSQ_ADDFRAGCNT GENMASK_ULL(41, 38) #define IRDMA_UDA_QPSQ_IPFRAGFLAGS_S 42 #define IRDMA_UDA_QPSQ_IPFRAGFLAGS GENMASK_ULL(43, 42) #define IRDMA_UDA_QPSQ_NOCHECKSUM_S 45 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45) #define IRDMA_UDA_QPSQ_AHIDXVALID_S 46 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46) #define IRDMA_UDA_QPSQ_LOCAL_FENCE_S 61 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61) #define IRDMA_UDA_QPSQ_AHIDX_S 0 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0) #define IRDMA_UDA_QPSQ_PROTOCOL_S 16 #define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16) #define IRDMA_UDA_QPSQ_EXTHDRLEN_S 32 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32) #define IRDMA_UDA_QPSQ_MULTICAST_S 63 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63) #define IRDMA_UDA_QPSQ_MACLEN_S 56 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56) #define IRDMA_UDA_QPSQ_MACLEN_LINE 2 #define IRDMA_UDA_QPSQ_IPLEN_S 48 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48) #define IRDMA_UDA_QPSQ_IPLEN_LINE 2 #define IRDMA_UDA_QPSQ_L4T_S 30 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30) #define IRDMA_UDA_QPSQ_L4T_LINE 2 #define IRDMA_UDA_QPSQ_IIPT_S 28 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28) #define IRDMA_UDA_QPSQ_IIPT_LINE 2 #define IRDMA_UDA_QPSQ_DO_LPB_LINE 3 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_S 45 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45) #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_LINE 3 #define IRDMA_UDA_QPSQ_IMMDATA_S 0 #define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0) /* Byte Offset 0 */ #define IRDMA_UDAQPC_IPV4_S 3 #define IRDMA_UDAQPC_IPV4 BIT_ULL(3) #define IRDMA_UDAQPC_INSERTVLANTAG_S 5 #define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5) #define IRDMA_UDAQPC_ISQP1_S 6 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6) #define IRDMA_UDAQPC_RQWQESIZE_S IRDMAQPC_RQWQESIZE_S #define IRDMA_UDAQPC_RQWQESIZE IRDMAQPC_RQWQESIZE #define IRDMA_UDAQPC_ECNENABLE_S 14 #define IRDMA_UDAQPC_ECNENABLE BIT_ULL(14) #define IRDMA_UDAQPC_PDINDEXHI_S 20 #define IRDMA_UDAQPC_PDINDEXHI GENMASK_ULL(21, 20) #define IRDMA_UDAQPC_DCTCPENABLE_S 25 #define IRDMA_UDAQPC_DCTCPENABLE BIT_ULL(25) #define IRDMA_UDAQPC_RCVTPHEN_S IRDMAQPC_RCVTPHEN_S #define IRDMA_UDAQPC_RCVTPHEN IRDMAQPC_RCVTPHEN #define IRDMA_UDAQPC_XMITTPHEN_S IRDMAQPC_XMITTPHEN_S #define IRDMA_UDAQPC_XMITTPHEN IRDMAQPC_XMITTPHEN #define IRDMA_UDAQPC_RQTPHEN_S IRDMAQPC_RQTPHEN_S #define IRDMA_UDAQPC_RQTPHEN IRDMAQPC_RQTPHEN #define IRDMA_UDAQPC_SQTPHEN_S IRDMAQPC_SQTPHEN_S #define IRDMA_UDAQPC_SQTPHEN IRDMAQPC_SQTPHEN #define IRDMA_UDAQPC_PPIDX_S IRDMAQPC_PPIDX_S #define IRDMA_UDAQPC_PPIDX IRDMAQPC_PPIDX #define IRDMA_UDAQPC_PMENA_S IRDMAQPC_PMENA_S #define IRDMA_UDAQPC_PMENA IRDMAQPC_PMENA #define IRDMA_UDAQPC_INSERTTAG2_S 11 #define IRDMA_UDAQPC_INSERTTAG2 BIT_ULL(11) #define IRDMA_UDAQPC_INSERTTAG3_S 14 #define IRDMA_UDAQPC_INSERTTAG3 BIT_ULL(14) #define IRDMA_UDAQPC_RQSIZE_S IRDMAQPC_RQSIZE_S #define IRDMA_UDAQPC_RQSIZE IRDMAQPC_RQSIZE #define IRDMA_UDAQPC_SQSIZE_S IRDMAQPC_SQSIZE_S #define IRDMA_UDAQPC_SQSIZE IRDMAQPC_SQSIZE #define IRDMA_UDAQPC_TXCQNUM_S IRDMAQPC_TXCQNUM_S #define IRDMA_UDAQPC_TXCQNUM IRDMAQPC_TXCQNUM #define IRDMA_UDAQPC_RXCQNUM_S IRDMAQPC_RXCQNUM_S #define IRDMA_UDAQPC_RXCQNUM IRDMAQPC_RXCQNUM #define IRDMA_UDAQPC_QPCOMPCTX_S IRDMAQPC_QPCOMPCTX_S #define IRDMA_UDAQPC_QPCOMPCTX IRDMAQPC_QPCOMPCTX #define IRDMA_UDAQPC_SQTPHVAL_S IRDMAQPC_SQTPHVAL_S #define IRDMA_UDAQPC_SQTPHVAL IRDMAQPC_SQTPHVAL #define IRDMA_UDAQPC_RQTPHVAL_S IRDMAQPC_RQTPHVAL_S #define IRDMA_UDAQPC_RQTPHVAL IRDMAQPC_RQTPHVAL #define IRDMA_UDAQPC_QSHANDLE_S IRDMAQPC_QSHANDLE_S #define IRDMA_UDAQPC_QSHANDLE IRDMAQPC_QSHANDLE #define IRDMA_UDAQPC_RQHDRRINGBUFSIZE_S 48 #define IRDMA_UDAQPC_RQHDRRINGBUFSIZE GENMASK_ULL(49, 48) #define IRDMA_UDAQPC_SQHDRRINGBUFSIZE_S 32 #define IRDMA_UDAQPC_SQHDRRINGBUFSIZE GENMASK_ULL(33, 32) #define IRDMA_UDAQPC_PRIVILEGEENABLE_S 25 #define IRDMA_UDAQPC_PRIVILEGEENABLE BIT_ULL(25) #define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE_S 26 #define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE BIT_ULL(26) #define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX_S 0 #define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX GENMASK_ULL(6, 0) #define IRDMA_UDAQPC_PRIVHDRGENENABLE_S 0 #define IRDMA_UDAQPC_PRIVHDRGENENABLE BIT_ULL(0) #define IRDMA_UDAQPC_RQHDRSPLITENABLE_S 3 #define IRDMA_UDAQPC_RQHDRSPLITENABLE BIT_ULL(3) #define IRDMA_UDAQPC_RQHDRRINGBUFENABLE_S 2 #define IRDMA_UDAQPC_RQHDRRINGBUFENABLE BIT_ULL(2) #define IRDMA_UDAQPC_SQHDRRINGBUFENABLE_S 1 #define IRDMA_UDAQPC_SQHDRRINGBUFENABLE BIT_ULL(1) #define IRDMA_UDAQPC_IPID_S 32 #define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32) #define IRDMA_UDAQPC_SNDMSS_S 16 #define IRDMA_UDAQPC_SNDMSS GENMASK_ULL(29, 16) #define IRDMA_UDAQPC_VLANTAG_S 0 #define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0) #define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI_S 20 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI GENMASK_ULL(21, 20) #define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO_S 48 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48) #define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX_S 24 #define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX GENMASK_ULL(29, 24) #define IRDMA_UDA_CQPSQ_MAV_ARPINDEX_S 48 #define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48) #define IRDMA_UDA_CQPSQ_MAV_TC_S 32 #define IRDMA_UDA_CQPSQ_MAV_TC GENMASK_ULL(39, 32) #define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT_S 32 #define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT GENMASK_ULL(39, 32) #define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL_S 0 #define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL GENMASK_ULL(19, 0) #define IRDMA_UDA_CQPSQ_MAV_ADDR0_S 32 #define IRDMA_UDA_CQPSQ_MAV_ADDR0 GENMASK_ULL(63, 32) #define IRDMA_UDA_CQPSQ_MAV_ADDR1_S 0 #define IRDMA_UDA_CQPSQ_MAV_ADDR1 GENMASK_ULL(31, 0) #define IRDMA_UDA_CQPSQ_MAV_ADDR2_S 32 #define IRDMA_UDA_CQPSQ_MAV_ADDR2 GENMASK_ULL(63, 32) #define IRDMA_UDA_CQPSQ_MAV_ADDR3_S 0 #define IRDMA_UDA_CQPSQ_MAV_ADDR3 GENMASK_ULL(31, 0) #define IRDMA_UDA_CQPSQ_MAV_WQEVALID_S 63 #define IRDMA_UDA_CQPSQ_MAV_WQEVALID BIT_ULL(63) #define IRDMA_UDA_CQPSQ_MAV_OPCODE_S 32 #define IRDMA_UDA_CQPSQ_MAV_OPCODE GENMASK_ULL(37, 32) #define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK_S 62 #define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK BIT_ULL(62) #define IRDMA_UDA_CQPSQ_MAV_IPV4VALID_S 59 #define IRDMA_UDA_CQPSQ_MAV_IPV4VALID BIT_ULL(59) #define IRDMA_UDA_CQPSQ_MAV_AVIDX_S 0 #define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(16, 0) #define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG_S 60 #define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG BIT_ULL(60) #define IRDMA_UDA_MGCTX_VFFLAG_S 29 #define IRDMA_UDA_MGCTX_VFFLAG BIT_ULL(29) #define IRDMA_UDA_MGCTX_DESTPORT_S 32 #define IRDMA_UDA_MGCTX_DESTPORT GENMASK_ULL(47, 32) #define IRDMA_UDA_MGCTX_VFID_S 22 #define IRDMA_UDA_MGCTX_VFID GENMASK_ULL(28, 22) #define IRDMA_UDA_MGCTX_VALIDENT_S 31 #define IRDMA_UDA_MGCTX_VALIDENT BIT_ULL(31) #define IRDMA_UDA_MGCTX_PFID_S 18 #define IRDMA_UDA_MGCTX_PFID GENMASK_ULL(21, 18) #define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT_S 30 #define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT BIT_ULL(30) #define IRDMA_UDA_MGCTX_QPID_S 0 #define IRDMA_UDA_MGCTX_QPID GENMASK_ULL(17, 0) #define IRDMA_UDA_CQPSQ_MG_WQEVALID_S 63 #define IRDMA_UDA_CQPSQ_MG_WQEVALID BIT_ULL(63) #define IRDMA_UDA_CQPSQ_MG_OPCODE_S 32 #define IRDMA_UDA_CQPSQ_MG_OPCODE GENMASK_ULL(37, 32) #define IRDMA_UDA_CQPSQ_MG_MGIDX_S 0 #define IRDMA_UDA_CQPSQ_MG_MGIDX GENMASK_ULL(12, 0) #define IRDMA_UDA_CQPSQ_MG_IPV4VALID_S 60 #define IRDMA_UDA_CQPSQ_MG_IPV4VALID BIT_ULL(60) #define IRDMA_UDA_CQPSQ_MG_VLANVALID_S 59 #define IRDMA_UDA_CQPSQ_MG_VLANVALID BIT_ULL(59) #define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID_S 0 #define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID GENMASK_ULL(5, 0) #define IRDMA_UDA_CQPSQ_MG_VLANID_S 32 #define IRDMA_UDA_CQPSQ_MG_VLANID GENMASK_ULL(43, 32) #define IRDMA_UDA_CQPSQ_QS_HANDLE_S 0 #define IRDMA_UDA_CQPSQ_QS_HANDLE GENMASK_ULL(9, 0) #define IRDMA_UDA_CQPSQ_QHASH_QPN_S 32 #define IRDMA_UDA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32) #define IRDMA_UDA_CQPSQ_QHASH__S 0 #define IRDMA_UDA_CQPSQ_QHASH_ BIT_ULL(0) #define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT_S 16 #define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16) #define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT_S 0 #define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0) #define IRDMA_UDA_CQPSQ_QHASH_ADDR0_S 32 #define IRDMA_UDA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32) #define IRDMA_UDA_CQPSQ_QHASH_ADDR1_S 0 #define IRDMA_UDA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0) #define IRDMA_UDA_CQPSQ_QHASH_ADDR2_S 32 #define IRDMA_UDA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32) #define IRDMA_UDA_CQPSQ_QHASH_ADDR3_S 0 #define IRDMA_UDA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0) #define IRDMA_UDA_CQPSQ_QHASH_WQEVALID_S 63 #define IRDMA_UDA_CQPSQ_QHASH_WQEVALID BIT_ULL(63) #define IRDMA_UDA_CQPSQ_QHASH_OPCODE_S 32 #define IRDMA_UDA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32) #define IRDMA_UDA_CQPSQ_QHASH_MANAGE_S 61 #define IRDMA_UDA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61) #define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID_S 60 #define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60) #define IRDMA_UDA_CQPSQ_QHASH_LANFWD_S 59 #define IRDMA_UDA_CQPSQ_QHASH_LANFWD BIT_ULL(59) #define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE_S 42 #define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42) #endif /* IRDMA_UDA_D_H */