Lines Matching refs:g6
62 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
77 mov %g6, %g2 ! arg2 = tagaccess
158 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
159 CPU_ADDR(%g5, %g6)
163 ldn [%g5 + CPU_MPCB], %g6
164 ld [%g6 + MPCB_WBCNT], %g5
166 st %g7, [%g6 + MPCB_WBCNT]
171 add %g6, %g7, %g7
174 ldn [%g6 + MPCB_WBUF], %g5
196 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
211 mov %g6, %g2 ! arg2 = tagaccess
292 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_SO1)
293 CPU_ADDR(%g5, %g6)
297 ldn [%g5 + CPU_MPCB], %g6
298 ld [%g6 + MPCB_WBCNT], %g5
300 st %g7, [%g6 + MPCB_WBCNT]
305 add %g6, %g7, %g7
308 ldn [%g6 + MPCB_WBUF], %g5
337 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
341 mov %g6, %g2 ! arg2 = tagaccess
417 mov MMU_PCONTEXT, %g6
418 ldxa [%g6]ASI_MMU_CTX, %g7
427 stxa %g5, [%g6]ASI_MMU_CTX