Lines Matching +full:6 +full:a

7 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
16 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
33 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
39         "Counter": "0,1,2,3,4,5,6,7",
50         "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
51         "Counter": "0,1,2,3,4,5,6,7",
57 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
63         "Counter": "0,1,2,3,4,5,6,7",
75         "Counter": "0,1,2,3,4,5,6,7",
87         "Counter": "0,1,2,3,4,5,6,7",
99         "Counter": "0,1,2,3,4,5,6,7",
105 …rval where the front-end delivered no uops for a period of at least 1 cycle which was not interrup…
110 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
111         "Counter": "0,1,2,3,4,5,6,7",
117 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
122 …nterval where the front-end delivered no uops for a period of 16 cycles which was not interrupted …
123         "Counter": "0,1,2,3,4,5,6,7",
129 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
135         "Counter": "0,1,2,3,4,5,6,7",
141 …val where the front-end delivered no uops for a period of at least 2 cycles which was not interrup…
146 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
147         "Counter": "0,1,2,3,4,5,6,7",
153 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
158 …where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted …
159         "Counter": "0,1,2,3,4,5,6,7",
165 … the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-sl…
170 …nterval where the front-end delivered no uops for a period of 32 cycles which was not interrupted …
171         "Counter": "0,1,2,3,4,5,6,7",
177 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
182 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
183         "Counter": "0,1,2,3,4,5,6,7",
189 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
194 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
195         "Counter": "0,1,2,3,4,5,6,7",
201 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
206 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
207         "Counter": "0,1,2,3,4,5,6,7",
213 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
218 …interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted …
219         "Counter": "0,1,2,3,4,5,6,7",
225 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
231         "Counter": "0,1,2,3,4,5,6,7",
242         "Counter": "0,1,2,3,4,5,6,7",
254         "Counter": "0,1,2,3,4,5,6,7",
264 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
268 …tion": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The …
283 …  "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
287 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
304         "CounterMask": "6",
333         "CounterMask": "6",
381         "Counter": "0,1,2,3,4,5,6,7",
384 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
390         "Counter": "0,1,2,3,4,5,6,7",
391         "CounterMask": "6",
394 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
400         "Counter": "0,1,2,3,4,5,6,7",
405 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
411         "Counter": "0,1,2,3,4,5,6,7",
414 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
420         "Counter": "0,1,2,3,4,5,6,7",
421         "CounterMask": "6",
424 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
430         "Counter": "0,1,2,3,4,5,6,7",
435 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…