Lines Matching +full:non +full:- +full:specified
1 perf-list(1)
5 ----
6 perf-list - List all symbolic event types
9 --------
15 -----------
17 various perf commands with the -e option.
20 -------
21 -d::
22 --desc::
25 --no-desc::
28 -v::
29 --long-desc::
32 --debug::
35 --details::
39 --deprecated::
42 --unit::
44 (e.g. --unit cpu, --unit msr, --unit cpu_core, --unit cpu_atom)
46 -j::
47 --json::
50 -o::
51 --output=::
56 ---------------
62 u - user-space counting
63 k - kernel counting
64 h - hypervisor counting
65 I - non idle counting
66 G - guest counting (in KVM guests)
67 H - host counting (not in KVM guests)
68 p - precise level
69 P - use maximum detected precise level
70 S - read sample value (PERF_SAMPLE_READ)
71 D - pin the event to the PMU
72 W - group is weak and will fallback to non-group if not schedulable,
73 e - group or event are exclusive and do not share the PMU
74 b - use BPF aggregration (see perf stat --bpf-counters)
75 R - retire latency value of the event
76 X - don't regroup the event to match PMUs
79 address should be. The 'p' modifier can be specified multiple times:
81 0 - SAMPLE_IP can have arbitrary skid
82 1 - SAMPLE_IP must have constant skid
83 2 - SAMPLE_IP requested to have 0 skid
84 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
88 which supports up to precise-level 2, and precise level 3 for
91 On AMD systems it is implemented using IBS OP (up to precise-level 2).
93 inherently non-precise and IBS is inherently precise. (i.e. ibs_op//,
95 works with event types 0x76 (cpu-cycles, CPU clocks not halted) and 0xC1
96 (micro-ops retired). Both events map to IBS execution sampling (IBS op)
98 Core Complex (CCX) -> Processor x86 Core -> Instruction Based Sampling (IBS)
102 Manual Volume 2: System Programming, 13.3 Instruction-Based
105 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
106 perf record -a -e r076:p ... # same as -e cpu-cycles:p
107 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
110 -----------------------------
115 …Lx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Prog…
117 Core Complex (CCX) -> Processor x86 Core -> MSR Registers section of the
133 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
139 perf stat -e r1a8 -a sleep 1
140 perf record -e r1a8 ...
144 perf record -e r1a8 -a sleep 1
145 perf record -e cpu/r1a8/ ...
146 perf record -e cpu/r0x1a8/ ...
161 28FH 03H op_cache_hit_miss.op_cache_hit Counts Op Cache micro-tag
165 EventSelect bits have to be specified via bits 32-35 as can be seen with:
171 perf stat -e r20000038f -a sleep 1
172 perf record -e r20000038f ...
176 perf record -e r20000038f -a sleep 1
177 perf record -e cpu/r20000038f/ ...
178 perf record -e cpu/r0x20000038f/ ...
184 --------------
195 be specified as
197 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
201 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
204 ---------------
208 with perf stat -a. They can be bound to one logical CPU, but will measure
214 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
223 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
224 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
228 perf stat -I 1000 -e power/energy-cores/ -a
231 -------------------
233 For non root users generally only context switched PMU events are available.
241 sysctl to -1, which allows non root to use these events.
248 -----------------
263 -------
267 intel-pt.txt document.
270 --------------------
272 Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
280 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
283 ----------------
290 perf stat -e cpu/event=0,umask=0x3,percore=1/
300 perf stat -e instructions/cpu=0,cpu=2/,cycles/cpu=1-2/ -a sleep 1
304 perf stat -e data_read/cpu=0/,data_write/cpu=1/ -a sleep 1
308 perf stat -e msr/tsc,cpu=cpu_core/ -a sleep 1
311 ------------
320 errors. Event groups can be specified using { }.
322 perf stat -e '{instructions,cycles}' ...
328 ref-cycles. Some special events have restrictions on which counter they
330 When too many events are specified in the group some of them will not
343 ---------------
347 perf record -e '{cycles,instructions}:S' ...
348 perf report --group
358 -------
364 . 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
368 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
388 types specified.
392 . '--raw-dump', shows the raw-dump of all the events.
393 . '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
396 include::intel-acr.txt[]
399 --------
400 linkperf:perf-stat[1], linkperf:perf-top[1],
401 linkperf:perf-record[1],
402 http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: …