Lines Matching +full:codec +full:- +full:analog +full:- +full:controls
1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
40 "ti,gpo-config-1",
41 "ti,gpo-config-2",
42 "ti,gpo-config-3",
43 "ti,gpo-config-4",
162 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
163 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
168 /* DRE Level. From -12 dB to -66 dB in 1 dB steps */
169 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
173 /* AGC Level. From -6 dB to -36 dB in 2 dB steps */
174 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
179 "Linear Phase", "Low Latency", "Ultra-low Latency"
226 /* Analog/Digital Selection */
227 static const char * const adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"};
228 static const char * const adcx140_analog_sel_text[] = {"Analog", "Line In"};
242 SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum);
263 SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum);
284 SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum);
305 SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum);
352 /* Analog Differential Inputs */
386 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
388 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
390 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
392 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
454 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
456 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
458 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
460 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
498 {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
516 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
517 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
518 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
519 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
520 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
521 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
522 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
523 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
525 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"},
526 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"},
527 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"},
529 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"},
530 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"},
531 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"},
533 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"},
534 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"},
535 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"},
537 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"},
538 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"},
539 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"},
541 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"},
542 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"},
543 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"},
545 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"},
546 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"},
547 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"},
549 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"},
550 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"},
551 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"},
553 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"},
554 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"},
555 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"},
571 {"MIC1 Analog Mux", "Line In", "MIC1P"},
572 {"MIC2 Analog Mux", "Line In", "MIC2P"},
573 {"MIC3 Analog Mux", "Line In", "MIC3P"},
574 {"MIC4 Analog Mux", "Line In", "MIC4P"},
576 {"MIC1P Input Mux", "Analog", "MIC1P"},
577 {"MIC1M Input Mux", "Analog", "MIC1M"},
578 {"MIC2P Input Mux", "Analog", "MIC2P"},
579 {"MIC2M Input Mux", "Analog", "MIC2M"},
580 {"MIC3P Input Mux", "Analog", "MIC3P"},
581 {"MIC3M Input Mux", "Analog", "MIC3M"},
582 {"MIC4P Input Mux", "Analog", "MIC4P"},
583 {"MIC4M Input Mux", "Analog", "MIC4M"},
605 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
606 uinfo->count = 1;
607 uinfo->value.integer.min = 0;
608 uinfo->value.integer.max = 1;
615 struct snd_soc_component *codec = snd_kcontrol_chip(kcontrol);
616 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
618 value->value.integer.value[0] = adcx140->phase_calib_on ? 1 : 0;
627 struct snd_soc_component *codec = snd_kcontrol_chip(kcontrol);
628 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
630 bool v = value->value.integer.value[0] ? true : false;
632 if (adcx140->phase_calib_on != v) {
633 adcx140->phase_calib_on = v;
640 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
642 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
644 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
646 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
682 if (adcx140->gpio_reset) {
683 gpiod_direction_output(adcx140->gpio_reset, 0);
686 gpiod_direction_output(adcx140->gpio_reset, 1);
688 ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET,
702 struct snd_soc_component *component = adcx140->component;
707 if (adcx140->micbias_vg && power_state)
711 ret = regmap_write(adcx140->regmap, ADCX140_PHASE_CALIB,
712 adcx140->phase_calib_on ? 0x00 : 0x40);
714 dev_err(component->dev, "%s: register write error %d\n",
718 regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,
726 struct snd_soc_component *component = dai->component;
744 dev_err(component->dev, "%s: Unsupported width %d\n",
746 return -EINVAL;
762 struct snd_soc_component *component = codec_dai->component;
777 dev_err(component->dev, "Invalid DAI clock provider\n");
778 return -EINVAL;
797 dev_err(component->dev, "Invalid DAI interface format\n");
798 return -EINVAL;
813 dev_err(component->dev, "Invalid DAI clock signal polarity\n");
814 return -EINVAL;
820 adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
845 struct snd_soc_component *component = codec_dai->component;
853 dev_err(component->dev, "Only lower adjacent slots are supported\n");
854 return -EINVAL;
864 dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
865 return -EINVAL;
868 adcx140->slot_width = slot_width;
887 ret = device_property_read_u32_array(adcx140->dev,
895 dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1);
896 return -EINVAL;
900 dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1);
901 return -EINVAL;
906 ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i,
923 gpio_count = device_property_count_u32(adcx140->dev,
924 "ti,gpio-config");
929 return -EINVAL;
931 ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config",
937 dev_err(adcx140->dev, "GPIO config out of range\n");
938 return -EINVAL;
942 dev_err(adcx140->dev, "GPIO drive out of range\n");
943 return -EINVAL;
949 return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val);
969 ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source",
973 adcx140->micbias_vg = false;
975 adcx140->micbias_vg = true;
978 ret = device_property_read_u32(adcx140->dev, "ti,vref-source",
984 dev_err(adcx140->dev, "Mic Bias source value is invalid\n");
985 return -EINVAL;
994 if (adcx140->supply_areg == NULL)
997 ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val);
999 dev_err(adcx140->dev, "setting sleep config failed %d\n", ret);
1006 pdm_count = device_property_count_u32(adcx140->dev,
1007 "ti,pdm-edge-select");
1009 ret = device_property_read_u32_array(adcx140->dev,
1010 "ti,pdm-edge-select",
1016 pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i);
1018 ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG,
1024 gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config");
1026 ret = device_property_read_u32_array(adcx140->dev,
1027 "ti,gpi-config",
1035 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0,
1043 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1,
1057 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,
1061 dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret);
1063 tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive");
1065 ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0,
1068 dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret);
1100 .controls = adcx140_snd_controls,
1114 .name = "tlv320adcx140-codec",
1141 regulator_disable(adcx140->supply_areg);
1149 adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL);
1151 return -ENOMEM;
1153 adcx140->phase_calib_on = false;
1154 adcx140->dev = &i2c->dev;
1156 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
1158 if (IS_ERR(adcx140->gpio_reset))
1159 dev_info(&i2c->dev, "Reset GPIO not defined\n");
1161 adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev,
1163 if (IS_ERR(adcx140->supply_areg)) {
1164 if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER)
1165 return -EPROBE_DEFER;
1167 adcx140->supply_areg = NULL;
1169 ret = regulator_enable(adcx140->supply_areg);
1171 dev_err(adcx140->dev, "Failed to enable areg\n");
1175 ret = devm_add_action_or_reset(&i2c->dev, adcx140_disable_regulator, adcx140);
1180 adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap);
1181 if (IS_ERR(adcx140->regmap)) {
1182 ret = PTR_ERR(adcx140->regmap);
1183 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1190 return devm_snd_soc_register_component(&i2c->dev,
1205 .name = "tlv320adcx140-codec",
1214 MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver");