Lines Matching full:in1r
74 "IN1R",
135 0x011, /* IN1R signal path */
377 SOC_DAPM_ENUM_EXT("IN1R Mux", cs48l32_in1muxr_enum,
470 "IN1L", "IN1R", "IN2L", "IN2R",
2557 SOC_SINGLE_RANGE_TLV("IN1R Volume", CS48L32_IN1R_CONTROL2,
2564 SOC_SINGLE_EXT("IN1R LP Switch", CS48L32_IN1R_CONTROL1, CS48L32_INx_LP_MODE_SHIFT,
2568 SOC_SINGLE("IN1R HPF Switch", CS48L32_IN1R_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0),
2575 SOC_SINGLE_EXT_TLV("IN1R Digital Volume", CS48L32_IN1R_CONTROL2,
2701 SOC_ENUM_EXT("IN1R Rate", cs48l32_input_rate[1], snd_soc_get_enum_double, cs48l32_in_rate_put),
2877 SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &cs48l32_inmux[1]),
2880 SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &cs48l32_dmode_mux[0]),
2925 SND_SOC_DAPM_PGA_E("IN1R PGA", CS48L32_INPUT_CONTROL, CS48L32_IN1R_EN_SHIFT,
3144 { "IN1R Mux", "Analog 1", "IN1RN_1" },
3145 { "IN1R Mux", "Analog 2", "IN1RN_2" },
3146 { "IN1R Mux", "Analog 1", "IN1RP_1" },
3147 { "IN1R Mux", "Analog 2", "IN1RP_2" },
3150 { "IN1R PGA", NULL, "IN1R Mode" },
3153 { "IN1R Mode", "Analog", "IN1R Mux" },
3157 { "IN1R Mode", "Digital", "IN1_PDMCLK" },
3158 { "IN1R Mode", "Digital", "IN1_PDMDATA" },
3161 { "IN1R PGA", NULL, "VOUT_MIC" },
3175 { "Ultrasonic 1 Input", "IN1R", "IN1R PGA" },
3180 { "Ultrasonic 2 Input", "IN1R", "IN1R PGA" },
3248 { "AUXPDM1 Analog Input", "IN1R", "IN1R PGA" },
3251 { "AUXPDM2 Analog Input", "IN1R", "IN1R PGA" },
3255 { "AUXPDM1 Input", "IN1 Digital", "IN1R PGA" },
3261 { "AUXPDM2 Input", "IN1 Digital", "IN1R PGA" },