Lines Matching +full:0 +full:x108000
31 #define MIXART_MEM(mgr,x) ((mgr)->mem[0].virt + (x))
36 #define DAUGHTER_TYPE_MASK 0x0F
37 #define DAUGHTER_VER_MASK 0xF0
40 #define MIXART_DAUGHTER_TYPE_NONE 0x00
41 #define MIXART_DAUGHTER_TYPE_COBRANET 0x08
42 #define MIXART_DAUGHTER_TYPE_AES 0x0E
50 …* -----------BAR 0 -------------------------------------------------------------------------------…
52 #define MIXART_PSEUDOREG 0x2000 /* base address for ps…
54 #define MIXART_PSEUDOREG_BOARDNUMBER MIXART_PSEUDOREG+0 /* board number */
57 #define MIXART_PSEUDOREG_PERF_STREAM_LOAD_OFFSET MIXART_PSEUDOREG+0x70 /* streaming load */
58 #define MIXART_PSEUDOREG_PERF_SYSTEM_LOAD_OFFSET MIXART_PSEUDOREG+0x78 /* system load (refere…
59 #define MIXART_PSEUDOREG_PERF_MAILBX_LOAD_OFFSET MIXART_PSEUDOREG+0x7C /* mailbox load */
60 #define MIXART_PSEUDOREG_PERF_INTERR_LOAD_OFFSET MIXART_PSEUDOREG+0x74 /* interrupt handling …
63 #define MIXART_PSEUDOREG_MXLX_BASE_ADDR_OFFSET MIXART_PSEUDOREG+0x9C /* 0x00600000 */
64 #define MIXART_PSEUDOREG_MXLX_SIZE_OFFSET MIXART_PSEUDOREG+0xA0 /* xilinx size in byte…
65 #define MIXART_PSEUDOREG_MXLX_STATUS_OFFSET MIXART_PSEUDOREG+0xA4 /* status = EMBEBBED_S…
68 #define MIXART_PSEUDOREG_ELF_STATUS_OFFSET MIXART_PSEUDOREG+0xB0 /* status = EMBEBBED_S…
75 #define MIXART_PSEUDOREG_DBRD_PRESENCE_OFFSET MIXART_PSEUDOREG+0x990
78 #define MIXART_PSEUDOREG_DBRD_TYPE_OFFSET MIXART_PSEUDOREG+0x994 /* Type and version of…
82 #define MIXART_PSEUDOREG_DXLX_BASE_ADDR_OFFSET MIXART_PSEUDOREG+0x998 /* get the address her…
83 #define MIXART_PSEUDOREG_DXLX_SIZE_OFFSET MIXART_PSEUDOREG+0x99C /* xilinx size in byte…
84 #define MIXART_PSEUDOREG_DXLX_STATUS_OFFSET MIXART_PSEUDOREG+0x9A0 /* status = EMBEBBED_S…
87 #define MIXART_FLOWTABLE_PTR 0x3000 /* pointer to flow tab…
92 #define MSG_INBOUND_POST_HEAD 0x010008 /* DRV posts MF + increment4 */
93 #define MSG_INBOUND_POST_TAIL 0x01000C /* EMB gets MF + increment4 */
95 #define MSG_OUTBOUND_POST_TAIL 0x01001C /* DRV gets MF + increment4 */
96 #define MSG_OUTBOUND_POST_HEAD 0x010018 /* EMB posts MF + increment4 */
98 #define MSG_INBOUND_FREE_TAIL 0x010004 /* DRV gets MFA + increment4 */
99 #define MSG_OUTBOUND_FREE_TAIL 0x010014 /* EMB gets MFA + increment4 */
101 #define MSG_OUTBOUND_FREE_HEAD 0x010010 /* DRV puts MFA + increment4 */
102 #define MSG_INBOUND_FREE_HEAD 0x010000 /* EMB puts MFA + increment4 */
105 #define MSG_BOUND_STACK_SIZE 0x004000 /* size of each following stack */
107 #define MSG_OUTBOUND_POST_STACK 0x108000 /* stack of messages to the DRV */
108 #define MSG_INBOUND_POST_STACK 0x104000 /* stack of messages to the EMB */
110 #define MSG_OUTBOUND_FREE_STACK 0x10C000 /* stack of free enveloped for EMB */
111 #define MSG_INBOUND_FREE_STACK 0x100000 /* stack of free enveloped for DRV */
115 #define MSG_FRAME_OFFSET 0x64
116 #define MSG_FRAME_SIZE 0x6400
129 #define MIXART_PCI_OMIMR_OFFSET 0x34 /* outbound message interrupt mask register…
130 #define MIXART_PCI_OMISR_OFFSET 0x30 /* outbound message interrupt status regist…
131 #define MIXART_PCI_ODBR_OFFSET 0x60 /* outbound doorbell register */
133 #define MIXART_BA1_BRUTAL_RESET_OFFSET 0x68 /* write 1 in LSBit to reset board */
135 #define MIXART_HOST_ALL_INTERRUPT_MASKED 0x02B /* 0000 0010 1011 */
136 #define MIXART_ALLOW_OUTBOUND_DOORBELL 0x023 /* 0000 0010 0011 */
137 #define MIXART_OIDI 0x008 /* 0000 0000 1000 */