Lines Matching +full:0 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
76 mflr 0
77 std 0, 16(1)
78 stdu 1,-752(1)
99 addi 9, 1, 256
100 SAVE_VRS 20, 0, 9
101 SAVE_VRS 21, 16, 9
102 SAVE_VRS 22, 32, 9
103 SAVE_VRS 23, 48, 9
104 SAVE_VRS 24, 64, 9
105 SAVE_VRS 25, 80, 9
106 SAVE_VRS 26, 96, 9
107 SAVE_VRS 27, 112, 9
108 SAVE_VRS 28, 128, 9
109 SAVE_VRS 29, 144, 9
110 SAVE_VRS 30, 160, 9
111 SAVE_VRS 31, 176, 9
113 SAVE_VSX 14, 192, 9
114 SAVE_VSX 15, 208, 9
115 SAVE_VSX 16, 224, 9
116 SAVE_VSX 17, 240, 9
117 SAVE_VSX 18, 256, 9
118 SAVE_VSX 19, 272, 9
119 SAVE_VSX 20, 288, 9
120 SAVE_VSX 21, 304, 9
121 SAVE_VSX 22, 320, 9
122 SAVE_VSX 23, 336, 9
123 SAVE_VSX 24, 352, 9
124 SAVE_VSX 25, 368, 9
125 SAVE_VSX 26, 384, 9
126 SAVE_VSX 27, 400, 9
127 SAVE_VSX 28, 416, 9
128 SAVE_VSX 29, 432, 9
129 SAVE_VSX 30, 448, 9
130 SAVE_VSX 31, 464, 9
134 addi 9, 1, 256
135 RESTORE_VRS 20, 0, 9
136 RESTORE_VRS 21, 16, 9
137 RESTORE_VRS 22, 32, 9
138 RESTORE_VRS 23, 48, 9
139 RESTORE_VRS 24, 64, 9
140 RESTORE_VRS 25, 80, 9
141 RESTORE_VRS 26, 96, 9
142 RESTORE_VRS 27, 112, 9
143 RESTORE_VRS 28, 128, 9
144 RESTORE_VRS 29, 144, 9
145 RESTORE_VRS 30, 160, 9
146 RESTORE_VRS 31, 176, 9
148 RESTORE_VSX 14, 192, 9
149 RESTORE_VSX 15, 208, 9
150 RESTORE_VSX 16, 224, 9
151 RESTORE_VSX 17, 240, 9
152 RESTORE_VSX 18, 256, 9
153 RESTORE_VSX 19, 272, 9
154 RESTORE_VSX 20, 288, 9
155 RESTORE_VSX 21, 304, 9
156 RESTORE_VSX 22, 320, 9
157 RESTORE_VSX 23, 336, 9
158 RESTORE_VSX 24, 352, 9
159 RESTORE_VSX 25, 368, 9
160 RESTORE_VSX 26, 384, 9
161 RESTORE_VSX 27, 400, 9
162 RESTORE_VSX 28, 416, 9
163 RESTORE_VSX 29, 432, 9
164 RESTORE_VSX 30, 448, 9
165 RESTORE_VSX 31, 464, 9
187 ld 0, 16(1)
188 mtlr 0
193 xxlor 0, 32+25, 32+25
195 vadduwm 0, 0, 4
204 vpermxor 12, 12, 0, 25
212 xxlor 32+25, 0, 0
214 vadduwm 9, 9, 13
222 vxor 5, 5, 9
230 xxlor 0, 32+25, 32+25
240 xxlor 32+25, 0, 0
241 vadduwm 0, 0, 4
250 xxlor 0, 32+25, 32+25
252 vpermxor 12, 12, 0, 25
260 xxlor 32+25, 0, 0
262 vadduwm 9, 9, 13
269 xxlor 0, 32+28, 32+28
272 vxor 5, 5, 9
287 xxlor 32+28, 0, 0
290 xxlor 0, 32+25, 32+25
292 vadduwm 0, 0, 5
301 vpermxor 15, 15, 0, 25
310 xxlor 32+25, 0, 0
314 vadduwm 9, 9, 14
322 vxor 4, 4, 9
328 xxlor 0, 32+25, 32+25
338 xxlor 32+25, 0, 0
340 vadduwm 0, 0, 5
349 xxlor 0, 32+25, 32+25
351 vpermxor 15, 15, 0, 25
359 xxlor 32+25, 0, 0
364 vadduwm 9, 9, 14
370 xxlor 0, 32+28, 32+28
375 vxor 4, 4, 9
388 xxlor 32+28, 0, 0
393 vadduwm 0, 0, 4
397 vpermxor 12, 12, 0, 20
402 vadduwm 9, 9, 13
406 vxor 5, 5, 9
413 vadduwm 0, 0, 4
417 vpermxor 12, 12, 0, 22
422 vadduwm 9, 9, 13
426 vxor 5, 5, 9
435 vadduwm 0, 0, 5
439 vpermxor 15, 15, 0, 20
446 vadduwm 9, 9, 14
450 vxor 4, 4, 9
455 vadduwm 0, 0, 5
459 vpermxor 15, 15, 0, 22
466 vadduwm 9, 9, 14
470 vxor 4, 4, 9
483 xxpermdi 32+\a0, 10, 11, 0 # a0, a1, a2, a3
485 xxpermdi 32+\a2, 12, 13, 0 # c0, c1, c2, c3
491 vadduwm \S+0, \S+0, 16-\S
492 vadduwm \S+4, \S+4, 17-\S
493 vadduwm \S+8, \S+8, 18-\S
494 vadduwm \S+12, \S+12, 19-\S
496 vadduwm \S+1, \S+1, 16-\S
497 vadduwm \S+5, \S+5, 17-\S
498 vadduwm \S+9, \S+9, 18-\S
499 vadduwm \S+13, \S+13, 19-\S
501 vadduwm \S+2, \S+2, 16-\S
502 vadduwm \S+6, \S+6, 17-\S
503 vadduwm \S+10, \S+10, 18-\S
504 vadduwm \S+14, \S+14, 19-\S
506 vadduwm \S+3, \S+3, 16-\S
507 vadduwm \S+7, \S+7, 17-\S
508 vadduwm \S+11, \S+11, 18-\S
509 vadduwm \S+15, \S+15, 19-\S
516 add 9, 14, 5
518 lxvw4x 0, 0, 9
519 lxvw4x 1, 17, 9
520 lxvw4x 2, 18, 9
521 lxvw4x 3, 19, 9
522 lxvw4x 4, 20, 9
523 lxvw4x 5, 21, 9
524 lxvw4x 6, 22, 9
525 lxvw4x 7, 23, 9
526 lxvw4x 8, 24, 9
527 lxvw4x 9, 25, 9
528 lxvw4x 10, 26, 9
529 lxvw4x 11, 27, 9
530 lxvw4x 12, 28, 9
531 lxvw4x 13, 29, 9
532 lxvw4x 14, 30, 9
533 lxvw4x 15, 31, 9
535 xxlxor \S+32, \S+32, 0
544 xxlxor \S+38, \S+38, 9
552 stxvw4x \S+32, 0, 16
580 cmpdi 6, 0
585 # r17 - r31 mainly for Write_256 macro.
603 li 14, 0 # offset to inp and outp
605 lxvw4x 48, 0, 3 # vr16, constants
610 # create (0, 1, 2, 3) counters
611 vspltisw 0, 0
615 vmrghw 4, 0, 1
617 vsldoi 30, 4, 5, 8 # vr30 counter, 4 (0, 1, 2, 3)
624 lxvw4x 32+20, 0, 11
643 vadduwm 31, 30, 25 # counter = (0, 1, 2, 3) + (4, 4, 4, 4)
656 xxspltw 32+0, 16, 0
661 xxspltw 32+4, 17, 0
665 xxspltw 32+8, 18, 0
666 xxspltw 32+9, 18, 1
669 xxspltw 32+12, 19, 0
675 xxspltw 32+16, 16, 0
680 xxspltw 32+20, 17, 0
684 xxspltw 32+24, 18, 0
688 xxspltw 32+28, 19, 0
700 xxlor 0, 32+30, 32+30
703 xxlor 32+30, 0, 0
704 TP_4x 0, 1, 2, 3
706 TP_4x 8, 9, 10, 11
709 xxlor 0, 48, 48
717 Add_state 0
718 xxlor 48, 0, 0
722 Write_256 0
724 addi 15, 15, -256 # len -=256
730 TP_4x 16+0, 16+1, 16+2, 16+3
732 TP_4x 16+8, 16+9, 16+10, 16+11
742 addi 15, 15, -256 # len +=256
752 cmpdi 15, 0
762 lxvw4x 48, 0, 3 # vr16, constants
771 lxvw4x 32+20, 0, 11
778 vspltw 0, 16, 0
783 vspltw 4, 17, 0
787 vspltw 8, 18, 0
788 vspltw 9, 18, 1
791 vspltw 12, 19, 0
804 TP_4x 0, 1, 2, 3
806 TP_4x 8, 9, 10, 11
809 Add_state 0
810 Write_256 0
812 addi 15, 15, -256 # len += 256
818 cmpdi 15, 0
831 li 3, 0
838 .long 0x22330011, 0x66774455, 0xaabb8899, 0xeeffccdd
839 .long 0x11223300, 0x55667744, 0x99aabb88, 0xddeeffcc