Lines Matching +full:0 +full:- +full:23
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define HSIO_PLL5G_CFG0 0x0000
12 #define HSIO_PLL5G_CFG1 0x0004
13 #define HSIO_PLL5G_CFG2 0x0008
14 #define HSIO_PLL5G_CFG3 0x000c
15 #define HSIO_PLL5G_CFG4 0x0010
16 #define HSIO_PLL5G_CFG5 0x0014
17 #define HSIO_PLL5G_CFG6 0x0018
18 #define HSIO_PLL5G_STATUS0 0x001c
19 #define HSIO_PLL5G_STATUS1 0x0020
20 #define HSIO_PLL5G_BIST_CFG0 0x0024
21 #define HSIO_PLL5G_BIST_CFG1 0x0028
22 #define HSIO_PLL5G_BIST_CFG2 0x002c
23 #define HSIO_PLL5G_BIST_STAT0 0x0030
24 #define HSIO_PLL5G_BIST_STAT1 0x0034
25 #define HSIO_RCOMP_CFG0 0x0038
26 #define HSIO_RCOMP_STATUS 0x003c
27 #define HSIO_SYNC_ETH_CFG 0x0040
28 #define HSIO_SYNC_ETH_PLL_CFG 0x0048
29 #define HSIO_S1G_DES_CFG 0x004c
30 #define HSIO_S1G_IB_CFG 0x0050
31 #define HSIO_S1G_OB_CFG 0x0054
32 #define HSIO_S1G_SER_CFG 0x0058
33 #define HSIO_S1G_COMMON_CFG 0x005c
34 #define HSIO_S1G_PLL_CFG 0x0060
35 #define HSIO_S1G_PLL_STATUS 0x0064
36 #define HSIO_S1G_DFT_CFG0 0x0068
37 #define HSIO_S1G_DFT_CFG1 0x006c
38 #define HSIO_S1G_DFT_CFG2 0x0070
39 #define HSIO_S1G_TP_CFG 0x0074
40 #define HSIO_S1G_RC_PLL_BIST_CFG 0x0078
41 #define HSIO_S1G_MISC_CFG 0x007c
42 #define HSIO_S1G_DFT_STATUS 0x0080
43 #define HSIO_S1G_MISC_STATUS 0x0084
44 #define HSIO_MCB_S1G_ADDR_CFG 0x0088
45 #define HSIO_S6G_DIG_CFG 0x008c
46 #define HSIO_S6G_DFT_CFG0 0x0090
47 #define HSIO_S6G_DFT_CFG1 0x0094
48 #define HSIO_S6G_DFT_CFG2 0x0098
49 #define HSIO_S6G_TP_CFG0 0x009c
50 #define HSIO_S6G_TP_CFG1 0x00a0
51 #define HSIO_S6G_RC_PLL_BIST_CFG 0x00a4
52 #define HSIO_S6G_MISC_CFG 0x00a8
53 #define HSIO_S6G_OB_ANEG_CFG 0x00ac
54 #define HSIO_S6G_DFT_STATUS 0x00b0
55 #define HSIO_S6G_ERR_CNT 0x00b4
56 #define HSIO_S6G_MISC_STATUS 0x00b8
57 #define HSIO_S6G_DES_CFG 0x00bc
58 #define HSIO_S6G_IB_CFG 0x00c0
59 #define HSIO_S6G_IB_CFG1 0x00c4
60 #define HSIO_S6G_IB_CFG2 0x00c8
61 #define HSIO_S6G_IB_CFG3 0x00cc
62 #define HSIO_S6G_IB_CFG4 0x00d0
63 #define HSIO_S6G_IB_CFG5 0x00d4
64 #define HSIO_S6G_OB_CFG 0x00d8
65 #define HSIO_S6G_OB_CFG1 0x00dc
66 #define HSIO_S6G_SER_CFG 0x00e0
67 #define HSIO_S6G_COMMON_CFG 0x00e4
68 #define HSIO_S6G_PLL_CFG 0x00e8
69 #define HSIO_S6G_ACJTAG_CFG 0x00ec
70 #define HSIO_S6G_GP_CFG 0x00f0
71 #define HSIO_S6G_IB_STATUS0 0x00f4
72 #define HSIO_S6G_IB_STATUS1 0x00f8
73 #define HSIO_S6G_ACJTAG_STATUS 0x00fc
74 #define HSIO_S6G_PLL_STATUS 0x0100
75 #define HSIO_S6G_REVID 0x0104
76 #define HSIO_MCB_S6G_ADDR_CFG 0x0108
77 #define HSIO_HW_CFG 0x010c
78 #define HSIO_HW_QSGMII_CFG 0x0110
79 #define HSIO_HW_QSGMII_STAT 0x0114
80 #define HSIO_CLK_CFG 0x0118
81 #define HSIO_TEMP_SENSOR_CTRL 0x011c
82 #define HSIO_TEMP_SENSOR_CFG 0x0120
83 #define HSIO_TEMP_SENSOR_STAT 0x0124
90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
106 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0))
107 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0)
122 #define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0)
131 #define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16))
132 #define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16)
133 #define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16)
147 #define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0)
149 #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22))
150 #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22)
151 #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22)
166 #define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0))
167 #define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0)
169 #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
170 #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16)
171 #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
172 #define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0))
173 #define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0)
175 #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
176 #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16)
177 #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
178 #define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0))
179 #define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0)
181 #define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23)
194 #define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0))
195 #define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0)
204 #define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0)
218 #define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0)
222 #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20))
223 #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20)
224 #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20)
228 #define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0))
229 #define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0)
236 #define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0)
241 #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0))
242 #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0)
253 #define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0))
254 #define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0)
258 #define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0))
259 #define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0)
261 #define HSIO_SYNC_ETH_CFG_RSZ 0x4
269 #define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0)
271 #define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0)
289 #define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0)
310 #define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
311 #define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0)
327 #define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
328 #define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
340 #define HSIO_S1G_SER_CFG_SER_ENALI BIT(0)
356 #define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0)
371 #define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
372 #define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
375 #define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23)
385 #define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0)
396 #define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
407 #define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
416 #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
417 #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
429 #define HSIO_S1G_MISC_CFG_LANE_RST BIT(0)
437 #define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0)
439 #define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
443 #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0))
444 #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0)
454 #define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0))
455 #define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0)
458 #define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23)
468 #define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0)
479 #define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
490 #define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
499 #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
500 #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
517 #define HSIO_S6G_MISC_CFG_LANE_RST BIT(0)
519 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
520 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23)
521 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
531 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0))
532 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0)
541 #define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0)
543 #define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
561 #define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0)
570 #define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20))
571 #define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20)
572 #define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20)
597 #define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0)
615 #define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0)
638 #define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0))
639 #define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0)
641 #define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18))
642 #define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18)
643 #define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
650 #define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0))
651 #define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0)
653 #define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18))
654 #define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18)
655 #define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
662 #define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0))
663 #define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0)
665 #define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18))
666 #define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18)
667 #define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
674 #define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0))
675 #define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0)
680 #define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
681 #define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23)
682 #define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
697 #define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
698 #define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
703 #define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0))
704 #define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0)
715 #define HSIO_S6G_SER_CFG_SER_ENALI BIT(0)
733 #define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0))
734 #define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0)
749 #define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0)
756 #define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0)
761 #define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0))
762 #define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0)
772 #define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0)
774 #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18))
775 #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18)
776 #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18)
783 #define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0))
784 #define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0)
788 #define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0)
793 #define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
794 #define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
811 #define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0))
812 #define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0)
816 #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0))
817 #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0)
825 #define HSIO_HW_CFG_QSGMII_ENA BIT(0)
830 #define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0)
835 #define HSIO_HW_QSGMII_STAT_SYNC BIT(0)
840 #define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0)
847 #define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0)
852 #define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0))
853 #define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0)
856 #define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0))
857 #define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0)