Lines Matching +full:0 +full:x0564
13 #define DISPC_REVISION 0x0000
14 #define DISPC_SYSCONFIG 0x0010
15 #define DISPC_SYSSTATUS 0x0014
16 #define DISPC_IRQSTATUS 0x0018
17 #define DISPC_IRQENABLE 0x001C
18 #define DISPC_CONTROL 0x0040
19 #define DISPC_CONFIG 0x0044
20 #define DISPC_CAPABLE 0x0048
21 #define DISPC_LINE_STATUS 0x005C
22 #define DISPC_LINE_NUMBER 0x0060
23 #define DISPC_GLOBAL_ALPHA 0x0074
24 #define DISPC_CONTROL2 0x0238
25 #define DISPC_CONFIG2 0x0620
26 #define DISPC_DIVISOR 0x0804
27 #define DISPC_GLOBAL_BUFFER 0x0800
28 #define DISPC_CONTROL3 0x0848
29 #define DISPC_CONFIG3 0x084C
30 #define DISPC_MSTANDBY_CTRL 0x0858
31 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
110 return 0x004C; in DISPC_DEFAULT_COLOR()
112 return 0x0050; in DISPC_DEFAULT_COLOR()
114 return 0x03AC; in DISPC_DEFAULT_COLOR()
116 return 0x0814; in DISPC_DEFAULT_COLOR()
119 return 0; in DISPC_DEFAULT_COLOR()
127 return 0x0054; in DISPC_TRANS_COLOR()
129 return 0x0058; in DISPC_TRANS_COLOR()
131 return 0x03B0; in DISPC_TRANS_COLOR()
133 return 0x0818; in DISPC_TRANS_COLOR()
136 return 0; in DISPC_TRANS_COLOR()
144 return 0x0064; in DISPC_TIMING_H()
147 return 0; in DISPC_TIMING_H()
149 return 0x0400; in DISPC_TIMING_H()
151 return 0x0840; in DISPC_TIMING_H()
154 return 0; in DISPC_TIMING_H()
162 return 0x0068; in DISPC_TIMING_V()
165 return 0; in DISPC_TIMING_V()
167 return 0x0404; in DISPC_TIMING_V()
169 return 0x0844; in DISPC_TIMING_V()
172 return 0; in DISPC_TIMING_V()
180 return 0x006C; in DISPC_POL_FREQ()
183 return 0; in DISPC_POL_FREQ()
185 return 0x0408; in DISPC_POL_FREQ()
187 return 0x083C; in DISPC_POL_FREQ()
190 return 0; in DISPC_POL_FREQ()
198 return 0x0070; in DISPC_DIVISORo()
201 return 0; in DISPC_DIVISORo()
203 return 0x040C; in DISPC_DIVISORo()
205 return 0x0838; in DISPC_DIVISORo()
208 return 0; in DISPC_DIVISORo()
217 return 0x007C; in DISPC_SIZE_MGR()
219 return 0x0078; in DISPC_SIZE_MGR()
221 return 0x03CC; in DISPC_SIZE_MGR()
223 return 0x0834; in DISPC_SIZE_MGR()
226 return 0; in DISPC_SIZE_MGR()
234 return 0x01D4; in DISPC_DATA_CYCLE1()
237 return 0; in DISPC_DATA_CYCLE1()
239 return 0x03C0; in DISPC_DATA_CYCLE1()
241 return 0x0828; in DISPC_DATA_CYCLE1()
244 return 0; in DISPC_DATA_CYCLE1()
252 return 0x01D8; in DISPC_DATA_CYCLE2()
255 return 0; in DISPC_DATA_CYCLE2()
257 return 0x03C4; in DISPC_DATA_CYCLE2()
259 return 0x082C; in DISPC_DATA_CYCLE2()
262 return 0; in DISPC_DATA_CYCLE2()
270 return 0x01DC; in DISPC_DATA_CYCLE3()
273 return 0; in DISPC_DATA_CYCLE3()
275 return 0x03C8; in DISPC_DATA_CYCLE3()
277 return 0x0830; in DISPC_DATA_CYCLE3()
280 return 0; in DISPC_DATA_CYCLE3()
288 return 0x0220; in DISPC_CPR_COEF_R()
291 return 0; in DISPC_CPR_COEF_R()
293 return 0x03BC; in DISPC_CPR_COEF_R()
295 return 0x0824; in DISPC_CPR_COEF_R()
298 return 0; in DISPC_CPR_COEF_R()
306 return 0x0224; in DISPC_CPR_COEF_G()
309 return 0; in DISPC_CPR_COEF_G()
311 return 0x03B8; in DISPC_CPR_COEF_G()
313 return 0x0820; in DISPC_CPR_COEF_G()
316 return 0; in DISPC_CPR_COEF_G()
324 return 0x0228; in DISPC_CPR_COEF_B()
327 return 0; in DISPC_CPR_COEF_B()
329 return 0x03B4; in DISPC_CPR_COEF_B()
331 return 0x081C; in DISPC_CPR_COEF_B()
334 return 0; in DISPC_CPR_COEF_B()
343 return 0x0080; in DISPC_OVL_BASE()
345 return 0x00BC; in DISPC_OVL_BASE()
347 return 0x014C; in DISPC_OVL_BASE()
349 return 0x0300; in DISPC_OVL_BASE()
351 return 0x0500; in DISPC_OVL_BASE()
354 return 0; in DISPC_OVL_BASE()
365 return 0x0000; in DISPC_BA0_OFFSET()
368 return 0x0008; in DISPC_BA0_OFFSET()
371 return 0; in DISPC_BA0_OFFSET()
381 return 0x0004; in DISPC_BA1_OFFSET()
384 return 0x000C; in DISPC_BA1_OFFSET()
387 return 0; in DISPC_BA1_OFFSET()
396 return 0; in DISPC_BA0_UV_OFFSET()
398 return 0x0544; in DISPC_BA0_UV_OFFSET()
400 return 0x04BC; in DISPC_BA0_UV_OFFSET()
402 return 0x0310; in DISPC_BA0_UV_OFFSET()
404 return 0x0118; in DISPC_BA0_UV_OFFSET()
407 return 0; in DISPC_BA0_UV_OFFSET()
416 return 0; in DISPC_BA1_UV_OFFSET()
418 return 0x0548; in DISPC_BA1_UV_OFFSET()
420 return 0x04C0; in DISPC_BA1_UV_OFFSET()
422 return 0x0314; in DISPC_BA1_UV_OFFSET()
424 return 0x011C; in DISPC_BA1_UV_OFFSET()
427 return 0; in DISPC_BA1_UV_OFFSET()
437 return 0x0008; in DISPC_POS_OFFSET()
439 return 0x009C; in DISPC_POS_OFFSET()
442 return 0; in DISPC_POS_OFFSET()
452 return 0x000C; in DISPC_SIZE_OFFSET()
455 return 0x00A8; in DISPC_SIZE_OFFSET()
458 return 0; in DISPC_SIZE_OFFSET()
466 return 0x0020; in DISPC_ATTR_OFFSET()
469 return 0x0010; in DISPC_ATTR_OFFSET()
472 return 0x0070; in DISPC_ATTR_OFFSET()
475 return 0; in DISPC_ATTR_OFFSET()
484 return 0; in DISPC_ATTR2_OFFSET()
486 return 0x0568; in DISPC_ATTR2_OFFSET()
488 return 0x04DC; in DISPC_ATTR2_OFFSET()
490 return 0x032C; in DISPC_ATTR2_OFFSET()
492 return 0x0310; in DISPC_ATTR2_OFFSET()
495 return 0; in DISPC_ATTR2_OFFSET()
503 return 0x0024; in DISPC_FIFO_THRESH_OFFSET()
506 return 0x0014; in DISPC_FIFO_THRESH_OFFSET()
509 return 0x008C; in DISPC_FIFO_THRESH_OFFSET()
512 return 0; in DISPC_FIFO_THRESH_OFFSET()
520 return 0x0028; in DISPC_FIFO_SIZE_STATUS_OFFSET()
523 return 0x0018; in DISPC_FIFO_SIZE_STATUS_OFFSET()
526 return 0x0088; in DISPC_FIFO_SIZE_STATUS_OFFSET()
529 return 0; in DISPC_FIFO_SIZE_STATUS_OFFSET()
537 return 0x002C; in DISPC_ROW_INC_OFFSET()
540 return 0x001C; in DISPC_ROW_INC_OFFSET()
543 return 0x00A4; in DISPC_ROW_INC_OFFSET()
546 return 0; in DISPC_ROW_INC_OFFSET()
554 return 0x0030; in DISPC_PIX_INC_OFFSET()
557 return 0x0020; in DISPC_PIX_INC_OFFSET()
560 return 0x0098; in DISPC_PIX_INC_OFFSET()
563 return 0; in DISPC_PIX_INC_OFFSET()
571 return 0x0034; in DISPC_WINDOW_SKIP_OFFSET()
576 return 0; in DISPC_WINDOW_SKIP_OFFSET()
579 return 0; in DISPC_WINDOW_SKIP_OFFSET()
587 return 0x0038; in DISPC_TABLE_BA_OFFSET()
592 return 0; in DISPC_TABLE_BA_OFFSET()
595 return 0; in DISPC_TABLE_BA_OFFSET()
604 return 0; in DISPC_FIR_OFFSET()
607 return 0x0024; in DISPC_FIR_OFFSET()
610 return 0x0090; in DISPC_FIR_OFFSET()
613 return 0; in DISPC_FIR_OFFSET()
622 return 0; in DISPC_FIR2_OFFSET()
624 return 0x0580; in DISPC_FIR2_OFFSET()
626 return 0x055C; in DISPC_FIR2_OFFSET()
628 return 0x0424; in DISPC_FIR2_OFFSET()
630 return 0x290; in DISPC_FIR2_OFFSET()
633 return 0; in DISPC_FIR2_OFFSET()
642 return 0; in DISPC_PIC_SIZE_OFFSET()
645 return 0x0028; in DISPC_PIC_SIZE_OFFSET()
648 return 0x0094; in DISPC_PIC_SIZE_OFFSET()
651 return 0; in DISPC_PIC_SIZE_OFFSET()
661 return 0; in DISPC_ACCU0_OFFSET()
664 return 0x002C; in DISPC_ACCU0_OFFSET()
667 return 0x0000; in DISPC_ACCU0_OFFSET()
670 return 0; in DISPC_ACCU0_OFFSET()
679 return 0; in DISPC_ACCU2_0_OFFSET()
681 return 0x0584; in DISPC_ACCU2_0_OFFSET()
683 return 0x0560; in DISPC_ACCU2_0_OFFSET()
685 return 0x0428; in DISPC_ACCU2_0_OFFSET()
687 return 0x0294; in DISPC_ACCU2_0_OFFSET()
690 return 0; in DISPC_ACCU2_0_OFFSET()
699 return 0; in DISPC_ACCU1_OFFSET()
702 return 0x0030; in DISPC_ACCU1_OFFSET()
705 return 0x0004; in DISPC_ACCU1_OFFSET()
708 return 0; in DISPC_ACCU1_OFFSET()
717 return 0; in DISPC_ACCU2_1_OFFSET()
719 return 0x0588; in DISPC_ACCU2_1_OFFSET()
721 return 0x0564; in DISPC_ACCU2_1_OFFSET()
723 return 0x042C; in DISPC_ACCU2_1_OFFSET()
725 return 0x0298; in DISPC_ACCU2_1_OFFSET()
728 return 0; in DISPC_ACCU2_1_OFFSET()
732 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
738 return 0; in DISPC_FIR_COEF_H_OFFSET()
741 return 0x0034 + i * 0x8; in DISPC_FIR_COEF_H_OFFSET()
744 return 0x0010 + i * 0x8; in DISPC_FIR_COEF_H_OFFSET()
747 return 0; in DISPC_FIR_COEF_H_OFFSET()
751 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
757 return 0; in DISPC_FIR_COEF_H2_OFFSET()
759 return 0x058C + i * 0x8; in DISPC_FIR_COEF_H2_OFFSET()
761 return 0x0568 + i * 0x8; in DISPC_FIR_COEF_H2_OFFSET()
763 return 0x0430 + i * 0x8; in DISPC_FIR_COEF_H2_OFFSET()
765 return 0x02A0 + i * 0x8; in DISPC_FIR_COEF_H2_OFFSET()
768 return 0; in DISPC_FIR_COEF_H2_OFFSET()
772 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
778 return 0; in DISPC_FIR_COEF_HV_OFFSET()
781 return 0x0038 + i * 0x8; in DISPC_FIR_COEF_HV_OFFSET()
784 return 0x0014 + i * 0x8; in DISPC_FIR_COEF_HV_OFFSET()
787 return 0; in DISPC_FIR_COEF_HV_OFFSET()
791 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
797 return 0; in DISPC_FIR_COEF_HV2_OFFSET()
799 return 0x0590 + i * 8; in DISPC_FIR_COEF_HV2_OFFSET()
801 return 0x056C + i * 0x8; in DISPC_FIR_COEF_HV2_OFFSET()
803 return 0x0434 + i * 0x8; in DISPC_FIR_COEF_HV2_OFFSET()
805 return 0x02A4 + i * 0x8; in DISPC_FIR_COEF_HV2_OFFSET()
808 return 0; in DISPC_FIR_COEF_HV2_OFFSET()
812 /* coef index i = {0, 1, 2, 3, 4,} */
818 return 0; in DISPC_CONV_COEF_OFFSET()
823 return 0x0074 + i * 0x4; in DISPC_CONV_COEF_OFFSET()
826 return 0; in DISPC_CONV_COEF_OFFSET()
830 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
836 return 0; in DISPC_FIR_COEF_V_OFFSET()
838 return 0x0124 + i * 0x4; in DISPC_FIR_COEF_V_OFFSET()
840 return 0x00B4 + i * 0x4; in DISPC_FIR_COEF_V_OFFSET()
843 return 0x0050 + i * 0x4; in DISPC_FIR_COEF_V_OFFSET()
846 return 0; in DISPC_FIR_COEF_V_OFFSET()
850 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
856 return 0; in DISPC_FIR_COEF_V2_OFFSET()
858 return 0x05CC + i * 0x4; in DISPC_FIR_COEF_V2_OFFSET()
860 return 0x05A8 + i * 0x4; in DISPC_FIR_COEF_V2_OFFSET()
862 return 0x0470 + i * 0x4; in DISPC_FIR_COEF_V2_OFFSET()
864 return 0x02E0 + i * 0x4; in DISPC_FIR_COEF_V2_OFFSET()
867 return 0; in DISPC_FIR_COEF_V2_OFFSET()
875 return 0x01AC; in DISPC_PRELOAD_OFFSET()
877 return 0x0174; in DISPC_PRELOAD_OFFSET()
879 return 0x00E8; in DISPC_PRELOAD_OFFSET()
881 return 0x00A0; in DISPC_PRELOAD_OFFSET()
884 return 0; in DISPC_PRELOAD_OFFSET()
892 return 0x0860; in DISPC_MFLAG_THRESHOLD_OFFSET()
894 return 0x0864; in DISPC_MFLAG_THRESHOLD_OFFSET()
896 return 0x0868; in DISPC_MFLAG_THRESHOLD_OFFSET()
898 return 0x086c; in DISPC_MFLAG_THRESHOLD_OFFSET()
900 return 0x0870; in DISPC_MFLAG_THRESHOLD_OFFSET()
903 return 0; in DISPC_MFLAG_THRESHOLD_OFFSET()