Lines Matching +full:rs485 +full:- +full:rx +full:- +full:during +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0+
31 #include <linux/dma-mapping.h>
34 #include <linux/dma/imx-dma.h>
126 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
155 #define UTS_LOOP (1<<12) /* Loop tx and rx */
162 /* We've been assigned a range on the "Low-density serial ports" major */
171 * filling the TX fifo incase CTS has been dropped.
175 #define DRIVER_NAME "IMX-uart"
257 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
258 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
261 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
262 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
263 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
275 writel(val, sport->port.membase + offset); in imx_uart_writel()
280 return readl(sport->port.membase + offset); in imx_uart_readl()
285 return sport->devdata->uts_reg; in imx_uart_uts_reg()
290 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
301 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
302 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
303 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
310 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
311 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
312 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
321 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); in imx_uart_rts_active()
330 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); in imx_uart_rts_inactive()
349 * and UTS[6-3]". in imx_uart_soft_reset()
362 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_soft_reset()
370 sport->idle_counter = 0; in imx_uart_soft_reset()
394 if (sport->dma_is_enabled) { in imx_uart_start_rx()
413 if (sport->tx_state == OFF) in imx_uart_stop_tx()
417 * We are maybe in the SMP context, so if the DMA TX thread is running in imx_uart_stop_tx()
420 if (sport->dma_is_txing) in imx_uart_stop_tx()
436 /* in rs485 mode disable transmitter */ in imx_uart_stop_tx()
437 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
438 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
439 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
441 if (port->rs485.delay_rts_after_send > 0) { in imx_uart_stop_tx()
442 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
443 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
450 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
451 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
454 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
457 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
463 if (!port->rs485_rx_during_tx_gpio) in imx_uart_stop_tx()
466 sport->tx_state = OFF; in imx_uart_stop_tx()
469 sport->tx_state = OFF; in imx_uart_stop_tx()
482 if (sport->dma_is_enabled) { in imx_uart_stop_rx_with_loopback_ctrl()
493 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_stop_rx_with_loopback_ctrl()
494 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_stop_rx_with_loopback_ctrl()
495 sport->have_rtscts && !sport->have_rtsgpio && loopback) { in imx_uart_stop_rx_with_loopback_ctrl()
511 * Stop RX and enable loopback in order to make sure RS485 bus in imx_uart_stop_rx()
522 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
524 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
532 struct tty_port *tport = &sport->port.state->port; in imx_uart_transmit_buffer()
535 if (sport->port.x_char) { in imx_uart_transmit_buffer()
537 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
538 sport->port.icount.tx++; in imx_uart_transmit_buffer()
539 sport->port.x_char = 0; in imx_uart_transmit_buffer()
543 if (kfifo_is_empty(&tport->xmit_fifo) || in imx_uart_transmit_buffer()
544 uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
545 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
549 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
552 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
553 * and the TX IRQ is disabled. in imx_uart_transmit_buffer()
557 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
569 uart_fifo_get(&sport->port, &c)) in imx_uart_transmit_buffer()
572 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in imx_uart_transmit_buffer()
573 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
575 if (kfifo_is_empty(&tport->xmit_fifo)) in imx_uart_transmit_buffer()
576 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
582 struct tty_port *tport = &sport->port.state->port; in imx_uart_dma_tx_callback()
583 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
587 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_dma_tx_callback()
589 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
595 uart_xmit_advance(&sport->port, sport->tx_bytes); in imx_uart_dma_tx_callback()
597 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
599 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
601 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in imx_uart_dma_tx_callback()
602 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
604 if (!kfifo_is_empty(&tport->xmit_fifo) && in imx_uart_dma_tx_callback()
605 !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
607 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
613 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_dma_tx_callback()
619 struct tty_port *tport = &sport->port.state->port; in imx_uart_dma_tx()
620 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
622 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
623 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
627 if (sport->dma_is_txing) in imx_uart_dma_tx()
634 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); in imx_uart_dma_tx()
635 sport->tx_bytes = kfifo_len(&tport->xmit_fifo); in imx_uart_dma_tx()
636 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, in imx_uart_dma_tx()
637 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes); in imx_uart_dma_tx()
639 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
641 dev_err(dev, "DMA mapping error for TX.\n"); in imx_uart_dma_tx()
647 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
649 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); in imx_uart_dma_tx()
652 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
653 desc->callback_param = sport; in imx_uart_dma_tx()
655 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes); in imx_uart_dma_tx()
662 sport->dma_is_txing = 1; in imx_uart_dma_tx()
672 struct tty_port *tport = &sport->port.state->port; in imx_uart_start_tx()
675 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo)) in imx_uart_start_tx()
679 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
684 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
685 if (sport->tx_state == OFF) { in imx_uart_start_tx()
687 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
694 * Since we are about to transmit we can not stop RX in imx_uart_start_tx()
696 * transmitted data being just looped to RX. in imx_uart_start_tx()
698 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && in imx_uart_start_tx()
699 !port->rs485_rx_during_tx_gpio) in imx_uart_start_tx()
702 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
704 if (port->rs485.delay_rts_before_send > 0) { in imx_uart_start_tx()
705 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
706 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
713 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
714 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
716 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
721 * tx-callback. in imx_uart_start_tx()
723 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
729 sport->tx_state = SEND; in imx_uart_start_tx()
732 sport->tx_state = SEND; in imx_uart_start_tx()
735 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
740 if (sport->dma_is_enabled) { in imx_uart_start_tx()
741 if (sport->port.x_char) { in imx_uart_start_tx()
742 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
743 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
751 if (!kfifo_is_empty(&tport->xmit_fifo) && in imx_uart_start_tx()
765 uart_handle_cts_change(&sport->port, usr1); in __imx_uart_rtsint()
766 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
776 uart_port_lock(&sport->port); in imx_uart_rtsint()
780 uart_port_unlock(&sport->port); in imx_uart_rtsint()
789 uart_port_lock(&sport->port); in imx_uart_txint()
791 uart_port_unlock(&sport->port); in imx_uart_txint()
795 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
796 * This is to be called from Rx ISRs only when some bytes were actually
803 * issuing soft reset to the UART (just stop/start of RX does not help). Note
809 /* To detect hardware 0xff flood we monitor RxD line between RX in imx_uart_check_flood()
815 * progress, so we might get RX interrupt later with USR2_WAKE bit in imx_uart_check_flood()
822 * We use 'idle_counter' to ensure that we got at least so many RX in imx_uart_check_flood()
829 * We count interrupts, not chars in 'idle-counter' for simplicity. in imx_uart_check_flood()
834 sport->idle_counter = 0; in imx_uart_check_flood()
835 } else if (++sport->idle_counter > 3) { in imx_uart_check_flood()
836 dev_warn(sport->port.dev, "RX flood detected: soft reset."); in imx_uart_check_flood()
837 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ in imx_uart_check_flood()
844 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
845 u32 usr2, rx; in __imx_uart_rxint() local
852 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) { in __imx_uart_rxint()
854 sport->port.icount.rx++; in __imx_uart_rxint()
856 if (unlikely(rx & URXD_ERR)) { in __imx_uart_rxint()
857 if (rx & URXD_BRK) { in __imx_uart_rxint()
858 sport->port.icount.brk++; in __imx_uart_rxint()
859 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
862 else if (rx & URXD_PRERR) in __imx_uart_rxint()
863 sport->port.icount.parity++; in __imx_uart_rxint()
864 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
865 sport->port.icount.frame++; in __imx_uart_rxint()
866 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
867 sport->port.icount.overrun++; in __imx_uart_rxint()
869 if (rx & sport->port.ignore_status_mask) in __imx_uart_rxint()
872 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
874 if (rx & URXD_BRK) in __imx_uart_rxint()
876 else if (rx & URXD_PRERR) in __imx_uart_rxint()
878 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
880 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
883 sport->port.sysrq = 0; in __imx_uart_rxint()
884 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) { in __imx_uart_rxint()
888 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
891 if (tty_insert_flip_char(port, rx, flg) == 0) in __imx_uart_rxint()
892 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
905 uart_port_lock(&sport->port); in imx_uart_rxint()
909 uart_port_unlock(&sport->port); in imx_uart_rxint()
932 if (sport->dte_mode) in imx_uart_get_hwmctrl()
947 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
952 sport->old_status = status; in imx_uart_mctrl_check()
955 sport->port.icount.rng++; in imx_uart_mctrl_check()
957 sport->port.icount.dsr++; in imx_uart_mctrl_check()
959 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
961 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
963 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
972 uart_port_lock(&sport->port); in imx_uart_int()
984 * actions, for example if a character that sits in the RX FIFO and that in imx_uart_int()
1037 sport->port.icount.overrun++; in imx_uart_int()
1042 uart_port_unlock(&sport->port); in imx_uart_int()
1057 /* If the TX DMA is working, return 0. */ in imx_uart_tx_empty()
1058 if (sport->dma_is_txing) in imx_uart_tx_empty()
1070 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1081 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1113 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1125 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_break_ctl()
1134 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_break_ctl()
1138 * This is our per-port timeout handler, for checking the
1146 if (sport->port.state) { in imx_uart_timeout()
1147 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_timeout()
1149 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_timeout()
1151 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1156 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1157 * [1] the RX DMA buffer is full.
1166 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1167 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1168 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1170 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1176 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1179 uart_port_lock(&sport->port); in imx_uart_dma_rx_callback()
1181 uart_port_unlock(&sport->port); in imx_uart_dma_rx_callback()
1186 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1189 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1191 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1197 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1200 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1201 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1203 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1204 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1207 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1210 uart_port_lock(&sport->port); in imx_uart_dma_rx_callback()
1212 uart_port_unlock(&sport->port); in imx_uart_dma_rx_callback()
1214 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1216 /* CPU claims ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1217 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1221 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1223 /* UART retrieves ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1224 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1228 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1230 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1233 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1234 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1239 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1245 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1246 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1247 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1251 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1252 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1254 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1257 dev_err(dev, "DMA mapping error for RX.\n"); in imx_uart_start_rx_dma()
1258 return -EINVAL; in imx_uart_start_rx_dma()
1262 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1267 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); in imx_uart_start_rx_dma()
1268 return -EINVAL; in imx_uart_start_rx_dma()
1270 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1271 desc->callback_param = sport; in imx_uart_start_rx_dma()
1273 dev_dbg(dev, "RX: prepare for the DMA.\n"); in imx_uart_start_rx_dma()
1274 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1275 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1282 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1289 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1291 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1293 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1297 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1300 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1306 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1310 sport->idle_counter = 0; in imx_uart_clear_rx_errors()
1332 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1333 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1334 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1335 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1336 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1337 kfree(sport->rx_buf); in imx_uart_dma_exit()
1338 sport->rx_buf = NULL; in imx_uart_dma_exit()
1341 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1342 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1343 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1344 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1351 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1355 /* Prepare for RX : */ in imx_uart_dma_init()
1356 chan = dma_request_chan(dev, "rx"); in imx_uart_dma_init()
1359 sport->dma_chan_rx = NULL; in imx_uart_dma_init()
1363 sport->dma_chan_rx = chan; in imx_uart_dma_init()
1366 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1369 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1370 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1372 dev_err(dev, "error in RX dma configuration.\n"); in imx_uart_dma_init()
1376 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1377 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1378 if (!sport->rx_buf) { in imx_uart_dma_init()
1379 ret = -ENOMEM; in imx_uart_dma_init()
1382 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1384 /* Prepare for TX : */ in imx_uart_dma_init()
1385 chan = dma_request_chan(dev, "tx"); in imx_uart_dma_init()
1387 dev_err(dev, "cannot get the TX DMA channel!\n"); in imx_uart_dma_init()
1388 sport->dma_chan_tx = NULL; in imx_uart_dma_init()
1392 sport->dma_chan_tx = chan; in imx_uart_dma_init()
1395 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1398 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1400 dev_err(dev, "error in TX dma configuration."); in imx_uart_dma_init()
1421 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1435 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1438 /* half the RX buffer size */
1449 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1452 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1454 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1473 lockdep_set_subclass(&port->lock, 1); in imx_uart_startup()
1477 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_startup()
1490 if (sport->have_rtscts) in imx_uart_startup()
1498 if (sport->inverted_rx) in imx_uart_startup()
1504 * configure tx polarity before enabling tx in imx_uart_startup()
1506 if (sport->inverted_tx) in imx_uart_startup()
1512 if (sport->dte_mode) in imx_uart_startup()
1520 if (!sport->have_rtscts) in imx_uart_startup()
1523 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1533 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1550 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_startup()
1562 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1563 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1564 if (sport->dma_is_txing) { in imx_uart_shutdown()
1565 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1566 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1567 sport->dma_is_txing = 0; in imx_uart_shutdown()
1569 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1570 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1571 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1573 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1576 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1580 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1584 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1586 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1590 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1595 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1601 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1607 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_shutdown()
1608 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_shutdown()
1609 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_shutdown()
1624 * We have to ensure the tx state machine ends up in OFF. This in imx_uart_shutdown()
1625 * is especially important for rs485 where we must not leave in imx_uart_shutdown()
1633 if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND) in imx_uart_shutdown()
1640 * OFF. In rs485 mode, tx_state might already have been in imx_uart_shutdown()
1646 loops = port->rs485.flags & SER_RS485_ENABLED ? in imx_uart_shutdown()
1647 port->rs485.delay_rts_after_send : 0; in imx_uart_shutdown()
1648 while (sport->tx_state != OFF && loops--) { in imx_uart_shutdown()
1649 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1651 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1654 if (sport->tx_state != OFF) { in imx_uart_shutdown()
1655 dev_warn(sport->port.dev, "unexpected tx_state %d\n", in imx_uart_shutdown()
1656 sport->tx_state); in imx_uart_shutdown()
1662 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_shutdown()
1664 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_shutdown()
1670 sport->tx_state = OFF; in imx_uart_shutdown()
1673 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1675 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1676 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1683 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1685 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1688 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1689 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1690 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1693 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1698 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1713 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1721 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1722 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1723 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1724 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1728 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1733 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1736 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_set_termios()
1746 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1749 if (!sport->have_rtscts) in imx_uart_set_termios()
1750 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1752 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1754 * RTS is mandatory for rs485 operation, so keep in imx_uart_set_termios()
1758 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1763 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1772 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1774 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1776 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1778 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1782 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1783 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1784 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1785 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1786 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1791 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1792 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1793 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1794 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1795 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1800 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1801 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1804 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1805 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1808 * Update the per-port timeout. in imx_uart_set_termios()
1810 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1812 /* custom-baudrate handling */ in imx_uart_set_termios()
1813 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1815 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1817 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1823 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1826 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1832 num -= 1; in imx_uart_set_termios()
1833 denom -= 1; in imx_uart_set_termios()
1856 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1861 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1862 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1864 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_set_termios()
1869 return port->type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1878 port->type = PORT_IMX; in imx_uart_config_port()
1891 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1892 ret = -EINVAL; in imx_uart_verify_port()
1893 if (port->irq != ser->irq) in imx_uart_verify_port()
1894 ret = -EINVAL; in imx_uart_verify_port()
1895 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1896 ret = -EINVAL; in imx_uart_verify_port()
1897 if (port->uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1898 ret = -EINVAL; in imx_uart_verify_port()
1899 if (port->mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1900 ret = -EINVAL; in imx_uart_verify_port()
1901 if (port->iobase != ser->port) in imx_uart_verify_port()
1902 ret = -EINVAL; in imx_uart_verify_port()
1903 if (ser->hub6 != 0) in imx_uart_verify_port()
1904 ret = -EINVAL; in imx_uart_verify_port()
1917 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1920 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1922 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1926 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_poll_init()
1931 * This prevents that a character that already sits in the RX fifo is in imx_uart_poll_init()
1954 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_poll_init()
1995 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
1996 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
1997 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1998 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
1999 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
2003 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
2010 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
2011 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
2012 rs485conf->flags & SER_RS485_RX_DURING_TX) { in imx_uart_rs485_config()
2065 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write()
2071 if (sport->port.sysrq) in imx_uart_console_write()
2074 locked = uart_port_trylock_irqsave(&sport->port, &flags); in imx_uart_console_write()
2076 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_console_write()
2093 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2104 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_console_write()
2144 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2146 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2165 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2185 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2186 co->index = 0; in imx_uart_console_setup()
2187 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2189 return -ENODEV; in imx_uart_console_setup()
2192 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2203 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2206 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2210 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2212 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2221 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_exit()
2223 clk_disable_unprepare(sport->clk_per); in imx_uart_console_exit()
2224 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_exit()
2237 .index = -1,
2262 uart_port_lock_irqsave(&sport->port, &flags); in imx_trigger_start_tx()
2263 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2264 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2265 uart_port_unlock_irqrestore(&sport->port, flags); in imx_trigger_start_tx()
2275 uart_port_lock_irqsave(&sport->port, &flags); in imx_trigger_stop_tx()
2276 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2277 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2278 uart_port_unlock_irqrestore(&sport->port, flags); in imx_trigger_stop_tx()
2290 /* Default RX DMA buffer configuration */
2296 struct device_node *np = pdev->dev.of_node; in imx_uart_probe()
2305 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2307 return -ENOMEM; in imx_uart_probe()
2309 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2313 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe()
2316 sport->port.line = ret; in imx_uart_probe()
2318 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") || in imx_uart_probe()
2319 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */ in imx_uart_probe()
2321 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode"); in imx_uart_probe()
2323 sport->have_rtsgpio = of_property_present(np, "rts-gpios"); in imx_uart_probe()
2325 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx"); in imx_uart_probe()
2327 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx"); in imx_uart_probe()
2329 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { in imx_uart_probe()
2330 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2331 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2333 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2334 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2337 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2338 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2339 sport->port.line); in imx_uart_probe()
2340 return -EINVAL; in imx_uart_probe()
2353 sport->port.dev = &pdev->dev; in imx_uart_probe()
2354 sport->port.mapbase = res->start; in imx_uart_probe()
2355 sport->port.membase = base; in imx_uart_probe()
2356 sport->port.type = PORT_IMX; in imx_uart_probe()
2357 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2358 sport->port.irq = rxirq; in imx_uart_probe()
2359 sport->port.fifosize = 32; in imx_uart_probe()
2360 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2361 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2362 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2363 /* RTS is required to control the RS485 transmitter */ in imx_uart_probe()
2364 if (sport->have_rtscts || sport->have_rtsgpio) in imx_uart_probe()
2365 sport->port.rs485_supported = imx_rs485_supported; in imx_uart_probe()
2366 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2367 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2369 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2370 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2371 return PTR_ERR(sport->gpios); in imx_uart_probe()
2373 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2374 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2375 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2376 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2380 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2381 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2382 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2383 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2387 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2390 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2392 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret); in imx_uart_probe()
2396 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2402 * signal cannot be set low during transmission in case the in imx_uart_probe()
2405 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2406 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2407 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2408 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2409 dev_err(&pdev->dev, in imx_uart_probe()
2410 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2423 * In case RS485 is enabled without GPIO RTS control, the UART IP in imx_uart_probe()
2427 * data from being fed into the RX FIFO, enable loopback mode in in imx_uart_probe()
2428 * UTS register, which disconnects the RX path from external RXD in imx_uart_probe()
2430 * no data can be fed to the RX FIFO that way. in imx_uart_probe()
2432 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2433 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_probe()
2447 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2478 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2479 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2480 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2481 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2488 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2489 dev_name(&pdev->dev), sport); in imx_uart_probe()
2491 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2496 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2497 dev_name(&pdev->dev), sport); in imx_uart_probe()
2499 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2504 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2505 dev_name(&pdev->dev), sport); in imx_uart_probe()
2507 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2512 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2513 dev_name(&pdev->dev), sport); in imx_uart_probe()
2515 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2520 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2524 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2527 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2536 uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2543 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_restore_context()
2544 if (!sport->context_saved) { in imx_uart_restore_context()
2545 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_restore_context()
2549 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2550 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2551 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2552 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2553 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2554 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2555 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2556 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2557 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2558 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2559 sport->context_saved = false; in imx_uart_restore_context()
2560 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_restore_context()
2568 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_save_context()
2569 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2570 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2571 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2572 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2573 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2574 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2575 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2576 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2577 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2578 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2579 sport->context_saved = true; in imx_uart_save_context()
2580 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_save_context()
2596 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2614 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2628 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2642 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2643 disable_irq(sport->port.irq); in imx_uart_suspend()
2645 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2662 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2663 enable_irq(sport->port.irq); in imx_uart_resume()
2665 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2674 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2676 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2683 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2685 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2708 .name = "imx-uart",
2740 MODULE_ALIAS("platform:imx-uart");