Lines Matching +full:rs485 +full:- +full:rts +full:- +full:active +full:- +full:low
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
14 #include <linux/dma-mapping.h>
30 /* All registers are 8-bit width */
119 /* 32-bit global registers only for i.MX7ULP/i.MX8x
124 /* 32-bit register definition */
245 #define DRIVER_NAME "fsl-lpuart"
338 .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */
348 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
349 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
350 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
351 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
352 { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, },
353 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
354 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
364 return (sport->devtype == LS1021A_LPUART || in is_layerscape_lpuart()
365 sport->devtype == LS1028A_LPUART); in is_layerscape_lpuart()
370 return sport->devtype == IMX7ULP_LPUART; in is_imx7ulp_lpuart()
375 return sport->devtype == IMX8ULP_LPUART; in is_imx8ulp_lpuart()
380 return sport->devtype == IMX8QXP_LPUART; in is_imx8qxp_lpuart()
385 switch (port->iotype) { in lpuart32_read()
387 return readl(port->membase + off); in lpuart32_read()
389 return ioread32be(port->membase + off); in lpuart32_read()
398 switch (port->iotype) { in lpuart32_write()
400 writel(val, port->membase + off); in lpuart32_write()
403 iowrite32be(val, port->membase + off); in lpuart32_write()
413 ret = clk_prepare_enable(sport->ipg_clk); in __lpuart_enable_clks()
417 ret = clk_prepare_enable(sport->baud_clk); in __lpuart_enable_clks()
419 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
423 clk_disable_unprepare(sport->baud_clk); in __lpuart_enable_clks()
424 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
433 return clk_get_rate(sport->baud_clk); in lpuart_get_baud_clk_rate()
435 return clk_get_rate(sport->ipg_clk); in lpuart_get_baud_clk_rate()
445 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
447 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
463 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
464 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
477 struct tty_port *tport = &sport->port.state->port; in lpuart_dma_tx()
478 struct scatterlist *sgl = sport->tx_sgl; in lpuart_dma_tx()
479 struct device *dev = sport->port.dev; in lpuart_dma_tx()
480 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx()
483 if (sport->dma_tx_in_progress) in lpuart_dma_tx()
486 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); in lpuart_dma_tx()
487 sport->dma_tx_bytes = kfifo_len(&tport->xmit_fifo); in lpuart_dma_tx()
488 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, in lpuart_dma_tx()
489 ARRAY_SIZE(sport->tx_sgl), sport->dma_tx_bytes); in lpuart_dma_tx()
491 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
498 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, in lpuart_dma_tx()
501 if (!sport->dma_tx_desc) { in lpuart_dma_tx()
502 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
508 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; in lpuart_dma_tx()
509 sport->dma_tx_desc->callback_param = sport; in lpuart_dma_tx()
510 sport->dma_tx_in_progress = true; in lpuart_dma_tx()
511 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); in lpuart_dma_tx()
517 return kfifo_is_empty(&port->state->port.xmit_fifo) || in lpuart_stopped_or_empty()
524 struct scatterlist *sgl = &sport->tx_sgl[0]; in lpuart_dma_tx_complete()
525 struct tty_port *tport = &sport->port.state->port; in lpuart_dma_tx_complete()
526 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx_complete()
529 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_dma_tx_complete()
530 if (!sport->dma_tx_in_progress) { in lpuart_dma_tx_complete()
531 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
535 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx_complete()
538 uart_xmit_advance(&sport->port, sport->dma_tx_bytes); in lpuart_dma_tx_complete()
539 sport->dma_tx_in_progress = false; in lpuart_dma_tx_complete()
540 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
542 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in lpuart_dma_tx_complete()
543 uart_write_wakeup(&sport->port); in lpuart_dma_tx_complete()
545 if (waitqueue_active(&sport->dma_wait)) { in lpuart_dma_tx_complete()
546 wake_up(&sport->dma_wait); in lpuart_dma_tx_complete()
550 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_dma_tx_complete()
552 if (!lpuart_stopped_or_empty(&sport->port)) in lpuart_dma_tx_complete()
555 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
560 switch (sport->port.iotype) { in lpuart_dma_datareg_addr()
562 return sport->port.mapbase + UARTDATA; in lpuart_dma_datareg_addr()
564 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; in lpuart_dma_datareg_addr()
566 return sport->port.mapbase + UARTDR; in lpuart_dma_datareg_addr()
580 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); in lpuart_dma_tx_request()
583 dev_err(sport->port.dev, in lpuart_dma_tx_request()
593 return sport->port.iotype == UPIO_MEM32 || in lpuart_is_32()
594 sport->port.iotype == UPIO_MEM32BE; in lpuart_is_32()
600 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_flush_buffer()
603 if (sport->lpuart_dma_tx_use) { in lpuart_flush_buffer()
604 if (sport->dma_tx_in_progress) { in lpuart_flush_buffer()
605 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], in lpuart_flush_buffer()
606 sport->dma_tx_nents, DMA_TO_DEVICE); in lpuart_flush_buffer()
607 sport->dma_tx_in_progress = false; in lpuart_flush_buffer()
613 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart_flush_buffer()
615 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart_flush_buffer()
617 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
619 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
626 while (!(readb(port->membase + offset) & bit)) in lpuart_wait_bit_set()
646 sport->port.fifosize = 0; in lpuart_poll_init()
648 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_poll_init()
650 writeb(0, sport->port.membase + UARTCR2); in lpuart_poll_init()
652 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_poll_init()
655 sport->port.membase + UARTPFIFO); in lpuart_poll_init()
659 sport->port.membase + UARTCFIFO); in lpuart_poll_init()
662 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
663 readb(sport->port.membase + UARTDR); in lpuart_poll_init()
664 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_poll_init()
667 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_poll_init()
668 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_poll_init()
671 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); in lpuart_poll_init()
672 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_poll_init()
681 writeb(c, port->membase + UARTDR); in lpuart_poll_put_char()
686 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) in lpuart_poll_get_char()
689 return readb(port->membase + UARTDR); in lpuart_poll_get_char()
698 sport->port.fifosize = 0; in lpuart32_poll_init()
700 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_poll_init()
703 lpuart32_write(&sport->port, 0, UARTCTRL); in lpuart32_poll_init()
705 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_poll_init()
708 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); in lpuart32_poll_init()
711 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); in lpuart32_poll_init()
714 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { in lpuart32_poll_init()
715 lpuart32_read(&sport->port, UARTDATA); in lpuart32_poll_init()
716 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); in lpuart32_poll_init()
720 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); in lpuart32_poll_init()
721 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_poll_init()
743 struct uart_port *port = &sport->port; in lpuart_transmit_buffer()
747 readb(port->membase + UARTTCFIFO) < sport->txfifo_size, in lpuart_transmit_buffer()
748 writeb(ch, port->membase + UARTDR)); in lpuart_transmit_buffer()
753 struct tty_port *tport = &sport->port.state->port; in lpuart32_transmit_buffer()
757 if (sport->port.x_char) { in lpuart32_transmit_buffer()
758 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); in lpuart32_transmit_buffer()
759 sport->port.icount.tx++; in lpuart32_transmit_buffer()
760 sport->port.x_char = 0; in lpuart32_transmit_buffer()
764 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart32_transmit_buffer()
765 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
769 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
772 while (txcnt < sport->txfifo_size && in lpuart32_transmit_buffer()
773 uart_fifo_get(&sport->port, &c)) { in lpuart32_transmit_buffer()
774 lpuart32_write(&sport->port, c, UARTDATA); in lpuart32_transmit_buffer()
775 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
780 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in lpuart32_transmit_buffer()
781 uart_write_wakeup(&sport->port); in lpuart32_transmit_buffer()
783 if (kfifo_is_empty(&tport->xmit_fifo)) in lpuart32_transmit_buffer()
784 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
793 temp = readb(port->membase + UARTCR2); in lpuart_start_tx()
794 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); in lpuart_start_tx()
796 if (sport->lpuart_dma_tx_use) { in lpuart_start_tx()
800 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) in lpuart_start_tx()
810 if (sport->lpuart_dma_tx_use) { in lpuart32_start_tx()
827 pm_runtime_mark_last_busy(port->dev); in lpuart_uart_pm()
828 pm_runtime_put_autosuspend(port->dev); in lpuart_uart_pm()
831 pm_runtime_get_sync(port->dev); in lpuart_uart_pm()
841 unsigned char sr1 = readb(port->membase + UARTSR1); in lpuart_tx_empty()
842 unsigned char sfifo = readb(port->membase + UARTSFIFO); in lpuart_tx_empty()
844 if (sport->dma_tx_in_progress) in lpuart_tx_empty()
861 if (sport->dma_tx_in_progress) in lpuart32_tx_empty()
877 uart_port_lock(&sport->port); in lpuart_txint()
879 uart_port_unlock(&sport->port); in lpuart_txint()
885 struct tty_port *port = &sport->port.state->port; in lpuart_rxint()
888 uart_port_lock(&sport->port); in lpuart_rxint()
890 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
892 sport->port.icount.rx++; in lpuart_rxint()
897 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
898 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
900 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart_rxint()
905 sport->port.icount.parity++; in lpuart_rxint()
907 sport->port.icount.frame++; in lpuart_rxint()
912 if (sr & sport->port.ignore_status_mask) { in lpuart_rxint()
918 sr &= sport->port.read_status_mask; in lpuart_rxint()
928 sport->port.sysrq = 0; in lpuart_rxint()
932 sport->port.icount.buf_overrun++; in lpuart_rxint()
937 sport->port.icount.overrun += overrun; in lpuart_rxint()
943 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
944 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
947 uart_unlock_and_check_sysrq(&sport->port); in lpuart_rxint()
954 uart_port_lock(&sport->port); in lpuart32_txint()
956 uart_port_unlock(&sport->port); in lpuart32_txint()
962 struct tty_port *port = &sport->port.state->port; in lpuart32_rxint()
966 uart_port_lock(&sport->port); in lpuart32_rxint()
968 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
970 sport->port.icount.rx++; in lpuart32_rxint()
975 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_rxint()
976 rx = lpuart32_read(&sport->port, UARTDATA); in lpuart32_rxint()
985 if (is_break && uart_handle_break(&sport->port)) in lpuart32_rxint()
988 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart32_rxint()
993 sport->port.icount.parity++; in lpuart32_rxint()
996 sport->port.icount.brk++; in lpuart32_rxint()
998 sport->port.icount.frame++; in lpuart32_rxint()
1002 sport->port.icount.overrun++; in lpuart32_rxint()
1004 if (sr & sport->port.ignore_status_mask) { in lpuart32_rxint()
1010 sr &= sport->port.read_status_mask; in lpuart32_rxint()
1025 if (sport->is_cs7) in lpuart32_rxint()
1029 sport->port.icount.buf_overrun++; in lpuart32_rxint()
1033 uart_unlock_and_check_sysrq(&sport->port); in lpuart32_rxint()
1043 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
1046 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { in lpuart_int()
1047 readb(sport->port.membase + UARTDR); in lpuart_int()
1048 uart_handle_break(&sport->port); in lpuart_int()
1050 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
1054 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) in lpuart_int()
1057 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) in lpuart_int()
1066 while (count--) { in lpuart_handle_sysrq_chars()
1075 struct circ_buf *ring = &sport->rx_ring; in lpuart_handle_sysrq()
1078 if (ring->head < ring->tail) { in lpuart_handle_sysrq()
1079 count = sport->rx_sgl.length - ring->tail; in lpuart_handle_sysrq()
1080 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1081 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1082 ring->tail = 0; in lpuart_handle_sysrq()
1085 if (ring->head > ring->tail) { in lpuart_handle_sysrq()
1086 count = ring->head - ring->tail; in lpuart_handle_sysrq()
1087 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1088 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1089 ring->tail = ring->head; in lpuart_handle_sysrq()
1106 struct tty_port *port = &sport->port.state->port; in lpuart_copy_rx_to_tty()
1109 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_copy_rx_to_tty()
1110 struct circ_buf *ring = &sport->rx_ring; in lpuart_copy_rx_to_tty()
1115 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart_copy_rx_to_tty()
1119 lpuart32_write(&sport->port, sr, UARTSTAT); in lpuart_copy_rx_to_tty()
1122 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1124 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1127 unsigned char sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1133 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1135 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1138 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1141 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1143 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1153 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1156 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1158 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1162 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1166 async_tx_ack(sport->dma_rx_desc); in lpuart_copy_rx_to_tty()
1168 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_copy_rx_to_tty()
1170 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_copy_rx_to_tty()
1172 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_copy_rx_to_tty()
1173 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_copy_rx_to_tty()
1178 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1182 * ring->head points to the end of data already written by the DMA. in lpuart_copy_rx_to_tty()
1183 * ring->tail points to the beginning of data to be read by the in lpuart_copy_rx_to_tty()
1188 ring->head = sport->rx_sgl.length - state.residue; in lpuart_copy_rx_to_tty()
1189 BUG_ON(ring->head > sport->rx_sgl.length); in lpuart_copy_rx_to_tty()
1194 if (sport->port.sysrq) { in lpuart_copy_rx_to_tty()
1200 * At this point ring->head may point to the first byte right after the in lpuart_copy_rx_to_tty()
1202 * 0 <= ring->head <= sport->rx_sgl.length in lpuart_copy_rx_to_tty()
1204 * However ring->tail must always points inside the dma buffer: in lpuart_copy_rx_to_tty()
1205 * 0 <= ring->tail <= sport->rx_sgl.length - 1 in lpuart_copy_rx_to_tty()
1211 if (ring->head < ring->tail) { in lpuart_copy_rx_to_tty()
1212 count = sport->rx_sgl.length - ring->tail; in lpuart_copy_rx_to_tty()
1214 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, in lpuart_copy_rx_to_tty()
1215 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1217 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1218 ring->tail = 0; in lpuart_copy_rx_to_tty()
1219 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1223 if (ring->tail < ring->head) { in lpuart_copy_rx_to_tty()
1224 count = ring->head - ring->tail; in lpuart_copy_rx_to_tty()
1225 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, in lpuart_copy_rx_to_tty()
1226 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1228 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1229 /* Wrap ring->head if needed */ in lpuart_copy_rx_to_tty()
1230 if (ring->head >= sport->rx_sgl.length) in lpuart_copy_rx_to_tty()
1231 ring->head = 0; in lpuart_copy_rx_to_tty()
1232 ring->tail = ring->head; in lpuart_copy_rx_to_tty()
1233 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1236 sport->last_residue = state.residue; in lpuart_copy_rx_to_tty()
1239 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1242 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_copy_rx_to_tty()
1245 if (!sport->dma_idle_int) in lpuart_copy_rx_to_tty()
1246 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); in lpuart_copy_rx_to_tty()
1259 struct dma_chan *chan = sport->dma_rx_chan; in lpuart32_dma_idleint()
1260 struct circ_buf *ring = &sport->rx_ring; in lpuart32_dma_idleint()
1264 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart32_dma_idleint()
1266 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart32_dma_idleint()
1270 ring->head = sport->rx_sgl.length - state.residue; in lpuart32_dma_idleint()
1271 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); in lpuart32_dma_idleint()
1283 sts = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_int()
1284 rxcount = lpuart32_read(&sport->port, UARTWATER); in lpuart32_int()
1287 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) in lpuart32_int()
1290 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) in lpuart32_int()
1293 if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int) in lpuart32_int()
1296 lpuart32_write(&sport->port, sts, UARTSTAT); in lpuart32_int()
1311 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_timer_func()
1312 struct circ_buf *ring = &sport->rx_ring; in lpuart_timer_func()
1317 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_timer_func()
1319 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_timer_func()
1323 ring->head = sport->rx_sgl.length - state.residue; in lpuart_timer_func()
1324 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); in lpuart_timer_func()
1327 if ((count != 0) && (sport->last_residue == state.residue)) in lpuart_timer_func()
1330 mod_timer(&sport->lpuart_timer, in lpuart_timer_func()
1331 jiffies + sport->dma_rx_timeout); in lpuart_timer_func()
1333 if (uart_port_trylock_irqsave(&sport->port, &flags)) { in lpuart_timer_func()
1334 sport->last_residue = state.residue; in lpuart_timer_func()
1335 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_timer_func()
1342 struct circ_buf *ring = &sport->rx_ring; in lpuart_start_rx_dma()
1344 struct tty_port *port = &sport->port.state->port; in lpuart_start_rx_dma()
1345 struct tty_struct *tty = port->tty; in lpuart_start_rx_dma()
1346 struct ktermios *termios = &tty->termios; in lpuart_start_rx_dma()
1347 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_start_rx_dma()
1348 unsigned int bits = tty_get_frame_size(termios->c_cflag); in lpuart_start_rx_dma()
1355 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; in lpuart_start_rx_dma()
1356 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); in lpuart_start_rx_dma()
1357 sport->rx_dma_rng_buf_len = max_t(int, in lpuart_start_rx_dma()
1358 sport->rxfifo_size * 2, in lpuart_start_rx_dma()
1359 sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1364 if (sport->rx_dma_rng_buf_len < 16) in lpuart_start_rx_dma()
1365 sport->rx_dma_rng_buf_len = 16; in lpuart_start_rx_dma()
1367 sport->last_residue = 0; in lpuart_start_rx_dma()
1368 sport->dma_rx_timeout = max(nsecs_to_jiffies( in lpuart_start_rx_dma()
1369 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL); in lpuart_start_rx_dma()
1371 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); in lpuart_start_rx_dma()
1372 if (!ring->buf) in lpuart_start_rx_dma()
1373 return -ENOMEM; in lpuart_start_rx_dma()
1375 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1376 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, in lpuart_start_rx_dma()
1380 dev_err(sport->port.dev, "DMA Rx mapping error\n"); in lpuart_start_rx_dma()
1381 return -EINVAL; in lpuart_start_rx_dma()
1391 dev_err(sport->port.dev, in lpuart_start_rx_dma()
1396 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, in lpuart_start_rx_dma()
1397 sg_dma_address(&sport->rx_sgl), in lpuart_start_rx_dma()
1398 sport->rx_sgl.length, in lpuart_start_rx_dma()
1399 sport->rx_sgl.length / 2, in lpuart_start_rx_dma()
1402 if (!sport->dma_rx_desc) { in lpuart_start_rx_dma()
1403 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); in lpuart_start_rx_dma()
1404 return -EFAULT; in lpuart_start_rx_dma()
1407 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; in lpuart_start_rx_dma()
1408 sport->dma_rx_desc->callback_param = sport; in lpuart_start_rx_dma()
1409 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); in lpuart_start_rx_dma()
1413 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_start_rx_dma()
1415 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); in lpuart_start_rx_dma()
1417 if (sport->dma_idle_int) { in lpuart_start_rx_dma()
1418 unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart_start_rx_dma()
1420 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL); in lpuart_start_rx_dma()
1423 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1424 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1434 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_dma_rx_free()
1437 if (!sport->dma_idle_int) in lpuart_dma_rx_free()
1438 del_timer_sync(&sport->lpuart_timer); in lpuart_dma_rx_free()
1440 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); in lpuart_dma_rx_free()
1441 kfree(sport->rx_ring.buf); in lpuart_dma_rx_free()
1442 sport->rx_ring.tail = 0; in lpuart_dma_rx_free()
1443 sport->rx_ring.head = 0; in lpuart_dma_rx_free()
1444 sport->dma_rx_desc = NULL; in lpuart_dma_rx_free()
1445 sport->dma_rx_cookie = -EINVAL; in lpuart_dma_rx_free()
1449 struct serial_rs485 *rs485) in lpuart_config_rs485() argument
1454 u8 modem = readb(sport->port.membase + UARTMODEM) & in lpuart_config_rs485()
1456 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1458 if (rs485->flags & SER_RS485_ENABLED) { in lpuart_config_rs485()
1459 /* Enable auto RS-485 RTS mode */ in lpuart_config_rs485()
1463 * The hardware defaults to RTS logic HIGH while transfer. in lpuart_config_rs485()
1464 * Switch polarity in case RTS shall be logic HIGH in lpuart_config_rs485()
1466 * Note: UART is assumed to be active high. in lpuart_config_rs485()
1468 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart_config_rs485()
1470 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1474 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1479 struct serial_rs485 *rs485) in lpuart32_config_rs485() argument
1484 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) in lpuart32_config_rs485()
1486 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1488 if (rs485->flags & SER_RS485_ENABLED) { in lpuart32_config_rs485()
1489 /* Enable auto RS-485 RTS mode */ in lpuart32_config_rs485()
1493 * The hardware defaults to RTS logic HIGH while transfer. in lpuart32_config_rs485()
1494 * Switch polarity in case RTS shall be logic HIGH in lpuart32_config_rs485()
1496 * Note: UART is assumed to be active high. in lpuart32_config_rs485()
1498 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart32_config_rs485()
1500 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1504 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1513 reg = readb(port->membase + UARTCR1); in lpuart_get_mctrl()
1536 reg = readb(port->membase + UARTCR1); in lpuart_set_mctrl()
1543 writeb(reg, port->membase + UARTCR1); in lpuart_set_mctrl()
1564 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; in lpuart_break_ctl()
1569 writeb(temp, port->membase + UARTCR2); in lpuart_break_ctl()
1598 /* Disable the TXINV to turn off break and re-enable transmitter. */ in lpuart32_break_ctl()
1611 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1615 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1617 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1619 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1623 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1626 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1627 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1628 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1631 if (uart_console(&sport->port)) in lpuart_setup_watermark()
1632 sport->rx_watermark = 1; in lpuart_setup_watermark()
1633 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1634 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1637 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1646 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1648 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1656 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark()
1660 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_setup_watermark()
1663 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_setup_watermark()
1667 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart32_setup_watermark()
1670 if (uart_console(&sport->port)) in lpuart32_setup_watermark()
1671 sport->rx_watermark = 1; in lpuart32_setup_watermark()
1672 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | in lpuart32_setup_watermark()
1674 lpuart32_write(&sport->port, val, UARTWATER); in lpuart32_setup_watermark()
1676 /* set RTS watermark */ in lpuart32_setup_watermark()
1677 if (!uart_console(&sport->port)) { in lpuart32_setup_watermark()
1678 val = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_setup_watermark()
1679 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); in lpuart32_setup_watermark()
1680 lpuart32_write(&sport->port, val, UARTMODIR); in lpuart32_setup_watermark()
1684 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); in lpuart32_setup_watermark()
1693 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark_enable()
1696 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_setup_watermark_enable()
1701 if (sport->dma_idle_int) in rx_dma_timer_init()
1704 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); in rx_dma_timer_init()
1705 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; in rx_dma_timer_init()
1706 add_timer(&sport->lpuart_timer); in rx_dma_timer_init()
1711 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); in lpuart_request_dma()
1712 if (IS_ERR(sport->dma_tx_chan)) { in lpuart_request_dma()
1713 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1715 PTR_ERR(sport->dma_tx_chan)); in lpuart_request_dma()
1716 sport->dma_tx_chan = NULL; in lpuart_request_dma()
1719 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); in lpuart_request_dma()
1720 if (IS_ERR(sport->dma_rx_chan)) { in lpuart_request_dma()
1721 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1723 PTR_ERR(sport->dma_rx_chan)); in lpuart_request_dma()
1724 sport->dma_rx_chan = NULL; in lpuart_request_dma()
1733 if (uart_console(&sport->port)) in lpuart_tx_dma_startup()
1736 if (!sport->dma_tx_chan) in lpuart_tx_dma_startup()
1739 ret = lpuart_dma_tx_request(&sport->port); in lpuart_tx_dma_startup()
1743 init_waitqueue_head(&sport->dma_wait); in lpuart_tx_dma_startup()
1744 sport->lpuart_dma_tx_use = true; in lpuart_tx_dma_startup()
1746 uartbaud = lpuart32_read(&sport->port, UARTBAUD); in lpuart_tx_dma_startup()
1747 lpuart32_write(&sport->port, in lpuart_tx_dma_startup()
1750 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1751 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1757 sport->lpuart_dma_tx_use = false; in lpuart_tx_dma_startup()
1765 if (uart_console(&sport->port)) in lpuart_rx_dma_startup()
1768 if (!sport->dma_rx_chan) in lpuart_rx_dma_startup()
1772 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); in lpuart_rx_dma_startup()
1778 if (!sport->dma_rx_timeout) in lpuart_rx_dma_startup()
1779 sport->dma_rx_timeout = 1; in lpuart_rx_dma_startup()
1781 sport->lpuart_dma_rx_use = true; in lpuart_rx_dma_startup()
1784 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { in lpuart_rx_dma_startup()
1785 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1787 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1793 sport->lpuart_dma_rx_use = false; in lpuart_rx_dma_startup()
1800 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_hw_setup()
1807 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_hw_setup()
1816 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_startup()
1818 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & in lpuart_startup()
1820 sport->port.fifosize = sport->txfifo_size; in lpuart_startup()
1822 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & in lpuart_startup()
1835 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_hw_disable()
1838 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_hw_disable()
1845 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_configure()
1846 if (!sport->lpuart_dma_rx_use) in lpuart32_configure()
1848 if (!sport->lpuart_dma_tx_use) in lpuart32_configure()
1850 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_configure()
1857 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_hw_setup()
1867 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_hw_setup()
1876 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_startup()
1878 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & in lpuart32_startup()
1880 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1882 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & in lpuart32_startup()
1891 sport->rxfifo_size = 16; in lpuart32_startup()
1892 sport->txfifo_size = 16; in lpuart32_startup()
1893 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1904 if (sport->lpuart_dma_rx_use) { in lpuart_dma_shutdown()
1905 lpuart_dma_rx_free(&sport->port); in lpuart_dma_shutdown()
1906 sport->lpuart_dma_rx_use = false; in lpuart_dma_shutdown()
1909 if (sport->lpuart_dma_tx_use) { in lpuart_dma_shutdown()
1910 if (wait_event_interruptible_timeout(sport->dma_wait, in lpuart_dma_shutdown()
1911 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { in lpuart_dma_shutdown()
1912 sport->dma_tx_in_progress = false; in lpuart_dma_shutdown()
1913 dmaengine_terminate_sync(sport->dma_tx_chan); in lpuart_dma_shutdown()
1915 sport->lpuart_dma_tx_use = false; in lpuart_dma_shutdown()
1918 if (sport->dma_tx_chan) in lpuart_dma_shutdown()
1919 dma_release_channel(sport->dma_tx_chan); in lpuart_dma_shutdown()
1920 if (sport->dma_rx_chan) in lpuart_dma_shutdown()
1921 dma_release_channel(sport->dma_rx_chan); in lpuart_dma_shutdown()
1933 temp = readb(port->membase + UARTCR2); in lpuart_shutdown()
1936 writeb(temp, port->membase + UARTCR2); in lpuart_shutdown()
1953 temp = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_shutdown()
1954 lpuart32_write(&sport->port, temp, UARTSTAT); in lpuart32_shutdown()
1980 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart_set_termios()
1983 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1984 old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_set_termios()
1985 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_set_termios()
1986 cr4 = readb(sport->port.membase + UARTCR4); in lpuart_set_termios()
1987 bdh = readb(sport->port.membase + UARTBDH); in lpuart_set_termios()
1988 modem = readb(sport->port.membase + UARTMODEM); in lpuart_set_termios()
1992 * - (7,e/o,1) in lpuart_set_termios()
1993 * - (8,n,1) in lpuart_set_termios()
1994 * - (8,m/s,1) in lpuart_set_termios()
1995 * - (8,e/o,1) in lpuart_set_termios()
1997 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart_set_termios()
1998 (termios->c_cflag & CSIZE) != CS7) { in lpuart_set_termios()
1999 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
2000 termios->c_cflag |= old_csize; in lpuart_set_termios()
2004 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart_set_termios()
2005 (termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
2008 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
2009 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart_set_termios()
2010 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
2011 termios->c_cflag |= CS8; in lpuart_set_termios()
2017 * When auto RS-485 RTS mode is enabled, in lpuart_set_termios()
2020 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart_set_termios()
2021 termios->c_cflag &= ~CRTSCTS; in lpuart_set_termios()
2023 if (termios->c_cflag & CRTSCTS) in lpuart_set_termios()
2028 termios->c_cflag &= ~CSTOPB; in lpuart_set_termios()
2030 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart_set_termios()
2031 if ((termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
2032 termios->c_cflag |= PARENB; in lpuart_set_termios()
2034 if (termios->c_cflag & PARENB) { in lpuart_set_termios()
2035 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
2037 if (termios->c_cflag & PARODD) in lpuart_set_termios()
2043 if ((termios->c_cflag & CSIZE) == CS8) in lpuart_set_termios()
2045 if (termios->c_cflag & PARODD) in lpuart_set_termios()
2055 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in lpuart_set_termios()
2061 * Since timer function acqures sport->port.lock, need to stop before in lpuart_set_termios()
2064 if (old && sport->lpuart_dma_rx_use) in lpuart_set_termios()
2065 lpuart_dma_rx_free(&sport->port); in lpuart_set_termios()
2067 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_set_termios()
2069 sport->port.read_status_mask = 0; in lpuart_set_termios()
2070 if (termios->c_iflag & INPCK) in lpuart_set_termios()
2071 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; in lpuart_set_termios()
2072 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart_set_termios()
2073 sport->port.read_status_mask |= UARTSR1_FE; in lpuart_set_termios()
2076 sport->port.ignore_status_mask = 0; in lpuart_set_termios()
2077 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
2078 sport->port.ignore_status_mask |= UARTSR1_PE; in lpuart_set_termios()
2079 if (termios->c_iflag & IGNBRK) { in lpuart_set_termios()
2080 sport->port.ignore_status_mask |= UARTSR1_FE; in lpuart_set_termios()
2085 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
2086 sport->port.ignore_status_mask |= UARTSR1_OR; in lpuart_set_termios()
2089 /* update the per-port timeout */ in lpuart_set_termios()
2090 uart_update_timeout(port, termios->c_cflag, baud); in lpuart_set_termios()
2093 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_set_termios()
2097 sport->port.membase + UARTCR2); in lpuart_set_termios()
2099 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios()
2100 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
2105 writeb(cr4 | brfa, sport->port.membase + UARTCR4); in lpuart_set_termios()
2106 writeb(bdh, sport->port.membase + UARTBDH); in lpuart_set_termios()
2107 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
2108 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_set_termios()
2109 writeb(cr1, sport->port.membase + UARTCR1); in lpuart_set_termios()
2110 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_set_termios()
2113 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_set_termios()
2115 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
2119 sport->lpuart_dma_rx_use = false; in lpuart_set_termios()
2122 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_set_termios()
2130 u32 clk = port->uartclk; in __lpuart32_serial_setbrg()
2133 * The idea is to use the best OSR (over-sampling rate) possible. in __lpuart32_serial_setbrg()
2134 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. in __lpuart32_serial_setbrg()
2155 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; in __lpuart32_serial_setbrg()
2159 if (tmp_diff > (baudrate - tmp)) { in __lpuart32_serial_setbrg()
2160 tmp_diff = baudrate - tmp; in __lpuart32_serial_setbrg()
2179 dev_warn(port->dev, in __lpuart32_serial_setbrg()
2188 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; in __lpuart32_serial_setbrg()
2204 __lpuart32_serial_setbrg(&sport->port, baudrate, in lpuart32_serial_setbrg()
2205 sport->lpuart_dma_rx_use, in lpuart32_serial_setbrg()
2206 sport->lpuart_dma_tx_use); in lpuart32_serial_setbrg()
2218 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart32_set_termios()
2220 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_set_termios()
2221 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_set_termios()
2222 modem = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_set_termios()
2223 sport->is_cs7 = false; in lpuart32_set_termios()
2227 * - (7,e/o,1) in lpuart32_set_termios()
2228 * - (8,n,1) in lpuart32_set_termios()
2229 * - (8,m/s,1) in lpuart32_set_termios()
2230 * - (8,e/o,1) in lpuart32_set_termios()
2232 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart32_set_termios()
2233 (termios->c_cflag & CSIZE) != CS7) { in lpuart32_set_termios()
2234 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2235 termios->c_cflag |= old_csize; in lpuart32_set_termios()
2239 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart32_set_termios()
2240 (termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2243 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2244 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart32_set_termios()
2245 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2246 termios->c_cflag |= CS8; in lpuart32_set_termios()
2252 * When auto RS-485 RTS mode is enabled, in lpuart32_set_termios()
2255 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart32_set_termios()
2256 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2258 if (termios->c_cflag & CRTSCTS) in lpuart32_set_termios()
2263 if (termios->c_cflag & CSTOPB) in lpuart32_set_termios()
2268 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart32_set_termios()
2269 if ((termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2270 termios->c_cflag |= PARENB; in lpuart32_set_termios()
2272 if ((termios->c_cflag & PARENB)) { in lpuart32_set_termios()
2273 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2278 if ((termios->c_cflag & CSIZE) == CS8) in lpuart32_set_termios()
2280 if (termios->c_cflag & PARODD) in lpuart32_set_termios()
2290 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); in lpuart32_set_termios()
2296 * Since timer function acqures sport->port.lock, need to stop before in lpuart32_set_termios()
2299 if (old && sport->lpuart_dma_rx_use) in lpuart32_set_termios()
2300 lpuart_dma_rx_free(&sport->port); in lpuart32_set_termios()
2302 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_set_termios()
2304 sport->port.read_status_mask = 0; in lpuart32_set_termios()
2305 if (termios->c_iflag & INPCK) in lpuart32_set_termios()
2306 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; in lpuart32_set_termios()
2307 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart32_set_termios()
2308 sport->port.read_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2311 sport->port.ignore_status_mask = 0; in lpuart32_set_termios()
2312 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2313 sport->port.ignore_status_mask |= UARTSTAT_PE; in lpuart32_set_termios()
2314 if (termios->c_iflag & IGNBRK) { in lpuart32_set_termios()
2315 sport->port.ignore_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2320 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2321 sport->port.ignore_status_mask |= UARTSTAT_OR; in lpuart32_set_termios()
2324 /* update the per-port timeout */ in lpuart32_set_termios()
2325 uart_update_timeout(port, termios->c_cflag, baud); in lpuart32_set_termios()
2333 lpuart32_write(&sport->port, 0, UARTMODIR); in lpuart32_set_termios()
2334 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_set_termios()
2338 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), in lpuart32_set_termios()
2341 lpuart32_write(&sport->port, bd, UARTBAUD); in lpuart32_set_termios()
2344 lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); in lpuart32_set_termios()
2346 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_set_termios()
2347 /* re-enable the CTS if needed */ in lpuart32_set_termios()
2348 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_set_termios()
2351 sport->is_cs7 = true; in lpuart32_set_termios()
2353 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2357 sport->lpuart_dma_rx_use = false; in lpuart32_set_termios()
2360 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_set_termios()
2382 port->type = PORT_LPUART; in lpuart_config_port()
2389 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) in lpuart_verify_port()
2390 ret = -EINVAL; in lpuart_verify_port()
2391 if (port->irq != ser->irq) in lpuart_verify_port()
2392 ret = -EINVAL; in lpuart_verify_port()
2393 if (ser->io_type != UPIO_MEM) in lpuart_verify_port()
2394 ret = -EINVAL; in lpuart_verify_port()
2395 if (port->uartclk / 16 != ser->baud_base) in lpuart_verify_port()
2396 ret = -EINVAL; in lpuart_verify_port()
2397 if (port->iobase != ser->port) in lpuart_verify_port()
2398 ret = -EINVAL; in lpuart_verify_port()
2399 if (ser->hub6 != 0) in lpuart_verify_port()
2400 ret = -EINVAL; in lpuart_verify_port()
2460 writeb(ch, port->membase + UARTDR); in lpuart_console_putchar()
2472 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart_console_write()
2478 locked = uart_port_trylock_irqsave(&sport->port, &flags); in lpuart_console_write()
2480 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_console_write()
2483 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2486 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2488 uart_console_write(&sport->port, s, count, lpuart_console_putchar); in lpuart_console_write()
2491 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_console_write()
2493 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2496 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_console_write()
2502 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart32_console_write()
2508 locked = uart_port_trylock_irqsave(&sport->port, &flags); in lpuart32_console_write()
2510 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_console_write()
2513 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_write()
2516 lpuart32_write(&sport->port, cr, UARTCTRL); in lpuart32_console_write()
2518 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); in lpuart32_console_write()
2521 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_console_write()
2523 lpuart32_write(&sport->port, old_cr, UARTCTRL); in lpuart32_console_write()
2526 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_console_write()
2540 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2547 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2562 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2564 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2568 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2578 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart_console_get_options()
2589 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2596 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2611 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_console_get_options()
2624 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart32_console_get_options()
2641 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) in lpuart_console_setup()
2642 co->index = 0; in lpuart_console_setup()
2644 sport = lpuart_ports[co->index]; in lpuart_console_setup()
2646 return -ENODEV; in lpuart_console_setup()
2661 return uart_set_options(&sport->port, co, baud, parity, bits, flow); in lpuart_console_setup()
2671 .index = -1,
2681 .index = -1,
2687 struct earlycon_device *dev = con->data; in lpuart_early_write()
2689 uart_console_write(&dev->port, s, n, lpuart_console_putchar); in lpuart_early_write()
2694 struct earlycon_device *dev = con->data; in lpuart32_early_write()
2696 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); in lpuart32_early_write()
2702 if (!device->port.membase) in lpuart_early_console_setup()
2703 return -ENODEV; in lpuart_early_console_setup()
2705 device->con->write = lpuart_early_write; in lpuart_early_console_setup()
2712 if (!device->port.membase) in lpuart32_early_console_setup()
2713 return -ENODEV; in lpuart32_early_console_setup()
2715 if (device->port.iotype != UPIO_MEM32) in lpuart32_early_console_setup()
2716 device->port.iotype = UPIO_MEM32BE; in lpuart32_early_console_setup()
2718 device->con->write = lpuart32_early_write; in lpuart32_early_console_setup()
2727 if (!device->port.membase) in ls1028a_early_console_setup()
2728 return -ENODEV; in ls1028a_early_console_setup()
2730 device->port.iotype = UPIO_MEM32; in ls1028a_early_console_setup()
2731 device->con->write = lpuart32_early_write; in ls1028a_early_console_setup()
2734 if (device->port.uartclk && device->baud) in ls1028a_early_console_setup()
2735 __lpuart32_serial_setbrg(&device->port, device->baud, in ls1028a_early_console_setup()
2739 cr = lpuart32_read(&device->port, UARTCTRL); in ls1028a_early_console_setup()
2741 lpuart32_write(&device->port, cr, UARTCTRL); in ls1028a_early_console_setup()
2749 if (!device->port.membase) in lpuart32_imx_early_console_setup()
2750 return -ENODEV; in lpuart32_imx_early_console_setup()
2752 device->port.iotype = UPIO_MEM32; in lpuart32_imx_early_console_setup()
2753 device->port.membase += IMX_REG_OFF; in lpuart32_imx_early_console_setup()
2754 device->con->write = lpuart32_early_write; in lpuart32_imx_early_console_setup()
2758 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2759 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2760 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2761 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2762 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
2763 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2764 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2790 struct uart_port *port = &sport->port; in lpuart_global_reset()
2796 ret = clk_prepare_enable(sport->ipg_clk); in lpuart_global_reset()
2798 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); in lpuart_global_reset()
2809 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart_global_reset()
2812 dev_warn(sport->port.dev, in lpuart_global_reset()
2814 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2819 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; in lpuart_global_reset()
2832 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2838 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); in lpuart_probe()
2839 struct device_node *np = pdev->dev.of_node; in lpuart_probe()
2845 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in lpuart_probe()
2847 return -ENOMEM; in lpuart_probe()
2849 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in lpuart_probe()
2850 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2851 return PTR_ERR(sport->port.membase); in lpuart_probe()
2853 sport->port.membase += sdata->reg_off; in lpuart_probe()
2854 sport->port.mapbase = res->start + sdata->reg_off; in lpuart_probe()
2855 sport->port.dev = &pdev->dev; in lpuart_probe()
2856 sport->port.type = PORT_LPUART; in lpuart_probe()
2857 sport->devtype = sdata->devtype; in lpuart_probe()
2858 sport->rx_watermark = sdata->rx_watermark; in lpuart_probe()
2859 sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || in lpuart_probe()
2864 sport->port.irq = ret; in lpuart_probe()
2865 sport->port.iotype = sdata->iotype; in lpuart_probe()
2867 sport->port.ops = &lpuart32_pops; in lpuart_probe()
2869 sport->port.ops = &lpuart_pops; in lpuart_probe()
2870 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); in lpuart_probe()
2871 sport->port.flags = UPF_BOOT_AUTOCONF; in lpuart_probe()
2874 sport->port.rs485_config = lpuart32_config_rs485; in lpuart_probe()
2876 sport->port.rs485_config = lpuart_config_rs485; in lpuart_probe()
2877 sport->port.rs485_supported = lpuart_rs485_supported; in lpuart_probe()
2879 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in lpuart_probe()
2880 if (IS_ERR(sport->ipg_clk)) { in lpuart_probe()
2881 ret = PTR_ERR(sport->ipg_clk); in lpuart_probe()
2882 return dev_err_probe(&pdev->dev, ret, "failed to get uart ipg clk\n"); in lpuart_probe()
2885 sport->baud_clk = NULL; in lpuart_probe()
2887 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); in lpuart_probe()
2888 if (IS_ERR(sport->baud_clk)) { in lpuart_probe()
2889 ret = PTR_ERR(sport->baud_clk); in lpuart_probe()
2890 return dev_err_probe(&pdev->dev, ret, "failed to get uart baud clk\n"); in lpuart_probe()
2896 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in lpuart_probe()
2900 dev_err(&pdev->dev, "serial%d out of range\n", ret); in lpuart_probe()
2901 return -EINVAL; in lpuart_probe()
2903 sport->port.line = ret; in lpuart_probe()
2908 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_probe()
2910 lpuart_ports[sport->port.line] = sport; in lpuart_probe()
2912 platform_set_drvdata(pdev, &sport->port); in lpuart_probe()
2922 pm_runtime_use_autosuspend(&pdev->dev); in lpuart_probe()
2923 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); in lpuart_probe()
2924 pm_runtime_set_active(&pdev->dev); in lpuart_probe()
2925 pm_runtime_enable(&pdev->dev); in lpuart_probe()
2926 pm_runtime_mark_last_busy(&pdev->dev); in lpuart_probe()
2932 ret = uart_get_rs485_mode(&sport->port); in lpuart_probe()
2936 ret = uart_add_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2940 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, in lpuart_probe()
2948 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2952 pm_runtime_disable(&pdev->dev); in lpuart_probe()
2953 pm_runtime_set_suspended(&pdev->dev); in lpuart_probe()
2954 pm_runtime_dont_use_autosuspend(&pdev->dev); in lpuart_probe()
2963 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_remove()
2967 if (sport->dma_tx_chan) in lpuart_remove()
2968 dma_release_channel(sport->dma_tx_chan); in lpuart_remove()
2970 if (sport->dma_rx_chan) in lpuart_remove()
2971 dma_release_channel(sport->dma_rx_chan); in lpuart_remove()
2973 pm_runtime_disable(&pdev->dev); in lpuart_remove()
2974 pm_runtime_set_suspended(&pdev->dev); in lpuart_remove()
2975 pm_runtime_dont_use_autosuspend(&pdev->dev); in lpuart_remove()
3001 val = lpuart32_read(&sport->port, UARTCTRL); in serial_lpuart_enable_wakeup()
3002 baud = lpuart32_read(&sport->port, UARTBAUD); in serial_lpuart_enable_wakeup()
3005 lpuart32_write(&sport->port, 0, UARTWATER); in serial_lpuart_enable_wakeup()
3008 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); in serial_lpuart_enable_wakeup()
3014 lpuart32_write(&sport->port, val, UARTCTRL); in serial_lpuart_enable_wakeup()
3015 lpuart32_write(&sport->port, baud, UARTBAUD); in serial_lpuart_enable_wakeup()
3017 val = readb(sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3022 writeb(val, sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3028 struct tty_port *port = &sport->port.state->port; in lpuart_uport_is_active()
3035 tty_dev = tty->dev; in lpuart_uport_is_active()
3041 (!console_suspend_enabled && uart_console(&sport->port))) in lpuart_uport_is_active()
3050 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_suspend_noirq()
3072 val = lpuart32_read(&sport->port, UARTSTAT); in lpuart_resume_noirq()
3073 lpuart32_write(&sport->port, val, UARTSTAT); in lpuart_resume_noirq()
3085 uart_suspend_port(&lpuart_reg, &sport->port); in lpuart_suspend()
3088 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3091 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart_suspend()
3093 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart_suspend()
3096 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
3098 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
3100 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3102 if (sport->lpuart_dma_rx_use) { in lpuart_suspend()
3105 * non-idle DMA channels. If port wakeup is enabled or if port in lpuart_suspend()
3110 lpuart_dma_rx_free(&sport->port); in lpuart_suspend()
3113 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3115 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
3116 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, in lpuart_suspend()
3119 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
3120 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
3122 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3125 if (sport->lpuart_dma_tx_use) { in lpuart_suspend()
3126 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3128 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
3130 lpuart32_write(&sport->port, temp, UARTBAUD); in lpuart_suspend()
3132 temp = readb(sport->port.membase + UARTCR5); in lpuart_suspend()
3134 writeb(temp, sport->port.membase + UARTCR5); in lpuart_suspend()
3136 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3137 sport->dma_tx_in_progress = false; in lpuart_suspend()
3138 dmaengine_terminate_sync(sport->dma_tx_chan); in lpuart_suspend()
3140 } else if (pm_runtime_active(sport->port.dev)) { in lpuart_suspend()
3142 pm_runtime_disable(sport->port.dev); in lpuart_suspend()
3143 pm_runtime_set_suspended(sport->port.dev); in lpuart_suspend()
3151 struct tty_port *port = &sport->port.state->port; in lpuart_console_fixup()
3152 struct uart_port *uport = &sport->port; in lpuart_console_fixup()
3163 console_suspend_enabled && uart_console(&sport->port)) { in lpuart_console_fixup()
3165 mutex_lock(&port->mutex); in lpuart_console_fixup()
3167 termios.c_cflag = uport->cons->cflag; in lpuart_console_fixup()
3168 if (port->tty && termios.c_cflag == 0) in lpuart_console_fixup()
3169 termios = port->tty->termios; in lpuart_console_fixup()
3170 uport->ops->set_termios(uport, &termios, NULL); in lpuart_console_fixup()
3171 mutex_unlock(&port->mutex); in lpuart_console_fixup()
3185 } else if (pm_runtime_active(sport->port.dev)) { in lpuart_resume()
3189 pm_runtime_set_active(sport->port.dev); in lpuart_resume()
3190 pm_runtime_enable(sport->port.dev); in lpuart_resume()
3194 uart_resume_port(&lpuart_reg, &sport->port); in lpuart_resume()
3211 .name = "fsl-lpuart",