Lines Matching +full:0 +full:xa010
30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32 #define PCI_DEVICE_ID_OCTPRO 0x0001
33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46 #define PCI_DEVICE_ID_TITAN_200I 0x8028
47 #define PCI_DEVICE_ID_TITAN_400I 0x8048
48 #define PCI_DEVICE_ID_TITAN_800I 0x8088
49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
52 #define PCI_DEVICE_ID_TITAN_100E 0xA010
53 #define PCI_DEVICE_ID_TITAN_200E 0xA012
54 #define PCI_DEVICE_ID_TITAN_400E 0xA013
55 #define PCI_DEVICE_ID_TITAN_800E 0xA014
56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
68 #define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253
69 #define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173
71 #define PCI_VENDOR_ID_AGESTAR 0x5372
72 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
73 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
74 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
76 #define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470
77 #define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853
79 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
80 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
81 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027
82 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
83 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046
84 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121
85 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
86 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145
87 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
88 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
89 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
90 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
91 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
92 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323
93 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
94 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343
95 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
96 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
98 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500 0x7003
99 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG 0x7024
100 #define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025
101 #define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026
104 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
105 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
109 * > 0 - number of ports
110 * = 0 - use board->num_ports
111 * < 0 - error
139 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
143 0xA000, 0x1000) },
145 0xA000, 0x1000) },
147 0xA000, 0x1000) },
149 0xA000, 0x1000) },
162 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" in moan_device()
176 iomem = pcim_iomap(priv->dev, bar, 0); in setup_port()
191 unsigned int bar = 0, offset = board->first_offset; in addidata_apci7800_setup()
240 int rc = 0; in pci_hp_diva_init()
282 if (idx > 0) in pci_hp_diva_setup()
289 offset = 0x18; in pci_hp_diva_setup()
303 if (!(dev->subsystem_device & 0x1000)) in pci_inteli960ni_init()
307 pci_read_config_dword(dev, 0x44, &oldval); in pci_inteli960ni_init()
308 if (oldval == 0x00001000L) { /* RESET value */ in pci_inteli960ni_init()
312 return 0; in pci_inteli960ni_init()
326 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { in pci_plx9050_init()
327 moan_device("no memory in bar 0", dev); in pci_plx9050_init()
328 return 0; in pci_plx9050_init()
331 irq_config = 0x41; in pci_plx9050_init()
334 irq_config = 0x43; in pci_plx9050_init()
346 irq_config = 0x5b; in pci_plx9050_init()
350 p = ioremap(pci_resource_start(dev, 0), 0x80); in pci_plx9050_init()
353 writel(irq_config, p + 0x4c); in pci_plx9050_init()
358 readl(p + 0x4c); in pci_plx9050_init()
361 return 0; in pci_plx9050_init()
368 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) in pci_plx9050_exit()
374 p = ioremap(pci_resource_start(dev, 0), 0x80); in pci_plx9050_exit()
376 writel(0, p + 0x4c); in pci_plx9050_exit()
381 readl(p + 0x4c); in pci_plx9050_exit()
386 #define NI8420_INT_ENABLE_REG 0x38
387 #define NI8420_INT_ENABLE_BIT 0x2000
392 unsigned int bar = 0; in pci_ni8420_exit()
394 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8420_exit()
411 #define MITE_IOWBSR1 0xc4
412 #define MITE_IOWCR1 0xf4
413 #define MITE_LCIMR1 0x08
414 #define MITE_LCIMR2 0x10
421 unsigned int bar = 0; in pci_ni8430_exit()
423 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8430_exit()
444 bar = 0; in sbs_setup()
447 /* first four channels map to 0, 0x100, 0x200, 0x300 */ in sbs_setup()
450 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ in sbs_setup()
451 offset += idx * board->uart_offset + 0xC00; in sbs_setup()
466 #define OCT_REG_CR_OFF 0x500
472 p = pci_ioremap_bar(dev, 0); in sbs_init()
477 writeb(0x10, p + OCT_REG_CR_OFF); in sbs_init()
479 writeb(0x0, p + OCT_REG_CR_OFF); in sbs_init()
482 writeb(0x4, p + OCT_REG_CR_OFF); in sbs_init()
485 return 0; in sbs_init()
496 p = pci_ioremap_bar(dev, 0); in sbs_exit()
499 writeb(0, p + OCT_REG_CR_OFF); in sbs_exit()
521 * Note: all 10x cards have PCI device ids 0x10..
522 * all 20x cards have PCI device ids 0x20..
530 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
531 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
538 switch (dev->device & 0xfff8) { in pci_siig10x_init()
540 data = 0xffdf; in pci_siig10x_init()
543 data = 0xf7ff; in pci_siig10x_init()
546 data = 0xfffb; in pci_siig10x_init()
550 p = ioremap(pci_resource_start(dev, 0), 0x80); in pci_siig10x_init()
554 writew(readw(p + 0x28) & data, p + 0x28); in pci_siig10x_init()
555 readw(p + 0x28); in pci_siig10x_init()
557 return 0; in pci_siig10x_init()
560 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
561 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
568 pci_read_config_byte(dev, 0x6f, &data); in pci_siig20x_init()
569 pci_write_config_byte(dev, 0x6f, data & 0xef); in pci_siig20x_init()
572 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || in pci_siig20x_init()
573 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { in pci_siig20x_init()
574 pci_read_config_byte(dev, 0x73, &data); in pci_siig20x_init()
575 pci_write_config_byte(dev, 0x73, data & 0xef); in pci_siig20x_init()
577 return 0; in pci_siig20x_init()
582 unsigned int type = dev->device & 0xff00; in pci_siig_init()
584 if (type == 0x1000) in pci_siig_init()
586 if (type == 0x2000) in pci_siig_init()
597 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; in pci_siig_setup()
604 return setup_port(priv, port, bar, offset, 0); in pci_siig_setup()
613 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
617 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
618 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
619 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
620 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
621 0xD079, 0
625 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
626 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
627 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
628 0xB157, 0
632 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
633 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
656 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) in pci_timedia_probe()
658 if ((dev->subsystem_device & 0x00f0) >= 0x70) { in pci_timedia_probe()
664 return 0; in pci_timedia_probe()
672 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { in pci_timedia_init()
674 for (j = 0; ids[j]; j++) in pci_timedia_init()
678 return 0; in pci_timedia_init()
690 unsigned int bar = 0, offset = board->first_offset; in pci_timedia_setup()
693 case 0: in pci_timedia_setup()
694 bar = 0; in pci_timedia_setup()
698 bar = 0; in pci_timedia_setup()
727 case 0: in titan_400l_800l_setup()
744 return 0; in pci_xircom_init()
750 unsigned int bar = 0; in pci_ni8420_init()
752 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8420_init()
754 return 0; in pci_ni8420_init()
766 return 0; in pci_ni8420_init()
769 #define MITE_IOWBSR1_WSIZE 0xa
770 #define MITE_IOWBSR1_WIN_OFFSET 0x800
774 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
781 unsigned int bar = 0; in pci_ni8430_init()
783 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { in pci_ni8430_init()
785 return 0; in pci_ni8430_init()
798 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) in pci_ni8430_init()
806 /* Enable IO Bus Interrupt 0 */ in pci_ni8430_init()
813 return 0; in pci_ni8430_init()
817 #define NI8430_PORTCON 0x0f
855 (priv->dev->subsystem_device & 0xff00) == 0x3000) { in pci_netmos_9900_setup()
857 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) in pci_netmos_9900_setup()
861 return setup_port(priv, port, bar, 0, board->reg_shift); in pci_netmos_9900_setup()
881 pi = c & 0xff; in pci_netmos_9900_numports()
886 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { in pci_netmos_9900_numports()
887 /* two possibilities: 0x30ps encodes number of parallel and in pci_netmos_9900_numports()
888 * serial ports, or 0x1000 indicates *something*. This is not in pci_netmos_9900_numports()
890 * to offer all functionality on functions 0..2, while still in pci_netmos_9900_numports()
893 sub_serports = dev->subsystem_device & 0xf; in pci_netmos_9900_numports()
894 if (sub_serports > 0) in pci_netmos_9900_numports()
898 return 0; in pci_netmos_9900_numports()
902 return 0; in pci_netmos_9900_numports()
907 /* subdevice 0x00PS means <P> parallel, <S> serial */ in pci_netmos_init()
908 unsigned int num_serial = dev->subsystem_device & 0xf; in pci_netmos_init()
912 return 0; in pci_netmos_init()
915 dev->subsystem_device == 0x0299) in pci_netmos_init()
916 return 0; in pci_netmos_init()
930 if (num_serial == 0) { in pci_netmos_init()
949 #define ITE_887x_MISCR 0x9c
950 #define ITE_887x_INTCBAR 0x78
951 #define ITE_887x_UARTBAR 0x7c
952 #define ITE_887x_PS0BAR 0x10
953 #define ITE_887x_POSIO0 0x60
967 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
978 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { in pci_ite887x_init()
990 if (ret != 0xff) { in pci_ite887x_init()
1004 type = inb(iobase->start + 0x18) & 0x0f; in pci_ite887x_init()
1007 case 0x2: /* ITE8871 (1P) */ in pci_ite887x_init()
1008 case 0xa: /* ITE8875 (1P) */ in pci_ite887x_init()
1009 ret = 0; in pci_ite887x_init()
1011 case 0xe: /* ITE8872 (2S1P) */ in pci_ite887x_init()
1014 case 0x6: /* ITE8873 (1S) */ in pci_ite887x_init()
1017 case 0x8: /* ITE8874 (2S) */ in pci_ite887x_init()
1026 for (i = 0; i < ret; i++) { in pci_ite887x_init()
1028 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), in pci_ite887x_init()
1030 ioport &= 0x0000FF00; /* the actual base address */ in pci_ite887x_init()
1031 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), in pci_ite887x_init()
1037 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ in pci_ite887x_init()
1043 /* disable interrupts (UARTx_Routing[3:0]) */ in pci_ite887x_init()
1044 miscr &= ~(0xf << (12 - 4 * i)); in pci_ite887x_init()
1051 if (ret <= 0) { in pci_ite887x_init()
1062 /* the ioport is bit 0-15 in POSIO0R */ in pci_ite887x_exit()
1064 ioport &= 0xffff; in pci_ite887x_exit()
1072 #define PCI_VENDOR_ID_ENDRUN 0x7401
1073 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1077 /* OxSemi Tornado devices are all 0xCxxx */ in pci_oxsemi_tornado_p()
1079 (dev->device & 0xf000) != 0xc000) in pci_oxsemi_tornado_p()
1082 /* EndRun devices are all 0xExxx */ in pci_oxsemi_tornado_p()
1084 (dev->device & 0xf000) != 0xe000) in pci_oxsemi_tornado_p()
1097 unsigned int number_uarts = 0; in pci_oxsemi_tornado_init()
1100 return 0; in pci_oxsemi_tornado_init()
1102 p = pci_iomap(dev, 0, 5); in pci_oxsemi_tornado_init()
1108 if (deviceID == 0x07000200) { in pci_oxsemi_tornado_init()
1120 #define OXSEMI_TORNADO_TCR_MASK 0xf
1121 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1122 #define OXSEMI_TORNADO_CPR_MIN 0x008
1123 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1134 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1219 for (i = 0; i < ARRAY_SIZE(p); i++) { in pci_oxsemi_tornado_get_divisor()
1225 tc = p[i][0]; in pci_oxsemi_tornado_get_divisor()
1234 if (srem == 0) { in pci_oxsemi_tornado_get_divisor()
1247 quot % 2 == 0) { in pci_oxsemi_tornado_get_divisor()
1326 #define QPCR_TEST_FOR1 0x3F
1327 #define QPCR_TEST_GET1 0x00
1328 #define QPCR_TEST_FOR2 0x40
1329 #define QPCR_TEST_GET2 0x40
1330 #define QPCR_TEST_FOR3 0x80
1331 #define QPCR_TEST_GET3 0x40
1332 #define QPCR_TEST_FOR4 0xC0
1333 #define QPCR_TEST_GET4 0x80
1335 #define QOPR_CLOCK_X1 0x0000
1336 #define QOPR_CLOCK_X2 0x0001
1337 #define QOPR_CLOCK_X4 0x0002
1338 #define QOPR_CLOCK_X8 0x0003
1339 #define QOPR_CLOCK_RATE_MASK 0x0003
1345 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1347 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1354 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1355 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1356 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1357 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1358 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1359 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1360 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1361 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1362 { 0, }
1371 outb(0xBF, base + UART_LCR); in pci_quatech_rqopr()
1383 outb(0xBF, base + UART_LCR); in pci_quatech_wqopr()
1395 outb(0xBF, base + UART_LCR); in pci_quatech_rqmcr()
1397 outb(val | 0x10, base + UART_SCR); in pci_quatech_rqmcr()
1411 outb(0xBF, base + UART_LCR); in pci_quatech_wqmcr()
1413 outb(val | 0x10, base + UART_SCR); in pci_quatech_wqmcr()
1425 outb(0xBF, base + UART_LCR); in pci_quatech_has_qmcr()
1427 if (val & 0x20) { in pci_quatech_has_qmcr()
1428 outb(0x80, UART_LCR); in pci_quatech_has_qmcr()
1429 if (!(inb(UART_SCR) & 0x20)) { in pci_quatech_has_qmcr()
1434 return 0; in pci_quatech_has_qmcr()
1443 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1447 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1451 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1455 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1460 return 0; in pci_quatech_test()
1468 if (pci_quatech_test(port) < 0) in pci_quatech_clock()
1510 int rs422 = 0; in pci_quatech_rs422()
1513 return 0; in pci_quatech_rs422()
1515 pci_quatech_wqmcr(port, 0xFF); in pci_quatech_rs422()
1534 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); in pci_quatech_init()
1537 unsigned long base = pci_resource_start(dev, 0); in pci_quatech_init()
1541 outl(inl(base + 0x38) | 0x00002000, base + 0x38); in pci_quatech_init()
1542 tmp = inl(base + 0x3c); in pci_quatech_init()
1543 outl(tmp | 0x01000000, base + 0x3c); in pci_quatech_init()
1544 outl(tmp & ~0x01000000, base + 0x3c); in pci_quatech_init()
1547 return 0; in pci_quatech_init()
1595 ret = setup_port(priv, port, idx, 0, board->reg_shift); in ce4100_serial_setup()
1609 return setup_port(priv, port, 2, idx * 8, 0); in pci_omegapci_setup()
1624 /* RTS will control by MCR if this bit is 0 */
1637 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); in pci_fintek_rs485_config()
1655 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); in pci_fintek_rs485_config()
1657 return 0; in pci_fintek_rs485_config()
1677 config_base = 0x40 + 0x08 * idx; in pci_fintek_setup()
1682 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); in pci_fintek_setup()
1697 return 0; in pci_fintek_setup()
1717 case 0x1104: /* 4 ports */ in pci_fintek_init()
1718 case 0x1108: /* 8 ports */ in pci_fintek_init()
1719 max_port = dev->device & 0xff; in pci_fintek_init()
1721 case 0x1112: /* 12 ports */ in pci_fintek_init()
1729 bar_data[0] = pci_resource_start(dev, 5); in pci_fintek_init()
1733 for (i = 0; i < max_port; ++i) { in pci_fintek_init()
1734 /* UART0 configuration offset start from 0x40 */ in pci_fintek_init()
1735 config_base = 0x40 + 0x08 * i; in pci_fintek_init()
1738 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; in pci_fintek_init()
1741 pci_write_config_byte(dev, config_base + 0x00, 0x01); in pci_fintek_init()
1744 pci_write_config_byte(dev, config_base + 0x01, 0x33); in pci_fintek_init()
1747 pci_write_config_byte(dev, config_base + 0x04, in pci_fintek_init()
1748 (u8)(iobase & 0xff)); in pci_fintek_init()
1751 pci_write_config_byte(dev, config_base + 0x05, in pci_fintek_init()
1752 (u8)((iobase & 0xff00) >> 8)); in pci_fintek_init()
1754 pci_write_config_byte(dev, config_base + 0x06, dev->irq); in pci_fintek_init()
1760 pci_write_config_byte(dev, config_base + 0x07, 0x01); in pci_fintek_init()
1795 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; in pci_fintek_f815xxa_setup()
1798 return 0; in pci_fintek_f815xxa_setup()
1806 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) in pci_fintek_f815xxa_init()
1810 case 0x1204: /* 4 ports */ in pci_fintek_f815xxa_init()
1811 case 0x1208: /* 8 ports */ in pci_fintek_f815xxa_init()
1812 max_port = dev->device & 0xff; in pci_fintek_f815xxa_init()
1814 case 0x1212: /* 12 ports */ in pci_fintek_f815xxa_init()
1822 pci_write_config_byte(dev, 0x209, 0x40); in pci_fintek_f815xxa_init()
1824 for (i = 0; i < max_port; ++i) { in pci_fintek_f815xxa_init()
1825 /* UART0 configuration offset start from 0x2A0 */ in pci_fintek_f815xxa_init()
1826 config_base = 0x2A0 + 0x08 * i; in pci_fintek_f815xxa_init()
1829 pci_write_config_byte(dev, config_base + 0x01, 0x33); in pci_fintek_f815xxa_init()
1832 pci_write_config_byte(dev, config_base + 0, 0x01); in pci_fintek_f815xxa_init()
1869 * port registers could return 0 momentarily. Functions like in kt_serial_in()
1872 * setting IER register inadvertently to 0, if the value read in kt_serial_in()
1873 * is 0, double check with ier value in uart_8250_port and use in kt_serial_in()
1879 if (val == 0) in kt_serial_in()
1903 return 0; in pci_eg20t_init()
1947 #define CH384_XINT_ENABLE_REG 0xEB
1948 #define CH384_XINT_ENABLE_BIT 0x02
1959 case 0x3853: /* 8 ports */ in pci_wch_ch38x_init()
1966 iobase = pci_resource_start(dev, 0); in pci_wch_ch38x_init()
1981 iobase = pci_resource_start(dev, 0); in pci_wch_ch38x_exit()
1982 outb(0x0, iobase + CH384_XINT_ENABLE_REG); in pci_wch_ch38x_exit()
1998 bar = 0; in pci_sunix_setup()
2007 return setup_port(priv, port, bar, offset, 0); in pci_sunix_setup()
2010 #define MOXA_PUART_GPIO_EN 0x09
2011 #define MOXA_PUART_GPIO_OUT 0x0A
2015 #define MOXA_RS232 0x00
2016 #define MOXA_RS422 0x01
2017 #define MOXA_RS485_4W 0x0B
2018 #define MOXA_RS485_2W 0x0F
2019 #define MOXA_UIR_OFFSET 0x04
2020 #define MOXA_EVEN_RS_MASK GENMASK(3, 0)
2024 MOXA_SUPP_RS232 = BIT(0),
2037 return FIELD_GET(0x00F0, device); in moxa_get_nports()
2055 switch (dev->device & 0x0F00) { in pci_moxa_supported_rs()
2056 case 0x0000: in pci_moxa_supported_rs()
2057 case 0x0600: in pci_moxa_supported_rs()
2059 case 0x0100: in pci_moxa_supported_rs()
2061 case 0x0300: in pci_moxa_supported_rs()
2064 return 0; in pci_moxa_supported_rs()
2086 return 0; in pci_moxa_set_interface()
2102 for (i = 0; i < num_ports; ++i) in pci_moxa_init()
2139 return setup_port(priv, port, bar, offset, 0); in pci_moxa_setup()
2199 .subvendor = 0xe4bf,
2601 .device = 0x4027,
2609 .device = 0x4028,
2617 .device = 0x4029,
2625 .device = 0x4019,
2633 .device = 0x4016,
2641 .device = 0x4015,
2649 .device = 0x400A,
2657 .device = 0x400E,
2665 .device = 0x400C,
2673 .device = 0x400B,
2681 .device = 0x400F,
2689 .device = 0x4010,
2697 .device = 0x4011,
2705 .device = 0x401D,
2713 .device = 0x401E,
2721 .device = 0x4013,
2729 .device = 0x4017,
2737 .device = 0x4018,
2745 .device = 0x4026,
2753 .device = 0x4021,
2761 .device = 0x8811,
2769 .device = 0x8812,
2777 .device = 0x8813,
2785 .device = 0x8814,
2792 .vendor = 0x10DB,
2793 .device = 0x8027,
2800 .vendor = 0x10DB,
2801 .device = 0x8028,
2808 .vendor = 0x10DB,
2809 .device = 0x8029,
2816 .vendor = 0x10DB,
2817 .device = 0x800C,
2824 .vendor = 0x10DB,
2825 .device = 0x800D,
2934 .vendor = 0x1c29,
2935 .device = 0x1104,
2942 .vendor = 0x1c29,
2943 .device = 0x1108,
2950 .vendor = 0x1c29,
2951 .device = 0x1112,
2969 .vendor = 0x1c29,
2970 .device = 0x1204,
2977 .vendor = 0x1c29,
2978 .device = 0x1208,
2985 .vendor = 0x1c29,
2986 .device = 0x1212,
3044 pbn_default = 0,
3195 * offset 0x10 from the UART base, while UART_IER is defined as 1
3636 .uart_offset = 0x400,
3643 .uart_offset = 0x400,
3650 .uart_offset = 0x400,
3661 .first_offset = 0x03,
3665 * This board uses the size of PCI Base region 0 to
3678 .uart_offset = 0x200,
3679 .first_offset = 0x1000,
3685 .uart_offset = 0x200,
3686 .first_offset = 0x1000,
3692 .uart_offset = 0x200,
3693 .first_offset = 0x1000,
3699 .uart_offset = 0x200,
3700 .first_offset = 0x1000,
3714 .first_offset = 0x10000,
3721 .reg_shift = 0,
3722 .first_offset = 0x20178,
3732 .uart_offset = 0x40,
3734 .first_offset = 0x200,
3740 .uart_offset = 0x40,
3742 .first_offset = 0x200,
3748 .uart_offset = 0x40,
3750 .first_offset = 0x200,
3774 .uart_offset = 0x10,
3775 .first_offset = 0x800,
3781 .uart_offset = 0x10,
3782 .first_offset = 0x800,
3788 .uart_offset = 0x10,
3789 .first_offset = 0x800,
3795 .uart_offset = 0x10,
3796 .first_offset = 0x800,
3805 .uart_offset = 0x200,
3806 .first_offset = 0x1000,
3812 .uart_offset = 0x200,
3813 .first_offset = 0x1000,
3819 .uart_offset = 0x200,
3820 .first_offset = 0x1000,
3826 .uart_offset = 0x200,
3827 .first_offset = 0x1000,
3839 .uart_offset = 0x200,
3856 .first_offset = 0x40,
3862 .first_offset = 0x40,
3868 .first_offset = 0x40,
3890 .first_offset = 0xC0,
3897 .first_offset = 0xC0,
3904 .first_offset = 0x00,
3909 .uart_offset = 0x8,
3914 .uart_offset = 0x8,
3919 .uart_offset = 0x8,
3924 .uart_offset = 0x8,
3929 .uart_offset = 0x8,
3935 .uart_offset = 0x200,
3936 .first_offset = 0x1000,
3942 .uart_offset = 0x200,
3943 .first_offset = 0x1000,
3949 .uart_offset = 0x200,
3950 .first_offset = 0x1000,
3956 .uart_offset = 0x200,
3957 .first_offset = 0x1000,
3963 .uart_offset = 0x200,
3969 .uart_offset = 0x200,
3975 .uart_offset = 0x200,
3980 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3983 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3987 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3988 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3989 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3993 { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), },
3995 { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), },
3997 { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), },
4000 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
4001 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
4002 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
4003 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
4004 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
4005 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
4008 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
4009 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
4010 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
4011 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
4012 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
4013 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
4014 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
4015 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
4016 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
4017 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
4018 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
4019 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
4020 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
4043 (dev->class & 0xff) > 6) in serial_pci_is_class_communication()
4046 return 0; in serial_pci_is_class_communication()
4052 * serial specs. Returns 0 on success, -ENODEV on failure.
4070 num_iomem = num_port = 0; in serial_pci_guess_board()
4071 for (i = 0; i < PCI_STD_NUM_BARS; i++) { in serial_pci_guess_board()
4082 * If there is 1 or 0 iomem regions, and exactly one port, in serial_pci_guess_board()
4089 return 0; in serial_pci_guess_board()
4098 num_port = 0; in serial_pci_guess_board()
4099 for (i = 0; i < PCI_STD_NUM_BARS; i++) { in serial_pci_guess_board()
4112 return 0; in serial_pci_guess_board()
4148 * <0 - error in pciserial_init_ports()
4149 * 0 - use board->num_ports in pciserial_init_ports()
4150 * >0 - number of ports in pciserial_init_ports()
4154 if (rc < 0) { in pciserial_init_ports()
4171 memset(&uart, 0, sizeof(uart)); in pciserial_init_ports()
4176 uart.port.irq = 0; in pciserial_init_ports()
4187 if (rc < 0) { in pciserial_init_ports()
4193 uart.port.irq = pci_irq_vector(dev, 0); in pciserial_init_ports()
4198 for (i = 0; i < nr_ports; i++) { in pciserial_init_ports()
4206 if (priv->line[i] < 0) { in pciserial_init_ports()
4231 for (i = 0; i < priv->nr; i++) in pciserial_detach_ports()
4253 for (i = 0; i < priv->nr; i++) in pciserial_suspend_ports()
4254 if (priv->line[i] >= 0) in pciserial_suspend_ports()
4275 for (i = 0; i < priv->nr; i++) in pciserial_resume_ports()
4276 if (priv->line[i] >= 0) in pciserial_resume_ports()
4346 if (rc == 0 && serial_pci_matches(board, &tmp)) in pciserial_init_one()
4356 return 0; in pciserial_init_one()
4374 return 0; in pciserial_suspend_one()
4393 return 0; in pciserial_resume_one()
4402 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4404 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4406 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4408 /* Advantech also use 0x3618 and 0xf618 */
4410 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4413 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4417 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4421 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4425 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4429 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4433 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4437 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4441 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4445 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4449 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4453 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4457 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4461 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4465 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4469 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4473 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4477 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4481 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4485 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 /* Unknown card - subdevice 0x1584 */
4530 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4532 /* Unknown card - subdevice 0x1588 */
4535 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4539 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4553 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4557 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4561 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4565 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4569 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4573 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4577 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4584 0x10b5, 0x106a, 0, 0,
4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 0, 0,
4656 0, 0,
4658 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 * For now just used the hex ID 0x950a.
4668 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4670 0, 0, pbn_b0_2_115200 },
4671 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4673 0, 0, pbn_b0_2_115200 },
4674 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4816 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4828 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4829 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4831 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4832 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4834 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4835 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4837 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4838 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4845 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4863 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4866 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4869 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5028 0, 0, pbn_computone_4 },
5031 0, 0, pbn_computone_8 },
5034 0, 0, pbn_computone_6 },
5037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5040 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5047 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
5050 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
5053 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
5056 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
5059 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
5062 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5065 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5115 * ACR = 0x10, and as such are not currently fully supported.
5118 0x1204, 0x0004, 0, 0,
5121 0x1208, 0x0004, 0, 0,
5124 0x1402, 0x0002, 0, 0,
5127 0x1404, 0x0004, 0, 0,
5130 0x1208, 0x0004, 0, 0,
5134 0x1204, 0x0004, 0, 0,
5137 0x1208, 0x0004, 0, 0,
5140 0x1208, 0x0004, 0, 0,
5146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5167 0xE4BF, PCI_ANY_ID, 0, 0,
5174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5190 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5191 0x1048, 0x1500, 0, 0,
5195 0xFF00, 0, 0, 0,
5202 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5235 0, 0,
5241 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5259 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5261 0, 0,
5266 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5268 0, 0,
5273 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5275 0, 0,
5281 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5283 0, 0,
5285 { PCI_VENDOR_ID_INTASHIELD, 0x0BA2,
5287 0, 0,
5289 { PCI_VENDOR_ID_INTASHIELD, 0x0BA3,
5291 0, 0,
5296 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5298 0, 0,
5300 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5302 0, 0,
5307 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5309 0, 0,
5314 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5316 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5318 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5320 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5325 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5327 0, 0,
5332 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5334 0, 0,
5339 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5341 0, 0,
5343 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5345 0, 0,
5347 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5349 0, 0,
5354 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5356 0, 0,
5361 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5363 0, 0,
5365 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5367 0, 0,
5369 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5371 0, 0,
5376 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5378 0, 0,
5383 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5385 0, 0,
5387 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5389 0, 0,
5394 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5396 0, 0,
5398 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5400 0, 0,
5402 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5404 0, 0,
5409 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5411 0, 0,
5413 { PCI_VENDOR_ID_INTASHIELD, 0x0C42,
5415 0, 0,
5417 { PCI_VENDOR_ID_INTASHIELD, 0x0C43,
5419 0, 0,
5424 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5426 0, 0,
5431 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5433 0, 0,
5435 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5437 0, 0,
5439 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5441 0, 0,
5446 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5448 0, 0,
5453 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5455 0, 0,
5457 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5459 0, 0,
5461 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5463 0, 0,
5468 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5470 0, 0,
5472 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5474 0, 0,
5476 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5478 0, 0,
5483 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5485 0, 0,
5487 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5489 0, 0,
5491 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5493 0, 0,
5498 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5500 0, 0,
5502 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5504 0, 0,
5506 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5508 0, 0,
5513 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5515 0, 0,
5517 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5519 0, 0,
5524 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5526 0, 0,
5528 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5530 0, 0,
5535 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5537 0, 0,
5539 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5541 0, 0,
5546 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5548 0, 0,
5553 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5555 0, 0,
5560 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5562 0, 0,
5567 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5569 0, 0,
5574 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5576 0, 0,
5581 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5583 0, 0,
5588 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5590 0, 0,
5595 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5597 0, 0,
5599 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5601 0, 0,
5606 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5608 0, 0,
5613 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5615 0, 0,
5617 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5619 0, 0,
5621 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5623 0, 0,
5628 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5630 0, 0,
5632 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5634 0, 0,
5639 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5641 0, 0,
5643 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5645 0, 0,
5650 { PCI_VENDOR_ID_INTASHIELD, 0x4026,
5652 0, 0,
5657 { PCI_VENDOR_ID_INTASHIELD, 0x4021,
5659 0, 0,
5667 0, 0, pbn_b2_4_921600 },
5670 0, 0, pbn_b2_8_921600 },
5680 PCI_VENDOR_ID_MAINPINE, 0x0200,
5681 0, 0, pbn_b0_2_115200 },
5684 PCI_VENDOR_ID_MAINPINE, 0x0300,
5685 0, 0, pbn_b0_4_115200 },
5688 PCI_VENDOR_ID_MAINPINE, 0x0400,
5689 0, 0, pbn_b0_2_115200 },
5692 PCI_VENDOR_ID_MAINPINE, 0x0500,
5693 0, 0, pbn_b0_4_115200 },
5696 PCI_VENDOR_ID_MAINPINE, 0x0600,
5697 0, 0, pbn_b0_2_115200 },
5700 PCI_VENDOR_ID_MAINPINE, 0x0700,
5701 0, 0, pbn_b0_4_115200 },
5704 PCI_VENDOR_ID_MAINPINE, 0x0800,
5705 0, 0, pbn_b0_8_115200 },
5708 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5709 0, 0, pbn_b0_2_115200 },
5712 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5713 0, 0, pbn_b0_4_115200 },
5716 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5717 0, 0, pbn_b0_8_115200 },
5720 PCI_VENDOR_ID_MAINPINE, 0x2000,
5721 0, 0, pbn_b0_1_115200 },
5724 PCI_VENDOR_ID_MAINPINE, 0x2100,
5725 0, 0, pbn_b0_1_115200 },
5728 PCI_VENDOR_ID_MAINPINE, 0x2200,
5729 0, 0, pbn_b0_2_115200 },
5732 PCI_VENDOR_ID_MAINPINE, 0x2300,
5733 0, 0, pbn_b0_2_115200 },
5736 PCI_VENDOR_ID_MAINPINE, 0x2400,
5737 0, 0, pbn_b0_4_115200 },
5740 PCI_VENDOR_ID_MAINPINE, 0x2500,
5741 0, 0, pbn_b0_4_115200 },
5744 PCI_VENDOR_ID_MAINPINE, 0x2600,
5745 0, 0, pbn_b0_8_115200 },
5748 PCI_VENDOR_ID_MAINPINE, 0x2700,
5749 0, 0, pbn_b0_8_115200 },
5752 PCI_VENDOR_ID_MAINPINE, 0x3000,
5753 0, 0, pbn_b0_1_115200 },
5756 PCI_VENDOR_ID_MAINPINE, 0x3100,
5757 0, 0, pbn_b0_1_115200 },
5760 PCI_VENDOR_ID_MAINPINE, 0x3200,
5761 0, 0, pbn_b0_2_115200 },
5764 PCI_VENDOR_ID_MAINPINE, 0x3300,
5765 0, 0, pbn_b0_2_115200 },
5768 PCI_VENDOR_ID_MAINPINE, 0x3400,
5769 0, 0, pbn_b0_4_115200 },
5772 PCI_VENDOR_ID_MAINPINE, 0x3500,
5773 0, 0, pbn_b0_4_115200 },
5776 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5777 0, 0, pbn_b0_8_115200 },
5780 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5781 0, 0, pbn_b0_8_115200 },
5787 { PCI_VENDOR_ID_PASEMI, 0xa004,
5788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5896 0,
5897 0,
5904 0,
5905 0,
5912 0,
5913 0,
5920 0,
5921 0,
5928 0,
5929 0,
5936 0,
5937 0,
5944 0,
5945 0,
5952 0,
5953 0,
5960 0,
5961 0,
5968 0,
5969 0,
5976 0,
5977 0,
5984 0,
5985 0,
5992 0,
5993 0,
6000 0,
6001 0,
6008 0,
6009 0,
6016 0,
6017 0,
6024 0,
6025 0,
6032 0,
6033 0,
6040 0,
6041 0,
6045 PCI_VENDOR_ID_IBM, 0x0299,
6046 0, 0, pbn_b0_bt_2_115200 },
6055 0xA000, 0x1000,
6056 0, 0, pbn_b0_1_115200 },
6060 0xA000, 0x1000,
6061 0, 0, pbn_b0_1_115200 },
6064 0xA000, 0x1000,
6065 0, 0, pbn_b0_1_115200 },
6068 0xA000, 0x1000,
6069 0, 0, pbn_b0_1_115200 },
6072 0xA000, 0x1000,
6073 0, 0, pbn_b0_1_115200 },
6076 0xA000, 0x3002,
6077 0, 0, pbn_NETMOS9900_2s_115200 },
6084 0xA000, 0x1000,
6085 0, 0, pbn_b0_1_115200 },
6088 0xA000, 0x3002,
6089 0, 0, pbn_b0_bt_2_115200 },
6092 0xA000, 0x3004,
6093 0, 0, pbn_b0_bt_4_115200 },
6099 0xA000, 0x1000,
6100 0, 0, pbn_b0_1_115200 },
6104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6126 0, 0, pbn_b0_bt_2_115200 },
6134 0, 0, pbn_b0_bt_4_115200 },
6138 0, 0, pbn_b0_bt_2_115200 },
6142 0, 0, pbn_b0_bt_4_115200 },
6146 0, 0, pbn_wch382_2 },
6150 0, 0, pbn_wch384_4 },
6154 0, 0, pbn_wch384_8 },
6158 { PCI_VENDOR_ID_REALTEK, 0x816a,
6160 0, 0, pbn_b0_1_115200 },
6162 { PCI_VENDOR_ID_REALTEK, 0x816b,
6164 0, 0, pbn_b0_1_115200 },
6167 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6168 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6169 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6170 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6171 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6172 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6175 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6176 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6179 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6188 0xffff00, pbn_default },
6192 0xffff00, pbn_default },
6196 0xffff00, pbn_default },
6197 { 0, }