Lines Matching +full:50 +full:- +full:mhz
1 /* SPDX-License-Identifier: GPL-2.0 */
8 /* (SCSI chip set used Tekram ASIC TRM-S1040) */
31 #define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
175 /* cmd->result */
296 /* --------- ------------- ---------------------------- */
297 /* 07-05 0 RSVD Reversed. Always 0. */
299 /* 03-00 0 OFFSET[03:00] Offset number from 0 to 15 */
306 #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */
315 /* --------- ------------- --------------------------- */
316 /* 07-06 0 RSVD Reversed. Always read 0 */
318 /* 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI */
326 /* at the Fast-20 rate. */
331 /* at the Fast-10 rate (or Fast-40 w/ LVDS). */
333 /* 02-00 0 PERIOD[2:0]/ Synchronous SCSI Transfer Rate. */
336 /* Rate for Fast-20 and Fast-10. */
340 /* For Fast-10 bit ALTPD = 0 and LVDS = 0 */
343 /* 000 100ns, 10.0 MHz */
344 /* 001 150ns, 6.6 MHz */
345 /* 010 200ns, 5.0 MHz */
346 /* 011 250ns, 4.0 MHz */
347 /* 100 300ns, 3.3 MHz */
348 /* 101 350ns, 2.8 MHz */
349 /* 110 400ns, 2.5 MHz */
350 /* 111 450ns, 2.2 MHz */
352 /* For Fast-20 bit ALTPD = 1 and LVDS = 0 */
355 /* 000 50ns, 20.0 MHz */
356 /* 001 75ns, 13.3 MHz */
357 /* 010 100ns, 10.0 MHz */
358 /* 011 125ns, 8.0 MHz */
359 /* 100 150ns, 6.6 MHz */
360 /* 101 175ns, 5.7 MHz */
361 /* 110 200ns, 5.0 MHz */
362 /* 111 250ns, 4.0 MHz KG: Maybe 225ns, 4.4 MHz */
364 /* For Fast-40 bit ALTPD = 0 and LVDS = 1 */
367 /* 000 25ns, 40.0 MHz */
368 /* 001 50ns, 20.0 MHz */
369 /* 010 75ns, 13.3 MHz */
370 /* 011 100ns, 10.0 MHz */
371 /* 100 125ns, 8.0 MHz */
372 /* 101 150ns, 6.6 MHz */
373 /* 110 175ns, 5.7 MHz */
374 /* 111 200ns, 5.0 MHz */
422 /* ---- ---------------------------------------- */
433 /* 50 Initiator transfer information out sequence without ATN */
511 #define GLOBALINT 0x20 /* DMA_INTEN bit 0-4 set */
557 #define CON5068 0x10 /* External 50/68 pin connected (low) */
559 #define CON50 0x04 /* Internal 50 pin connected (low!) */
563 #define TRM_S1040_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */
575 /* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */