415  *		010	100ns, 10.0 MHz
417  *		100	150ns,  6.6 MHz
425  *		011	100ns, 10.0 MHz
426  *		100	125ns,  8.0 MHz
433 /* real period:48ns,76ns,100ns,124ns,148ns,176ns,200ns,248ns */
435 static u16 clock_speed[] = { 200, 133, 100, 80, 67, 58, 50, 40 };
1849  * KG: Currently called from  StatusPhase1 ()
1889 	 * KG: We need to drain the buffers before we draw any conclusions!  in data_out_phase0()
1897 	 * KG: Stop DMA engine pushing more data into the SCSI FIFO  in data_out_phase0()
1915 		 * KG: Right, we can't just rely on the SCSI_COUNTER, because this  in data_out_phase0()
1957 		/* KG: What is this supposed to be useful for? WIDE padding stuff? */  in data_out_phase0()
1966 		 * KG: Oops again. Same thinko as above: The SCSI might have been  in data_out_phase0()
1972 		 * KG: This is nonsense: We have been WRITING data to the bus  in data_out_phase0()
1988 			/* KG: Most ugly hack! Apparently, this works around a chip bug */  in data_out_phase0()
2031 	 * KG: DataIn is much more tricky than DataOut. When the device is finished  in data_in_phase0()
2053 		 * KG: We should wait for the DMA FIFO to be empty ...  in data_in_phase0()
2100 		/* KG: Less than or equal to 4 bytes can not be transferred via DMA, it seems. */  in data_in_phase0()
2180 		 * KG: This was in DATAOUT. Does it also belong here?  in data_in_phase0()
2196 			 * KG: Seems to be correct ...  in data_in_phase0()
2200 		/* KG: This should not be needed any more! */  in data_in_phase0()
2228 	/* KG: The target may decide to disconnect: Empty FIFO before! */  in data_in_phase0()
2264 		 * KG: What should we do: Use SCSI Cmd 0x90/0x92?  in data_io_transfer()
2382 		 * KG: despite the fact that we are using 16 bits I/O ops  in data_io_transfer()
3498 	/* KG: Can this prevent crap sense data ? */  in request_sense()
3525 		waiting_set_timer(acb, HZ / 100);  in request_sense()