Lines Matching +full:8 +full:- +full:n +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
24 #define MD(x) (1 << (x))
25 #define MODE_COMMON (1 << 31)
34 {"LmMnSCBPTR", 0x20, 16, MD(0)|MD(1)|MD(2)|MD(3)|MD(4) },
35 {"LmMnDDBPTR", 0x22, 16, MD(0)|MD(1)|MD(2)|MD(3)|MD(4) },
41 {"LmXMTPRIMCS", 0x44, 8, MODE_COMMON },
42 {"LmCONSTAT", 0x45, 8, MODE_COMMON },
43 {"LmMnDMAERRS", 0x46, 8, MD(0)|MD(1) },
44 {"LmMnSGDMAERRS", 0x47, 8, MD(0)|MD(1) },
45 {"LmMnEXPHDRP", 0x48, 8, MD(0) },
46 {"LmMnSASAALIGN", 0x48, 8, MD(1) },
47 {"LmMnMSKHDRP", 0x49, 8, MD(0) },
48 {"LmMnSTPALIGN", 0x49, 8, MD(1) },
49 {"LmMnRCVHDRP", 0x4A, 8, MD(0) },
50 {"LmMnXMTHDRP", 0x4A, 8, MD(1) },
51 {"LmALIGNMODE", 0x4B, 8, MD(1) },
53 {"LmMnXMTCNT", 0x4C, 32, MD(1) },
56 {"LmMnACKOFS", 0x58, 8, MD(1) },
57 {"LmMnXFRLVL", 0x59, 8, MD(0)|MD(1) },
58 {"LmMnSGDMACTL", 0x5A, 8, MD(0)|MD(1) },
59 {"LmMnSGDMASTAT", 0x5B, 8, MD(0)|MD(1) },
60 {"LmMnDDMACTL", 0x5C, 8, MD(0)|MD(1) },
61 {"LmMnDDMASTAT", 0x5D, 8, MD(0)|MD(1) },
62 {"LmMnDDMAMODE", 0x5E, 16, MD(0)|MD(1) },
63 {"LmMnPIPECTL", 0x61, 8, MD(0)|MD(1) },
64 {"LmMnACTSCB", 0x62, 16, MD(0)|MD(1) },
65 {"LmMnSGBHADR", 0x64, 8, MD(0)|MD(1) },
66 {"LmMnSGBADR", 0x65, 8, MD(0)|MD(1) },
67 {"LmMnSGDCNT", 0x66, 8, MD(0)|MD(1) },
68 {"LmMnSGDMADR", 0x68, 32, MD(0)|MD(1) },
69 {"LmMnSGDMADR", 0x6C, 32, MD(0)|MD(1) },
70 {"LmMnXFRCNT", 0x70, 32, MD(0)|MD(1) },
71 {"LmMnXMTCRC", 0x74, 32, MD(1) },
74 {"LmMnDPSEL", 0x7B, 8, MD(0)|MD(1) },
75 {"LmDPTHSTAT", 0x7C, 8, MODE_COMMON },
76 {"LmMnHOLDLVL", 0x7D, 8, MD(0) },
77 {"LmMnSATAFS", 0x7E, 8, MD(1) },
78 {"LmMnCMPLTSTAT", 0x7F, 8, MD(0)|MD(1) },
81 {"LmGPRMINT", 0x88, 8, MODE_COMMON },
86 {"LmMnXMTHDRSIZE",0x92, 8, MD(1) },
87 {"LmMnXMTSIZE", 0x93, 8, MD(1) },
90 {"LmMnXMTROFS", 0x98, 32, MD(1) },
99 {"LmAWTCTL", 0xBA, 8, MODE_COMMON },
101 {"LmMnXMTSTAT", 0xC4, 8, MD(1) },
102 {"LmHWTSTATEN", 0xC5, 8, MODE_COMMON },
103 {"LmMnRRDYRC", 0xC6, 8, MD(0) },
104 {"LmMnRRDYTC", 0xC6, 8, MD(1) },
105 {"LmHWTSTAT", 0xC7, 8, MODE_COMMON },
106 {"LmMnDATABUFADR",0xC8, 16, MD(0)|MD(1) },
107 {"LmDWSSTATUS", 0xCB, 8, MODE_COMMON },
108 {"LmMnACTSTAT", 0xCE, 16, MD(0)|MD(1) },
109 {"LmMnREQSCB", 0xD2, 16, MD(0)|MD(1) },
111 {"LmRCVASTAT", 0xD9, 8, MODE_COMMON },
112 {"LmINTDIS1", 0xDA, 8, MODE_COMMON },
113 {"LmPSTORESEL", 0xDB, 8, MODE_COMMON },
122 {"OOB_BFLTR" ,0x100, 8, MD(5)},
134 {"OOB_XMIT_BURST" ,0x118, 8, MD(5)},
135 {"OOB_SEND_PAIRS" ,0x119, 8, MD(5)},
136 {"OOB_INIT_IDLE" ,0x11A, 8, MD(5)},
137 {"OOB_INIT_NEGO" ,0x11C, 8, MD(5)},
138 {"OOB_SAS_IDLE" ,0x11E, 8, MD(5)},
139 {"OOB_SAS_NEGO" ,0x120, 8, MD(5)},
140 {"OOB_WAKE_IDLE" ,0x122, 8, MD(5)},
141 {"OOB_WAKE_NEGO" ,0x124, 8, MD(5)},
142 {"OOB_DATA_KBITS" ,0x126, 8, MD(5)},
149 {"OOB_SIG_GEN" ,0x140, 8, MD(5)},
150 {"OOB_XMIT" ,0x141, 8, MD(5)},
151 {"FUNCTION_MAKS" ,0x142, 8, MD(5)},
152 {"OOB_MODE" ,0x143, 8, MD(5)},
153 {"CURRENT_STATUS" ,0x144, 8, MD(5)},
154 {"SPEED_MASK" ,0x145, 8, MD(5)},
155 {"PRIM_COUNT" ,0x146, 8, MD(5)},
156 {"OOB_SIGNALS" ,0x148, 8, MD(5)},
157 {"OOB_DATA_DET" ,0x149, 8, MD(5)},
158 {"OOB_TIME_OUT" ,0x14C, 8, MD(5)},
159 {"OOB_TIMER_ENABLE" ,0x14D, 8, MD(5)},
160 {"OOB_STATUS" ,0x14E, 8, MD(5)},
161 {"HOT_PLUG_DELAY" ,0x150, 8, MD(5)},
162 {"RCD_DELAY" ,0x151, 8, MD(5)},
163 {"COMSAS_TIMER" ,0x152, 8, MD(5)},
164 {"SNTT_DELAY" ,0x153, 8, MD(5)},
165 {"SPD_CHNG_DELAY" ,0x154, 8, MD(5)},
166 {"SNLT_DELAY" ,0x155, 8, MD(5)},
167 {"SNWT_DELAY" ,0x156, 8, MD(5)},
168 {"ALIGN_DELAY" ,0x157, 8, MD(5)},
169 {"INT_ENABLE_0" ,0x158, 8, MD(5)},
170 {"INT_ENABLE_1" ,0x159, 8, MD(5)},
171 {"INT_ENABLE_2" ,0x15A, 8, MD(5)},
172 {"INT_ENABLE_3" ,0x15B, 8, MD(5)},
173 {"OOB_TEST_REG" ,0x15C, 8, MD(5)},
174 {"PHY_CONTROL_0" ,0x160, 8, MD(5)},
175 {"PHY_CONTROL_1" ,0x161, 8, MD(5)},
176 {"PHY_CONTROL_2" ,0x162, 8, MD(5)},
177 {"PHY_CONTROL_3" ,0x163, 8, MD(5)},
178 {"PHY_OOB_CAL_TX" ,0x164, 8, MD(5)},
179 {"PHY_OOB_CAL_RX" ,0x165, 8, MD(5)},
180 {"OOB_PHY_CAL_TX" ,0x166, 8, MD(5)},
181 {"OOB_PHY_CAL_RX" ,0x167, 8, MD(5)},
182 {"PHY_CONTROL_4" ,0x168, 8, MD(5)},
183 {"PHY_TEST" ,0x169, 8, MD(5)},
184 {"PHY_PWR_CTL" ,0x16A, 8, MD(5)},
185 {"PHY_PWR_DELAY" ,0x16B, 8, MD(5)},
186 {"OOB_SM_CON" ,0x16C, 8, MD(5)},
187 {"ADDR_TRAP_1" ,0x16D, 8, MD(5)},
188 {"ADDR_NEXT_1" ,0x16E, 8, MD(5)},
189 {"NEXT_ST_1" ,0x16F, 8, MD(5)},
190 {"OOB_SM_STATE" ,0x170, 8, MD(5)},
191 {"ADDR_TRAP_2" ,0x171, 8, MD(5)},
192 {"ADDR_NEXT_2" ,0x172, 8, MD(5)},
193 {"NEXT_ST_2" ,0x173, 8, MD(5)},
197 #define STR_8BIT " %30s[0x%04x]:0x%02x\n"
198 #define STR_16BIT " %30s[0x%04x]:0x%04x\n"
199 #define STR_32BIT " %30s[0x%04x]:0x%08x\n"
200 #define STR_64BIT " %30s[0x%04x]:0x%llx\n"
216 #define MSTR_8BIT " Mode:%02d %30s[0x%04x]:0x%02x\n"
217 #define MSTR_16BIT " Mode:%02d %30s[0x%04x]:0x%04x\n"
218 #define MSTR_32BIT " Mode:%02d %30s[0x%04x]:0x%08x\n"
228 #define PRINT_MIS_byte(_ha, _n) asd_printk(STR_8BIT, #_n,CSEQ_##_n-CMAPPEDSCR,\
230 #define PRINT_MIS_word(_ha, _n) asd_printk(STR_16BIT,#_n,CSEQ_##_n-CMAPPEDSCR,\
233 asd_printk(STR_32BIT,#_n,CSEQ_##_n-CMAPPEDSCR,\
236 asd_printk(STR_64BIT, #_n,CSEQ_##_n-CMAPPEDSCR, \
242 asd_printk("%20s 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", \
245 asd_read_reg_word(_ha, CMDP_REG(_n, 1)), \
254 asd_printk("%20s 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", \
257 asd_read_reg_byte(_ha, CMDP_REG(_n, 1)), \
269 asd_printk("CSEQ STATE\n"); in asd_dump_cseq_state()
271 asd_printk("ARP2 REGISTERS\n"); in asd_dump_cseq_state()
293 asd_printk("IOP REGISTERS\n"); in asd_dump_cseq_state()
298 asd_printk("CIO REGISTERS\n"); in asd_dump_cseq_state()
308 for (mode = 0; mode < 8; mode++) in asd_dump_cseq_state()
310 for (mode = 0; mode < 8; mode++) in asd_dump_cseq_state()
312 for (mode = 0; mode < 8; mode++) in asd_dump_cseq_state()
314 for (mode = 0; mode < 8; mode++) in asd_dump_cseq_state()
318 for (mode = 0; mode < 8; mode++) in asd_dump_cseq_state()
329 asd_printk("SCRATCH MEMORY\n"); in asd_dump_cseq_state()
331 asd_printk("MIP 4 >>>>>\n"); in asd_dump_cseq_state()
349 asd_printk("MIP 5 >>>>\n"); in asd_dump_cseq_state()
359 asd_printk("MIP 6 >>>>\n"); in asd_dump_cseq_state()
375 asd_printk("MIP 7 >>>>\n"); in asd_dump_cseq_state()
387 asd_printk("MDP 0 >>>>\n"); in asd_dump_cseq_state()
388 asd_printk("%-20s %6s %6s %6s %6s %6s %6s %6s %6s\n", in asd_dump_cseq_state()
389 "Mode: ", "0", "1", "2", "3", "4", "5", "6", "7"); in asd_dump_cseq_state()
396 asd_printk("MDP 0 Mode 8 >>>>\n"); in asd_dump_cseq_state()
412 asd_printk("MDP 1 Mode 8 >>>>\n"); in asd_dump_cseq_state()
416 asd_printk("MDP 2 Mode 8 >>>>\n"); in asd_dump_cseq_state()
431 asd_printk(STR_8BIT, #_n, LmSEQ_##_n(_lseq)-LmSCRATCH(_lseq), \
434 asd_printk(STR_16BIT, #_n, LmSEQ_##_n(_lseq)-LmSCRATCH(_lseq), \
437 asd_printk(STR_32BIT, #_n, LmSEQ_##_n(_lseq)-LmSCRATCH(_lseq), \
440 asd_printk(STR_64BIT, #_n, LmSEQ_##_n(_lseq)-LmSCRATCH(_lseq), \
450 case 8: in asd_print_lseq_cio_reg()
451 asd_printk("%20s[0x%x]: 0x%02x\n", LSEQmCIOREGS[i].name, in asd_print_lseq_cio_reg()
458 asd_printk("%20s[0x%x]: 0x%04x\n", LSEQmCIOREGS[i].name, in asd_print_lseq_cio_reg()
465 asd_printk("%20s[0x%x]: 0x%08x\n", LSEQmCIOREGS[i].name, in asd_print_lseq_cio_reg()
478 asd_printk("LSEQ %d STATE\n", lseq); in asd_dump_lseq_state()
480 asd_printk("LSEQ%d: ARP2 REGISTERS\n", lseq); in asd_dump_lseq_state()
501 asd_printk("LSEQ%d: IOP REGISTERS\n", lseq); in asd_dump_lseq_state()
509 asd_printk("LSEQ%d: CIO REGISTERS\n", lseq); in asd_dump_lseq_state()
510 asd_printk("Mode common:\n"); in asd_dump_lseq_state()
512 for (mode = 0; mode < 8; mode++) { in asd_dump_lseq_state()
521 asd_printk("Mode unique:\n"); in asd_dump_lseq_state()
522 for (mode = 0; mode < 8; mode++) { in asd_dump_lseq_state()
526 asd_printk("Mode %d\n", mode); in asd_dump_lseq_state()
528 if (!(LSEQmCIOREGS[i].mode & (1 << mode))) in asd_dump_lseq_state()
534 asd_printk("SCRATCH MEMORY\n"); in asd_dump_lseq_state()
536 asd_printk("LSEQ%d MIP 0 >>>>\n", lseq); in asd_dump_lseq_state()
550 asd_printk("LSEQ%d MIP 1 >>>>\n", lseq); in asd_dump_lseq_state()
566 asd_printk("LSEQ%d MIP 2 >>>>\n", lseq); in asd_dump_lseq_state()
579 asd_printk("LSEQ%d MIP 3 >>>>\n", lseq); in asd_dump_lseq_state()
589 asd_printk("LSEQ%d MDP 0 MODE %d >>>>\n", lseq, mode); in asd_dump_lseq_state()
615 asd_printk("LSEQ%d MDP 0 MODE 5 >>>>\n", lseq); in asd_dump_lseq_state()
632 asd_printk("LSEQ%d MDP 0 MODE 0 >>>>\n", lseq); in asd_dump_lseq_state()
644 asd_printk("LSEQ%d MDP 0 MODE 1 >>>>\n", lseq); in asd_dump_lseq_state()
654 asd_printk("LSEQ%d MDP 0 MODE 2 >>>>\n", lseq); in asd_dump_lseq_state()
662 asd_printk("LSEQ%d MDP 0 MODE 4/5 >>>>\n", lseq); in asd_dump_lseq_state()
675 asd_printk("LSEQ%d MDP 1 MODE 0 >>>>\n", lseq); in asd_dump_lseq_state()
679 asd_printk("LSEQ%d MDP 1 MODE 1 >>>>\n", lseq); in asd_dump_lseq_state()
683 asd_printk("LSEQ%d MDP 1 MODE 2 >>>>\n", lseq); in asd_dump_lseq_state()
688 asd_printk("LSEQ%d MDP 1 MODE 4/5 >>>>\n", lseq); in asd_dump_lseq_state()
696 asd_printk("LSEQ%d MDP 2 MODE 0 >>>>\n", lseq); in asd_dump_lseq_state()
703 asd_printk("LSEQ%d MDP 2 MODE 1 >>>>\n", lseq); in asd_dump_lseq_state()
709 asd_printk("LSEQ%d MDP 2 MODE 2 >>>>\n", lseq); in asd_dump_lseq_state()
716 asd_printk("LSEQ%d MDP 2 MODE 4/5 >>>>\n", lseq); in asd_dump_lseq_state()
724 * asd_dump_seq_state -- dump CSEQ and LSEQ states
745 switch ((dl->status_block[1] & 0x70) >> 3) { in asd_dump_frame_rcvd()
747 ASD_DPRINTK("STP proto device-to-host FIS:\n"); in asd_dump_frame_rcvd()
751 ASD_DPRINTK("SAS proto IDENTIFY:\n"); in asd_dump_frame_rcvd()
754 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); in asd_dump_frame_rcvd()
755 for (i = 0; i < phy->sas_phy.frame_rcvd_size; i+=4) in asd_dump_frame_rcvd()
756 ASD_DPRINTK("%02x: %02x %02x %02x %02x\n", in asd_dump_frame_rcvd()
758 phy->frame_rcvd[i], in asd_dump_frame_rcvd()
759 phy->frame_rcvd[i+1], in asd_dump_frame_rcvd()
760 phy->frame_rcvd[i+2], in asd_dump_frame_rcvd()
761 phy->frame_rcvd[i+3]); in asd_dump_frame_rcvd()
762 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); in asd_dump_frame_rcvd()