5  *	 JZ4740 SoC RTC driver
19 #include <linux/rtc.h>
64 	struct rtc_device *rtc;  member
73 static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)  in jz4740_rtc_reg_read()  argument
75 	return readl(rtc->base + reg);  in jz4740_rtc_reg_read()
78 static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)  in jz4740_rtc_wait_write_ready()  argument
82 	return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl,  in jz4740_rtc_wait_write_ready()
86 static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)  in jz4780_rtc_enable_write()  argument
91 	ret = jz4740_rtc_wait_write_ready(rtc);  in jz4780_rtc_enable_write()
95 	writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);  in jz4780_rtc_enable_write()
97 	return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl,  in jz4780_rtc_enable_write()
101 static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,  in jz4740_rtc_reg_write()  argument
106 	if (rtc->type >= ID_JZ4760)  in jz4740_rtc_reg_write()
107 		ret = jz4780_rtc_enable_write(rtc);  in jz4740_rtc_reg_write()
109 		ret = jz4740_rtc_wait_write_ready(rtc);  in jz4740_rtc_reg_write()
111 		writel(val, rtc->base + reg);  in jz4740_rtc_reg_write()
116 static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,  in jz4740_rtc_ctrl_set_bits()  argument
123 	spin_lock_irqsave(&rtc->lock, flags);  in jz4740_rtc_ctrl_set_bits()
125 	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);  in jz4740_rtc_ctrl_set_bits()
135 	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);  in jz4740_rtc_ctrl_set_bits()
137 	spin_unlock_irqrestore(&rtc->lock, flags);  in jz4740_rtc_ctrl_set_bits()
144 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);  in jz4740_rtc_read_time()  local
148 	if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)  in jz4740_rtc_read_time()
155 	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);  in jz4740_rtc_read_time()
156 	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);  in jz4740_rtc_read_time()
160 		secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);  in jz4740_rtc_read_time()
173 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);  in jz4740_rtc_set_time()  local
176 	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));  in jz4740_rtc_set_time()
180 	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);  in jz4740_rtc_set_time()
185 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);  in jz4740_rtc_read_alarm()  local
189 	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);  in jz4740_rtc_read_alarm()
191 	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);  in jz4740_rtc_read_alarm()
204 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);  in jz4740_rtc_set_alarm()  local
207 	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);  in jz4740_rtc_set_alarm()
209 		ret = jz4740_rtc_ctrl_set_bits(rtc,  in jz4740_rtc_set_alarm()
217 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);  in jz4740_rtc_alarm_irq_enable()  local
218 	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);  in jz4740_rtc_alarm_irq_enable()
231 	struct jz4740_rtc *rtc = data;  in jz4740_rtc_irq()  local
235 	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);  in jz4740_rtc_irq()
243 	rtc_update_irq(rtc->rtc, 1, events);  in jz4740_rtc_irq()
245 	jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);  in jz4740_rtc_irq()
252 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);  in jz4740_rtc_poweroff()  local
253 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);  in jz4740_rtc_poweroff()
263 	{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
264 	{ .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
265 	{ .compatible = "ingenic,jz4770-rtc", .data = (void *)ID_JZ4780 },
266 	{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
271 static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc,  in jz4740_rtc_set_wakeup_params()  argument
286 	 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.  in jz4740_rtc_set_wakeup_params()
293 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks);  in jz4740_rtc_set_wakeup_params()
297 	 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.  in jz4740_rtc_set_wakeup_params()
304 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks);  in jz4740_rtc_set_wakeup_params()
309 	struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k);  in jz4740_rtc_clk32k_enable()  local
311 	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CKPCR,  in jz4740_rtc_clk32k_enable()
318 	struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k);  in jz4740_rtc_clk32k_disable()  local
320 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CKPCR, 0);  in jz4740_rtc_clk32k_disable()
325 	struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k);  in jz4740_rtc_clk32k_is_enabled()  local
328 	ckpcr = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CKPCR);  in jz4740_rtc_clk32k_is_enabled()
343 	struct jz4740_rtc *rtc;  in jz4740_rtc_probe()  local
348 	rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);  in jz4740_rtc_probe()
349 	if (!rtc)  in jz4740_rtc_probe()
352 	rtc->type = (uintptr_t)device_get_match_data(dev);  in jz4740_rtc_probe()
358 	rtc->base = devm_platform_ioremap_resource(pdev, 0);  in jz4740_rtc_probe()
359 	if (IS_ERR(rtc->base))  in jz4740_rtc_probe()
360 		return PTR_ERR(rtc->base);  in jz4740_rtc_probe()
362 	clk = devm_clk_get_enabled(dev, "rtc");  in jz4740_rtc_probe()
364 		return dev_err_probe(dev, PTR_ERR(clk), "Failed to get RTC clock\n");  in jz4740_rtc_probe()
366 	spin_lock_init(&rtc->lock);  in jz4740_rtc_probe()
368 	platform_set_drvdata(pdev, rtc);  in jz4740_rtc_probe()
376 	rtc->rtc = devm_rtc_allocate_device(dev);  in jz4740_rtc_probe()
377 	if (IS_ERR(rtc->rtc))  in jz4740_rtc_probe()
378 		return dev_err_probe(dev, PTR_ERR(rtc->rtc),  in jz4740_rtc_probe()
379 				     "Failed to allocate rtc device\n");  in jz4740_rtc_probe()
381 	rtc->rtc->ops = &jz4740_rtc_ops;  in jz4740_rtc_probe()
382 	rtc->rtc->range_max = U32_MAX;  in jz4740_rtc_probe()
385 	jz4740_rtc_set_wakeup_params(rtc, np, rate);  in jz4740_rtc_probe()
388 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);  in jz4740_rtc_probe()
390 	ret = devm_rtc_register_device(rtc->rtc);  in jz4740_rtc_probe()
395 			       pdev->name, rtc);  in jz4740_rtc_probe()
397 		return dev_err_probe(dev, ret, "Failed to request rtc irq\n");  in jz4740_rtc_probe()
409 		rtc->clk32k.init = CLK_HW_INIT_HW("clk32k", __clk_get_hw(clk),  in jz4740_rtc_probe()
412 		ret = devm_clk_hw_register(dev, &rtc->clk32k);  in jz4740_rtc_probe()
418 						  &rtc->clk32k);  in jz4740_rtc_probe()
430 		.name  = "jz4740-rtc",
439 MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
440 MODULE_ALIAS("platform:jz4740-rtc");