Lines Matching refs:wcss
155 static int q6v5_wcss_reset(struct q6v5_wcss *wcss) in q6v5_wcss_reset() argument
162 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
164 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
167 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
169 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
172 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
176 dev_err(wcss->dev, in q6v5_wcss_reset()
181 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
183 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
188 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
191 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
193 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
197 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
200 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
203 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
209 val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
213 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
215 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
219 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
222 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
224 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
227 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
229 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
232 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
234 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
241 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_start() local
244 qcom_q6v5_prepare(&wcss->q6v5); in q6v5_wcss_start()
247 ret = reset_control_deassert(wcss->wcss_reset); in q6v5_wcss_start()
249 dev_err(wcss->dev, "wcss_reset failed\n"); in q6v5_wcss_start()
253 ret = reset_control_deassert(wcss->wcss_q6_reset); in q6v5_wcss_start()
255 dev_err(wcss->dev, "wcss_q6_reset failed\n"); in q6v5_wcss_start()
260 ret = regmap_update_bits(wcss->halt_map, in q6v5_wcss_start()
261 wcss->halt_nc + TCSR_GLOBAL_CFG0, in q6v5_wcss_start()
267 ret = regmap_update_bits(wcss->halt_map, in q6v5_wcss_start()
268 wcss->halt_nc + TCSR_GLOBAL_CFG1, in q6v5_wcss_start()
274 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); in q6v5_wcss_start()
276 ret = q6v5_wcss_reset(wcss); in q6v5_wcss_start()
280 ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); in q6v5_wcss_start()
282 dev_err(wcss->dev, "start timed out\n"); in q6v5_wcss_start()
287 reset_control_assert(wcss->wcss_q6_reset); in q6v5_wcss_start()
290 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_start()
295 static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss *wcss) in q6v5_wcss_qcs404_power_on() argument
301 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_qcs404_power_on()
303 reset_control_deassert(wcss->wcss_reset); in q6v5_wcss_qcs404_power_on()
307 ret = clk_prepare_enable(wcss->gcc_abhs_cbcr); in q6v5_wcss_qcs404_power_on()
312 reset_control_deassert(wcss->wcss_q6_bcr_reset); in q6v5_wcss_qcs404_power_on()
315 ret = clk_prepare_enable(wcss->ahbfabric_cbcr_clk); in q6v5_wcss_qcs404_power_on()
320 ret = clk_prepare_enable(wcss->lcc_csr_cbcr); in q6v5_wcss_qcs404_power_on()
325 ret = clk_prepare_enable(wcss->ahbs_cbcr); in q6v5_wcss_qcs404_power_on()
330 ret = clk_prepare_enable(wcss->tcm_slave_cbcr); in q6v5_wcss_qcs404_power_on()
335 ret = clk_prepare_enable(wcss->qdsp6ss_abhm_cbcr); in q6v5_wcss_qcs404_power_on()
340 ret = clk_prepare_enable(wcss->qdsp6ss_axim_cbcr); in q6v5_wcss_qcs404_power_on()
345 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
347 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
349 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_qcs404_power_on()
353 dev_err(wcss->dev, in q6v5_wcss_qcs404_power_on()
358 writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE); in q6v5_wcss_qcs404_power_on()
361 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
363 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
366 ret = clk_prepare_enable(wcss->gcc_axim_cbcr); in q6v5_wcss_qcs404_power_on()
371 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
373 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
376 writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
378 writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
380 writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
382 writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
389 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) | in q6v5_wcss_qcs404_power_on()
390 (1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_qcs404_power_on()
393 writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
394 writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
396 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
398 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
401 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
403 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
406 ret = clk_prepare_enable(wcss->lcc_bcr_sleep); in q6v5_wcss_qcs404_power_on()
413 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
415 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
416 clk_disable_unprepare(wcss->gcc_axim_cbcr); in q6v5_wcss_qcs404_power_on()
418 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
420 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
422 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
424 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
425 clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); in q6v5_wcss_qcs404_power_on()
427 clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); in q6v5_wcss_qcs404_power_on()
429 clk_disable_unprepare(wcss->tcm_slave_cbcr); in q6v5_wcss_qcs404_power_on()
431 clk_disable_unprepare(wcss->ahbs_cbcr); in q6v5_wcss_qcs404_power_on()
433 clk_disable_unprepare(wcss->lcc_csr_cbcr); in q6v5_wcss_qcs404_power_on()
435 clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); in q6v5_wcss_qcs404_power_on()
437 clk_disable_unprepare(wcss->gcc_abhs_cbcr); in q6v5_wcss_qcs404_power_on()
442 static inline int q6v5_wcss_qcs404_reset(struct q6v5_wcss *wcss) in q6v5_wcss_qcs404_reset() argument
446 writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC); in q6v5_wcss_qcs404_reset()
449 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_reset()
451 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_reset()
458 struct q6v5_wcss *wcss = rproc->priv; in q6v5_qcs404_wcss_start() local
461 ret = clk_prepare_enable(wcss->xo); in q6v5_qcs404_wcss_start()
465 ret = regulator_enable(wcss->cx_supply); in q6v5_qcs404_wcss_start()
469 qcom_q6v5_prepare(&wcss->q6v5); in q6v5_qcs404_wcss_start()
471 ret = q6v5_wcss_qcs404_power_on(wcss); in q6v5_qcs404_wcss_start()
473 dev_err(wcss->dev, "wcss clk_enable failed\n"); in q6v5_qcs404_wcss_start()
477 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); in q6v5_qcs404_wcss_start()
479 q6v5_wcss_qcs404_reset(wcss); in q6v5_qcs404_wcss_start()
481 ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); in q6v5_qcs404_wcss_start()
483 dev_err(wcss->dev, "start timed out\n"); in q6v5_qcs404_wcss_start()
490 regulator_disable(wcss->cx_supply); in q6v5_qcs404_wcss_start()
492 clk_disable_unprepare(wcss->xo); in q6v5_qcs404_wcss_start()
497 static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss, in q6v5_wcss_halt_axi_port() argument
525 dev_err(wcss->dev, "port failed halt\n"); in q6v5_wcss_halt_axi_port()
531 static int q6v5_qcs404_wcss_shutdown(struct q6v5_wcss *wcss) in q6v5_qcs404_wcss_shutdown() argument
536 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); in q6v5_qcs404_wcss_shutdown()
539 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
541 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
544 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) & in q6v5_qcs404_wcss_shutdown()
546 wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_qcs404_wcss_shutdown()
549 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
551 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
553 clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); in q6v5_qcs404_wcss_shutdown()
554 clk_disable_unprepare(wcss->lcc_csr_cbcr); in q6v5_qcs404_wcss_shutdown()
555 clk_disable_unprepare(wcss->tcm_slave_cbcr); in q6v5_qcs404_wcss_shutdown()
556 clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); in q6v5_qcs404_wcss_shutdown()
557 clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); in q6v5_qcs404_wcss_shutdown()
559 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_qcs404_wcss_shutdown()
561 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_qcs404_wcss_shutdown()
563 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_qcs404_wcss_shutdown()
565 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_qcs404_wcss_shutdown()
567 clk_disable_unprepare(wcss->ahbs_cbcr); in q6v5_qcs404_wcss_shutdown()
568 clk_disable_unprepare(wcss->lcc_bcr_sleep); in q6v5_qcs404_wcss_shutdown()
570 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_qcs404_wcss_shutdown()
572 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_qcs404_wcss_shutdown()
574 clk_disable_unprepare(wcss->gcc_abhs_cbcr); in q6v5_qcs404_wcss_shutdown()
576 ret = reset_control_assert(wcss->wcss_reset); in q6v5_qcs404_wcss_shutdown()
578 dev_err(wcss->dev, "wcss_reset failed\n"); in q6v5_qcs404_wcss_shutdown()
583 ret = reset_control_deassert(wcss->wcss_reset); in q6v5_qcs404_wcss_shutdown()
585 dev_err(wcss->dev, "wcss_reset failed\n"); in q6v5_qcs404_wcss_shutdown()
590 clk_disable_unprepare(wcss->gcc_axim_cbcr); in q6v5_qcs404_wcss_shutdown()
595 static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss) in q6v5_wcss_powerdown() argument
601 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); in q6v5_wcss_powerdown()
604 val = readl(wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
606 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
611 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
615 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
618 ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS, in q6v5_wcss_powerdown()
622 dev_err(wcss->dev, in q6v5_wcss_powerdown()
628 reset_control_assert(wcss->wcss_aon_reset); in q6v5_wcss_powerdown()
631 val = readl(wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
633 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
636 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_powerdown()
641 static int q6v5_q6_powerdown(struct q6v5_wcss *wcss) in q6v5_q6_powerdown() argument
648 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6); in q6v5_q6_powerdown()
651 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
653 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
656 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
658 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
662 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
666 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
670 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
674 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_q6_powerdown()
676 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_q6_powerdown()
681 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
683 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
687 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
691 ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS, in q6v5_q6_powerdown()
695 dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret); in q6v5_q6_powerdown()
700 reset_control_assert(wcss->wcss_reset); in q6v5_q6_powerdown()
703 reset_control_assert(wcss->wcss_q6_reset); in q6v5_q6_powerdown()
710 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_stop() local
714 if (wcss->requires_force_stop) { in q6v5_wcss_stop()
715 ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL); in q6v5_wcss_stop()
717 dev_err(wcss->dev, "timed out on wait\n"); in q6v5_wcss_stop()
722 if (wcss->version == WCSS_QCS404) { in q6v5_wcss_stop()
723 ret = q6v5_qcs404_wcss_shutdown(wcss); in q6v5_wcss_stop()
727 ret = q6v5_wcss_powerdown(wcss); in q6v5_wcss_stop()
732 ret = q6v5_q6_powerdown(wcss); in q6v5_wcss_stop()
737 qcom_q6v5_unprepare(&wcss->q6v5); in q6v5_wcss_stop()
744 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_da_to_va() local
747 offset = da - wcss->mem_reloc; in q6v5_wcss_da_to_va()
748 if (offset < 0 || offset + len > wcss->mem_size) in q6v5_wcss_da_to_va()
751 return wcss->mem_region + offset; in q6v5_wcss_da_to_va()
756 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_load() local
759 ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, in q6v5_wcss_load()
760 0, wcss->mem_region, wcss->mem_phys, in q6v5_wcss_load()
761 wcss->mem_size, &wcss->mem_reloc); in q6v5_wcss_load()
765 qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size); in q6v5_wcss_load()
787 static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss, in q6v5_wcss_init_reset() argument
790 struct device *dev = wcss->dev; in q6v5_wcss_init_reset()
793 wcss->wcss_aon_reset = devm_reset_control_get_exclusive(dev, "wcss_aon_reset"); in q6v5_wcss_init_reset()
794 if (IS_ERR(wcss->wcss_aon_reset)) { in q6v5_wcss_init_reset()
795 dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n"); in q6v5_wcss_init_reset()
796 return PTR_ERR(wcss->wcss_aon_reset); in q6v5_wcss_init_reset()
800 wcss->wcss_reset = devm_reset_control_get_exclusive(dev, "wcss_reset"); in q6v5_wcss_init_reset()
801 if (IS_ERR(wcss->wcss_reset)) { in q6v5_wcss_init_reset()
802 dev_err(wcss->dev, "unable to acquire wcss_reset\n"); in q6v5_wcss_init_reset()
803 return PTR_ERR(wcss->wcss_reset); in q6v5_wcss_init_reset()
807 wcss->wcss_q6_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_reset"); in q6v5_wcss_init_reset()
808 if (IS_ERR(wcss->wcss_q6_reset)) { in q6v5_wcss_init_reset()
809 dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); in q6v5_wcss_init_reset()
810 return PTR_ERR(wcss->wcss_q6_reset); in q6v5_wcss_init_reset()
814 wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset"); in q6v5_wcss_init_reset()
815 if (IS_ERR(wcss->wcss_q6_bcr_reset)) { in q6v5_wcss_init_reset()
816 dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); in q6v5_wcss_init_reset()
817 return PTR_ERR(wcss->wcss_q6_bcr_reset); in q6v5_wcss_init_reset()
823 static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, in q6v5_wcss_init_mmio() argument
835 wcss->reg_base = devm_ioremap(&pdev->dev, res->start, in q6v5_wcss_init_mmio()
837 if (!wcss->reg_base) in q6v5_wcss_init_mmio()
840 if (wcss->version == WCSS_IPQ8074) { in q6v5_wcss_init_mmio()
841 wcss->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb"); in q6v5_wcss_init_mmio()
842 if (IS_ERR(wcss->rmb_base)) in q6v5_wcss_init_mmio()
843 return PTR_ERR(wcss->rmb_base); in q6v5_wcss_init_mmio()
853 wcss->halt_map = syscon_node_to_regmap(syscon); in q6v5_wcss_init_mmio()
855 if (IS_ERR(wcss->halt_map)) in q6v5_wcss_init_mmio()
856 return PTR_ERR(wcss->halt_map); in q6v5_wcss_init_mmio()
867 wcss->halt_q6 = halt_reg[0]; in q6v5_wcss_init_mmio()
868 wcss->halt_wcss = halt_reg[1]; in q6v5_wcss_init_mmio()
869 wcss->halt_nc = halt_reg[2]; in q6v5_wcss_init_mmio()
874 static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) in q6v5_alloc_memory_region() argument
878 struct device *dev = wcss->dev; in q6v5_alloc_memory_region()
890 wcss->mem_phys = rmem->base; in q6v5_alloc_memory_region()
891 wcss->mem_reloc = rmem->base; in q6v5_alloc_memory_region()
892 wcss->mem_size = rmem->size; in q6v5_alloc_memory_region()
893 wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size); in q6v5_alloc_memory_region()
894 if (!wcss->mem_region) { in q6v5_alloc_memory_region()
903 static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) in q6v5_wcss_init_clock() argument
907 wcss->xo = devm_clk_get(wcss->dev, "xo"); in q6v5_wcss_init_clock()
908 if (IS_ERR(wcss->xo)) { in q6v5_wcss_init_clock()
909 ret = PTR_ERR(wcss->xo); in q6v5_wcss_init_clock()
911 dev_err(wcss->dev, "failed to get xo clock"); in q6v5_wcss_init_clock()
915 wcss->gcc_abhs_cbcr = devm_clk_get(wcss->dev, "gcc_abhs_cbcr"); in q6v5_wcss_init_clock()
916 if (IS_ERR(wcss->gcc_abhs_cbcr)) { in q6v5_wcss_init_clock()
917 ret = PTR_ERR(wcss->gcc_abhs_cbcr); in q6v5_wcss_init_clock()
919 dev_err(wcss->dev, "failed to get gcc abhs clock"); in q6v5_wcss_init_clock()
923 wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr"); in q6v5_wcss_init_clock()
924 if (IS_ERR(wcss->gcc_axim_cbcr)) { in q6v5_wcss_init_clock()
925 ret = PTR_ERR(wcss->gcc_axim_cbcr); in q6v5_wcss_init_clock()
927 dev_err(wcss->dev, "failed to get gcc axim clock\n"); in q6v5_wcss_init_clock()
931 wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev, in q6v5_wcss_init_clock()
933 if (IS_ERR(wcss->ahbfabric_cbcr_clk)) { in q6v5_wcss_init_clock()
934 ret = PTR_ERR(wcss->ahbfabric_cbcr_clk); in q6v5_wcss_init_clock()
936 dev_err(wcss->dev, "failed to get ahbfabric clock\n"); in q6v5_wcss_init_clock()
940 wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "tcsr_lcc_cbc"); in q6v5_wcss_init_clock()
941 if (IS_ERR(wcss->lcc_csr_cbcr)) { in q6v5_wcss_init_clock()
942 ret = PTR_ERR(wcss->lcc_csr_cbcr); in q6v5_wcss_init_clock()
944 dev_err(wcss->dev, "failed to get csr cbcr clk\n"); in q6v5_wcss_init_clock()
948 wcss->ahbs_cbcr = devm_clk_get(wcss->dev, in q6v5_wcss_init_clock()
950 if (IS_ERR(wcss->ahbs_cbcr)) { in q6v5_wcss_init_clock()
951 ret = PTR_ERR(wcss->ahbs_cbcr); in q6v5_wcss_init_clock()
953 dev_err(wcss->dev, "failed to get ahbs_cbcr clk\n"); in q6v5_wcss_init_clock()
957 wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev, in q6v5_wcss_init_clock()
959 if (IS_ERR(wcss->tcm_slave_cbcr)) { in q6v5_wcss_init_clock()
960 ret = PTR_ERR(wcss->tcm_slave_cbcr); in q6v5_wcss_init_clock()
962 dev_err(wcss->dev, "failed to get tcm cbcr clk\n"); in q6v5_wcss_init_clock()
966 wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "lcc_abhm_cbc"); in q6v5_wcss_init_clock()
967 if (IS_ERR(wcss->qdsp6ss_abhm_cbcr)) { in q6v5_wcss_init_clock()
968 ret = PTR_ERR(wcss->qdsp6ss_abhm_cbcr); in q6v5_wcss_init_clock()
970 dev_err(wcss->dev, "failed to get abhm cbcr clk\n"); in q6v5_wcss_init_clock()
974 wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "lcc_axim_cbc"); in q6v5_wcss_init_clock()
975 if (IS_ERR(wcss->qdsp6ss_axim_cbcr)) { in q6v5_wcss_init_clock()
976 ret = PTR_ERR(wcss->qdsp6ss_axim_cbcr); in q6v5_wcss_init_clock()
978 dev_err(wcss->dev, "failed to get axim cbcr clk\n"); in q6v5_wcss_init_clock()
982 wcss->lcc_bcr_sleep = devm_clk_get(wcss->dev, "lcc_bcr_sleep"); in q6v5_wcss_init_clock()
983 if (IS_ERR(wcss->lcc_bcr_sleep)) { in q6v5_wcss_init_clock()
984 ret = PTR_ERR(wcss->lcc_bcr_sleep); in q6v5_wcss_init_clock()
986 dev_err(wcss->dev, "failed to get bcr cbcr clk\n"); in q6v5_wcss_init_clock()
993 static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss) in q6v5_wcss_init_regulator() argument
995 wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); in q6v5_wcss_init_regulator()
996 if (IS_ERR(wcss->cx_supply)) in q6v5_wcss_init_regulator()
997 return PTR_ERR(wcss->cx_supply); in q6v5_wcss_init_regulator()
999 regulator_set_load(wcss->cx_supply, 100000); in q6v5_wcss_init_regulator()
1007 struct q6v5_wcss *wcss; in q6v5_wcss_probe() local
1016 desc->firmware_name, sizeof(*wcss)); in q6v5_wcss_probe()
1022 wcss = rproc->priv; in q6v5_wcss_probe()
1023 wcss->dev = &pdev->dev; in q6v5_wcss_probe()
1024 wcss->version = desc->version; in q6v5_wcss_probe()
1026 wcss->version = desc->version; in q6v5_wcss_probe()
1027 wcss->requires_force_stop = desc->requires_force_stop; in q6v5_wcss_probe()
1029 ret = q6v5_wcss_init_mmio(wcss, pdev); in q6v5_wcss_probe()
1033 ret = q6v5_alloc_memory_region(wcss); in q6v5_wcss_probe()
1037 if (wcss->version == WCSS_QCS404) { in q6v5_wcss_probe()
1038 ret = q6v5_wcss_init_clock(wcss); in q6v5_wcss_probe()
1042 ret = q6v5_wcss_init_regulator(wcss); in q6v5_wcss_probe()
1047 ret = q6v5_wcss_init_reset(wcss, desc); in q6v5_wcss_probe()
1051 ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, NULL); in q6v5_wcss_probe()
1055 qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss"); in q6v5_wcss_probe()
1056 qcom_add_pdm_subdev(rproc, &wcss->pdm_subdev); in q6v5_wcss_probe()
1057 qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); in q6v5_wcss_probe()
1060 wcss->sysmon = qcom_add_sysmon_subdev(rproc, in q6v5_wcss_probe()
1076 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_remove() local
1078 qcom_q6v5_deinit(&wcss->q6v5); in q6v5_wcss_remove()
1079 qcom_remove_pdm_subdev(rproc, &wcss->pdm_subdev); in q6v5_wcss_remove()