Lines Matching +full:vs2 +full:- +full:ldo2 +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/regulator/mt6358-regulator.h>
16 #include <dt-bindings/regulator/mediatek,mt6397-regulator.h>
36 #define MT6358_BUCK(match, vreg, supply, min, max, step, \ argument
42 .supply_name = supply, \
48 .n_voltages = ((max) - (min)) / (step) + 1, \
65 #define MT6358_LDO(match, vreg, supply, volt_ranges, enreg, enbit, vosel, vosel_mask) \ argument
69 .supply_name = supply, \
90 #define MT6358_LDO1(match, vreg, supply, min, max, step, \ argument
95 .supply_name = supply, \
101 .n_voltages = ((max) - (min)) / (step) + 1, \
115 #define MT6358_REG_FIXED(match, vreg, supply, enreg, enbit, volt) \ argument
119 .supply_name = supply, \
143 .supply_name = "vsys-" match, \
149 .n_voltages = ((max) - (min)) / (step) + 1, \
166 #define MT6366_LDO(match, vreg, volt_ranges, supply, enreg, enbit, vosel, vosel_mask) \ argument
170 .supply_name = supply, \
191 #define MT6366_LDO1(match, vreg, supply, min, max, step, \ argument
196 .supply_name = supply, \
202 .n_voltages = ((max) - (min)) / (step) + 1, \
216 #define MT6366_REG_FIXED(match, vreg, supply, enreg, enbit, volt) \ argument
220 .supply_name = supply, \
373 const struct mt6358_regulator_info *info = to_regulator_info(rdev->desc); in mt6358_get_buck_voltage_sel()
376 ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val); in mt6358_get_buck_voltage_sel()
378 dev_err(&rdev->dev, in mt6358_get_buck_voltage_sel()
380 info->desc.name, ret); in mt6358_get_buck_voltage_sel()
384 ret = (regval & info->da_vsel_mask) >> (ffs(info->da_vsel_mask) - 1); in mt6358_get_buck_voltage_sel()
391 const struct mt6358_regulator_info *info = to_regulator_info(rdev->desc); in mt6358_get_status()
395 ret = regmap_read(rdev->regmap, info->status_reg, ®val); in mt6358_get_status()
397 dev_info(&rdev->dev, "Failed to get enable reg: %d\n", ret); in mt6358_get_status()
401 return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; in mt6358_get_status()
407 const struct mt6358_regulator_info *info = to_regulator_info(rdev->desc); in mt6358_regulator_set_mode()
418 return -EINVAL; in mt6358_regulator_set_mode()
421 dev_dbg(&rdev->dev, "mt6358 buck set_mode %#x, %#x, %#x\n", in mt6358_regulator_set_mode()
422 info->modeset_reg, info->modeset_mask, val); in mt6358_regulator_set_mode()
424 val <<= ffs(info->modeset_mask) - 1; in mt6358_regulator_set_mode()
426 return regmap_update_bits(rdev->regmap, info->modeset_reg, in mt6358_regulator_set_mode()
427 info->modeset_mask, val); in mt6358_regulator_set_mode()
432 const struct mt6358_regulator_info *info = to_regulator_info(rdev->desc); in mt6358_regulator_get_mode()
435 ret = regmap_read(rdev->regmap, info->modeset_reg, ®val); in mt6358_regulator_get_mode()
437 dev_err(&rdev->dev, in mt6358_regulator_get_mode()
442 switch ((regval & info->modeset_mask) >> (ffs(info->modeset_mask) - 1)) { in mt6358_regulator_get_mode()
448 return -EINVAL; in mt6358_regulator_get_mode()
505 MT6358_BUCK("buck_vdram1", VDRAM1, "vsys-vdram1", 500000, 2087500, 12500,
507 MT6358_BUCK("buck_vcore", VCORE, "vsys-vcore", 500000, 1293750, 6250,
509 MT6358_BUCK("buck_vpa", VPA, "vsys-vpa", 500000, 3650000, 50000,
511 MT6358_BUCK("buck_vproc11", VPROC11, "vsys-vproc11", 500000, 1293750, 6250,
513 MT6358_BUCK("buck_vproc12", VPROC12, "vsys-vproc12", 500000, 1293750, 6250,
515 MT6358_BUCK("buck_vgpu", VGPU, "vsys-vgpu", 500000, 1293750, 6250,
517 MT6358_BUCK("buck_vs2", VS2, "vsys-vs2", 500000, 2087500, 12500,
519 MT6358_BUCK("buck_vmodem", VMODEM, "vsys-vmodem", 500000, 1293750, 6250,
521 MT6358_BUCK("buck_vs1", VS1, "vsys-vs1", 1000000, 2587500, 12500,
523 MT6358_REG_FIXED("ldo_vrf12", VRF12, "vs2-ldo2", MT6358_LDO_VRF12_CON0, 0, 1200000),
524 MT6358_REG_FIXED("ldo_vio18", VIO18, "vs1-ldo1", MT6358_LDO_VIO18_CON0, 0, 1800000),
525 MT6358_REG_FIXED("ldo_vcamio", VCAMIO, "vs1-ldo1", MT6358_LDO_VCAMIO_CON0, 0, 1800000),
526 MT6358_REG_FIXED("ldo_vcn18", VCN18, "vs1-ldo1", MT6358_LDO_VCN18_CON0, 0, 1800000),
527 MT6358_REG_FIXED("ldo_vfe28", VFE28, "vsys-ldo1", MT6358_LDO_VFE28_CON0, 0, 2800000),
528 MT6358_REG_FIXED("ldo_vcn28", VCN28, "vsys-ldo1", MT6358_LDO_VCN28_CON0, 0, 2800000),
529 MT6358_REG_FIXED("ldo_vxo22", VXO22, "vsys-ldo1", MT6358_LDO_VXO22_CON0, 0, 2200000),
530 MT6358_REG_FIXED("ldo_vaux18", VAUX18, "vsys-ldo1", MT6358_LDO_VAUX18_CON0, 0, 1800000),
531 MT6358_REG_FIXED("ldo_vbif28", VBIF28, "vsys-ldo1", MT6358_LDO_VBIF28_CON0, 0, 2800000),
532 MT6358_REG_FIXED("ldo_vio28", VIO28, "vsys-ldo2", MT6358_LDO_VIO28_CON0, 0, 2800000),
533 MT6358_REG_FIXED("ldo_va12", VA12, "vs2-ldo2", MT6358_LDO_VA12_CON0, 0, 1200000),
534 MT6358_REG_FIXED("ldo_vrf18", VRF18, "vs1-ldo1", MT6358_LDO_VRF18_CON0, 0, 1800000),
535 MT6358_REG_FIXED("ldo_vaud28", VAUD28, "vsys-ldo1", MT6358_LDO_VAUD28_CON0, 0, 2800000),
536 MT6358_LDO("ldo_vdram2", VDRAM2, "vs2-ldo1", vdram2,
538 MT6358_LDO("ldo_vsim1", VSIM1, "vsys-ldo1", vsim,
540 MT6358_LDO("ldo_vibr", VIBR, "vsys-ldo3", vibr,
542 MT6358_LDO("ldo_vusb", VUSB, "vsys-ldo1", vusb,
544 MT6358_LDO("ldo_vcamd", VCAMD, "vs2-ldo4", vcamd,
546 MT6358_LDO("ldo_vefuse", VEFUSE, "vs1-ldo1", vefuse,
548 MT6358_LDO("ldo_vmch", VMCH, "vsys-ldo2", vmch_vemc,
550 MT6358_LDO("ldo_vcama1", VCAMA1, "vsys-ldo3", vcama,
552 MT6358_LDO("ldo_vemc", VEMC, "vsys-ldo2", vmch_vemc,
554 MT6358_LDO("ldo_vcn33", VCN33, "vsys-ldo3", vcn33,
556 MT6358_LDO("ldo_vcama2", VCAMA2, "vsys-ldo3", vcama,
558 MT6358_LDO("ldo_vmc", VMC, "vsys-ldo2", vmc,
560 MT6358_LDO("ldo_vldo28", VLDO28, "vsys-ldo2", vldo28,
563 MT6358_LDO("ldo_vsim2", VSIM2, "vsys-ldo2", vsim,
565 MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, "vs2-ldo3", 500000, 1293750, 6250,
567 MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, "vs2-ldo3", 500000, 1293750, 6250,
569 MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, "vs2-ldo3", 500000, 1293750, 6250,
571 MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, "vs2-ldo3", 500000, 1293750, 6250,
589 MT6366_BUCK("vs2", VS2, 500000, 2087500, 12500,
595 MT6366_REG_FIXED("vrf12", VRF12, "vs2-ldo2", MT6358_LDO_VRF12_CON0, 0, 1200000),
596 MT6366_REG_FIXED("vio18", VIO18, "vs1-ldo1", MT6358_LDO_VIO18_CON0, 0, 1800000),
597 MT6366_REG_FIXED("vfe28", VFE28, "vsys-ldo1", MT6358_LDO_VFE28_CON0, 0, 2800000),
598 MT6366_REG_FIXED("vcn28", VCN28, "vsys-ldo1", MT6358_LDO_VCN28_CON0, 0, 2800000),
599 MT6366_REG_FIXED("vxo22", VXO22, "vsys-ldo1", MT6358_LDO_VXO22_CON0, 0, 2200000),
600 MT6366_REG_FIXED("vaux18", VAUX18, "vsys-ldo1", MT6358_LDO_VAUX18_CON0, 0, 1800000),
601 MT6366_REG_FIXED("vbif28", VBIF28, "vsys-ldo1", MT6358_LDO_VBIF28_CON0, 0, 2800000),
602 MT6366_REG_FIXED("vio28", VIO28, "vsys-ldo2", MT6358_LDO_VIO28_CON0, 0, 2800000),
603 MT6366_REG_FIXED("va12", VA12, "vs2-ldo2", MT6358_LDO_VA12_CON0, 0, 1200000),
604 MT6366_REG_FIXED("vrf18", VRF18, "vs1-ldo1", MT6358_LDO_VRF18_CON0, 0, 1800000),
605 MT6366_REG_FIXED("vaud28", VAUD28, "vsys-ldo1", MT6358_LDO_VAUD28_CON0, 0, 2800000),
606 MT6366_LDO("vdram2", VDRAM2, vdram2, "vs2-ldo1",
608 MT6366_LDO("vsim1", VSIM1, vsim, "vsys-ldo1",
610 MT6366_LDO("vibr", VIBR, vibr, "vsys-ldo3",
612 MT6366_LDO("vusb", VUSB, vusb, "vsys-ldo1",
614 MT6366_LDO("vefuse", VEFUSE, vefuse, "vs1-ldo1",
616 MT6366_LDO("vmch", VMCH, vmch_vemc, "vsys-ldo2",
618 MT6366_LDO("vemc", VEMC, vmch_vemc, "vsys-ldo3",
620 MT6366_LDO("vcn33", VCN33, vcn33, "vsys-ldo3",
622 MT6366_LDO("vmc", VMC, vmc, "vsys-ldo2",
624 MT6366_LDO("vsim2", VSIM2, vsim, "vsys-ldo2",
626 MT6366_LDO("vcn18", VCN18, mt6366_vcn18_vm18, "vs1-ldo1",
628 MT6366_LDO("vm18", VM18, mt6366_vcn18_vm18, "vs1-ldo1",
630 MT6366_LDO("vmddr", VMDDR, mt6366_vmddr, "vs2-ldo1",
632 MT6366_LDO1("vsram-proc11", VSRAM_PROC11, "vs2-ldo3", 500000, 1293750, 6250,
634 MT6366_LDO1("vsram-others", VSRAM_OTHERS, "vs2-ldo3", 500000, 1293750, 6250,
636 MT6366_LDO1("vsram-gpu", VSRAM_GPU, "vs2-ldo3", 500000, 1293750, 6250,
638 MT6366_LDO1("vsram-proc12", VSRAM_PROC12, "vs2-ldo3", 500000, 1293750, 6250,
640 MT6366_LDO1("vsram-core", VSRAM_CORE, "vs2-ldo3", 500000, 1293750, 6250,
646 struct mt6397_chip *mt6397 = dev_get_drvdata(dev->parent); in mt6358_sync_vcn33_setting()
657 ret = regmap_read(mt6397->regmap, MT6358_LDO_VCN33_CON0_1, &val); in mt6358_sync_vcn33_setting()
667 ret = regmap_update_bits(mt6397->regmap, MT6358_LDO_VCN33_CON0_0, BIT(0), BIT(0)); in mt6358_sync_vcn33_setting()
674 ret = regmap_update_bits(mt6397->regmap, MT6358_LDO_VCN33_CON0_1, BIT(0), 0); in mt6358_sync_vcn33_setting()
685 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); in mt6358_regulator_probe()
691 switch (mt6397->chip_id) { in mt6358_regulator_probe()
701 dev_err(&pdev->dev, "unsupported chip ID: %d\n", mt6397->chip_id); in mt6358_regulator_probe()
702 return -EINVAL; in mt6358_regulator_probe()
705 ret = mt6358_sync_vcn33_setting(&pdev->dev); in mt6358_regulator_probe()
710 config.dev = &pdev->dev; in mt6358_regulator_probe()
711 config.regmap = mt6397->regmap; in mt6358_regulator_probe()
713 rdev = devm_regulator_register(&pdev->dev, in mt6358_regulator_probe()
717 dev_err(&pdev->dev, "failed to register %s\n", in mt6358_regulator_probe()
727 {"mt6358-regulator", 0},
734 .name = "mt6358-regulator",
743 MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>");