Lines Matching +full:1 +full:hz
8 * - Supports frequencies between 0.5Hz and 2048Hz with following steps:
9 * - 0.5 Hz steps from 0.5 Hz to 32 Hz
10 * - 2 Hz steps from 2 Hz to 128 Hz
11 * - 8 Hz steps from 8 Hz to 512 Hz
12 * - 32 Hz steps from 32 Hz to 2048 Hz
37 #define MC33XS2410_GLB_CTRL_MODE_NORMAL FIELD_PREP(MC33XS2410_GLB_CTRL_MODE, 1)
40 /* chan in { 1 ... 4 } */
41 #define MC33XS2410_PWM_CTRL1_POL_INV(chan) BIT((chan) + 1)
44 /* chan in { 1 ... 4 } */
45 #define MC33XS2410_PWM_CTRL3_EN(chan) BIT(4 + (chan) - 1)
47 /* chan in { 1 ... 4 } */
48 #define MC33XS2410_PWM_FREQ(chan) (0x08 + (chan) - 1)
52 /* chan in { 1 ... 4 } */
53 #define MC33XS2410_PWM_DC(chan) (0x0c + (chan) - 1)
102 for (i = 0; i < len - 1; i++) in mc33xs2410_read_regs()
106 ret = spi_sync_transfer(spi, &t, 1); in mc33xs2410_read_regs()
110 for (i = 1; i < len; i++) in mc33xs2410_read_regs()
111 val[i - 1] = FIELD_GET(MC33XS2410_FRAME_OUT_DATA, rx[i]); in mc33xs2410_read_regs()
118 return mc33xs2410_write_regs(spi, ®, &val, 1); in mc33xs2410_write_reg()
123 return mc33xs2410_read_regs(spi, ®, flag, val, 1); in mc33xs2410_read_reg()
169 case MC33XS2410_PWM_MAX_PERIOD(3) + 1 ... MC33XS2410_PWM_MAX_PERIOD(2): in mc33xs2410_pwm_get_freq()
172 case MC33XS2410_PWM_MAX_PERIOD(2) + 1 ... MC33XS2410_PWM_MAX_PERIOD(1): in mc33xs2410_pwm_get_freq()
173 step = 1; in mc33xs2410_pwm_get_freq()
175 case MC33XS2410_PWM_MAX_PERIOD(1) + 1 ... MC33XS2410_PWM_MAX_PERIOD(0): in mc33xs2410_pwm_get_freq()
186 FIELD_PREP(MC33XS2410_PWM_FREQ_COUNT, count - 1); in mc33xs2410_pwm_get_freq()
195 * - 0 = 0.5Hz in mc33xs2410_pwm_get_period()
196 * - 1 = 2Hz in mc33xs2410_pwm_get_period()
197 * - 2 = 8Hz in mc33xs2410_pwm_get_period()
198 * - 3 = 32Hz in mc33xs2410_pwm_get_period()
199 * frequency = (code + 1) x steps. in mc33xs2410_pwm_get_period()
205 doubled_steps = 1 << (FIELD_GET(MC33XS2410_PWM_FREQ_STEP, reg) * 2); in mc33xs2410_pwm_get_period()
207 doubled_freq = (code + 1) * doubled_steps; in mc33xs2410_pwm_get_period()
226 MC33XS2410_PWM_FREQ(pwm->hwpwm + 1), in mc33xs2410_pwm_apply()
227 MC33XS2410_PWM_DC(pwm->hwpwm + 1), in mc33xs2410_pwm_apply()
252 rel_dc = div64_u64(duty_cycle * 256, period) - 1; in mc33xs2410_pwm_apply()
254 wr_val[1] = rel_dc; in mc33xs2410_pwm_apply()
256 wr_val[1] = 0; in mc33xs2410_pwm_apply()
258 wr_val[1] = 255; in mc33xs2410_pwm_apply()
261 mask = MC33XS2410_PWM_CTRL1_POL_INV(pwm->hwpwm + 1); in mc33xs2410_pwm_apply()
268 mask = MC33XS2410_PWM_CTRL3_EN(pwm->hwpwm + 1); in mc33xs2410_pwm_apply()
271 wr_val[3] = rd_val[1] | mask; in mc33xs2410_pwm_apply()
273 wr_val[3] = rd_val[1] & ~mask; in mc33xs2410_pwm_apply()
284 MC33XS2410_PWM_FREQ(pwm->hwpwm + 1), in mc33xs2410_pwm_get_state()
285 MC33XS2410_PWM_DC(pwm->hwpwm + 1), in mc33xs2410_pwm_get_state()
298 state->polarity = (val[2] & MC33XS2410_PWM_CTRL1_POL_INV(pwm->hwpwm + 1)) ? in mc33xs2410_pwm_get_state()
300 state->enabled = !!(val[3] & MC33XS2410_PWM_CTRL3_EN(pwm->hwpwm + 1)); in mc33xs2410_pwm_get_state()
301 state->duty_cycle = DIV_ROUND_UP_ULL((val[1] + 1) * state->period, 256); in mc33xs2410_pwm_get_state()