1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/pwm.h>
28  * struct crystalcove_pwm - Crystal Cove PWM controller
45 	/* clk_div 1 - 128, maps to register values 0-127 */  in crc_pwm_calc_clk_div()
47 		clk_div--;  in crc_pwm_calc_clk_div()
52 static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in crc_pwm_apply()  argument
59 	if (state->period > PWM_MAX_PERIOD_NS) {  in crc_pwm_apply()
60 		dev_err(dev, "un-supported period_ns\n");  in crc_pwm_apply()
61 		return -EINVAL;  in crc_pwm_apply()
64 	if (state->polarity != PWM_POLARITY_NORMAL)  in crc_pwm_apply()
65 		return -EINVAL;  in crc_pwm_apply()
67 	if (pwm_is_enabled(pwm) && !state->enabled) {  in crc_pwm_apply()
68 		err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);  in crc_pwm_apply()
75 	if (pwm_get_duty_cycle(pwm) != state->duty_cycle ||  in crc_pwm_apply()
76 	    pwm_get_period(pwm) != state->period) {  in crc_pwm_apply()
77 		u64 level = state->duty_cycle * PWM_MAX_LEVEL;  in crc_pwm_apply()
79 		do_div(level, state->period);  in crc_pwm_apply()
81 		err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);  in crc_pwm_apply()
88 	if (pwm_is_enabled(pwm) && state->enabled &&  in crc_pwm_apply()
89 	    pwm_get_period(pwm) != state->period) {  in crc_pwm_apply()
91 		err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0);  in crc_pwm_apply()
98 	if (pwm_get_period(pwm) != state->period ||  in crc_pwm_apply()
99 	    pwm_is_enabled(pwm) != state->enabled) {  in crc_pwm_apply()
100 		int clk_div = crc_pwm_calc_clk_div(state->period);  in crc_pwm_apply()
101 		int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0;  in crc_pwm_apply()
103 		err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,  in crc_pwm_apply()
111 	if (!pwm_is_enabled(pwm) && state->enabled) {  in crc_pwm_apply()
112 		err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);  in crc_pwm_apply()
122 static int crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,  in crc_pwm_get_state()  argument
130 	error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);  in crc_pwm_get_state()
136 	error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);  in crc_pwm_get_state()
144 	state->period =  in crc_pwm_get_state()
146 	state->duty_cycle =  in crc_pwm_get_state()
147 		DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);  in crc_pwm_get_state()
148 	state->polarity = PWM_POLARITY_NORMAL;  in crc_pwm_get_state()
149 	state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);  in crc_pwm_get_state()
163 	struct device *dev = pdev->dev.parent;  in crystalcove_pwm_probe()
166 	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*crc_pwm));  in crystalcove_pwm_probe()
171 	chip->ops = &crc_pwm_ops;  in crystalcove_pwm_probe()
174 	crc_pwm->regmap = pmic->regmap;  in crystalcove_pwm_probe()
176 	return devm_pwmchip_add(&pdev->dev, chip);  in crystalcove_pwm_probe()
188 MODULE_DESCRIPTION("Intel Crystalcove (CRC) PWM support");