Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:f_
1 // SPDX-License-Identifier: GPL-2.0
3 * R8A77995 processor support - PFC hardware block.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
9 * R-Car Gen3 processor support - PFC hardware block.
21 PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
41 * F_() : just information
46 #define GPSR0_8 F_(MLB_SIG, IP0_27_24)
47 #define GPSR0_7 F_(MLB_DAT, IP0_23_20)
48 #define GPSR0_6 F_(MLB_CLK, IP0_19_16)
49 #define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
50 #define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
51 #define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
52 #define GPSR0_2 F_(IRQ0_A, IP0_3_0)
57 #define GPSR1_31 F_(QPOLB, IP4_27_24)
58 #define GPSR1_30 F_(QPOLA, IP4_23_20)
59 #define GPSR1_29 F_(DU_CDE, IP4_19_16)
60 #define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
61 #define GPSR1_27 F_(DU_DISP, IP4_11_8)
62 #define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
63 #define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
64 #define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
65 #define GPSR1_23 F_(DU_DR7, IP3_27_24)
66 #define GPSR1_22 F_(DU_DR6, IP3_23_20)
67 #define GPSR1_21 F_(DU_DR5, IP3_19_16)
68 #define GPSR1_20 F_(DU_DR4, IP3_15_12)
69 #define GPSR1_19 F_(DU_DR3, IP3_11_8)
70 #define GPSR1_18 F_(DU_DR2, IP3_7_4)
71 #define GPSR1_17 F_(DU_DR1, IP3_3_0)
72 #define GPSR1_16 F_(DU_DR0, IP2_31_28)
73 #define GPSR1_15 F_(DU_DG7, IP2_27_24)
74 #define GPSR1_14 F_(DU_DG6, IP2_23_20)
75 #define GPSR1_13 F_(DU_DG5, IP2_19_16)
76 #define GPSR1_12 F_(DU_DG4, IP2_15_12)
77 #define GPSR1_11 F_(DU_DG3, IP2_11_8)
78 #define GPSR1_10 F_(DU_DG2, IP2_7_4)
79 #define GPSR1_9 F_(DU_DG1, IP2_3_0)
80 #define GPSR1_8 F_(DU_DG0, IP1_31_28)
81 #define GPSR1_7 F_(DU_DB7, IP1_27_24)
82 #define GPSR1_6 F_(DU_DB6, IP1_23_20)
83 #define GPSR1_5 F_(DU_DB5, IP1_19_16)
84 #define GPSR1_4 F_(DU_DB4, IP1_15_12)
85 #define GPSR1_3 F_(DU_DB3, IP1_11_8)
86 #define GPSR1_2 F_(DU_DB2, IP1_7_4)
87 #define GPSR1_1 F_(DU_DB1, IP1_3_0)
88 #define GPSR1_0 F_(DU_DB0, IP0_31_28)
91 #define GPSR2_31 F_(NFCE_N, IP8_19_16)
92 #define GPSR2_30 F_(NFCLE, IP8_15_12)
93 #define GPSR2_29 F_(NFALE, IP8_11_8)
94 #define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
95 #define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
96 #define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
97 #define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
98 #define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
99 #define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
100 #define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
101 #define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
102 #define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
103 #define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
104 #define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
105 #define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
106 #define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
107 #define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
108 #define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
109 #define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
110 #define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
111 #define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
112 #define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
113 #define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
114 #define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
115 #define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
116 #define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
118 #define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
119 #define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
120 #define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
121 #define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
125 #define GPSR3_9 F_(NFDATA7, IP9_31_28)
126 #define GPSR3_8 F_(NFDATA6, IP9_27_24)
127 #define GPSR3_7 F_(NFDATA5, IP9_23_20)
128 #define GPSR3_6 F_(NFDATA4, IP9_19_16)
129 #define GPSR3_5 F_(NFDATA3, IP9_15_12)
130 #define GPSR3_4 F_(NFDATA2, IP9_11_8)
131 #define GPSR3_3 F_(NFDATA1, IP9_7_4)
132 #define GPSR3_2 F_(NFDATA0, IP9_3_0)
133 #define GPSR3_1 F_(NFWE_N, IP8_31_28)
134 #define GPSR3_0 F_(NFRE_N, IP8_27_24)
137 #define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
138 #define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
139 #define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
140 #define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
143 #define GPSR4_25 F_(SCK2, IP12_11_8)
144 #define GPSR4_24 F_(TX1_A, IP12_7_4)
145 #define GPSR4_23 F_(RX1_A, IP12_3_0)
146 #define GPSR4_22 F_(SCK1_A, IP11_31_28)
147 #define GPSR4_21 F_(TX0_A, IP11_27_24)
148 #define GPSR4_20 F_(RX0_A, IP11_23_20)
149 #define GPSR4_19 F_(SCK0_A, IP11_19_16)
150 #define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
151 #define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
152 #define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
157 #define GPSR4_11 F_(SDA1, IP11_3_0)
158 #define GPSR4_10 F_(SCL1, IP10_31_28)
161 #define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
162 #define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
163 #define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
164 #define GPSR4_4 F_(SSI_WS34, IP10_15_12)
165 #define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
166 #define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
167 #define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
168 #define GPSR4_0 F_(NFRB_N, IP8_23_20)
189 #define GPSR5_2 F_(CAN_CLK, IP12_23_20)
190 #define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
191 #define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
209 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
210 …IOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
211 …2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
212 … FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
213 … FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
214 …NC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
215 … FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
216 … FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
217 … FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
218 … FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
219 …UT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
220 …UT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
221 …OUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
222 …OUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
223 … FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
224 … FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
225 … FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
226 …FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
227 …M(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
228 …T11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
229 …12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
230 …T13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
231 …T14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
232 …T15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
233 …UT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
234 …UT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
235 …T18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
236 …T19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
237 …20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
238 …OUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
239 …T22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
240 …23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
241 …0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
243 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
244 …QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
245 …QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
246 …QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
247 …Q2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
248 …QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
249 …QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
250 …QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
251 … FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
252 … FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
253 … FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
254 … FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
255 … FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
256 … FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
257 …FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
258 …DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
259 …S2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
260 … FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
261 … FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
262 …FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
263 …1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
264 …_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
265 …SI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
266 … FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
267 … FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
268 …FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
269 …SI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
270 …F3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
271 …OF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
272 …OF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
273 …OF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
274 …M(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
275 … FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
277 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
278 … FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
279 …(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
280 …FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
281 …FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
282 …CE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
283 …RB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
284 …FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
285 …FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
286 … FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
287 … FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
288 … FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
289 … FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
290 … FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
291 … FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
292 … FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
293 … FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
294 …KA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
295 …O_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
296 …O_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
297 …SO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
298 …) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
299 …SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
300 …SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
301 … FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
302 … FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
303 …_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
304 …P_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
305 …VTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
306 …FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
307 …FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
308 … FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
309 …AN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
311 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
312 …) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
313 …) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
314 …) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
315 …E_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
316 …H_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
317 …FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
318 …0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
319 …0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
320 …) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
321 …) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
399 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
406 #define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0))
407 #define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0))
408 #define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
409 #define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
458 PINMUX_RESERVED = 0,
464 #define F_(x, y) macro
472 #undef F_
475 #define F_(x, y) macro
482 #undef F_
946 * Pins not associated with a GPIO port.
958 /* - AUDIO CLOCK ------------------------------------------------------------- */
960 /* CLK A */
988 /* - EtherAVB --------------------------------------------------------------- */
1025 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1054 RCAR_GP_PIN(5, 0),
1081 /* - CAN ------------------------------------------------------------------ */
1111 /* - CAN Clock -------------------------------------------------------------- */
1120 /* - CAN FD ----------------------------------------------------------------- */
1136 /* - DU --------------------------------------------------------------------- */
1155 /* R[7:0], G[7:0], B[7:0] */
1161 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1164 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1217 /* - I2C -------------------------------------------------------------------- */
1220 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1248 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1255 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1261 /* - MLB+ ------------------------------------------------------------------- */
1263 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7),
1269 /* - MMC ------------------------------------------------------------------- */
1271 /* D[0:7] */
1275 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1285 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1291 /* - MSIOF0 ----------------------------------------------------------------- */
1346 /* - MSIOF1 ----------------------------------------------------------------- */
1401 /* - MSIOF2 ----------------------------------------------------------------- */
1404 RCAR_GP_PIN(0, 3),
1413 RCAR_GP_PIN(0, 6),
1422 RCAR_GP_PIN(0, 2),
1431 RCAR_GP_PIN(0, 7),
1440 RCAR_GP_PIN(0, 8),
1449 RCAR_GP_PIN(0, 4),
1458 RCAR_GP_PIN(0, 5),
1465 /* - MSIOF3 ----------------------------------------------------------------- */
1531 RCAR_GP_PIN(1, 9),
1558 RCAR_GP_PIN(1, 0),
1574 /* - PWM0 ------------------------------------------------------------------ */
1602 /* - PWM1 ------------------------------------------------------------------ */
1630 /* - PWM2 ------------------------------------------------------------------ */
1658 /* - PWM3 ------------------------------------------------------------------ */
1679 RCAR_GP_PIN(4, 0),
1686 /* - QSPI0 ------------------------------------------------------------------ */
1689 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
1694 /* - QSPI1 ------------------------------------------------------------------ */
1703 /* - RPC -------------------------------------------------------------------- */
1705 /* Octal-SPI flash: C/SCLK */
1707 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 6),
1713 /* Octal-SPI flash: S#/CS, DQS */
1721 /* DQ[0:7] */
1725 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 10),
1748 /* - SCIF0 ------------------------------------------------------------------ */
1784 /* - SCIF1 ------------------------------------------------------------------ */
1821 /* - SCIF2 ------------------------------------------------------------------ */
1836 /* - SCIF3 ------------------------------------------------------------------ */
1865 /* - SCIF4 ------------------------------------------------------------------ */
1894 /* - SCIF5 ------------------------------------------------------------------ */
1897 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1904 RCAR_GP_PIN(0, 6),
1923 /* - SCIF Clock ------------------------------------------------------------- */
1932 /* - SSI ---------------------------------------------------------------*/
1976 /* - USB0 ------------------------------------------------------------------- */
1979 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1985 /* - VIN4 ------------------------------------------------------------------- */
2013 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
2059 RCAR_GP_PIN(2, 0),
2152 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
2153 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
2488 #define F_(x, y) FN_##y macro
2490 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2491 GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2504 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2538 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2572 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2573 GROUP(-22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2587 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2621 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2622 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2648 { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
2649 GROUP(-18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2668 #undef F_
2671 #define F_(x, y) x, macro
2673 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2683 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2693 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2703 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2713 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2723 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2733 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2743 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2753 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2763 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2773 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
2783 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
2793 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
2803 { PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32,
2804 GROUP(-24, 4, 4),
2810 #undef F_
2813 #define F_(x, y) x, macro
2815 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2816 GROUP(-1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, -1,
2817 1, 1, 1, 1, 1, 1, -4, 1, 1, 1, 1, 1, 1),
2837 /* RESERVED 9, 8, 7, 6 */
2845 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2846 GROUP(1, 1, 1, 1, 1, 1, -26),
2854 /* RESERVED 25-0 */ ))
2866 [POCCTRL0] = { 0xe6060380, },
2867 [POCCTRL2] = { 0xe6060388, },
2868 [TDSELCTRL] = { 0xe60603c0, },
2876 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9): in r8a77995_pin_to_pocctrl()
2878 return 29 - (pin - RCAR_GP_PIN(3, 0)); in r8a77995_pin_to_pocctrl()
2882 return 0; in r8a77995_pin_to_pocctrl()
2885 return -EINVAL; in r8a77995_pin_to_pocctrl()
2890 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2891 [ 0] = RCAR_GP_PIN(1, 9), /* DU_DG1 */
2900 [ 9] = RCAR_GP_PIN(1, 0), /* DU_DB0 */
2902 [11] = RCAR_GP_PIN(0, 8), /* MLB_SIG */
2903 [12] = RCAR_GP_PIN(0, 7), /* MLB_DAT */
2904 [13] = RCAR_GP_PIN(0, 6), /* MLB_CLK */
2905 [14] = RCAR_GP_PIN(0, 5), /* MSIOF2_RXD */
2906 [15] = RCAR_GP_PIN(0, 4), /* MSIOF2_TXD */
2907 [16] = RCAR_GP_PIN(0, 3), /* MSIOF2_SCK */
2908 [17] = RCAR_GP_PIN(0, 2), /* IRQ0_A */
2909 [18] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
2910 [19] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
2924 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2925 [ 0] = RCAR_GP_PIN(2, 9), /* VI4_DATA8 */
2934 [ 9] = RCAR_GP_PIN(2, 0), /* VI4_CLK */
2958 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2959 [ 0] = RCAR_GP_PIN(3, 8), /* NFDATA6 */
2967 [ 8] = RCAR_GP_PIN(3, 0), /* NFRE# (PUEN) / NFWE# (PUD) */
2968 [ 9] = RCAR_GP_PIN(4, 0), /* NFRB# */
2992 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2993 [ 0] = RCAR_GP_PIN(4, 31), /* CAN0_RX_A */
2996 [ 3] = RCAR_GP_PIN(5, 0), /* TPU0TO0_A */
3002 [ 9] = RCAR_GP_PIN(4, 22), /* SCK1_A */
3015 [22] = RCAR_GP_PIN(4, 9), /* SDA0 */
3024 [31] = RCAR_GP_PIN(3, 9), /* NFDATA7 */
3026 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
3027 [ 0] = RCAR_GP_PIN(6, 10), /* QSPI1_IO3 */
3028 [ 1] = RCAR_GP_PIN(6, 9), /* QSPI1_IO2 */
3036 [ 9] = RCAR_GP_PIN(6, 1), /* QSPI0_MOSI_IO0 */
3037 [10] = RCAR_GP_PIN(6, 0), /* QSPI0_SPCLK */
3049 [22] = RCAR_GP_PIN(5, 9), /* AVB0_TX_CTL */
3060 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) {
3061 [ 0] = SH_PFC_PIN_NONE,
3070 [ 9] = SH_PFC_PIN_NONE,
3104 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); in r8a77995_pin_to_bias_reg()
3112 case RCAR_GP_PIN(3, 0): /* NFRE# */ in r8a77995_pin_to_bias_reg()
3138 if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit))) in r8a77995_pinmux_get_bias()
3140 else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit)) in r8a77995_pinmux_get_bias()
3157 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit); in r8a77995_pinmux_set_bias()
3161 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit); in r8a77995_pinmux_set_bias()
3165 sh_pfc_write(pfc, reg->pud, updown); in r8a77995_pinmux_set_bias()
3167 sh_pfc_write(pfc, reg->puen, enable); in r8a77995_pinmux_set_bias()
3179 .unlock_reg = 0xe6060000, /* PMMR */