Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:f_
1 // SPDX-License-Identifier: GPL-2.0
3 * R8A77980 processor support - PFC hardware block.
8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
10 * R-Car Gen3 processor support - PFC hardware block.
22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
43 * F_() : just information
48 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
49 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
50 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
51 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
52 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
53 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
54 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
55 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
56 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
57 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
58 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
59 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
60 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
61 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
62 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
63 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
64 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
65 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
66 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
67 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
68 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
69 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
72 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
73 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
74 #define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
75 #define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
76 #define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
77 #define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
78 #define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
79 #define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
80 #define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
99 #define GPSR1_0 F_(IRQ0, IP2_27_24)
102 #define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
103 #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
104 #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
105 #define GPSR2_26 F_(SDA3, IP10_7_4)
106 #define GPSR2_25 F_(SCL3, IP10_3_0)
107 #define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
108 #define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
109 #define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
110 #define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
111 #define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
112 #define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
113 #define GPSR2_18 F_(IRQ5, IP9_7_4)
114 #define GPSR2_17 F_(IRQ4, IP9_3_0)
115 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
116 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
117 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
118 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
119 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
120 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
121 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
122 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
123 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
124 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
125 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
126 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
127 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
128 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
129 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
130 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
131 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
134 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
135 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
136 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
137 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
138 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
139 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
140 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
141 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
142 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
143 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
144 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
145 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
146 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
147 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
148 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
149 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
150 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
172 #define GPSR4_5 F_(SDA2, IP7_27_24)
173 #define GPSR4_4 F_(SCL2, IP7_23_20)
174 #define GPSR4_3 F_(SDA1, IP7_19_16)
175 #define GPSR4_2 F_(SCL1, IP7_15_12)
176 #define GPSR4_1 F_(SDA0, IP7_11_8)
177 #define GPSR4_0 F_(SCL0, IP7_7_4)
197 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
198 …R_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
199 …ER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
200 …HER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
201 …HER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
202 …R_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
203 …) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
204 …) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
205 …REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
206 …) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
207 …(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
208 …ETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
209 … FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
210 … FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
211 …M(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
212 …M(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
213 … FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
214 …(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
215 …(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
216 …ETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
217 …B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
218 …OF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
219 …MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
220 …(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
221 …2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
222 …) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
223 …_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
224 …SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
225 …_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
226 …SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
227 …AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
228 … FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
229 …TS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
230 …TS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
231 …HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
232 …HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
233 … FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
234 …S2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
235 …S2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
236 …HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
237 … FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
238 …MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
239 …(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
240 …(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
241 …MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
242 …MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
243 …MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
244 …ANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
245 …ANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
246 …ANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
247 …ATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
248 …ATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
249 …ATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
250 …TA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
251 …FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
252 …FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
253 … FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
254 … FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
255 …SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
256 …DA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
257 …) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
258 … F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
259 …CL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
260 …A2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
261 … FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
262 … FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
263 …M(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
264 …FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
265 …2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
266 …3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
267 …M(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
268 …GRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
269 …RF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
270 …Q4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
271 …Q5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
272 …M(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
273 …M(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
274 …M(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
275 …M(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
276 …TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
277 …TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
278 …L3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
279 …A3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
280 …_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
281 …_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
282 …TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
346 /* MOD_SEL0 */ /* 0 */ /* 1 */
374 PINMUX_RESERVED = 0,
380 #define F_(x, y) macro
388 #undef F_
391 #define F_(x, y) macro
398 #undef F_
844 * Pins not associated with a GPIO port.
856 /* - AVB -------------------------------------------------------------------- */
891 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
932 /* - CANFD0 ----------------------------------------------------------------- */
948 /* - CANFD1 ----------------------------------------------------------------- */
957 /* - CANFD Clock ------------------------------------------------------------ */
973 /* - DU --------------------------------------------------------------------- */
976 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
977 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
978 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
979 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
980 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
981 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
992 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
993 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
994 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
996 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
997 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
999 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
1000 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
1016 RCAR_GP_PIN(0, 18),
1023 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1030 RCAR_GP_PIN(0, 21),
1050 /* - GETHER ----------------------------------------------------------------- */
1074 RCAR_GP_PIN(0, 18),
1081 RCAR_GP_PIN(0, 19),
1091 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1111 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1143 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1144 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1145 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1146 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
1155 /* - HSCIF0 ----------------------------------------------------------------- */
1158 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
1165 RCAR_GP_PIN(0, 12),
1172 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1199 /* - HSCIF1 ----------------------------------------------------------------- */
1216 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1222 /* - HSCIF2 ----------------------------------------------------------------- */
1245 /* - HSCIF3 ----------------------------------------------------------------- */
1255 RCAR_GP_PIN(2, 0),
1268 /* - I2C0 ------------------------------------------------------------------- */
1271 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1277 /* - I2C1 ------------------------------------------------------------------- */
1286 /* - I2C2 ------------------------------------------------------------------- */
1295 /* - I2C3 ------------------------------------------------------------------- */
1304 /* - I2C4 ------------------------------------------------------------------- */
1313 /* - I2C5 ------------------------------------------------------------------- */
1316 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1322 /* - INTC-EX ---------------------------------------------------------------- */
1325 RCAR_GP_PIN(1, 0),
1332 RCAR_GP_PIN(0, 12),
1339 RCAR_GP_PIN(0, 13),
1346 RCAR_GP_PIN(0, 14),
1366 /* - MMC -------------------------------------------------------------------- */
1368 /* MMC_D[0:7] */
1369 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1409 /* - MSIOF0 ----------------------------------------------------------------- */
1453 /* - MSIOF1 ----------------------------------------------------------------- */
1491 RCAR_GP_PIN(3, 0),
1497 /* - MSIOF2 ----------------------------------------------------------------- */
1500 RCAR_GP_PIN(2, 0),
1541 /* - MSIOF3 ----------------------------------------------------------------- */
1544 RCAR_GP_PIN(0, 20),
1551 RCAR_GP_PIN(0, 21),
1558 RCAR_GP_PIN(0, 18),
1565 RCAR_GP_PIN(0, 19),
1572 RCAR_GP_PIN(0, 17),
1579 RCAR_GP_PIN(0, 16),
1585 /* - PWM0 ------------------------------------------------------------------- */
1588 RCAR_GP_PIN(0, 15),
1601 /* - PWM1 ------------------------------------------------------------------- */
1617 /* - PWM2 ------------------------------------------------------------------- */
1633 /* - PWM3 ------------------------------------------------------------------- */
1649 /* - PWM4 ------------------------------------------------------------------- */
1665 /* - QSPI0 ------------------------------------------------------------------ */
1668 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1674 /* - QSPI1 ------------------------------------------------------------------ */
1683 /* - RPC -------------------------------------------------------------------- */
1685 /* Octal-SPI flash: C/SCLK */
1687 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1693 /* Octal-SPI flash: S#/CS, DQS */
1701 /* DQ[0:7] */
1705 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1735 /* - SCIF0 ------------------------------------------------------------------ */
1758 /* - SCIF1 ------------------------------------------------------------------ */
1761 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1788 /* - SCIF3 ------------------------------------------------------------------ */
1798 RCAR_GP_PIN(2, 0),
1811 /* - SCIF4 ------------------------------------------------------------------ */
1814 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1821 RCAR_GP_PIN(0, 0),
1828 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1834 /* - SCIF Clock ------------------------------------------------------------- */
1837 RCAR_GP_PIN(0, 10),
1850 /* - TMU -------------------------------------------------------------------- */
1880 /* - TPU ------------------------------------------------------------------- */
1910 /* - VIN0 ------------------------------------------------------------------- */
1914 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1941 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1984 RCAR_GP_PIN(2, 0),
1990 /* - VIN1 ------------------------------------------------------------------- */
1994 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2030 RCAR_GP_PIN(3, 0),
2138 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
2139 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
2507 #define F_(x, y) FN_##y macro
2509 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2510 GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2537 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2538 0, 0,
2539 0, 0,
2540 0, 0,
2541 0, 0,
2571 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2572 0, 0,
2573 0, 0,
2605 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2606 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2628 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2629 GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2660 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2661 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2681 #undef F_
2684 #define F_(x, y) x, macro
2686 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2696 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2706 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2716 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2726 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2736 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2746 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2756 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2766 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2776 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2786 { PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
2787 GROUP(-12, 4, 4, 4, 4, 4),
2796 #undef F_
2799 #define F_(x, y) x, macro
2801 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2802 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1),
2804 /* RESERVED 31-12 */
2830 [POCCTRL0] = { 0xe6060380, },
2831 [POCCTRL1] = { 0xe6060384, },
2832 [POCCTRL2] = { 0xe6060388, },
2833 [POCCTRL3] = { 0xe606038c, },
2834 [TDSELCTRL] = { 0xe60603c0, },
2840 int bit = pin & 0x1f; in r8a77980_pin_to_pocctrl()
2843 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21): in r8a77980_pin_to_pocctrl()
2847 case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9): in r8a77980_pin_to_pocctrl()
2853 return bit - 10; in r8a77980_pin_to_pocctrl()
2856 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16): in r8a77980_pin_to_pocctrl()
2862 return pin - 25; in r8a77980_pin_to_pocctrl()
2866 return 0; in r8a77980_pin_to_pocctrl()
2873 return -EINVAL; in r8a77980_pin_to_pocctrl()
2878 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2879 [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
2880 [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
2881 [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
2882 [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
2883 [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
2884 [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
2885 [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
2886 [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
2887 [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
2888 [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
2889 [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
2890 [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
2891 [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
2892 [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
2893 [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
2894 [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
2895 [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
2896 [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
2897 [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
2898 [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
2899 [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
2900 [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
2912 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2913 [ 0] = PIN_FSCLKST, /* FSCLKST */
2915 [ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */
2921 [ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
2922 [ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
2930 [17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
2938 [25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
2946 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2947 [ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
2949 [ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
2956 [ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
2957 [10] = RCAR_GP_PIN(4, 0), /* SCL0 */
2971 [24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */
2980 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2981 [ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */
2988 [ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */
2990 [ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */
3009 [28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
3014 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
3015 [ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
3020 [ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
3024 [ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
3060 .unlock_reg = 0xe6060000, /* PMMR */