110 	struct npcm8xx_gpio	gpio_bank[NPCM8XX_GPIO_BANK_NUM];  member
1904 		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];  in npcm8xx_get_drive_strength()
1925 		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];  in npcm8xx_set_drive_strength()
2056 		&npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK];  in npcm_gpio_set_direction()
2147 		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];  in npcm_set_debounce()
2174 		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];  in npcm8xx_config_get()
2236 		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];  in npcm8xx_config_set_one()
2330 		pctrl->gpio_bank[id].base = fwnode_iomap(child, 0);  in npcm8xx_gpio_fw()
2331 		if (!pctrl->gpio_bank[id].base)  in npcm8xx_gpio_fw()
2334 		ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4,  in npcm8xx_gpio_fw()
2335 				 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN,  in npcm8xx_gpio_fw()
2336 				 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT,  in npcm8xx_gpio_fw()
2339 				 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM,  in npcm8xx_gpio_fw()
2352 		pctrl->gpio_bank[id].irq = ret;  in npcm8xx_gpio_fw()
2353 		pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;  in npcm8xx_gpio_fw()
2354 		pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK;  in npcm8xx_gpio_fw()
2355 		pctrl->gpio_bank[id].pinctrl_id = args.args[0];  in npcm8xx_gpio_fw()
2356 		pctrl->gpio_bank[id].gc.base = -1;  in npcm8xx_gpio_fw()
2357 		pctrl->gpio_bank[id].gc.ngpio = args.args[2];  in npcm8xx_gpio_fw()
2358 		pctrl->gpio_bank[id].gc.owner = THIS_MODULE;  in npcm8xx_gpio_fw()
2359 		pctrl->gpio_bank[id].gc.parent = dev;  in npcm8xx_gpio_fw()
2360 		pctrl->gpio_bank[id].gc.fwnode = child;  in npcm8xx_gpio_fw()
2361 		pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);  in npcm8xx_gpio_fw()
2362 		if (pctrl->gpio_bank[id].gc.label == NULL)  in npcm8xx_gpio_fw()
2365 		pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;  in npcm8xx_gpio_fw()
2366 		pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input;  in npcm8xx_gpio_fw()
2367 		pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input;  in npcm8xx_gpio_fw()
2368 		pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output;  in npcm8xx_gpio_fw()
2369 		pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;  in npcm8xx_gpio_fw()
2370 		pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;  in npcm8xx_gpio_fw()
2371 		pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;  in npcm8xx_gpio_fw()
2372 		pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free;  in npcm8xx_gpio_fw()
2374 			pctrl->gpio_bank[id].debounce.set_val[i] = false;  in npcm8xx_gpio_fw()
2375 		pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges;  in npcm8xx_gpio_fw()
2390 		girq = &pctrl->gpio_bank[id].gc.irq;  in npcm8xx_gpio_register()
2391 		girq->chip = &pctrl->gpio_bank[id].irq_chip;  in npcm8xx_gpio_register()
2400 		girq->parents[0] = pctrl->gpio_bank[id].irq;  in npcm8xx_gpio_register()
2404 					     &pctrl->gpio_bank[id].gc,  in npcm8xx_gpio_register()
2405 					     &pctrl->gpio_bank[id]);  in npcm8xx_gpio_register()