Lines Matching full:phy
3 * Mediatek MT7621 PCI PHY Driver
7 #include <dt-bindings/phy/phy.h>
13 #include <linux/phy/phy.h>
66 * struct mt7621_pci_phy - Mt7621 Pcie PHY core
69 * @phy: pointer to the kernel PHY device
72 * @has_dual_port: if the phy has dual ports.
79 struct phy *phy; member
86 static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy, in mt7621_phy_rmw() argument
98 regmap_read(phy->regmap, reg, &val); in mt7621_phy_rmw()
101 regmap_write(phy->regmap, reg, val); in mt7621_phy_rmw()
104 static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy) in mt7621_bypass_pipe_rst() argument
106 mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_RST); in mt7621_bypass_pipe_rst()
107 mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_CMD_FRC); in mt7621_bypass_pipe_rst()
109 if (phy->has_dual_port) { in mt7621_bypass_pipe_rst()
110 mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH, in mt7621_bypass_pipe_rst()
112 mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH, in mt7621_bypass_pipe_rst()
117 static int mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) in mt7621_set_phy_for_ssc() argument
119 struct device *dev = phy->dev; in mt7621_set_phy_for_ssc()
122 clk_rate = clk_get_rate(phy->sys_clk); in mt7621_set_phy_for_ssc()
126 /* Set PCIe Port PHY to disable SSC */ in mt7621_set_phy_for_ssc()
128 mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG, in mt7621_set_phy_for_ssc()
134 mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG, RG_PE1_PHY_EN, in mt7621_set_phy_for_ssc()
137 if (phy->has_dual_port) { in mt7621_set_phy_for_ssc()
138 mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH, in mt7621_set_phy_for_ssc()
144 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, in mt7621_set_phy_for_ssc()
149 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, in mt7621_set_phy_for_ssc()
153 mt7621_phy_rmw(phy, RG_PE1_H_PLL_FBKSEL_REG, in mt7621_set_phy_for_ssc()
158 mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG, in mt7621_set_phy_for_ssc()
163 mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG, in mt7621_set_phy_for_ssc()
168 mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG, in mt7621_set_phy_for_ssc()
176 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, in mt7621_set_phy_for_ssc()
183 mt7621_phy_rmw(phy, RG_PE1_LCDDS_CLK_PH_INV_REG, in mt7621_set_phy_for_ssc()
187 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, in mt7621_set_phy_for_ssc()
196 mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG, RG_PE1_H_PLL_BR, in mt7621_set_phy_for_ssc()
201 mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG, in mt7621_set_phy_for_ssc()
210 static int mt7621_pci_phy_init(struct phy *phy) in mt7621_pci_phy_init() argument
212 struct mt7621_pci_phy *mphy = phy_get_drvdata(phy); in mt7621_pci_phy_init()
220 static int mt7621_pci_phy_power_on(struct phy *phy) in mt7621_pci_phy_power_on() argument
222 struct mt7621_pci_phy *mphy = phy_get_drvdata(phy); in mt7621_pci_phy_power_on()
224 /* Enable PHY and disable force mode */ in mt7621_pci_phy_power_on()
236 static int mt7621_pci_phy_power_off(struct phy *phy) in mt7621_pci_phy_power_off() argument
238 struct mt7621_pci_phy *mphy = phy_get_drvdata(phy); in mt7621_pci_phy_power_off()
240 /* Disable PHY */ in mt7621_pci_phy_power_off()
252 static int mt7621_pci_phy_exit(struct phy *phy) in mt7621_pci_phy_exit() argument
265 static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev, in mt7621_pcie_phy_of_xlate()
275 dev_dbg(dev, "PHY for 0x%px (dual port = %d)\n", in mt7621_pcie_phy_of_xlate()
278 return mt7621_phy->phy; in mt7621_pcie_phy_of_xlate()
298 struct mt7621_pci_phy *phy; in mt7621_pci_phy_probe() local
300 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); in mt7621_pci_phy_probe()
301 if (!phy) in mt7621_pci_phy_probe()
306 phy->bypass_pipe_rst = true; in mt7621_pci_phy_probe()
308 phy->dev = dev; in mt7621_pci_phy_probe()
309 platform_set_drvdata(pdev, phy); in mt7621_pci_phy_probe()
311 phy->port_base = devm_platform_ioremap_resource(pdev, 0); in mt7621_pci_phy_probe()
312 if (IS_ERR(phy->port_base)) { in mt7621_pci_phy_probe()
313 dev_err(dev, "failed to remap phy regs\n"); in mt7621_pci_phy_probe()
314 return PTR_ERR(phy->port_base); in mt7621_pci_phy_probe()
317 phy->regmap = devm_regmap_init_mmio(phy->dev, phy->port_base, in mt7621_pci_phy_probe()
319 if (IS_ERR(phy->regmap)) in mt7621_pci_phy_probe()
320 return PTR_ERR(phy->regmap); in mt7621_pci_phy_probe()
322 phy->phy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops); in mt7621_pci_phy_probe()
323 if (IS_ERR(phy->phy)) { in mt7621_pci_phy_probe()
324 dev_err(dev, "failed to create phy\n"); in mt7621_pci_phy_probe()
325 return PTR_ERR(phy->phy); in mt7621_pci_phy_probe()
328 phy->sys_clk = devm_clk_get(dev, NULL); in mt7621_pci_phy_probe()
329 if (IS_ERR(phy->sys_clk)) { in mt7621_pci_phy_probe()
330 dev_err(dev, "failed to get phy clock\n"); in mt7621_pci_phy_probe()
331 return PTR_ERR(phy->sys_clk); in mt7621_pci_phy_probe()
334 phy_set_drvdata(phy->phy, phy); in mt7621_pci_phy_probe()
342 { .compatible = "mediatek,mt7621-pci-phy" },
350 .name = "mt7621-pci-phy",
358 MODULE_DESCRIPTION("MediaTek MT7621 PCIe PHY driver");