Lines Matching +full:axi +full:- +full:dma +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0 */
14 #define RP_ENABLE 1
32 #define DMA_END_ENGINE_1_SHIFT 1
84 #define ATR0_PCIE_ATR_SIZE_SHIFT 1
90 /* PCIe AXI slave table init defines */
92 #define ATR_SIZE_MASK GENMASK(6, 1)
133 * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+
134 * |12|11|10|9| intx |7|6|5|4|3|2|1|0| DMA error | DMA end |
135 * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+
137 * 0-7 (0-7) DMA interrupt end : reserved for vendor implement
138 * 8-15 (8-15) DMA error : reserved for vendor implement
139 * 16 (16) AXI post error (PLDA_AXI_POST_ERR)
140 * 17 (17) AXI fetch error (PLDA_AXI_FETCH_ERR)
141 * 18 (18) AXI discard error (PLDA_AXI_DISCARD_ERR)
142 * 19 (19) AXI doorbell (PLDA_PCIE_DOORBELL)
147 * 24 (27-24) INTx interruts (PLDA_INTX)
216 msi->vector_phy = IMSI_ADDR; in plda_set_default_msi()
217 msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS; in plda_set_default_msi()
224 value = readl_relaxed(plda->bridge_addr + GEN_SETTINGS); in plda_pcie_enable_root_port()
226 writel_relaxed(value, plda->bridge_addr + GEN_SETTINGS); in plda_pcie_enable_root_port()
234 value = readl_relaxed(plda->bridge_addr + PCIE_PCI_IDS_DW1); in plda_pcie_set_standard_class()
237 writel_relaxed(value, plda->bridge_addr + PCIE_PCI_IDS_DW1); in plda_pcie_set_standard_class()
244 value = readl_relaxed(plda->bridge_addr + PCIE_WINROM); in plda_pcie_set_pref_win_64bit()
246 writel_relaxed(value, plda->bridge_addr + PCIE_WINROM); in plda_pcie_set_pref_win_64bit()
253 value = readl_relaxed(plda->bridge_addr + PMSG_SUPPORT_RX); in plda_pcie_disable_ltr()
255 writel_relaxed(value, plda->bridge_addr + PMSG_SUPPORT_RX); in plda_pcie_disable_ltr()
262 value = readl_relaxed(plda->bridge_addr + PCI_MISC); in plda_pcie_disable_func()
264 writel_relaxed(value, plda->bridge_addr + PCI_MISC); in plda_pcie_disable_func()
269 void __iomem *addr = plda->bridge_addr + CONFIG_SPACE_ADDR_OFFSET; in plda_pcie_write_rc_bar()