27 #define PCIECORE_CTLANDSTATUS		0x50
28 #define PIM1_1L				0x80
29 #define IBAR2				0x98
30 #define IR2MSK				0x9c
31 #define PIM2_1L				0xa0
32 #define IBAR3L				0xb4
33 #define IR3MSKL				0xbc
34 #define PIM3_1L				0xc4
35 #define OMR1BARL			0x100
36 #define OMR2BARL			0x118
37 #define OMR3BARL			0x130
38 #define CFGBARL				0x154
39 #define CFGBARH				0x158
40 #define CFGCTL				0x15c
41 #define RTDID				0x160
42 #define BRIDGE_CFG_0			0x2000
43 #define BRIDGE_CFG_4			0x2010
44 #define BRIDGE_STATUS_0			0x2600
46 #define LINK_UP_MASK			0x00000100
47 #define AXI_EP_CFG_ACCESS		0x10000
48 #define EN_COHERENCY			0xF0000000
49 #define EN_REG				0x00000001
50 #define OB_LO_IO			0x00000002
51 #define XGENE_PCIE_DEVICEID		0xE004
52 #define PIPE_PHY_RATE_RD(src)		((0xc000 & (u32)(src)) >> 0xe)
54 #define XGENE_V1_PCI_EXP_CAP		0x40
119 	u32 rtdid_val = 0;  in xgene_pcie_set_rtdid_reg()
153 	if ((pci_is_root_bus(bus) && devfn != 0) ||  in xgene_pcie_map_bus()
167 	ret = pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val);  in xgene_pcie_config_read32()
175 	 * controller fabricates return data of 0xFFFF0001 ("device exists  in xgene_pcie_config_read32()
176 	 * but is not ready") instead of 0xFFFFFFFF (PCI_ERROR_RESPONSE)  in xgene_pcie_config_read32()
182 	    ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))  in xgene_pcie_config_read32()
206 	if (ret < 0) {  in xgene_get_csr_resource()
212 	if (ret == 0) {  in xgene_get_csr_resource()
220 	return 0;  in xgene_get_csr_resource()
248 	return 0;  in xgene_pcie_ecam_init()
284 	u32 val32 = 0;  in xgene_pcie_set_ib_mask()
288 	val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);  in xgene_pcie_set_ib_mask()
291 	val32 = xgene_pcie_readl(port, addr + 0x04);  in xgene_pcie_set_ib_mask()
292 	val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);  in xgene_pcie_set_ib_mask()
293 	xgene_pcie_writel(port, addr + 0x04, val);  in xgene_pcie_set_ib_mask()
295 	val32 = xgene_pcie_readl(port, addr + 0x04);  in xgene_pcie_set_ib_mask()
296 	val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);  in xgene_pcie_set_ib_mask()
297 	xgene_pcie_writel(port, addr + 0x04, val);  in xgene_pcie_set_ib_mask()
299 	val32 = xgene_pcie_readl(port, addr + 0x08);  in xgene_pcie_set_ib_mask()
300 	val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);  in xgene_pcie_set_ib_mask()
301 	xgene_pcie_writel(port, addr + 0x08, val);  in xgene_pcie_set_ib_mask()
338 	return 0;  in xgene_pcie_init_port()
358 	return 0;  in xgene_pcie_map_reg()
368 	u64 mask = 0;  in xgene_pcie_setup_ob_reg()
382 		dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",  in xgene_pcie_setup_ob_reg()
386 	xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));  in xgene_pcie_setup_ob_reg()
387 	xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));  in xgene_pcie_setup_ob_reg()
388 	xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));  in xgene_pcie_setup_ob_reg()
389 	xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));  in xgene_pcie_setup_ob_reg()
390 	xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));  in xgene_pcie_setup_ob_reg()
440 	return 0;  in xgene_pcie_map_ranges()
447 	xgene_pcie_writel(port, pim_reg + 0x04,  in xgene_pcie_setup_pims()
449 	xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));  in xgene_pcie_setup_pims()
450 	xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));  in xgene_pcie_setup_pims()
464 	if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {  in xgene_pcie_select_ib_reg()
465 		*ib_reg_mask |= (1 << 0);  in xgene_pcie_select_ib_reg()
466 		return 0;  in xgene_pcie_select_ib_reg()
493 	if (region < 0) {  in xgene_pcie_setup_ib_reg()
503 	case 0:  in xgene_pcie_setup_ib_reg()
507 		writel(upper_32_bits(cpu_addr), bar_addr + 0x4);  in xgene_pcie_setup_ib_reg()
517 		xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));  in xgene_pcie_setup_ib_reg()
519 		xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));  in xgene_pcie_setup_ib_reg()
533 	u8 ib_reg_mask = 0;  in xgene_pcie_parse_map_dma_ranges()
544 		dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",  in xgene_pcie_parse_map_dma_ranges()
548 	return 0;  in xgene_pcie_parse_map_dma_ranges()
557 		xgene_pcie_writel(port, i, 0);  in xgene_pcie_clear_config()
563 	u32 val, lanes = 0, speed = 0;  in xgene_pcie_setup()
585 	return 0;  in xgene_pcie_setup()