Lines Matching +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
7 /* ----------------------------------------------------- */
9 /* ----------------------------------------------------- */
71 #define MAC0_ON BIT(7)
72 #define MAC1_ON BIT(0)
73 #define MAC0_READY BIT(0)
74 #define MAC1_READY BIT(0)
76 /* ----------------------------------------------------- */
78 /* ----------------------------------------------------- */
123 /* ----------------------------------------------------- */
125 /* ----------------------------------------------------- */
133 /* ----------------------------------------------------- */
135 /* ----------------------------------------------------- */
140 /* ----------------------------------------------------- */
142 /* ----------------------------------------------------- */
166 /* ----------------------------------------------------- */
168 /* ----------------------------------------------------- */
221 /* ----------------------------------------------------- */
223 /* ----------------------------------------------------- */
269 /* Dual MAC Co-Existence Register */
272 /* ----------------------------------------------------- */
274 /* ----------------------------------------------------- */
333 /* ----------------------------------------------------- */
335 /* ----------------------------------------------------- */
349 /* ----------------------------------------------------- */
351 /* ----------------------------------------------------- */
358 /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
359 /* ----------------------------------------------------- */
361 /* ----------------------------------------------------- */
368 #define RRSR_1M BIT(0)
369 #define RRSR_2M BIT(1)
370 #define RRSR_5_5M BIT(2)
371 #define RRSR_11M BIT(3)
372 #define RRSR_6M BIT(4)
373 #define RRSR_9M BIT(5)
374 #define RRSR_12M BIT(6)
375 #define RRSR_18M BIT(7)
376 #define RRSR_24M BIT(8)
377 #define RRSR_36M BIT(9)
378 #define RRSR_48M BIT(10)
379 #define RRSR_54M BIT(11)
380 #define RRSR_MCS0 BIT(12)
381 #define RRSR_MCS1 BIT(13)
382 #define RRSR_MCS2 BIT(14)
383 #define RRSR_MCS3 BIT(15)
384 #define RRSR_MCS4 BIT(16)
385 #define RRSR_MCS5 BIT(17)
386 #define RRSR_MCS6 BIT(18)
387 #define RRSR_MCS7 BIT(19)
388 #define BRSR_ACKSHORTPMB BIT(23)
390 /* ----------------------------------------------------- */
392 /* ----------------------------------------------------- */
427 #define RATE_1M BIT(0)
428 #define RATE_2M BIT(1)
429 #define RATE_5_5M BIT(2)
430 #define RATE_11M BIT(3)
432 #define RATE_6M BIT(4)
433 #define RATE_9M BIT(5)
434 #define RATE_12M BIT(6)
435 #define RATE_18M BIT(7)
436 #define RATE_24M BIT(8)
437 #define RATE_36M BIT(9)
438 #define RATE_48M BIT(10)
439 #define RATE_54M BIT(11)
441 #define RATE_MCS0 BIT(12)
442 #define RATE_MCS1 BIT(13)
443 #define RATE_MCS2 BIT(14)
444 #define RATE_MCS3 BIT(15)
445 #define RATE_MCS4 BIT(16)
446 #define RATE_MCS5 BIT(17)
447 #define RATE_MCS6 BIT(18)
448 #define RATE_MCS7 BIT(19)
450 #define RATE_MCS8 BIT(20)
451 #define RATE_MCS9 BIT(21)
452 #define RATE_MCS10 BIT(22)
453 #define RATE_MCS11 BIT(23)
454 #define RATE_MCS12 BIT(24)
455 #define RATE_MCS13 BIT(25)
456 #define RATE_MCS14 BIT(26)
457 #define RATE_MCS15 BIT(27)
472 /* ----------------------------------------------------- */
473 /* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
474 /* ----------------------------------------------------- */
475 #define BW_OPMODE_20MHZ BIT(2)
476 #define BW_OPMODE_5G BIT(1)
477 #define BW_OPMODE_11J BIT(0)
480 /* ----------------------------------------------------- */
482 /* ----------------------------------------------------- */
483 #define CAM_VALID BIT(15)
485 #define CAM_USEDK BIT(5)
498 #define CAM_WRITE BIT(16)
500 #define CAM_POLLINIG BIT(31)
502 /* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
508 /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */
509 /* ----------------------------------------------------- */
511 /* ----------------------------------------------------- */
513 #define IMR_BCNDMAINT6 BIT(31)
514 #define IMR_BCNDMAINT5 BIT(30)
515 #define IMR_BCNDMAINT4 BIT(29)
516 #define IMR_BCNDMAINT3 BIT(28)
517 #define IMR_BCNDMAINT2 BIT(27)
518 #define IMR_BCNDMAINT1 BIT(26)
519 #define IMR_BCNDOK8 BIT(25)
520 #define IMR_BCNDOK7 BIT(24)
521 #define IMR_BCNDOK6 BIT(23)
522 #define IMR_BCNDOK5 BIT(22)
523 #define IMR_BCNDOK4 BIT(21)
524 #define IMR_BCNDOK3 BIT(20)
525 #define IMR_BCNDOK2 BIT(19)
526 #define IMR_BCNDOK1 BIT(18)
527 #define IMR_TIMEOUT2 BIT(17)
528 #define IMR_TIMEOUT1 BIT(16)
529 #define IMR_TXFOVW BIT(15)
530 #define IMR_PSTIMEOUT BIT(14)
531 #define IMR_BCNINT BIT(13)
532 #define IMR_RXFOVW BIT(12)
533 #define IMR_RDU BIT(11)
534 #define IMR_ATIMEND BIT(10)
535 #define IMR_BDOK BIT(9)
536 #define IMR_HIGHDOK BIT(8)
537 #define IMR_TBDOK BIT(7)
538 #define IMR_MGNTDOK BIT(6)
539 #define IMR_TBDER BIT(5)
540 #define IMR_BKDOK BIT(4)
541 #define IMR_BEDOK BIT(3)
542 #define IMR_VIDOK BIT(2)
543 #define IMR_VODOK BIT(1)
544 #define IMR_ROK BIT(0)
546 #define IMR_TXERR BIT(11)
547 #define IMR_RXERR BIT(10)
548 #define IMR_C2HCMD BIT(9)
549 #define IMR_CPWM BIT(8)
550 #define IMR_OCPINT BIT(1)
551 #define IMR_WLANOFF BIT(0)
553 /* ----------------------------------------------------- */
555 /* ----------------------------------------------------- */
560 /* ----------------------------------------------------- */
562 /* ----------------------------------------------------- */
571 /* HT20<->40 default Tx Power Index Difference */
603 #define RTL8190_EEPROM_ID 0x8129 /* 0-1 */
604 #define EEPROM_HPON 0x02 /* LDO settings.2-5 */
605 #define EEPROM_CLK 0x06 /* Clock settings.6-7 */
608 #define EEPROM_VID 0x28 /* SE Vendor ID.A-B */
609 #define EEPROM_DID 0x2A /* SE Device ID. C-D */
610 #define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */
611 #define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */
616 #define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */
630 /*5GL channel 32-64 */
638 /* 5GM channel 100-140 */
646 /* 5GH channel 149-165 */
690 /* ----------------------------------------------------- */
692 /* ----------------------------------------------------- */
693 #define RCR_APPFCS BIT(31)
694 #define RCR_APP_MIC BIT(30)
695 #define RCR_APP_ICV BIT(29)
696 #define RCR_APP_PHYST_RXFF BIT(28)
697 #define RCR_APP_BA_SSN BIT(27)
698 #define RCR_ENMBID BIT(24)
699 #define RCR_LSIGEN BIT(23)
700 #define RCR_MFBEN BIT(22)
701 #define RCR_HTC_LOC_CTRL BIT(14)
702 #define RCR_AMF BIT(13)
703 #define RCR_ACF BIT(12)
704 #define RCR_ADF BIT(11)
705 #define RCR_AICV BIT(9)
706 #define RCR_ACRC32 BIT(8)
707 #define RCR_CBSSID_BCN BIT(7)
708 #define RCR_CBSSID_DATA BIT(6)
709 #define RCR_APWRMGT BIT(5)
710 #define RCR_ADD3 BIT(4)
711 #define RCR_AB BIT(3)
712 #define RCR_AM BIT(2)
713 #define RCR_APM BIT(1)
714 #define RCR_AAP BIT(0)
718 /* ----------------------------------------------------- */
719 /* 8192C Regsiter Bit and Content definition */
720 /* ----------------------------------------------------- */
721 /* ----------------------------------------------------- */
723 /* ----------------------------------------------------- */
726 #define SW18_FPWM BIT(3)
730 #define ISO_MD2PP BIT(0)
731 #define ISO_UA2USB BIT(1)
732 #define ISO_UD2CORE BIT(2)
733 #define ISO_PA2PCIE BIT(3)
734 #define ISO_PD2CORE BIT(4)
735 #define ISO_IP2MAC BIT(5)
736 #define ISO_DIOP BIT(6)
737 #define ISO_DIOE BIT(7)
738 #define ISO_EB2CORE BIT(8)
739 #define ISO_DIOR BIT(9)
741 #define PWC_EV25V BIT(14)
742 #define PWC_EV12V BIT(15)
746 #define FEN_BBRSTB BIT(0)
747 #define FEN_BB_GLB_RSTN BIT(1)
748 #define FEN_USBA BIT(2)
749 #define FEN_UPLL BIT(3)
750 #define FEN_USBD BIT(4)
751 #define FEN_DIO_PCIE BIT(5)
752 #define FEN_PCIEA BIT(6)
753 #define FEN_PPLL BIT(7)
754 #define FEN_PCIED BIT(8)
755 #define FEN_DIOE BIT(9)
756 #define FEN_CPUEN BIT(10)
757 #define FEN_DCORE BIT(11)
758 #define FEN_ELDR BIT(12)
759 #define FEN_DIO_RF BIT(13)
760 #define FEN_HWPDN BIT(14)
761 #define FEN_MREGEN BIT(15)
764 #define PFM_LDALL BIT(0)
765 #define PFM_ALDN BIT(1)
766 #define PFM_LDKP BIT(2)
767 #define PFM_WOWL BIT(3)
768 #define ENPDN BIT(4)
769 #define PDN_PL BIT(5)
770 #define APFM_ONMAC BIT(8)
771 #define APFM_OFF BIT(9)
772 #define APFM_RSM BIT(10)
773 #define AFSM_HSUS BIT(11)
774 #define AFSM_PCIE BIT(12)
775 #define APDM_MAC BIT(13)
776 #define APDM_HOST BIT(14)
777 #define APDM_HPDN BIT(15)
778 #define RDY_MACON BIT(16)
779 #define SUS_HOST BIT(17)
780 #define ROP_ALD BIT(20)
781 #define ROP_PWR BIT(21)
782 #define ROP_SPS BIT(22)
783 #define SOP_MRST BIT(25)
784 #define SOP_FUSE BIT(26)
785 #define SOP_ABG BIT(27)
786 #define SOP_AMB BIT(28)
787 #define SOP_RCK BIT(29)
788 #define SOP_A8M BIT(30)
789 #define XOP_BTCK BIT(31)
792 #define ANAD16V_EN BIT(0)
793 #define ANA8M BIT(1)
794 #define MACSLP BIT(4)
795 #define LOADER_CLK_EN BIT(5)
796 #define _80M_SSC_DIS BIT(7)
797 #define _80M_SSC_EN_HO BIT(8)
798 #define PHY_SSC_RSTB BIT(9)
799 #define SEC_CLK_EN BIT(10)
800 #define MAC_CLK_EN BIT(11)
801 #define SYS_CLK_EN BIT(12)
802 #define RING_CLK_EN BIT(13)
806 #define BOOT_FROM_EEPROM BIT(4)
807 #define EEPROM_EN BIT(5)
810 #define AFE_BGEN BIT(0)
811 #define AFE_MBEN BIT(1)
812 #define MAC_ID_EN BIT(7)
815 #define WLOCK_ALL BIT(0)
816 #define WLOCK_00 BIT(1)
817 #define WLOCK_04 BIT(2)
818 #define WLOCK_08 BIT(3)
819 #define WLOCK_40 BIT(4)
820 #define R_DIS_PRST_0 BIT(5)
821 #define R_DIS_PRST_1 BIT(6)
822 #define LOCK_ALL_EN BIT(7)
825 #define RF_EN BIT(0)
826 #define RF_RSTB BIT(1)
827 #define RF_SDMRSTB BIT(2)
832 #define LDA15_EN BIT(0)
833 #define LDA15_STBY BIT(1)
834 #define LDA15_OBUF BIT(2)
835 #define LDA15_REG_VOS BIT(3)
841 #define LDV12_EN BIT(0)
842 #define LDV12_SDBY BIT(1)
843 #define LPLDO_HSM BIT(2)
844 #define LPLDO_LSM_DIS BIT(3)
849 #define XTAL_EN BIT(0)
850 #define XTAL_BSEL BIT(1)
853 #define XTAL_GATE_USB BIT(8)
855 #define XTAL_GATE_AFE BIT(11)
857 #define XTAL_RF_GATE BIT(14)
859 #define XTAL_GATE_DIG BIT(17)
861 #define XTAL_BT_GATE BIT(20)
866 #define CKDLY_AFE BIT(26)
867 #define CKDLY_USB BIT(27)
868 #define CKDLY_DIG BIT(28)
869 #define CKDLY_BT BIT(29)
873 #define APLL_EN BIT(0)
874 #define APLL_320_EN BIT(1)
875 #define APLL_FREF_SEL BIT(2)
876 #define APLL_EDGE_SEL BIT(3)
877 #define APLL_WDOGB BIT(4)
878 #define APLL_LPFEN BIT(5)
888 #define APLL_320EN BIT(14)
889 #define APLL_80EN BIT(15)
890 #define APLL_1MEN BIT(24)
894 #define ALD_EN BIT(18)
895 #define EF_PD BIT(19)
896 #define EF_FLAG BIT(31)
899 #define EF_TRPT BIT(7)
900 #define LDOE25_EN BIT(31)
903 #define MCUFWDL_EN BIT(0)
904 #define MCUFWDL_RDY BIT(1)
905 #define FWDL_CHKSUM_RPT BIT(2)
906 #define MACINI_RDY BIT(3)
907 #define BBINI_RDY BIT(4)
908 #define RFINI_RDY BIT(5)
909 #define WINTINI_RDY BIT(6)
910 #define MAC1_WINTINI_RDY BIT(11)
911 #define CPRST BIT(23)
914 #define XCLK_VLD BIT(0)
915 #define ACLK_VLD BIT(1)
916 #define UCLK_VLD BIT(2)
917 #define PCLK_VLD BIT(3)
918 #define PCIRSTB BIT(4)
919 #define V15_VLD BIT(5)
920 #define TRP_B15V_EN BIT(7)
921 #define SIC_IDLE BIT(8)
922 #define BD_MAC2 BIT(9)
923 #define BD_MAC1 BIT(10)
924 #define IC_MACPHY_MODE BIT(11)
925 #define PAD_HWPD_IDN BIT(22)
926 #define TRP_VAUX_EN BIT(23)
927 #define TRP_BT_EN BIT(24)
928 #define BD_PKG_SEL BIT(25)
929 #define BD_HCI_SEL BIT(26)
930 #define TYPE_ID BIT(27)
932 #define HCI_TXDMA_EN BIT(0)
933 #define HCI_RXDMA_EN BIT(1)
934 #define TXDMA_EN BIT(2)
935 #define RXDMA_EN BIT(3)
936 #define PROTOCOL_EN BIT(4)
937 #define SCHEDULE_EN BIT(5)
938 #define MACTXEN BIT(6)
939 #define MACRXEN BIT(7)
940 #define ENSWBCN BIT(8)
941 #define ENSEC BIT(9)
943 #define HQSEL_VOQ BIT(0)
944 #define HQSEL_VIQ BIT(1)
945 #define HQSEL_BEQ BIT(2)
946 #define HQSEL_BKQ BIT(3)
947 #define HQSEL_MGTQ BIT(4)
948 #define HQSEL_HIQ BIT(5)
964 #define LD_RQPN BIT(31)
966 #define DROP_DATA_EN BIT(9)
979 /* ----------------------------------------------------- */
981 /* ----------------------------------------------------- */
983 #define EN_AMPDU_RTY_NEW BIT(7)
984 #define EN_BCNQ_DL BIT(22)
990 /* ----------------------------------------------------- */
992 /* ----------------------------------------------------- */
1000 #define DIS_EDCA_CNT_DWN BIT(11)
1003 #define EN_BCN_FUNCTION BIT(3)
1004 #define DIS_TSF_UDT BIT(4)
1007 #define ACMHW_HWEN BIT(0)
1008 #define ACMHW_BEQEN BIT(1)
1009 #define ACMHW_VIQEN BIT(2)
1010 #define ACMHW_VOQEN BIT(3)
1012 /* ----------------------------------------------------- */
1014 /* ----------------------------------------------------- */
1017 #define TSFRST BIT(0)
1018 #define DIS_GCLK BIT(1)
1019 #define PAD_SEL BIT(2)
1020 #define PWR_ST BIT(6)
1021 #define PWRBIT_OW_EN BIT(7)
1022 #define ACRC BIT(8)
1023 #define CFENDFORM BIT(9)
1024 #define ICV BIT(10)
1027 #define SCR_TXUSEDK BIT(0)
1028 #define SCR_RXUSEDK BIT(1)
1029 #define SCR_TXENCENABLE BIT(2)
1030 #define SCR_RXENCENABLE BIT(3)
1031 #define SCR_SKBYA2 BIT(4)
1032 #define SCR_NOSKMC BIT(5)
1033 #define SCR_TXBCUSEDK BIT(6)
1034 #define SCR_RXBCUSEDK BIT(7)
1048 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
1050 /* RF_Mode, TRxRN, NumOf L-STF */
1052 /* 3. RF register 0x00-2E */
1053 /* 4. Bit Mask for BB/RF register */
1365 /* Bit Mask */