Lines Matching +full:rx +full:- +full:equalizer
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2018-2024 Intel Corporation
6 #include "iwl-trans.h"
7 #include "iwl-fh.h"
8 #include "iwl-context-info-gen3.h"
10 #include "iwl-prph.h"
42 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_ctxt_info_dbg_enable()
46 if (fw_mon->size) { in iwl_pcie_ctxt_info_dbg_enable()
52 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); in iwl_pcie_ctxt_info_dbg_enable()
53 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); in iwl_pcie_ctxt_info_dbg_enable()
59 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; in iwl_pcie_ctxt_info_dbg_enable()
61 switch (le32_to_cpu(fw_mon_cfg->buf_location)) { in iwl_pcie_ctxt_info_dbg_enable()
75 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { in iwl_pcie_ctxt_info_dbg_enable()
77 &trans->dbg.fw_mon_ini[alloc_id].frags[0]; in iwl_pcie_ctxt_info_dbg_enable()
79 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); in iwl_pcie_ctxt_info_dbg_enable()
80 dbg_cfg->hwm_size = cpu_to_le32(frag->size); in iwl_pcie_ctxt_info_dbg_enable()
81 dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset); in iwl_pcie_ctxt_info_dbg_enable()
84 dbg_cfg->debug_token_config); in iwl_pcie_ctxt_info_dbg_enable()
88 trans->dbg.fw_mon_ini[alloc_id].num_frags); in iwl_pcie_ctxt_info_dbg_enable()
93 le32_to_cpu(fw_mon_cfg->buf_location)); in iwl_pcie_ctxt_info_dbg_enable()
111 trans->cfg->min_txq_size); in iwl_pcie_ctxt_info_gen3_init()
113 switch (trans_pcie->rx_buf_size) { in iwl_pcie_ctxt_info_gen3_init()
115 return -EINVAL; in iwl_pcie_ctxt_info_gen3_init()
134 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), in iwl_pcie_ctxt_info_gen3_init()
135 &trans_pcie->prph_scratch_dma_addr, in iwl_pcie_ctxt_info_gen3_init()
138 return -ENOMEM; in iwl_pcie_ctxt_info_gen3_init()
140 prph_sc_ctrl = &prph_scratch->ctrl_cfg; in iwl_pcie_ctxt_info_gen3_init()
142 prph_sc_ctrl->version.version = 0; in iwl_pcie_ctxt_info_gen3_init()
143 prph_sc_ctrl->version.mac_id = in iwl_pcie_ctxt_info_gen3_init()
144 cpu_to_le16((u16)trans->hw_rev); in iwl_pcie_ctxt_info_gen3_init()
145 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); in iwl_pcie_ctxt_info_gen3_init()
150 if (trans->trans_cfg->imr_enabled) in iwl_pcie_ctxt_info_gen3_init()
153 if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL && in iwl_pcie_ctxt_info_gen3_init()
161 /* initialize RX default queue */ in iwl_pcie_ctxt_info_gen3_init()
162 prph_sc_ctrl->rbd_cfg.free_rbd_addr = in iwl_pcie_ctxt_info_gen3_init()
163 cpu_to_le64(trans_pcie->rxq->bd_dma); in iwl_pcie_ctxt_info_gen3_init()
165 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, in iwl_pcie_ctxt_info_gen3_init()
167 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); in iwl_pcie_ctxt_info_gen3_init()
169 /* initialize the Step equalizer data */ in iwl_pcie_ctxt_info_gen3_init()
170 prph_sc_ctrl->step_cfg.mbx_addr_0 = cpu_to_le32(trans->mbx_addr_0_step); in iwl_pcie_ctxt_info_gen3_init()
171 prph_sc_ctrl->step_cfg.mbx_addr_1 = cpu_to_le32(trans->mbx_addr_1_step); in iwl_pcie_ctxt_info_gen3_init()
174 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); in iwl_pcie_ctxt_info_gen3_init()
184 * dummy TR/CR tail pointers - which shouldn't be necessary as we don't in iwl_pcie_ctxt_info_gen3_init()
189 prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE, in iwl_pcie_ctxt_info_gen3_init()
190 &trans_pcie->prph_info_dma_addr, in iwl_pcie_ctxt_info_gen3_init()
193 ret = -ENOMEM; in iwl_pcie_ctxt_info_gen3_init()
198 ctxt_info_gen3 = dma_alloc_coherent(trans->dev, in iwl_pcie_ctxt_info_gen3_init()
200 &trans_pcie->ctxt_info_dma_addr, in iwl_pcie_ctxt_info_gen3_init()
203 ret = -ENOMEM; in iwl_pcie_ctxt_info_gen3_init()
207 ctxt_info_gen3->prph_info_base_addr = in iwl_pcie_ctxt_info_gen3_init()
208 cpu_to_le64(trans_pcie->prph_info_dma_addr); in iwl_pcie_ctxt_info_gen3_init()
209 ctxt_info_gen3->prph_scratch_base_addr = in iwl_pcie_ctxt_info_gen3_init()
210 cpu_to_le64(trans_pcie->prph_scratch_dma_addr); in iwl_pcie_ctxt_info_gen3_init()
211 ctxt_info_gen3->prph_scratch_size = in iwl_pcie_ctxt_info_gen3_init()
213 ctxt_info_gen3->cr_head_idx_arr_base_addr = in iwl_pcie_ctxt_info_gen3_init()
214 cpu_to_le64(trans_pcie->rxq->rb_stts_dma); in iwl_pcie_ctxt_info_gen3_init()
215 ctxt_info_gen3->tr_tail_idx_arr_base_addr = in iwl_pcie_ctxt_info_gen3_init()
216 cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2); in iwl_pcie_ctxt_info_gen3_init()
217 ctxt_info_gen3->cr_tail_idx_arr_base_addr = in iwl_pcie_ctxt_info_gen3_init()
218 cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4); in iwl_pcie_ctxt_info_gen3_init()
219 ctxt_info_gen3->mtr_base_addr = in iwl_pcie_ctxt_info_gen3_init()
220 cpu_to_le64(trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id]->dma_addr); in iwl_pcie_ctxt_info_gen3_init()
221 ctxt_info_gen3->mcr_base_addr = in iwl_pcie_ctxt_info_gen3_init()
222 cpu_to_le64(trans_pcie->rxq->used_bd_dma); in iwl_pcie_ctxt_info_gen3_init()
223 ctxt_info_gen3->mtr_size = in iwl_pcie_ctxt_info_gen3_init()
225 ctxt_info_gen3->mcr_size = in iwl_pcie_ctxt_info_gen3_init()
226 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); in iwl_pcie_ctxt_info_gen3_init()
228 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; in iwl_pcie_ctxt_info_gen3_init()
229 trans_pcie->prph_info = prph_info; in iwl_pcie_ctxt_info_gen3_init()
230 trans_pcie->prph_scratch = prph_scratch; in iwl_pcie_ctxt_info_gen3_init()
233 trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len, in iwl_pcie_ctxt_info_gen3_init()
234 &trans_pcie->iml_dma_addr, in iwl_pcie_ctxt_info_gen3_init()
236 if (!trans_pcie->iml) { in iwl_pcie_ctxt_info_gen3_init()
237 ret = -ENOMEM; in iwl_pcie_ctxt_info_gen3_init()
241 memcpy(trans_pcie->iml, trans->iml, trans->iml_len); in iwl_pcie_ctxt_info_gen3_init()
247 trans_pcie->ctxt_info_dma_addr); in iwl_pcie_ctxt_info_gen3_init()
249 trans_pcie->iml_dma_addr); in iwl_pcie_ctxt_info_gen3_init()
250 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); in iwl_pcie_ctxt_info_gen3_init()
258 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), in iwl_pcie_ctxt_info_gen3_init()
259 trans_pcie->ctxt_info_gen3, in iwl_pcie_ctxt_info_gen3_init()
260 trans_pcie->ctxt_info_dma_addr); in iwl_pcie_ctxt_info_gen3_init()
261 trans_pcie->ctxt_info_gen3 = NULL; in iwl_pcie_ctxt_info_gen3_init()
263 dma_free_coherent(trans->dev, PAGE_SIZE, prph_info, in iwl_pcie_ctxt_info_gen3_init()
264 trans_pcie->prph_info_dma_addr); in iwl_pcie_ctxt_info_gen3_init()
267 dma_free_coherent(trans->dev, in iwl_pcie_ctxt_info_gen3_init()
270 trans_pcie->prph_scratch_dma_addr); in iwl_pcie_ctxt_info_gen3_init()
279 if (trans_pcie->iml) { in iwl_pcie_ctxt_info_gen3_free()
280 dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml, in iwl_pcie_ctxt_info_gen3_free()
281 trans_pcie->iml_dma_addr); in iwl_pcie_ctxt_info_gen3_free()
282 trans_pcie->iml_dma_addr = 0; in iwl_pcie_ctxt_info_gen3_free()
283 trans_pcie->iml = NULL; in iwl_pcie_ctxt_info_gen3_free()
291 if (!trans_pcie->ctxt_info_gen3) in iwl_pcie_ctxt_info_gen3_free()
295 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), in iwl_pcie_ctxt_info_gen3_free()
296 trans_pcie->ctxt_info_gen3, in iwl_pcie_ctxt_info_gen3_free()
297 trans_pcie->ctxt_info_dma_addr); in iwl_pcie_ctxt_info_gen3_free()
298 trans_pcie->ctxt_info_dma_addr = 0; in iwl_pcie_ctxt_info_gen3_free()
299 trans_pcie->ctxt_info_gen3 = NULL; in iwl_pcie_ctxt_info_gen3_free()
301 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), in iwl_pcie_ctxt_info_gen3_free()
302 trans_pcie->prph_scratch, in iwl_pcie_ctxt_info_gen3_free()
303 trans_pcie->prph_scratch_dma_addr); in iwl_pcie_ctxt_info_gen3_free()
304 trans_pcie->prph_scratch_dma_addr = 0; in iwl_pcie_ctxt_info_gen3_free()
305 trans_pcie->prph_scratch = NULL; in iwl_pcie_ctxt_info_gen3_free()
308 dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info, in iwl_pcie_ctxt_info_gen3_free()
309 trans_pcie->prph_info_dma_addr); in iwl_pcie_ctxt_info_gen3_free()
310 trans_pcie->prph_info_dma_addr = 0; in iwl_pcie_ctxt_info_gen3_free()
311 trans_pcie->prph_info = NULL; in iwl_pcie_ctxt_info_gen3_free()
320 if (pnvm_data->n_chunks != UNFRAGMENTED_PNVM_PAYLOADS_NUMBER) { in iwl_pcie_load_payloads_continuously()
322 pnvm_data->n_chunks); in iwl_pcie_load_payloads_continuously()
323 return -EINVAL; in iwl_pcie_load_payloads_continuously()
326 len0 = pnvm_data->chunks[0].len; in iwl_pcie_load_payloads_continuously()
327 len1 = pnvm_data->chunks[1].len; in iwl_pcie_load_payloads_continuously()
328 if (len1 > 0xFFFFFFFF - len0) { in iwl_pcie_load_payloads_continuously()
330 return -EINVAL; in iwl_pcie_load_payloads_continuously()
334 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, in iwl_pcie_load_payloads_continuously()
335 &dram->physical); in iwl_pcie_load_payloads_continuously()
336 if (!dram->block) { in iwl_pcie_load_payloads_continuously()
338 return -ENOMEM; in iwl_pcie_load_payloads_continuously()
341 dram->size = len; in iwl_pcie_load_payloads_continuously()
342 memcpy(dram->block, pnvm_data->chunks[0].data, len0); in iwl_pcie_load_payloads_continuously()
343 memcpy((u8 *)dram->block + len0, pnvm_data->chunks[1].data, len1); in iwl_pcie_load_payloads_continuously()
353 struct iwl_dram_data *cur_payload_dram = &dram_regions->drams[0]; in iwl_pcie_load_payloads_segments()
354 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; in iwl_pcie_load_payloads_segments()
362 desc_dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent in iwl_pcie_load_payloads_segments()
365 &desc_dram->physical); in iwl_pcie_load_payloads_segments()
366 if (!desc_dram->block) { in iwl_pcie_load_payloads_segments()
368 return -ENOMEM; in iwl_pcie_load_payloads_segments()
370 desc_dram->size = len; in iwl_pcie_load_payloads_segments()
371 memset(desc_dram->block, 0, len); in iwl_pcie_load_payloads_segments()
374 dram_regions->n_regions = 0; in iwl_pcie_load_payloads_segments()
375 for (i = 0; i < pnvm_data->n_chunks; i++) { in iwl_pcie_load_payloads_segments()
376 len = pnvm_data->chunks[i].len; in iwl_pcie_load_payloads_segments()
377 data = pnvm_data->chunks[i].data; in iwl_pcie_load_payloads_segments()
384 trans->dev); in iwl_pcie_load_payloads_segments()
385 return -ENOMEM; in iwl_pcie_load_payloads_segments()
388 dram_regions->n_regions++; in iwl_pcie_load_payloads_segments()
393 addresses = desc_dram->block; in iwl_pcie_load_payloads_segments()
394 for (i = 0; i < pnvm_data->n_chunks; i++) { in iwl_pcie_load_payloads_segments()
395 addresses->mem_descs[i] = in iwl_pcie_load_payloads_segments()
396 cpu_to_le64(dram_regions->drams[i].physical); in iwl_pcie_load_payloads_segments()
409 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
410 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data; in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
414 if (trans->pnvm_loaded) in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
417 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
418 return -EBUSY; in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
420 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
423 if (!pnvm_payloads->n_chunks) { in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
425 return -EINVAL; in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
434 trans->pnvm_loaded = true; in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
440 &dram_regions->drams[0]); in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
442 dram_regions->n_regions = 1; in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
443 trans->pnvm_loaded = true; in iwl_trans_pcie_ctx_info_gen3_load_pnvm()
456 for (i = 0; i < dram_regions->n_regions; i++) in iwl_dram_regions_size()
457 total_size += dram_regions->drams[i].size; in iwl_dram_regions_size()
466 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_pcie_set_pnvm_segments()
467 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data; in iwl_pcie_set_pnvm_segments()
469 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = in iwl_pcie_set_pnvm_segments()
470 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical); in iwl_pcie_set_pnvm_segments()
471 prph_sc_ctrl->pnvm_cfg.pnvm_size = in iwl_pcie_set_pnvm_segments()
479 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_pcie_set_continuous_pnvm()
481 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = in iwl_pcie_set_continuous_pnvm()
482 cpu_to_le64(trans_pcie->pnvm_data.drams[0].physical); in iwl_pcie_set_continuous_pnvm()
483 prph_sc_ctrl->pnvm_cfg.pnvm_size = in iwl_pcie_set_continuous_pnvm()
484 cpu_to_le32(trans_pcie->pnvm_data.drams[0].size); in iwl_pcie_set_continuous_pnvm()
490 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_ctx_info_gen3_set_pnvm()
505 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
506 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data; in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
510 if (trans->reduce_power_loaded) in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
513 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
516 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size)) in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
517 return -EBUSY; in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
519 if (!payloads->n_chunks) { in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
521 return -EINVAL; in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
530 trans->reduce_power_loaded = true; in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
536 &dram_regions->drams[0]); in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
538 dram_regions->n_regions = 1; in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
539 trans->reduce_power_loaded = true; in iwl_trans_pcie_ctx_info_gen3_load_reduce_power()
550 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_pcie_set_reduce_power_segments()
551 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data; in iwl_pcie_set_reduce_power_segments()
553 prph_sc_ctrl->reduce_power_cfg.base_addr = in iwl_pcie_set_reduce_power_segments()
554 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical); in iwl_pcie_set_reduce_power_segments()
555 prph_sc_ctrl->reduce_power_cfg.size = in iwl_pcie_set_reduce_power_segments()
563 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_pcie_set_continuous_reduce_power()
565 prph_sc_ctrl->reduce_power_cfg.base_addr = in iwl_pcie_set_continuous_reduce_power()
566 cpu_to_le64(trans_pcie->reduced_tables_data.drams[0].physical); in iwl_pcie_set_continuous_reduce_power()
567 prph_sc_ctrl->reduce_power_cfg.size = in iwl_pcie_set_continuous_reduce_power()
568 cpu_to_le32(trans_pcie->reduced_tables_data.drams[0].size); in iwl_pcie_set_continuous_reduce_power()
575 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_ctx_info_gen3_set_reduce_power()