Lines Matching +full:6 +full:kg
39 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
49 .macAddr = {0, 2, 3, 4, 5, 6},
90 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
182 /* 6-24,36,48,54 */
243 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
244 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
305 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
426 /* 6-24,36,48,54 */
439 * 4,5,6,7,12,13,14,15,20,21,22,23
453 * 4,5,6,7,12,13,14,15,20,21,22,23
476 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
486 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
497 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
508 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
519 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
530 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
535 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
536 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
537 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
538 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
539 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
540 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
541 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
542 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
552 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
563 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
627 .templateVersion = 6,
653 .eepromWriteEnableGpio = 6,
668 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
760 /* 6-24,36,48,54 */
821 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
822 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
883 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1004 /* 6-24,36,48,54 */
1017 * 4,5,6,7,12,13,14,15,20,21,22,23
1031 * 4,5,6,7,12,13,14,15,20,21,22,23
1054 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1064 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1075 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1086 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1097 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1108 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1113 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1114 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1115 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1116 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1117 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1118 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1119 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1120 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1130 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1141 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1232 .eepromWriteEnableGpio = 6,
1247 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1339 /* 6-24,36,48,54 */
1400 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1401 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1462 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1583 /* 6-24,36,48,54 */
1596 * 4,5,6,7,12,13,14,15,20,21,22,23
1610 * 4,5,6,7,12,13,14,15,20,21,22,23
1633 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1643 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1654 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1665 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1676 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1687 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1692 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1693 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1694 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1695 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1696 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1697 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1698 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1699 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1709 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1720 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1811 .eepromWriteEnableGpio = 6,
1826 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1918 /* 6-24,36,48,54 */
1979 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1980 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2041 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2162 /* 6-24,36,48,54 */
2175 * 4,5,6,7,12,13,14,15,20,21,22,23
2189 * 4,5,6,7,12,13,14,15,20,21,22,23
2212 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2222 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2233 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2244 /* Data[3].ctledges[6].bchannel */ 0xFF,
2255 /* Data[4].ctledges[6].bchannel */ 0xFF,
2266 /* Data[5].ctledges[6].bchannel */ 0xFF,
2271 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2272 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2273 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2274 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2275 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2276 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2277 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2278 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2288 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2299 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2389 .eepromWriteEnableGpio = 6,
2404 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2496 /* 6-24,36,48,54 */
2557 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2558 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2619 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2740 /* 6-24,36,48,54 */
2753 * 4,5,6,7,12,13,14,15,20,21,22,23
2767 * 4,5,6,7,12,13,14,15,20,21,22,23
2790 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2800 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2811 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2822 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2833 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2844 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2849 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2850 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2851 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2852 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2853 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2854 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2855 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2856 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2866 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2877 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
3735 regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; in ar9003_hw_ant_ctrl_apply()
3814 reg |= 0x5 << 6; in ar9003_hw_drive_strength_apply()
3972 (6 << 17) | (1 << 20) | in ar9003_hw_internal_regulator_apply()
3977 (6 << 17) | (1 << 20) | in ar9003_hw_internal_regulator_apply()
3983 (6 << 17) | (1 << 20) | in ar9003_hw_internal_regulator_apply()
4187 u32 data = 0, ko, kg; in ar9003_hw_thermo_cal_apply() local
4194 kg = (data >> 8) & 0xff; in ar9003_hw_thermo_cal_apply()
4195 if (ko || kg) { in ar9003_hw_thermo_cal_apply()
4200 kg + 256); in ar9003_hw_thermo_cal_apply()
4483 /* 6 (LSB), 9, 12, 18 (MSB) */ in ar9003_hw_tx_power_regwrite()
4534 /* 6 (LSB), 7, 12, 13 (MSB) */ in ar9003_hw_tx_power_regwrite()
4565 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6), in ar9003_hw_tx_power_regwrite()
4572 /* 6 (LSB), 7, 12, 13 (MSB) */ in ar9003_hw_tx_power_regwrite()
4856 t1[2] = eep->base_ext1.tempslopextension[6]; in ar9003_hw_power_control_override()