Lines Matching +full:rmii +full:- +full:refclk +full:- +full:in
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2021-2025 NXP
4 * Author: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
20 #include "nxp-c45-tja11xx.h"
197 #define NXP_C45_SKB_CB(skb) ((struct nxp_c45_skb_cb *)(skb)->cb)
302 return phydev->drv->driver_data; in nxp_c45_get_data()
310 return phy_data->regmap; in nxp_c45_get_regmap()
319 if (reg_field->size == 0) { in nxp_c45_read_reg_field()
321 return -EINVAL; in nxp_c45_read_reg_field()
324 ret = phy_read_mmd(phydev, reg_field->devad, reg_field->reg); in nxp_c45_read_reg_field()
328 mask = reg_field->size == 1 ? BIT(reg_field->offset) : in nxp_c45_read_reg_field()
329 GENMASK(reg_field->offset + reg_field->size - 1, in nxp_c45_read_reg_field()
330 reg_field->offset); in nxp_c45_read_reg_field()
332 ret >>= reg_field->offset; in nxp_c45_read_reg_field()
344 if (reg_field->size == 0) { in nxp_c45_write_reg_field()
346 return -EINVAL; in nxp_c45_write_reg_field()
349 mask = reg_field->size == 1 ? BIT(reg_field->offset) : in nxp_c45_write_reg_field()
350 GENMASK(reg_field->offset + reg_field->size - 1, in nxp_c45_write_reg_field()
351 reg_field->offset); in nxp_c45_write_reg_field()
352 set = val << reg_field->offset; in nxp_c45_write_reg_field()
354 return phy_modify_mmd_changed(phydev, reg_field->devad, in nxp_c45_write_reg_field()
355 reg_field->reg, mask, set); in nxp_c45_write_reg_field()
361 if (reg_field->size != 1) { in nxp_c45_set_reg_field()
363 return -EINVAL; in nxp_c45_set_reg_field()
372 if (reg_field->size != 1) { in nxp_c45_clear_reg_field()
374 return -EINVAL; in nxp_c45_clear_reg_field()
382 return phydev->irq <= 0; in nxp_c45_poll_txts()
390 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in _nxp_c45_ptp_gettimex64()
392 nxp_c45_set_reg_field(priv->phydev, ®map->ltc_read); in _nxp_c45_ptp_gettimex64()
393 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
394 regmap->vend1_ltc_rd_nsec_0); in _nxp_c45_ptp_gettimex64()
395 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
396 regmap->vend1_ltc_rd_nsec_1) << 16; in _nxp_c45_ptp_gettimex64()
397 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
398 regmap->vend1_ltc_rd_sec_0); in _nxp_c45_ptp_gettimex64()
399 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
400 regmap->vend1_ltc_rd_sec_1) << 16; in _nxp_c45_ptp_gettimex64()
411 mutex_lock(&priv->ptp_lock); in nxp_c45_ptp_gettimex64()
413 mutex_unlock(&priv->ptp_lock); in nxp_c45_ptp_gettimex64()
422 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in _nxp_c45_ptp_settime64()
424 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0, in _nxp_c45_ptp_settime64()
425 ts->tv_nsec); in _nxp_c45_ptp_settime64()
426 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1, in _nxp_c45_ptp_settime64()
427 ts->tv_nsec >> 16); in _nxp_c45_ptp_settime64()
428 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0, in _nxp_c45_ptp_settime64()
429 ts->tv_sec); in _nxp_c45_ptp_settime64()
430 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1, in _nxp_c45_ptp_settime64()
431 ts->tv_sec >> 16); in _nxp_c45_ptp_settime64()
432 nxp_c45_set_reg_field(priv->phydev, ®map->ltc_write); in _nxp_c45_ptp_settime64()
442 mutex_lock(&priv->ptp_lock); in nxp_c45_ptp_settime64()
444 mutex_unlock(&priv->ptp_lock); in nxp_c45_ptp_settime64()
452 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev); in nxp_c45_ptp_adjfine()
453 const struct nxp_c45_regmap *regmap = data->regmap; in nxp_c45_ptp_adjfine()
458 mutex_lock(&priv->ptp_lock); in nxp_c45_ptp_adjfine()
462 subns_inc_val = PPM_TO_SUBNS_INC(ppb, data->ptp_clk_period); in nxp_c45_ptp_adjfine()
464 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
465 regmap->vend1_rate_adj_subns_0, in nxp_c45_ptp_adjfine()
472 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
473 regmap->vend1_rate_adj_subns_1, in nxp_c45_ptp_adjfine()
475 mutex_unlock(&priv->ptp_lock); in nxp_c45_ptp_adjfine()
485 mutex_lock(&priv->ptp_lock); in nxp_c45_ptp_adjtime()
490 mutex_unlock(&priv->ptp_lock); in nxp_c45_ptp_adjtime()
498 ts->tv_nsec = hwts->nsec; in nxp_c45_reconstruct_ts()
499 if ((ts->tv_sec & TS_SEC_MASK) < (hwts->sec & TS_SEC_MASK)) in nxp_c45_reconstruct_ts()
500 ts->tv_sec -= TS_SEC_MASK + 1; in nxp_c45_reconstruct_ts()
501 ts->tv_sec &= ~TS_SEC_MASK; in nxp_c45_reconstruct_ts()
502 ts->tv_sec |= hwts->sec & TS_SEC_MASK; in nxp_c45_reconstruct_ts()
509 return ntohs(header->sequence_id) == hwts->sequence_id && in nxp_c45_match_ts()
510 ptp_get_msgtype(header, type) == hwts->msg_type && in nxp_c45_match_ts()
511 header->domain_number == hwts->domain_number; in nxp_c45_match_ts()
517 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in nxp_c45_get_extts()
519 extts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
520 regmap->vend1_ext_trg_data_0); in nxp_c45_get_extts()
521 extts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
522 regmap->vend1_ext_trg_data_1) << 16; in nxp_c45_get_extts()
523 extts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
524 regmap->vend1_ext_trg_data_2); in nxp_c45_get_extts()
525 extts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
526 regmap->vend1_ext_trg_data_3) << 16; in nxp_c45_get_extts()
527 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
528 regmap->vend1_ext_trg_ctrl, RING_DONE); in nxp_c45_get_extts()
548 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in tja1120_get_extts()
549 struct phy_device *phydev = priv->phydev; in tja1120_get_extts()
555 regmap->vend1_ext_trg_ctrl); in tja1120_get_extts()
567 regmap->vend1_ext_trg_ctrl, RING_DONE); in tja1120_get_extts()
581 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in nxp_c45_read_egress_ts()
582 struct phy_device *phydev = priv->phydev; in nxp_c45_read_egress_ts()
584 hwts->domain_number = in nxp_c45_read_egress_ts()
585 nxp_c45_read_reg_field(phydev, ®map->domain_number); in nxp_c45_read_egress_ts()
586 hwts->msg_type = in nxp_c45_read_egress_ts()
587 nxp_c45_read_reg_field(phydev, ®map->msg_type); in nxp_c45_read_egress_ts()
588 hwts->sequence_id = in nxp_c45_read_egress_ts()
589 nxp_c45_read_reg_field(phydev, ®map->sequence_id); in nxp_c45_read_egress_ts()
590 hwts->nsec = in nxp_c45_read_egress_ts()
591 nxp_c45_read_reg_field(phydev, ®map->nsec_15_0); in nxp_c45_read_egress_ts()
592 hwts->nsec |= in nxp_c45_read_egress_ts()
593 nxp_c45_read_reg_field(phydev, ®map->nsec_29_16) << 16; in nxp_c45_read_egress_ts()
594 hwts->sec = nxp_c45_read_reg_field(phydev, ®map->sec_1_0); in nxp_c45_read_egress_ts()
595 hwts->sec |= nxp_c45_read_reg_field(phydev, ®map->sec_4_2) << 2; in nxp_c45_read_egress_ts()
604 mutex_lock(&priv->ptp_lock); in nxp_c45_get_hwtxts()
605 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL, in nxp_c45_get_hwtxts()
607 reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0); in nxp_c45_get_hwtxts()
614 mutex_unlock(&priv->ptp_lock); in nxp_c45_get_hwtxts()
632 struct phy_device *phydev = priv->phydev; in tja1120_get_hwtxts()
637 mutex_lock(&priv->ptp_lock); in tja1120_get_hwtxts()
658 mutex_unlock(&priv->ptp_lock); in tja1120_get_hwtxts()
672 spin_lock_irqsave(&priv->tx_queue.lock, flags); in nxp_c45_process_txts()
673 skb_queue_walk_safe(&priv->tx_queue, skb, tmp) { in nxp_c45_process_txts()
674 ts_match = nxp_c45_match_ts(NXP_C45_SKB_CB(skb)->header, txts, in nxp_c45_process_txts()
675 NXP_C45_SKB_CB(skb)->type); in nxp_c45_process_txts()
679 __skb_unlink(skb, &priv->tx_queue); in nxp_c45_process_txts()
682 spin_unlock_irqrestore(&priv->tx_queue.lock, flags); in nxp_c45_process_txts()
685 nxp_c45_ptp_gettimex64(&priv->caps, &ts, NULL); in nxp_c45_process_txts()
692 phydev_warn(priv->phydev, in nxp_c45_process_txts()
700 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev); in nxp_c45_do_aux_work()
701 bool poll_txts = nxp_c45_poll_txts(priv->phydev); in nxp_c45_do_aux_work()
711 while (!skb_queue_empty_lockless(&priv->tx_queue) && poll_txts) { in nxp_c45_do_aux_work()
712 ts_valid = data->get_egressts(priv, &hwts); in nxp_c45_do_aux_work()
714 /* Still more skbs in the queue */ in nxp_c45_do_aux_work()
722 while ((skb = skb_dequeue(&priv->rx_queue)) != NULL) { in nxp_c45_do_aux_work()
723 nxp_c45_ptp_gettimex64(&priv->caps, &ts, NULL); in nxp_c45_do_aux_work()
724 ts_raw = __be32_to_cpu(NXP_C45_SKB_CB(skb)->header->reserved2); in nxp_c45_do_aux_work()
729 shhwtstamps_rx->hwtstamp = ns_to_ktime(timespec64_to_ns(&ts)); in nxp_c45_do_aux_work()
730 NXP_C45_SKB_CB(skb)->header->reserved2 = 0; in nxp_c45_do_aux_work()
734 if (priv->extts) { in nxp_c45_do_aux_work()
735 ts_valid = data->get_extts(priv, &ts); in nxp_c45_do_aux_work()
736 if (ts_valid && timespec64_compare(&ts, &priv->extts_ts) != 0) { in nxp_c45_do_aux_work()
737 priv->extts_ts = ts; in nxp_c45_do_aux_work()
738 event.index = priv->extts_index; in nxp_c45_do_aux_work()
741 ptp_clock_event(priv->ptp_clock, &event); in nxp_c45_do_aux_work()
746 return reschedule ? 1 : -1; in nxp_c45_do_aux_work()
752 struct phy_device *phydev = priv->phydev; in nxp_c45_gpio_config()
761 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in nxp_c45_perout_enable()
762 struct phy_device *phydev = priv->phydev; in nxp_c45_perout_enable()
765 pin = ptp_find_pin(priv->ptp_clock, PTP_PF_PEROUT, perout->index); in nxp_c45_perout_enable()
770 nxp_c45_clear_reg_field(priv->phydev, in nxp_c45_perout_enable()
771 ®map->pps_enable); in nxp_c45_perout_enable()
772 nxp_c45_clear_reg_field(priv->phydev, in nxp_c45_perout_enable()
773 ®map->pps_polarity); in nxp_c45_perout_enable()
784 if (perout->period.sec != 1 || perout->period.nsec != 0) { in nxp_c45_perout_enable()
786 return -EINVAL; in nxp_c45_perout_enable()
789 if (!(perout->flags & PTP_PEROUT_PHASE)) { in nxp_c45_perout_enable()
790 if (perout->start.sec != 0 || perout->start.nsec != 0) { in nxp_c45_perout_enable()
792 return -EINVAL; in nxp_c45_perout_enable()
795 if (perout->phase.nsec != 0 && in nxp_c45_perout_enable()
796 perout->phase.nsec != (NSEC_PER_SEC >> 1)) { in nxp_c45_perout_enable()
798 return -EINVAL; in nxp_c45_perout_enable()
801 if (perout->phase.nsec == 0) in nxp_c45_perout_enable()
802 nxp_c45_clear_reg_field(priv->phydev, in nxp_c45_perout_enable()
803 ®map->pps_polarity); in nxp_c45_perout_enable()
805 nxp_c45_set_reg_field(priv->phydev, in nxp_c45_perout_enable()
806 ®map->pps_polarity); in nxp_c45_perout_enable()
811 nxp_c45_set_reg_field(priv->phydev, ®map->pps_enable); in nxp_c45_perout_enable()
819 if (extts->flags & PTP_RISING_EDGE) in nxp_c45_set_rising_or_falling()
823 if (extts->flags & PTP_FALLING_EDGE) in nxp_c45_set_rising_or_falling()
831 /* PTP_EXTTS_REQUEST may have only the PTP_ENABLE_FEATURE flag set. In in nxp_c45_set_rising_and_falling()
834 if (extts->flags & PTP_RISING_EDGE || in nxp_c45_set_rising_and_falling()
835 extts->flags == PTP_ENABLE_FEATURE) in nxp_c45_set_rising_and_falling()
844 if (extts->flags & PTP_FALLING_EDGE) in nxp_c45_set_rising_and_falling()
857 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev); in nxp_c45_extts_enable()
861 if ((extts->flags & PTP_RISING_EDGE) && in nxp_c45_extts_enable()
862 (extts->flags & PTP_FALLING_EDGE) && in nxp_c45_extts_enable()
863 !data->ext_ts_both_edges) in nxp_c45_extts_enable()
864 return -EOPNOTSUPP; in nxp_c45_extts_enable()
866 pin = ptp_find_pin(priv->ptp_clock, PTP_PF_EXTTS, extts->index); in nxp_c45_extts_enable()
872 priv->extts = false; in nxp_c45_extts_enable()
877 if (data->ext_ts_both_edges) in nxp_c45_extts_enable()
878 nxp_c45_set_rising_and_falling(priv->phydev, extts); in nxp_c45_extts_enable()
880 nxp_c45_set_rising_or_falling(priv->phydev, extts); in nxp_c45_extts_enable()
883 priv->extts = true; in nxp_c45_extts_enable()
884 priv->extts_index = extts->index; in nxp_c45_extts_enable()
885 ptp_schedule_worker(priv->ptp_clock, 0); in nxp_c45_extts_enable()
895 switch (req->type) { in nxp_c45_ptp_enable()
897 return nxp_c45_extts_enable(priv, &req->extts, on); in nxp_c45_ptp_enable()
899 return nxp_c45_perout_enable(priv, &req->perout, on); in nxp_c45_ptp_enable()
901 return -EOPNOTSUPP; in nxp_c45_ptp_enable()
924 return -EINVAL; in nxp_c45_ptp_verify_pin()
932 return -EOPNOTSUPP; in nxp_c45_ptp_verify_pin()
940 priv->caps = (struct ptp_clock_info) { in nxp_c45_init_ptp_clock()
961 priv->ptp_clock = ptp_clock_register(&priv->caps, in nxp_c45_init_ptp_clock()
962 &priv->phydev->mdio.dev); in nxp_c45_init_ptp_clock()
964 if (IS_ERR(priv->ptp_clock)) in nxp_c45_init_ptp_clock()
965 return PTR_ERR(priv->ptp_clock); in nxp_c45_init_ptp_clock()
967 if (!priv->ptp_clock) in nxp_c45_init_ptp_clock()
968 return -ENOMEM; in nxp_c45_init_ptp_clock()
979 switch (priv->hwts_tx) { in nxp_c45_txtstamp()
981 NXP_C45_SKB_CB(skb)->type = type; in nxp_c45_txtstamp()
982 NXP_C45_SKB_CB(skb)->header = ptp_parse_header(skb, type); in nxp_c45_txtstamp()
983 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in nxp_c45_txtstamp()
984 skb_queue_tail(&priv->tx_queue, skb); in nxp_c45_txtstamp()
985 if (nxp_c45_poll_txts(priv->phydev)) in nxp_c45_txtstamp()
986 ptp_schedule_worker(priv->ptp_clock, 0); in nxp_c45_txtstamp()
1005 if (!priv->hwts_rx) in nxp_c45_rxtstamp()
1008 NXP_C45_SKB_CB(skb)->header = header; in nxp_c45_rxtstamp()
1009 skb_queue_tail(&priv->rx_queue, skb); in nxp_c45_rxtstamp()
1010 ptp_schedule_worker(priv->ptp_clock, 0); in nxp_c45_rxtstamp()
1021 struct phy_device *phydev = priv->phydev; in nxp_c45_hwtstamp()
1024 if (cfg->tx_type < 0 || cfg->tx_type > HWTSTAMP_TX_ON) in nxp_c45_hwtstamp()
1025 return -ERANGE; in nxp_c45_hwtstamp()
1028 priv->hwts_tx = cfg->tx_type; in nxp_c45_hwtstamp()
1030 switch (cfg->rx_filter) { in nxp_c45_hwtstamp()
1032 priv->hwts_rx = 0; in nxp_c45_hwtstamp()
1037 priv->hwts_rx = 1; in nxp_c45_hwtstamp()
1038 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; in nxp_c45_hwtstamp()
1041 return -ERANGE; in nxp_c45_hwtstamp()
1044 if (priv->hwts_rx || priv->hwts_tx) { in nxp_c45_hwtstamp()
1046 data->regmap->vend1_event_msg_filt, in nxp_c45_hwtstamp()
1048 data->ptp_enable(phydev, true); in nxp_c45_hwtstamp()
1051 data->regmap->vend1_event_msg_filt, in nxp_c45_hwtstamp()
1053 data->ptp_enable(phydev, false); in nxp_c45_hwtstamp()
1056 if (nxp_c45_poll_txts(priv->phydev)) in nxp_c45_hwtstamp()
1059 if (priv->hwts_tx) in nxp_c45_hwtstamp()
1060 nxp_c45_set_reg_field(phydev, &data->regmap->irq_egr_ts_en); in nxp_c45_hwtstamp()
1062 nxp_c45_clear_reg_field(phydev, &data->regmap->irq_egr_ts_en); in nxp_c45_hwtstamp()
1074 ts_info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | in nxp_c45_ts_info()
1077 ts_info->phc_index = ptp_clock_index(priv->ptp_clock); in nxp_c45_ts_info()
1078 ts_info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); in nxp_c45_ts_info()
1079 ts_info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in nxp_c45_ts_info()
1136 return ARRAY_SIZE(common_hw_stats) + (phy_data ? phy_data->n_stats : 0); in nxp_c45_get_sset_count()
1151 idx = i - ARRAY_SIZE(common_hw_stats); in nxp_c45_get_strings()
1152 ethtool_puts(&data, phy_data->stats[idx].name); in nxp_c45_get_strings()
1170 idx = i - ARRAY_SIZE(common_hw_stats); in nxp_c45_get_stats()
1171 reg_field = &phy_data->stats[idx].counter; in nxp_c45_get_stats()
1209 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in nxp_c45_config_intr()
1245 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in tja1120_config_intr()
1262 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_handle_interrupt()
1275 irq = nxp_c45_read_reg_field(phydev, &data->regmap->irq_egr_ts_status); in nxp_c45_handle_interrupt()
1277 /* If ack_ptp_irq is false, the IRQ bit is self-clear and will in nxp_c45_handle_interrupt()
1281 if (data->ack_ptp_irq) in nxp_c45_handle_interrupt()
1284 while (data->get_egressts(priv, &hwts)) in nxp_c45_handle_interrupt()
1290 data->nmi_handler(phydev, &ret); in nxp_c45_handle_interrupt()
1319 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_start()
1330 ret = nxp_c45_read_reg_field(phydev, ®map->cable_test_valid); in nxp_c45_cable_test_get_status()
1338 ®map->cable_test_result); in nxp_c45_cable_test_get_status()
1358 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_get_status()
1372 return -EINVAL; in nxp_c45_get_sqi()
1384 if (phydev->state == PHY_NOLINK) { in tja1120_link_change_notify()
1401 return -EINVAL; in nxp_c45_check_delay()
1406 return -EINVAL; in nxp_c45_check_delay()
1419 data->counters_enable(phydev); in nxp_c45_counters_enable()
1427 data->regmap->vend1_ptp_clk_period, in nxp_c45_ptp_init()
1428 data->ptp_clk_period); in nxp_c45_ptp_init()
1429 nxp_c45_clear_reg_field(phydev, &data->regmap->ltc_lock_ctrl); in nxp_c45_ptp_init()
1431 data->ptp_init(phydev); in nxp_c45_ptp_init()
1436 /* The delay in degree phase is 73.8 + phase_offset_raw * 0.9. in nxp_c45_get_phase_shift()
1441 phase_offset_raw -= 738; in nxp_c45_get_phase_shift()
1453 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_set_delays()
1454 u64 tx_delay = priv->tx_delay; in nxp_c45_set_delays()
1455 u64 rx_delay = priv->rx_delay; in nxp_c45_set_delays()
1458 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_set_delays()
1459 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in nxp_c45_set_delays()
1468 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_set_delays()
1469 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in nxp_c45_set_delays()
1481 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_get_delays()
1484 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_get_delays()
1485 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in nxp_c45_get_delays()
1486 ret = device_property_read_u32(&phydev->mdio.dev, in nxp_c45_get_delays()
1487 "tx-internal-delay-ps", in nxp_c45_get_delays()
1488 &priv->tx_delay); in nxp_c45_get_delays()
1490 priv->tx_delay = DEFAULT_ID_PS; in nxp_c45_get_delays()
1492 ret = nxp_c45_check_delay(phydev, priv->tx_delay); in nxp_c45_get_delays()
1495 "tx-internal-delay-ps invalid value\n"); in nxp_c45_get_delays()
1500 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_get_delays()
1501 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in nxp_c45_get_delays()
1502 ret = device_property_read_u32(&phydev->mdio.dev, in nxp_c45_get_delays()
1503 "rx-internal-delay-ps", in nxp_c45_get_delays()
1504 &priv->rx_delay); in nxp_c45_get_delays()
1506 priv->rx_delay = DEFAULT_ID_PS; in nxp_c45_get_delays()
1508 ret = nxp_c45_check_delay(phydev, priv->rx_delay); in nxp_c45_get_delays()
1511 "rx-internal-delay-ps invalid value\n"); in nxp_c45_get_delays()
1521 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_set_phy_mode()
1528 switch (phydev->interface) { in nxp_c45_set_phy_mode()
1532 return -EINVAL; in nxp_c45_set_phy_mode()
1542 phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n"); in nxp_c45_set_phy_mode()
1543 return -EINVAL; in nxp_c45_set_phy_mode()
1556 return -EINVAL; in nxp_c45_set_phy_mode()
1563 phydev_err(phydev, "rev-mii mode not supported\n"); in nxp_c45_set_phy_mode()
1564 return -EINVAL; in nxp_c45_set_phy_mode()
1571 phydev_err(phydev, "rmii mode not supported\n"); in nxp_c45_set_phy_mode()
1572 return -EINVAL; in nxp_c45_set_phy_mode()
1578 if (priv->flags & TJA11XX_REVERSE_MODE) in nxp_c45_set_phy_mode()
1587 return -EINVAL; in nxp_c45_set_phy_mode()
1595 return -EINVAL; in nxp_c45_set_phy_mode()
1674 if (phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, GENMASK(31, 4))) in nxp_c45_config_init()
1684 phydev->autoneg = AUTONEG_DISABLE; in nxp_c45_config_init()
1697 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); in nxp_c45_get_features()
1698 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, phydev->supported); in nxp_c45_get_features()
1705 struct device_node *node = phydev->mdio.dev.of_node; in nxp_c45_parse_dt()
1706 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_parse_dt()
1711 if (of_property_read_bool(node, "nxp,rmii-refclk-out")) in nxp_c45_parse_dt()
1712 priv->flags |= TJA11XX_REVERSE_MODE; in nxp_c45_parse_dt()
1725 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in nxp_c45_probe()
1727 return -ENOMEM; in nxp_c45_probe()
1729 skb_queue_head_init(&priv->tx_queue); in nxp_c45_probe()
1730 skb_queue_head_init(&priv->rx_queue); in nxp_c45_probe()
1732 priv->phydev = phydev; in nxp_c45_probe()
1734 phydev->priv = priv; in nxp_c45_probe()
1738 mutex_init(&priv->ptp_lock); in nxp_c45_probe()
1750 priv->mii_ts.rxtstamp = nxp_c45_rxtstamp; in nxp_c45_probe()
1751 priv->mii_ts.txtstamp = nxp_c45_txtstamp; in nxp_c45_probe()
1752 priv->mii_ts.hwtstamp = nxp_c45_hwtstamp; in nxp_c45_probe()
1753 priv->mii_ts.ts_info = nxp_c45_ts_info; in nxp_c45_probe()
1754 phydev->mii_ts = &priv->mii_ts; in nxp_c45_probe()
1758 phydev->default_timestamp = true; in nxp_c45_probe()
1784 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_remove()
1786 if (priv->ptp_clock) in nxp_c45_remove()
1787 ptp_clock_unregister(priv->ptp_clock); in nxp_c45_remove()
1789 skb_queue_purge(&priv->tx_queue); in nxp_c45_remove()
1790 skb_queue_purge(&priv->rx_queue); in nxp_c45_remove()
1971 u32 id = phydev->is_c45 ? phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] : in tja11xx_phy_id_compare()
1972 phydev->phy_id; in tja11xx_phy_id_compare()
1974 return phy_id_compare(id, phydrv->phy_id, phydrv->phy_id_mask); in tja11xx_phy_id_compare()
2174 MODULE_AUTHOR("Radu Pirea <radu-nicolae.pirea@oss.nxp.com>");