Lines Matching +full:rx +full:- +full:equalizer
1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
167 #define DP83867_LED_FN_LINK_RX_TX 0xb /* Link established, blink for rx or tx activity */
212 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
219 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
224 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
225 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol()
228 return -EINVAL; in dp83867_set_wol()
242 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
244 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
246 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
248 (wol->sopass[5] << 8) | wol->sopass[4]); in dp83867_set_wol()
255 if (wol->wolopts & WAKE_UCAST) in dp83867_set_wol()
260 if (wol->wolopts & WAKE_BCAST) in dp83867_set_wol()
280 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | in dp83867_get_wol()
282 wol->wolopts = 0; in dp83867_get_wol()
287 wol->wolopts |= WAKE_UCAST; in dp83867_get_wol()
290 wol->wolopts |= WAKE_BCAST; in dp83867_get_wol()
293 wol->wolopts |= WAKE_MAGIC; in dp83867_get_wol()
298 wol->sopass[0] = (sopass_val & 0xff); in dp83867_get_wol()
299 wol->sopass[1] = (sopass_val >> 8); in dp83867_get_wol()
303 wol->sopass[2] = (sopass_val & 0xff); in dp83867_get_wol()
304 wol->sopass[3] = (sopass_val >> 8); in dp83867_get_wol()
308 wol->sopass[4] = (sopass_val & 0xff); in dp83867_get_wol()
309 wol->sopass[5] = (sopass_val >> 8); in dp83867_get_wol()
311 wol->wolopts |= WAKE_MAGICSECURE; in dp83867_get_wol()
315 wol->wolopts = 0; in dp83867_get_wol()
322 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83867_config_intr()
389 phydev->duplex = DUPLEX_FULL; in dp83867_read_status()
391 phydev->duplex = DUPLEX_HALF; in dp83867_read_status()
394 phydev->speed = SPEED_1000; in dp83867_read_status()
396 phydev->speed = SPEED_100; in dp83867_read_status()
398 phydev->speed = SPEED_10; in dp83867_read_status()
428 return -EINVAL; in dp83867_get_downshift()
441 return -E2BIG; in dp83867_set_downshift()
463 return -EINVAL; in dp83867_set_downshift()
477 switch (tuna->id) { in dp83867_get_tunable()
481 return -EOPNOTSUPP; in dp83867_get_tunable()
488 switch (tuna->id) { in dp83867_set_tunable()
492 return -EOPNOTSUPP; in dp83867_set_tunable()
498 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_port_mirroring()
500 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) in dp83867_config_port_mirroring()
511 struct dp83867_private *dp83867 = phydev->priv; in dp83867_verify_rgmii_cfg()
516 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { in dp83867_verify_rgmii_cfg()
527 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" in dp83867_verify_rgmii_cfg()
528 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", in dp83867_verify_rgmii_cfg()
532 /* RX delay *must* be specified if internal delay of RX is used. */ in dp83867_verify_rgmii_cfg()
533 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
534 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && in dp83867_verify_rgmii_cfg()
535 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
536 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
537 return -EINVAL; in dp83867_verify_rgmii_cfg()
541 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
542 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && in dp83867_verify_rgmii_cfg()
543 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
544 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
545 return -EINVAL; in dp83867_verify_rgmii_cfg()
554 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init_io_impedance()
555 struct device *dev = &phydev->mdio.dev; in dp83867_of_init_io_impedance()
556 struct device_node *of_node = dev->of_node; in dp83867_of_init_io_impedance()
564 if (ret != -ENOENT && ret != -EOPNOTSUPP) in dp83867_of_init_io_impedance()
569 if (of_property_read_bool(of_node, "ti,max-output-impedance")) in dp83867_of_init_io_impedance()
570 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; in dp83867_of_init_io_impedance()
571 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) in dp83867_of_init_io_impedance()
572 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; in dp83867_of_init_io_impedance()
574 dp83867->io_impedance = -1; /* leave at default */ in dp83867_of_init_io_impedance()
590 return -ERANGE; in dp83867_of_init_io_impedance()
592 dp83867->io_impedance = val; in dp83867_of_init_io_impedance()
599 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
600 struct device *dev = &phydev->mdio.dev; in dp83867_of_init()
601 struct device_node *of_node = dev->of_node; in dp83867_of_init()
605 return -ENODEV; in dp83867_of_init()
608 ret = of_property_read_u32(of_node, "ti,clk-output-sel", in dp83867_of_init()
609 &dp83867->clk_output_sel); in dp83867_of_init()
612 dp83867->set_clk_output = true; in dp83867_of_init()
616 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && in dp83867_of_init()
617 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { in dp83867_of_init()
618 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
619 dp83867->clk_output_sel); in dp83867_of_init()
620 return -EINVAL; in dp83867_of_init()
628 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, in dp83867_of_init()
629 "ti,dp83867-rxctrl-strap-quirk"); in dp83867_of_init()
631 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, in dp83867_of_init()
632 "ti,sgmii-ref-clock-output-enable"); in dp83867_of_init()
634 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; in dp83867_of_init()
635 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", in dp83867_of_init()
636 &dp83867->rx_id_delay); in dp83867_of_init()
637 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { in dp83867_of_init()
639 "ti,rx-internal-delay value of %u out of range\n", in dp83867_of_init()
640 dp83867->rx_id_delay); in dp83867_of_init()
641 return -EINVAL; in dp83867_of_init()
644 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; in dp83867_of_init()
645 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", in dp83867_of_init()
646 &dp83867->tx_id_delay); in dp83867_of_init()
647 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { in dp83867_of_init()
649 "ti,tx-internal-delay value of %u out of range\n", in dp83867_of_init()
650 dp83867->tx_id_delay); in dp83867_of_init()
651 return -EINVAL; in dp83867_of_init()
654 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) in dp83867_of_init()
655 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; in dp83867_of_init()
657 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) in dp83867_of_init()
658 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; in dp83867_of_init()
660 ret = of_property_read_u32(of_node, "ti,fifo-depth", in dp83867_of_init()
661 &dp83867->tx_fifo_depth); in dp83867_of_init()
663 ret = of_property_read_u32(of_node, "tx-fifo-depth", in dp83867_of_init()
664 &dp83867->tx_fifo_depth); in dp83867_of_init()
666 dp83867->tx_fifo_depth = in dp83867_of_init()
670 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
671 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
672 dp83867->tx_fifo_depth); in dp83867_of_init()
673 return -EINVAL; in dp83867_of_init()
676 ret = of_property_read_u32(of_node, "rx-fifo-depth", in dp83867_of_init()
677 &dp83867->rx_fifo_depth); in dp83867_of_init()
679 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
681 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
682 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
683 dp83867->rx_fifo_depth); in dp83867_of_init()
684 return -EINVAL; in dp83867_of_init()
692 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
695 /* For non-OF device, the RX and TX ID values are either strapped in dp83867_of_init()
696 * or take from default value. So, we init RX & TX ID values here in dp83867_of_init()
701 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX; in dp83867_of_init()
702 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) & in dp83867_of_init()
705 /* Per datasheet, IO impedance is default to 50-ohm, so we set the in dp83867_of_init()
709 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2; in dp83867_of_init()
711 /* For non-OF device, the RX and TX FIFO depths are taken from in dp83867_of_init()
712 * default value. So, we init RX & TX FIFO depths here in dp83867_of_init()
715 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
716 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
726 phydev->interrupts = PHY_INTERRUPT_DISABLED; in dp83867_suspend()
737 phydev->interrupts = PHY_INTERRUPT_ENABLED; in dp83867_resume()
750 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), in dp83867_probe()
753 return -ENOMEM; in dp83867_probe()
755 phydev->priv = dp83867; in dp83867_probe()
762 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_init()
777 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
784 * be set to 0x2. This may causes the PHY link to be unstable - in dp83867_config_init()
796 phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
802 val |= (dp83867->tx_fifo_depth << in dp83867_config_init()
805 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
807 val |= (dp83867->rx_fifo_depth << in dp83867_config_init()
849 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in dp83867_config_init()
852 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in dp83867_config_init()
855 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in dp83867_config_init()
861 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) in dp83867_config_init()
862 delay |= dp83867->rx_id_delay; in dp83867_config_init()
863 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) in dp83867_config_init()
864 delay |= dp83867->tx_id_delay << in dp83867_config_init()
872 if (dp83867->io_impedance >= 0) in dp83867_config_init()
875 dp83867->io_impedance); in dp83867_config_init()
877 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
904 /* SGMII type is set to 4-wire mode by default. in dp83867_config_init()
906 * switch on 6-wire mode. in dp83867_config_init()
908 if (dp83867->sgmii_ref_clk_en) in dp83867_config_init()
918 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
931 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) in dp83867_config_init()
935 if (dp83867->set_clk_output) { in dp83867_config_init()
938 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { in dp83867_config_init()
942 val = dp83867->clk_output_sel << in dp83867_config_init()
968 /* Configure the DSP Feedforward Equalizer Configuration register to in dp83867_phy_reset()
991 * hence no new in-band message from PHY to MAC side SGMII. in dp83867_link_change_notify()
994 * SGMII wouldn`t receive new in-band message from TI PHY with in dp83867_link_change_notify()
996 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg in dp83867_link_change_notify()
999 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_link_change_notify()
1025 return -EINVAL; in dp83867_led_brightness_set()
1042 return -EINVAL; in dp83867_led_mode()
1068 return -EOPNOTSUPP; in dp83867_led_mode()
1169 return -EINVAL; in dp83867_led_polarity_set()