Lines Matching full:tr
505 struct tc35815_regs __iomem *tr = in tc_mdio_read() local
509 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA); in tc_mdio_read()
511 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { in tc_mdio_read()
516 return tc_readl(&tr->MD_Data) & 0xffff; in tc_mdio_read()
522 struct tc35815_regs __iomem *tr = in tc_mdio_write() local
526 tc_writel(val, &tr->MD_Data); in tc_mdio_write()
528 &tr->MD_CA); in tc_mdio_write()
530 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { in tc_mdio_write()
548 struct tc35815_regs __iomem *tr = in tc_handle_link_change() local
552 reg = tc_readl(&tr->MAC_Ctl); in tc_handle_link_change()
554 tc_writel(reg, &tr->MAC_Ctl); in tc_handle_link_change()
559 tc_writel(reg, &tr->MAC_Ctl); in tc_handle_link_change()
561 tc_writel(reg, &tr->MAC_Ctl); in tc_handle_link_change()
574 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr, in tc_handle_link_change()
575 &tr->Tx_Ctl); in tc_handle_link_change()
725 struct tc35815_regs __iomem *tr = in tc35815_init_dev_addr() local
730 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) in tc35815_init_dev_addr()
734 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl); in tc35815_init_dev_addr()
735 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) in tc35815_init_dev_addr()
737 data = tc_readl(&tr->PROM_Data); in tc35815_init_dev_addr()
1183 struct tc35815_regs __iomem *tr = in tc35815_schedule_restart() local
1189 tc_writel(0, &tr->Int_En); in tc35815_schedule_restart()
1190 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl); in tc35815_schedule_restart()
1197 struct tc35815_regs __iomem *tr = in tc35815_tx_timeout() local
1201 dev->name, tc_readl(&tr->Tx_Stat)); in tc35815_tx_timeout()
1312 struct tc35815_regs __iomem *tr = in tc35815_send_packet() local
1321 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); in tc35815_send_packet()
1432 struct tc35815_regs __iomem *tr = in tc35815_interrupt() local
1434 u32 dmactl = tc_readl(&tr->DMA_Ctl); in tc35815_interrupt()
1439 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl); in tc35815_interrupt()
1442 (void)tc_readl(&tr->Int_Src); /* flush */ in tc35815_interrupt()
1621 struct tc35815_regs __iomem *tr = in tc35815_poll() local
1630 status = tc_readl(&tr->Int_Src); in tc35815_poll()
1634 &tr->Int_Src); /* write to clear */ in tc35815_poll()
1639 &tr->Int_Src); in tc35815_poll()
1645 status = tc_readl(&tr->Int_Src); in tc35815_poll()
1652 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl); in tc35815_poll()
1695 struct tc35815_regs __iomem *tr = in tc35815_check_tx_stat() local
1697 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh); in tc35815_check_tx_stat()
1782 struct tc35815_regs __iomem *tr = in tc35815_txdone() local
1808 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); in tc35815_txdone()
1850 struct tc35815_regs __iomem *tr = in tc35815_get_stats() local
1854 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt); in tc35815_get_stats()
1863 struct tc35815_regs __iomem *tr = in tc35815_set_cam_entry() local
1869 saved_addr = tc_readl(&tr->CAM_Adr); in tc35815_set_cam_entry()
1876 tc_writel(cam_index - 2, &tr->CAM_Adr); in tc35815_set_cam_entry()
1877 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000; in tc35815_set_cam_entry()
1879 tc_writel(cam_data, &tr->CAM_Data); in tc35815_set_cam_entry()
1881 tc_writel(cam_index + 2, &tr->CAM_Adr); in tc35815_set_cam_entry()
1883 tc_writel(cam_data, &tr->CAM_Data); in tc35815_set_cam_entry()
1886 tc_writel(cam_index, &tr->CAM_Adr); in tc35815_set_cam_entry()
1888 tc_writel(cam_data, &tr->CAM_Data); in tc35815_set_cam_entry()
1890 tc_writel(cam_index + 4, &tr->CAM_Adr); in tc35815_set_cam_entry()
1891 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff; in tc35815_set_cam_entry()
1893 tc_writel(cam_data, &tr->CAM_Data); in tc35815_set_cam_entry()
1896 tc_writel(saved_addr, &tr->CAM_Adr); in tc35815_set_cam_entry()
1910 struct tc35815_regs __iomem *tr = in tc35815_set_multicast_list() local
1922 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl); in tc35815_set_multicast_list()
1927 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl); in tc35815_set_multicast_list()
1933 tc_writel(0, &tr->CAM_Ctl); in tc35815_set_multicast_list()
1942 tc_writel(ena_bits, &tr->CAM_Ena); in tc35815_set_multicast_list()
1943 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); in tc35815_set_multicast_list()
1945 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); in tc35815_set_multicast_list()
1946 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); in tc35815_set_multicast_list()
2020 struct tc35815_regs __iomem *tr = in tc35815_chip_reset() local
2024 tc_writel(MAC_Reset, &tr->MAC_Ctl); in tc35815_chip_reset()
2027 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) { in tc35815_chip_reset()
2034 tc_writel(0, &tr->MAC_Ctl); in tc35815_chip_reset()
2037 tc_writel(0, &tr->DMA_Ctl); in tc35815_chip_reset()
2038 tc_writel(0, &tr->TxThrsh); in tc35815_chip_reset()
2039 tc_writel(0, &tr->TxPollCtr); in tc35815_chip_reset()
2040 tc_writel(0, &tr->RxFragSize); in tc35815_chip_reset()
2041 tc_writel(0, &tr->Int_En); in tc35815_chip_reset()
2042 tc_writel(0, &tr->FDA_Bas); in tc35815_chip_reset()
2043 tc_writel(0, &tr->FDA_Lim); in tc35815_chip_reset()
2044 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */ in tc35815_chip_reset()
2045 tc_writel(0, &tr->CAM_Ctl); in tc35815_chip_reset()
2046 tc_writel(0, &tr->Tx_Ctl); in tc35815_chip_reset()
2047 tc_writel(0, &tr->Rx_Ctl); in tc35815_chip_reset()
2048 tc_writel(0, &tr->CAM_Ena); in tc35815_chip_reset()
2049 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */ in tc35815_chip_reset()
2052 tc_writel(DMA_TestMode, &tr->DMA_Ctl); in tc35815_chip_reset()
2054 tc_writel(i, &tr->CAM_Adr); in tc35815_chip_reset()
2055 tc_writel(0, &tr->CAM_Data); in tc35815_chip_reset()
2057 tc_writel(0, &tr->DMA_Ctl); in tc35815_chip_reset()
2063 struct tc35815_regs __iomem *tr = in tc35815_chip_init() local
2071 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); in tc35815_chip_init()
2072 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); in tc35815_chip_init()
2076 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl); in tc35815_chip_init()
2078 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl); in tc35815_chip_init()
2079 tc_writel(0, &tr->TxPollCtr); /* Batch mode */ in tc35815_chip_init()
2080 tc_writel(TX_THRESHOLD, &tr->TxThrsh); in tc35815_chip_init()
2081 tc_writel(INT_EN_CMD, &tr->Int_En); in tc35815_chip_init()
2084 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas); in tc35815_chip_init()
2086 &tr->FDA_Lim); in tc35815_chip_init()
2092 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */ in tc35815_chip_init()
2093 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */ in tc35815_chip_init()
2102 tc_writel(txctl, &tr->Tx_Ctl); in tc35815_chip_init()