Lines Matching +full:gmii +full:- +full:to +full:- +full:rgmii
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
68 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
70 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
75 #define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */
77 /* SGMII/RGMII status register */
94 #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
108 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
133 /* GMII ADDR defines */
164 /* MAC GMII or MII Transmit Protocol Engine Status */
166 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
182 /* MAC GMII or MII Receive Protocol Engine Status */
185 /*--- DMA BLOCK defines ---*/
203 #define DMA_BUS_MODE_RPBL_MASK 0x007e0000 /* Rx-Programmable Burst Len */
267 * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
268 * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
269 * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
270 * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
271 * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
272 * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
273 * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
274 * 1,11 - Reserved
284 * is set to 0. This allows pause frames with a quanta of 0 to be sent
285 * as an XOFF message to the link peer.