Lines Matching +full:0 +full:x000e000e
36 module_param_named(msg_level, mtk_msg_level, int, 0);
37 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
47 .tx_irq_mask = 0x1a1c,
48 .tx_irq_status = 0x1a18,
50 .rx_ptr = 0x0900,
51 .rx_cnt_cfg = 0x0904,
52 .pcrx_ptr = 0x0908,
53 .glo_cfg = 0x0a04,
54 .rst_idx = 0x0a08,
55 .delay_irq = 0x0a0c,
56 .irq_status = 0x0a20,
57 .irq_mask = 0x0a28,
58 .adma_rx_dbg0 = 0x0a38,
59 .int_grp = 0x0a50,
62 .qtx_cfg = 0x1800,
63 .qtx_sch = 0x1804,
64 .rx_ptr = 0x1900,
65 .rx_cnt_cfg = 0x1904,
66 .qcrx_ptr = 0x1908,
67 .glo_cfg = 0x1a04,
68 .rst_idx = 0x1a08,
69 .delay_irq = 0x1a0c,
70 .fc_th = 0x1a10,
71 .tx_sch_rate = 0x1a14,
72 .int_grp = 0x1a20,
73 .hred = 0x1a44,
74 .ctx_ptr = 0x1b00,
75 .dtx_ptr = 0x1b04,
76 .crx_ptr = 0x1b10,
77 .drx_ptr = 0x1b14,
78 .fq_head = 0x1b20,
79 .fq_tail = 0x1b24,
80 .fq_count = 0x1b28,
81 .fq_blen = 0x1b2c,
83 .gdm1_cnt = 0x2400,
85 [0] = 0x4444,
87 .ppe_base = 0x0c00,
89 [0] = 0x2800,
90 [1] = 0x2c00,
92 .pse_iq_sta = 0x0110,
93 .pse_oq_sta = 0x0118,
97 .tx_irq_mask = 0x0a28,
98 .tx_irq_status = 0x0a20,
100 .rx_ptr = 0x0900,
101 .rx_cnt_cfg = 0x0904,
102 .pcrx_ptr = 0x0908,
103 .glo_cfg = 0x0a04,
104 .rst_idx = 0x0a08,
105 .delay_irq = 0x0a0c,
106 .irq_status = 0x0a20,
107 .irq_mask = 0x0a28,
108 .int_grp = 0x0a50,
113 .tx_irq_mask = 0x461c,
114 .tx_irq_status = 0x4618,
116 .rx_ptr = 0x4100,
117 .rx_cnt_cfg = 0x4104,
118 .pcrx_ptr = 0x4108,
119 .glo_cfg = 0x4204,
120 .rst_idx = 0x4208,
121 .delay_irq = 0x420c,
122 .irq_status = 0x4220,
123 .irq_mask = 0x4228,
124 .adma_rx_dbg0 = 0x4238,
125 .int_grp = 0x4250,
128 .qtx_cfg = 0x4400,
129 .qtx_sch = 0x4404,
130 .rx_ptr = 0x4500,
131 .rx_cnt_cfg = 0x4504,
132 .qcrx_ptr = 0x4508,
133 .glo_cfg = 0x4604,
134 .rst_idx = 0x4608,
135 .delay_irq = 0x460c,
136 .fc_th = 0x4610,
137 .int_grp = 0x4620,
138 .hred = 0x4644,
139 .ctx_ptr = 0x4700,
140 .dtx_ptr = 0x4704,
141 .crx_ptr = 0x4710,
142 .drx_ptr = 0x4714,
143 .fq_head = 0x4720,
144 .fq_tail = 0x4724,
145 .fq_count = 0x4728,
146 .fq_blen = 0x472c,
147 .tx_sch_rate = 0x4798,
149 .gdm1_cnt = 0x1c00,
151 [0] = 0x3333,
152 [1] = 0x4444,
154 .ppe_base = 0x2000,
156 [0] = 0x4800,
157 [1] = 0x4c00,
159 .pse_iq_sta = 0x0180,
160 .pse_oq_sta = 0x01a0,
164 .tx_irq_mask = 0x461c,
165 .tx_irq_status = 0x4618,
167 .rx_ptr = 0x6900,
168 .rx_cnt_cfg = 0x6904,
169 .pcrx_ptr = 0x6908,
170 .glo_cfg = 0x6a04,
171 .rst_idx = 0x6a08,
172 .delay_irq = 0x6a0c,
173 .irq_status = 0x6a20,
174 .irq_mask = 0x6a28,
175 .adma_rx_dbg0 = 0x6a38,
176 .int_grp = 0x6a50,
179 .qtx_cfg = 0x4400,
180 .qtx_sch = 0x4404,
181 .rx_ptr = 0x4500,
182 .rx_cnt_cfg = 0x4504,
183 .qcrx_ptr = 0x4508,
184 .glo_cfg = 0x4604,
185 .rst_idx = 0x4608,
186 .delay_irq = 0x460c,
187 .fc_th = 0x4610,
188 .int_grp = 0x4620,
189 .hred = 0x4644,
190 .ctx_ptr = 0x4700,
191 .dtx_ptr = 0x4704,
192 .crx_ptr = 0x4710,
193 .drx_ptr = 0x4714,
194 .fq_head = 0x4720,
195 .fq_tail = 0x4724,
196 .fq_count = 0x4728,
197 .fq_blen = 0x472c,
198 .tx_sch_rate = 0x4798,
200 .gdm1_cnt = 0x1c00,
202 [0] = 0x3333,
203 [1] = 0x4444,
204 [2] = 0xcccc,
206 .ppe_base = 0x2000,
208 [0] = 0x4800,
209 [1] = 0x4c00,
210 [2] = 0x5000,
212 .pse_iq_sta = 0x0180,
213 .pse_oq_sta = 0x01a0,
316 return 0; in mtk_mdio_busy_wait()
332 if (ret < 0) in _mtk_mdio_write_c22()
344 if (ret < 0) in _mtk_mdio_write_c22()
347 return 0; in _mtk_mdio_write_c22()
356 if (ret < 0) in _mtk_mdio_write_c45()
368 if (ret < 0) in _mtk_mdio_write_c45()
380 if (ret < 0) in _mtk_mdio_write_c45()
383 return 0; in _mtk_mdio_write_c45()
391 if (ret < 0) in _mtk_mdio_read_c22()
402 if (ret < 0) in _mtk_mdio_read_c22()
414 if (ret < 0) in _mtk_mdio_read_c45()
426 if (ret < 0) in _mtk_mdio_read_c45()
437 if (ret < 0) in _mtk_mdio_read_c45()
480 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; in mt7621_gmac0_rgmii_adjust()
485 return 0; in mt7621_gmac0_rgmii_adjust()
507 mtk_m32(eth, 0, MTK_XGMAC_FORCE_MODE(MTK_GMAC1_ID), in mtk_setup_bridge_switch()
528 0 : mac->id; in mtk_mac_select_pcs()
553 return 0; in mtk_mac_prepare()
562 int val, ge_mode, err = 0; in mtk_mac_config()
622 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) in mtk_mac_config()
628 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, in mtk_mac_config()
630 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); in mtk_mac_config()
640 ge_mode = 0; in mtk_mac_config()
718 return 0; in mtk_mac_finish()
730 MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK, 0, in mtk_mac_link_down()
736 mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, in mtk_mac_link_down()
861 mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id)); in mtk_xgdm_mac_link_up()
905 mtk_m32(eth, MAC_MCR_EEE100M | MAC_MCR_EEE1G, 0, MTK_MAC_MCR(mac->id)); in mtk_mac_disable_tx_lpi()
943 mtk_m32(eth, 0, MAC_MCR_EEE100M | MAC_MCR_EEE1G, MTK_MAC_MCR(mac->id)); in mtk_mac_enable_tx_lpi()
945 return 0; in mtk_mac_enable_tx_lpi()
968 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); in mtk_mdio_config()
1089 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
1095 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
1103 return 0; in mtk_set_mac_address()
1126 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); in mtk_stats_update_mac()
1130 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); in mtk_stats_update_mac()
1132 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); in mtk_stats_update_mac()
1134 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); in mtk_stats_update_mac()
1136 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); in mtk_stats_update_mac()
1138 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); in mtk_stats_update_mac()
1140 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); in mtk_stats_update_mac()
1142 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); in mtk_stats_update_mac()
1146 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); in mtk_stats_update_mac()
1148 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); in mtk_stats_update_mac()
1150 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); in mtk_stats_update_mac()
1151 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); in mtk_stats_update_mac()
1155 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); in mtk_stats_update_mac()
1158 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); in mtk_stats_update_mac()
1160 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); in mtk_stats_update_mac()
1162 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); in mtk_stats_update_mac()
1163 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); in mtk_stats_update_mac()
1167 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); in mtk_stats_update_mac()
1178 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_stats_update()
1316 for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) { in mtk_init_fq_dma()
1330 for (i = 0; i < len; i++) { in mtk_init_fq_dma()
1343 txd->txd4 = 0; in mtk_init_fq_dma()
1345 txd->txd5 = 0; in mtk_init_fq_dma()
1346 txd->txd6 = 0; in mtk_init_fq_dma()
1347 txd->txd7 = 0; in mtk_init_fq_dma()
1348 txd->txd8 = 0; in mtk_init_fq_dma()
1358 return 0; in mtk_init_fq_dma()
1435 tx_buf->flags = 0; in mtk_tx_unmap()
1527 data = 0; in mtk_tx_set_dma_desc_v2()
1539 data = 0; in mtk_tx_set_dma_desc_v2()
1544 WRITE_ONCE(desc->txd7, 0); in mtk_tx_set_dma_desc_v2()
1545 WRITE_ONCE(desc->txd8, 0); in mtk_tx_set_dma_desc_v2()
1582 int k = 0; in mtk_tx_map()
1591 memset(itx_buf, 0, sizeof(*itx_buf)); in mtk_tx_map()
1609 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mtk_tx_map()
1611 unsigned int offset = 0; in mtk_tx_map()
1618 (i & 0x1)) { in mtk_tx_map()
1629 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); in mtk_tx_map()
1646 memset(tx_buf, 0, sizeof(*tx_buf)); in mtk_tx_map()
1664 if (k & 0x1) in mtk_tx_map()
1692 return 0; in mtk_tx_map()
1718 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mtk_cal_txd_req()
1734 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_queue_stopped()
1741 return 0; in mtk_queue_stopped()
1748 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_wake_queue()
1791 if (skb_cow_head(skb, 0)) { in mtk_start_xmit()
1804 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) in mtk_start_xmit()
1829 return ð->rx_ring[0]; in mtk_get_rx_ring()
1831 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { in mtk_get_rx_ring()
1852 ring = ð->rx_ring[0]; in mtk_update_rx_cpu_idx()
1855 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { in mtk_update_rx_cpu_idx()
1875 .order = 0, in mtk_create_page_pool()
1894 if (err < 0) in mtk_create_page_pool()
1967 return 0; in mtk_xdp_frame_map()
1983 int err, index = 0, n_desc = 1, nr_frags; in mtk_xdp_submit_frame()
1991 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; in mtk_xdp_submit_frame()
2005 memset(tx_buf, 0, sizeof(*tx_buf)); in mtk_xdp_submit_frame()
2011 if (err < 0) in mtk_xdp_submit_frame()
2017 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { in mtk_xdp_submit_frame()
2024 memset(tx_buf, 0, sizeof(*tx_buf)); in mtk_xdp_submit_frame()
2028 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); in mtk_xdp_submit_frame()
2068 return 0; in mtk_xdp_submit_frame()
2096 int i, nxmit = 0; in mtk_xdp_xmit()
2101 for (i = 0; i < num_frame; i++) { in mtk_xdp_xmit()
2186 u64 addr64 = 0; in mtk_poll_rx()
2189 int done = 0, bytes = 0; in mtk_poll_rx()
2191 int ppe_idx = 0; in mtk_poll_rx()
2197 int mac = 0; in mtk_poll_rx()
2230 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || in mtk_poll_rx()
2331 skb_set_hash(skb, jhash_1word(hash, 0), in mtk_poll_rx()
2338 skb_set_hash(skb, jhash_1word(hash, 0), in mtk_poll_rx()
2354 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); in mtk_poll_rx()
2364 skb_record_rx_queue(skb, 0); in mtk_poll_rx()
2467 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) in mtk_poll_tx_qdma()
2517 mtk_poll_tx_done(eth, state, 0, tx_buf->data); in mtk_poll_tx_pdma()
2575 int tx_done = 0; in mtk_napi_tx()
2584 "done tx %d, intr 0x%08x/0x%x\n", tx_done, in mtk_napi_tx()
2605 int rx_done_total = 0; in mtk_napi_rx()
2619 "done rx %d, intr 0x%08x/0x%x\n", rx_done, in mtk_napi_rx()
2659 for (i = 0; i < ring_size; i++) { in mtk_tx_alloc()
2666 txd->txd4 = 0; in mtk_tx_alloc()
2668 txd->txd5 = 0; in mtk_tx_alloc()
2669 txd->txd6 = 0; in mtk_tx_alloc()
2670 txd->txd7 = 0; in mtk_tx_alloc()
2671 txd->txd8 = 0; in mtk_tx_alloc()
2685 for (i = 0; i < ring_size; i++) { in mtk_tx_alloc()
2687 ring->dma_pdma[i].txd4 = 0; in mtk_tx_alloc()
2711 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { in mtk_tx_alloc()
2732 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); in mtk_tx_alloc()
2736 return 0; in mtk_tx_alloc()
2749 for (i = 0; i < ring->dma_size; i++) in mtk_tx_clean()
2818 for (i = 0; i < rx_dma_size; i++) { in mtk_rx_alloc()
2858 rxd->rxd3 = 0; in mtk_rx_alloc()
2859 rxd->rxd4 = 0; in mtk_rx_alloc()
2861 rxd->rxd5 = 0; in mtk_rx_alloc()
2862 rxd->rxd6 = 0; in mtk_rx_alloc()
2863 rxd->rxd7 = 0; in mtk_rx_alloc()
2864 rxd->rxd8 = 0; in mtk_rx_alloc()
2899 return 0; in mtk_rx_alloc()
2904 u64 addr64 = 0; in mtk_rx_clean()
2908 for (i = 0; i < ring->dma_size; i++) { in mtk_rx_clean()
2946 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; in mtk_hwlro_rx_init()
2947 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; in mtk_hwlro_rx_init()
2989 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); in mtk_hwlro_rx_init()
3000 return 0; in mtk_hwlro_rx_init()
3012 for (i = 0; i < 10; i++) { in mtk_hwlro_rx_uninit()
3023 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); in mtk_hwlro_rx_uninit()
3026 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); in mtk_hwlro_rx_uninit()
3053 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); in mtk_hwlro_inval_ipaddr()
3058 int cnt = 0; in mtk_hwlro_get_ip_cnt()
3061 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { in mtk_hwlro_get_ip_cnt()
3090 return 0; in mtk_hwlro_add_ipaddr()
3105 mac->hwlro_ip[fsp->location] = 0; in mtk_hwlro_del_ipaddr()
3112 return 0; in mtk_hwlro_del_ipaddr()
3121 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { in mtk_hwlro_netdev_disable()
3122 mac->hwlro_ip[i] = 0; in mtk_hwlro_netdev_disable()
3128 mac->hwlro_ip_cnt = 0; in mtk_hwlro_netdev_disable()
3144 fsp->m_u.tcp_ip4_spec.ip4dst = 0; in mtk_hwlro_get_fdir_entry()
3146 fsp->h_u.tcp_ip4_spec.ip4src = 0; in mtk_hwlro_get_fdir_entry()
3147 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; in mtk_hwlro_get_fdir_entry()
3148 fsp->h_u.tcp_ip4_spec.psrc = 0; in mtk_hwlro_get_fdir_entry()
3149 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; in mtk_hwlro_get_fdir_entry()
3150 fsp->h_u.tcp_ip4_spec.pdst = 0; in mtk_hwlro_get_fdir_entry()
3151 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; in mtk_hwlro_get_fdir_entry()
3152 fsp->h_u.tcp_ip4_spec.tos = 0; in mtk_hwlro_get_fdir_entry()
3153 fsp->m_u.tcp_ip4_spec.tos = 0xff; in mtk_hwlro_get_fdir_entry()
3155 return 0; in mtk_hwlro_get_fdir_entry()
3163 int cnt = 0; in mtk_hwlro_get_fdir_all()
3166 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { in mtk_hwlro_get_fdir_all()
3178 return 0; in mtk_hwlro_get_fdir_all()
3205 return 0; in mtk_set_features()
3251 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); in mtk_dma_init()
3256 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); in mtk_dma_init()
3277 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); in mtk_dma_init()
3280 return 0; in mtk_dma_init()
3291 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_dma_free()
3295 for (j = 0; j < txqs; j++) in mtk_dma_free()
3304 eth->phy_scratch_ring = 0; in mtk_dma_free()
3308 mtk_rx_clean(eth, ð->rx_ring[0], true); in mtk_dma_free()
3317 for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) { in mtk_dma_free()
3356 if (eth->irq[MTK_FE_IRQ_TX] >= 0 && eth->irq[MTK_FE_IRQ_RX] >= 0) in mtk_get_irqs()
3357 return 0; in mtk_get_irqs()
3377 for (i = 0; i < MTK_FE_IRQ_NUM; i++) { in mtk_get_irqs()
3387 if (eth->irq[i] < 0) { in mtk_get_irqs()
3393 return 0; in mtk_get_irqs()
3457 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; in mtk_start_dma()
3491 return 0; in mtk_start_dma()
3504 val &= ~0xffff; in mtk_gdm_config()
3555 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) in mtk_device_event()
3562 if (mac->speed > 0 && mac->speed <= s.base.speed) in mtk_device_event()
3563 s.base.speed = 0; in mtk_device_event()
3579 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); in mtk_open()
3598 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_open()
3601 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_open()
3607 target_mac->ppe_idx = 0; in mtk_open()
3616 target_mac->ppe_idx = 0; in mtk_open()
3617 gdm_config = soc->reg_map->gdma_to_ppe[0]; in mtk_open()
3635 return 0; in mtk_open()
3638 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { in mtk_open()
3644 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, in mtk_open()
3661 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); in mtk_open()
3664 return 0; in mtk_open()
3680 for (i = 0; i < 10; i++) { in mtk_stop_dma()
3704 return 0; in mtk_stop()
3706 for (i = 0; i < MTK_MAX_DEVS; i++) in mtk_stop()
3723 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_stop()
3726 return 0; in mtk_stop()
3758 return 0; in mtk_xdp_setup()
3788 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) in mtk_clk_disable()
3796 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { in mtk_clk_enable()
3802 return 0; in mtk_clk_enable()
3805 while (--clk >= 0) in mtk_clk_enable()
3902 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); in mtk_hw_reset()
3927 0x6f8ff); in mtk_hw_reset()
3930 0x3ffffff); in mtk_hw_reset()
4002 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); in mtk_hw_check_dma_hang()
4004 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); in mtk_hw_check_dma_hang()
4007 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); in mtk_hw_check_dma_hang()
4011 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && in mtk_hw_check_dma_hang()
4012 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); in mtk_hw_check_dma_hang()
4016 eth->reset.wdma_hang_count = 0; in mtk_hw_check_dma_hang()
4023 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); in mtk_hw_check_dma_hang()
4024 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); in mtk_hw_check_dma_hang()
4026 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; in mtk_hw_check_dma_hang()
4027 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; in mtk_hw_check_dma_hang()
4028 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; in mtk_hw_check_dma_hang()
4030 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); in mtk_hw_check_dma_hang()
4031 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); in mtk_hw_check_dma_hang()
4037 eth->reset.qdma_hang_count = 0; in mtk_hw_check_dma_hang()
4044 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); in mtk_hw_check_dma_hang()
4046 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && in mtk_hw_check_dma_hang()
4051 eth->reset.adma_hang_count = 0; in mtk_hw_check_dma_hang()
4057 eth->reset.wdma_hang_count = 0; in mtk_hw_check_dma_hang()
4058 eth->reset.qdma_hang_count = 0; in mtk_hw_check_dma_hang()
4059 eth->reset.adma_hang_count = 0; in mtk_hw_check_dma_hang()
4092 return 0; in mtk_hw_init()
4119 mtk_tx_irq_disable(eth, ~0); in mtk_hw_init()
4120 mtk_rx_irq_disable(eth, ~0); in mtk_hw_init()
4122 return 0; in mtk_hw_init()
4144 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); in mtk_hw_init()
4147 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); in mtk_hw_init()
4150 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); in mtk_hw_init()
4157 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_hw_init()
4185 mtk_tx_irq_disable(eth, ~0); in mtk_hw_init()
4186 mtk_rx_irq_disable(eth, ~0); in mtk_hw_init()
4193 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); in mtk_hw_init()
4201 mtk_w32(eth, 0x00600009, PSE_IQ_REV(8)); in mtk_hw_init()
4206 mtk_w32(eth, 0x00002300, PSE_DROP_CFG); in mtk_hw_init()
4211 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0)); in mtk_hw_init()
4212 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1)); in mtk_hw_init()
4213 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2)); in mtk_hw_init()
4216 mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES); in mtk_hw_init()
4217 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); in mtk_hw_init()
4220 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); in mtk_hw_init()
4226 for (i = 0; i < 0x80; i += 0x4) in mtk_hw_init()
4227 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); in mtk_hw_init()
4230 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); in mtk_hw_init()
4233 mtk_w32(eth, 0x00000300, PSE_PPE_DROP(0)); in mtk_hw_init()
4236 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); in mtk_hw_init()
4239 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); in mtk_hw_init()
4240 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); in mtk_hw_init()
4241 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); in mtk_hw_init()
4242 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); in mtk_hw_init()
4243 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); in mtk_hw_init()
4244 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); in mtk_hw_init()
4245 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); in mtk_hw_init()
4246 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); in mtk_hw_init()
4249 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); in mtk_hw_init()
4250 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); in mtk_hw_init()
4251 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); in mtk_hw_init()
4252 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); in mtk_hw_init()
4253 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); in mtk_hw_init()
4254 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); in mtk_hw_init()
4255 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); in mtk_hw_init()
4256 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); in mtk_hw_init()
4259 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); in mtk_hw_init()
4260 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); in mtk_hw_init()
4261 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); in mtk_hw_init()
4262 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); in mtk_hw_init()
4263 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); in mtk_hw_init()
4264 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); in mtk_hw_init()
4267 return 0; in mtk_hw_init()
4281 return 0; in mtk_hw_deinit()
4288 return 0; in mtk_hw_deinit()
4297 mtk_tx_irq_disable(eth, ~0); in mtk_uninit()
4298 mtk_rx_irq_disable(eth, ~0); in mtk_uninit()
4316 return 0; in mtk_change_mtu()
4353 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_prepare_for_reset()
4357 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); in mtk_prepare_for_reset()
4360 for (i = 0; i < 2; i++) { in mtk_prepare_for_reset()
4369 unsigned long restart = 0; in mtk_pending_work()
4384 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_pending_work()
4400 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_pending_work()
4435 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_free_dev()
4441 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { in mtk_free_dev()
4447 return 0; in mtk_free_dev()
4454 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_unreg_dev()
4464 return 0; in mtk_unreg_dev()
4471 for (i = 0; i < MTK_MAX_DEVS; i++) in mtk_sgmii_destroy()
4483 return 0; in mtk_cleanup()
4553 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) in mtk_get_strings()
4585 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { in mtk_ethtool_pp_stats()
4621 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) in mtk_get_ethtool_stats()
4637 ret = 0; in mtk_get_rxnfc()
4645 ret = 0; in mtk_get_rxnfc()
4716 unsigned int queue = 0; in mtk_select_queue()
4724 queue = 0; in mtk_select_queue()
4821 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); in mtk_add_mac()
4822 mac->hwlro_ip_cnt = 0; in mtk_add_mac()
4836 mac->hw_stats->reg_offset = id * 0x80; in mtk_add_mac()
4838 mac->hw_stats->reg_offset = id * 0x40; in mtk_add_mac()
4863 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { in mtk_add_mac()
4954 return 0; in mtk_add_mac()
4969 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_eth_set_dma_device()
4997 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_sgmii_init()
5003 flags = 0; in mtk_sgmii_init()
5017 return 0; in mtk_sgmii_init()
5056 eth->base = devm_platform_ioremap_resource(pdev, 0); in mtk_probe()
5111 regmap_write(cci, 0, 3); in mtk_probe()
5132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in mtk_probe()
5140 "sram", 0); in mtk_probe()
5157 for (i = 0;; i++) { in mtk_probe()
5171 wdma_phy = res ? res->start + wdma_base : 0; in mtk_probe()
5181 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { in mtk_probe()
5225 mtk_handle_irq, 0, in mtk_probe()
5229 mtk_handle_irq_tx, 0, in mtk_probe()
5235 mtk_handle_irq_rx, 0, in mtk_probe()
5252 for (i = 0; i < ppe_num; i++) { in mtk_probe()
5255 ppe_addr += (i == 2 ? 0xc00 : i * 0x400); in mtk_probe()
5269 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_probe()
5279 "mediatek frame engine at 0x%08lx, irq %d\n", in mtk_probe()
5286 eth->dummy_dev = alloc_netdev_dummy(0); in mtk_probe()
5299 return 0; in mtk_probe()
5325 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_remove()
5397 .ana_rgc3 = 0x2028,
5456 .ana_rgc3 = 0x128,
5482 .ana_rgc3 = 0x128,
5512 .ana_rgc3 = 0x128,
5542 .ana_rgc3 = 0x128,