1 /* SPDX-License-Identifier: GPL-2.0 */
18 #include "mbox.h"
171 	u8			dir;  member
300 	int	cgx_users;  /* number of cgx users - used only by PFs */
426 	bool	per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
432 	bool    cpt_rxc;   /* Is CPT-RXC supported */
468 	struct otx2_mbox mbox;  member
583 	/* Mbox */
592 	/* MSI-X */
649 	struct mutex		mbox_lock; /* Serialize mbox up and down msgs */
665 	writeq(val, rvu->afreg_base + ((block << 28) | offset));  in rvu_write64()
670 	return readq(rvu->afreg_base + ((block << 28) | offset));  in rvu_read64()
675 	writeq(val, rvu->pfreg_base + offset);  in rvupf_write64()
680 	return readq(rvu->pfreg_base + offset);  in rvupf_read64()
697 	struct pci_dev *pdev = rvu->pdev;  in is_rvu_pre_96xx_C0()
699 	return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||  in is_rvu_pre_96xx_C0()
700 		(pdev->revision == 0x10) || (pdev->revision == 0x11) ||  in is_rvu_pre_96xx_C0()
701 		(pdev->revision == 0x14));  in is_rvu_pre_96xx_C0()
706 	struct pci_dev *pdev = rvu->pdev;  in is_rvu_96xx_A0()
708 	return (pdev->revision == 0x00);  in is_rvu_96xx_A0()
713 	struct pci_dev *pdev = rvu->pdev;  in is_rvu_96xx_B0()
715 	return (pdev->revision == 0x00) || (pdev->revision == 0x01);  in is_rvu_96xx_B0()
720 	struct pci_dev *pdev = rvu->pdev;  in is_rvu_95xx_A0()
722 	return (pdev->revision == 0x10) || (pdev->revision == 0x11);  in is_rvu_95xx_A0()
738 	struct pci_dev *pdev = rvu->pdev;  in is_rvu_otx2()
740 	u8 midr = pdev->revision & 0xF0;  in is_rvu_otx2()
749 	struct pci_dev *pdev = rvu->pdev;  in is_cnf10ka_a0()
751 	if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A &&  in is_cnf10ka_a0()
752 	    (pdev->revision & 0x0F) == 0x0)  in is_cnf10ka_a0()
759 	struct pci_dev *pdev = rvu->pdev;  in is_cn10ka_a0()
761 	if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A &&  in is_cn10ka_a0()
762 	    (pdev->revision & 0x0F) == 0x0)  in is_cn10ka_a0()
769 	struct pci_dev *pdev = rvu->pdev;  in is_cn10ka_a1()
771 	if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A &&  in is_cn10ka_a1()
772 	    (pdev->revision & 0x0F) == 0x1)  in is_cn10ka_a1()
779 	struct pci_dev *pdev = rvu->pdev;  in is_cn10kb()
781 	if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B)  in is_cn10kb()
816 	struct rvu_hwinfo *hw = rvu->hw;  in rvu_nix_chan_cgx()
818 	if (!hw->cap.programmable_chans)  in rvu_nix_chan_cgx()
821 	return rvu->hw->cgx_chan_base +  in rvu_nix_chan_cgx()
822 		(cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;  in rvu_nix_chan_cgx()
830 	struct rvu_hwinfo *hw = rvu->hw;  in rvu_nix_chan_lbk()
832 	if (!hw->cap.programmable_chans)  in rvu_nix_chan_lbk()
835 	return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;  in rvu_nix_chan_lbk()
840 	struct rvu_hwinfo *hw = rvu->hw;  in rvu_nix_chan_sdp()
842 	if (!hw->cap.programmable_chans)  in rvu_nix_chan_sdp()
845 	return hw->sdp_chan_base + chan;  in rvu_nix_chan_sdp()
850 	return rvu->hw->cpt_chan_base + chan;  in rvu_nix_chan_cpt()
855 	struct pci_dev *pdev = rvu->pdev;  in is_rvu_supports_nix1()
857 	if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX)  in is_rvu_supports_nix1()
870 		(rvu->vf_devid == RVU_LBK_VF_DEVID));  in is_lbk_vf()
886 	return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&  in is_rvu_fwdata_valid()
887 		(rvu->fwdata->version == RVU_FWDATA_VERSION);  in is_rvu_fwdata_valid()
934 	if (rvu->rep_pcifunc && rvu->rep_pcifunc == pcifunc)  in is_rep_dev()
953 	return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&  in is_pf_cgxmapped()
954 		!is_sdp_pf(rvu, rvu_make_pcifunc(rvu->pdev, pf, 0));  in is_pf_cgxmapped()
966 		is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc)));  in is_cgx_vf()
974 /* Mbox APIs */
1138 /* CN10K RVU - LMT*/
1158 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,