Lines Matching +full:rx +full:- +full:equalizer
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
511 __le32 mrq; /* Multiple Rx Queues */
529 /* Receive Descriptor - Packet Split */
537 __le32 mrq; /* Multiple Rx Queues */
553 __le16 length[3]; /* length of buffers 1-3 */
567 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
577 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
770 * RW - register is both readable and writable
771 * RO - register is read only
772 * WO - register is write only
773 * R/clr - register is read only and is cleared when read
774 * A - register array
776 #define E1000_CTRL 0x00000 /* Device Control - RW */
777 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
778 #define E1000_STATUS 0x00008 /* Device Status - RO */
779 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
780 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
781 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
782 #define E1000_FLA 0x0001C /* Flash Access - RW */
783 #define E1000_MDIC 0x00020 /* MDI Control - RW */
785 #define INTEL_CE_GBE_MDIO_RCOMP_BASE (hw->ce4100_gbe_mdio_base_virt)
793 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
795 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
796 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
797 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
798 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
799 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
800 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
801 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
802 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
803 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
807 * RMII/RGMII function is switched by this register - RW
833 #define E1000_RCTL 0x00100 /* RX Control - RW */
834 #define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
835 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
836 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
837 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
838 #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
839 #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
840 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
841 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
842 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
843 #define E1000_TCTL 0x00400 /* TX Control - RW */
844 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
845 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
846 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
847 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
848 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
853 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
859 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
864 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
865 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
866 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
867 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
868 #define E1000_RDFH 0x02410 /* RX Data FIFO Head - RW */
869 #define E1000_RDFT 0x02418 /* RX Data FIFO Tail - RW */
870 #define E1000_RDFHS 0x02420 /* RX Data FIFO Head Saved - RW */
871 #define E1000_RDFTS 0x02428 /* RX Data FIFO Tail Saved - RW */
872 #define E1000_RDFPC 0x02430 /* RX Data FIFO Packet Count - RW */
873 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
874 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
875 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
876 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
877 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
878 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
879 #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
880 #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
881 #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
882 #define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
883 #define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
884 #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
885 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
886 #define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
887 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
888 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
889 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
890 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
892 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
893 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
894 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
895 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
896 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
897 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
898 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
899 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
900 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
901 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
902 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
903 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
904 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
905 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
907 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
908 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
909 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
910 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
911 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
912 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
914 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
915 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
916 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
917 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
918 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
919 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
920 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
921 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
922 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
923 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
924 #define E1000_DC 0x04030 /* Defer Count - R/clr */
925 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
926 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
927 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
928 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
929 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
930 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
931 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
932 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
933 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
934 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
935 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
936 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
937 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
938 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
939 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
940 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
941 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
942 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
943 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
944 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
945 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
946 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
947 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
948 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
949 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
950 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
951 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
952 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
953 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
954 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
955 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
956 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
957 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
958 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
959 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
960 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
961 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
962 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
963 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
964 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
965 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
966 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
967 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
968 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
969 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
970 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
971 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
973 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
974 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
979 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
981 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
983 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
984 #define E1000_RA 0x05400 /* Receive Address - RW Array */
985 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
986 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
987 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
988 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
989 #define E1000_MANC 0x05820 /* Management Control - RW */
990 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
991 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
992 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
993 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
994 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
995 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
997 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
998 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1000 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
1001 #define E1000_MDPHYA 0x0003C /* PHY address - RW */
1002 #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
1003 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
1005 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
1006 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1007 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1008 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1009 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1017 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1018 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1019 #define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1020 #define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1069 * RX Control - RW */
1071 #define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1072 #define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1073 #define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1074 #define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1075 #define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1076 #define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1077 #define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1078 #define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1079 #define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1080 #define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1420 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1425 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1427 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1476 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1477 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1489 /* Constants used to interpret the masked PCI-X bus speed. */
1490 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1491 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1492 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1508 * (0-small, 1-large) */
1509 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1578 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1620 /* In-Band Control */
1624 /* Half-Duplex Control */
1692 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1693 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1694 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
1695 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1697 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1708 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1712 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1723 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1724 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1725 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1726 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1728 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1738 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error …
1742 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error …
1752 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1753 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1754 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1755 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1757 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1767 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error …
1771 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error …
1781 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1782 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1783 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1784 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1786 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1796 #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error …
1800 #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error …
1819 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1820 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1821 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1830 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1831 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1832 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1833 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1835 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1836 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1837 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1935 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1944 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1955 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1956 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
2024 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
2025 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
2026 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
2091 #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2097 /* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2134 /* PCI-Ex registers*/
2136 /* PCI-Ex Control Register */
2178 /* PCI-Ex Config Space */
2183 /* EEPROM Commands - Microwire */
2190 /* EEPROM Commands - SPI */
2194 #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2292 /* Collision distance is a 0-based value that applies to
2293 * half-duplex-capable hardware only. */
2353 #define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2354 #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2364 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2412 /* Number of milliseconds we wait for auto-negotiation to complete */
2429 * status = the 8 bit status field of the RX descriptor with EOP set
2430 * error = the 8 bit error field of the RX descriptor with EOP set
2431 * length = the sum of all the length fields of the RX descriptors that
2438 * handler's Rx processing routine when RxErrors have been detected.
2445 * frame_length--;
2453 ((adapter)->tbi_compatibility_on && \
2457 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2458 ((length) <= ((adapter)->max_frame_size + 1))) : \
2459 (((length) > (adapter)->min_frame_size) && \
2460 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2487 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2488 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2491 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2522 /* IGP01E1000 AGC Registers - stores the cable length values*/
2556 /* IGP01E1000 PCS Initialization register - stores the polarity status when
2614 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2651 /* 1000BASE-T Control Register */
2667 /* 1000BASE-T Status Register */
2704 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2705 * 100BASE-TX/10BASE-T:
2712 /* 1=Enable Extended 10BASE-T distance
2713 * (Lower 10BASE-T RX Threshold)
2714 * 0=Normal 10BASE-T RX Threshold */
2716 /* 1=5-Bit interface in 100BASE-TX
2717 * 0=MII interface in 100BASE-TX */
2731 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2732 * 3=110-140M;4=>140M */
2752 * within 1ms in 1000BASE-T
2783 /* IGP01E1000 Specific Port Config Register - R/W */
2791 /* IGP01E1000 Specific Port Status Register - R/O */
2805 /* IGP01E1000 Specific Port Control Register - R/W */
2811 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2836 #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2846 #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2847 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2849 /* IGP02E1000 AGC Register Length 9-bit mask */
2852 /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2856 /* The precision error of the cable length is +/- 10 meters */
2866 * on Link-Up */
2908 * 15-5: page
2909 * 4-0: register offset
2928 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
2947 #define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
2980 #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
2982 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
2986 #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
2987 #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
2988 #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
2990 #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10…
2991 #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Hal…
3001 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabl…
3002 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
3003 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
3006 #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
3020 #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
3021 #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
3078 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */